Voltage gain amplifier for automotive radar

Abstract

The present disclosure relates to a voltage gain amplifier for automotive radar. Disclosed herein is a voltage gain amplifier for use in an automotive radar receiver chain. The voltage gain amplifier utilizes pole-to-zero cancellation to yield a desired transfer function without gain peaking at a bandwidth where peaking is desired, and utilizes a low pass filter that is effectively formed by a feedback loop that includes a high pass filter and a differential amplifier to ensure a desired level of attenuation at the desired bandwidth. In some instances, a chopper can be utilized in the feedback loop before the high pass filter and after the differential amplifier in order to reduce the bandwidth of the differential amplifier in the feedback loop.

Description

Technical Field

[0001] The present disclosure relates to the field of voltage gain amplifiers used in receiver chains of automotive radar devices, and in particular to the design of a voltage gain amplifier that is able to provide a desired level of attenuation in the aliasing band resulting from a given receiver chain configuration while avoiding gain peaking issues. Background Art

[0002] Radar systems are now commonly used in automotive driver assistance systems, for example, to determine the distance to other vehicles and objects near a vehicle utilizing the radar system. As an example, a vehicle's cruise control system may utilize radar so that when there are no nearby vehicles ahead of the vehicle utilizing the radar system, the vehicle utilizing the radar system maintains a set speed, but when there are nearby vehicles ahead of the vehicle utilizing the radar system, the vehicle utilizing the radar system slows down to maintain a set distance between itself and the nearby vehicles.

[0003] Such radar systems include a transmission chain that transmits radio waves and a reception chain that receives radio waves that have been reflected from nearby vehicles or objects and returned to the vehicle employing the radar system. By analyzing the received radio waves, the distance to the nearby vehicle or object can be determined.

[0004] Reference Figure 1 Now, a receive chain 10 for a vehicle-mounted radar system is described. Receive chain 10 includes a mixer 11 that receives an input RF signal RX_IN from a radar wave receiver. The input RF signal RX_IN represents radar waves reflected from a target and returned to receive chain 10.

[0005] The local oscillator output signal LO_IN is amplified by amplifier 12, and mixer 11 mixes the amplified local oscillator output signal LO_IN with the input RF signal RX_IN to produce a baseband signal. High-pass filter 13 filters the baseband signal to attenuate the DC branch and outputs the baseband signal in differential form. The outputs of high-pass filter 13 are differential signals Vinp and Vinm, and each output also carries the input common-mode voltage Vicm.

[0006] The voltage gain amplifier (VGA) 15 disclosed herein receives a differential input signal, Vicm+Vinp, at its non-inverting input terminal and a differential input signal, Vicm-Vinm, at its inverting input terminal. The VGA 15 generates output differential signals, Voutp and Voutm, which are received as inputs by a second voltage gain amplifier (VGA2) 24 that provides further amplification.

[0007] Note that the second VGA 24 can be of any design and in some cases does not have the same structure and functionality as the VGA 15. The output of the second VGA 24 is received and filtered by the low-pass filter 16 to produce output differential signals Vlpfp and Vlpfm, which are then converted to the digital domain by the analog-to-digital converter (ADC) 17. The digital signal output OUT from the ADC 17 can be used to determine the distance between the vehicle incorporating the receive chain 10 and nearby vehicles or objects.

[0008] In this example, the IF bandwidth is approximately 25 MHz, and the ADC 17 driven by the VGA 15 is a 12-bit ADC with a sampling frequency of 100 MHz. The result of the 25 MHz IF bandwidth and the 100 MHz sampling frequency is an aliasing band between 75 MHz and 100 MHz. Therefore, an attenuation of approximately 72 dB between 75 MHz and 100 MHz is desired to avoid inadvertently sampling signals in the aliasing band.

[0009] The low-pass filter 16 is therefore designed to act as an anti-aliasing filter and is placed after the second VGA 24 because, if the low-pass filter 16 were placed before the VGA 15, the noise introduced by the low-pass filter 16 would be amplified, which is undesirable. As a result, signals in the 75 MHz to 100 MHz aliasing band are present at the input of the VGA 15 and can saturate the VGA 15, drowning out the desired signals in the mid-band.

[0010] Therefore, the design of the VGA 15 needs to attenuate signals in the aliasing band. Attempts to create VGAs that attenuate signals in the aliasing band have been made, but they have disadvantages. For example, gain peaking may occur in the bandwidth where attenuation is desired, making it impossible to achieve the desired attenuation level.

[0011] Therefore, further development is needed. Summary of the Invention

[0012] Disclosed herein is a circuit (e.g., a voltage gain amplifier) ​​comprising: an amplifier having an input that receives an input signal and generates an output signal at an output, wherein the output signal includes a desired low-frequency component and an undesired high-frequency component; a high-pass filter that receives the output signal and is configured to filter out the desired low-frequency component and pass the undesired high-frequency component; and a transistor circuit coupled between the input of the amplifier and ground, wherein the transistor circuit is driven by the undesired high-frequency components of the output signal passed through the high-pass filter such that the transistor circuit removes those undesired high-frequency components from the input signal.

[0013] Also disclosed herein is a circuit comprising: an amplifier having an input for receiving an input signal and generating an output signal at an output, wherein the output signal includes undesired high-frequency components; a first chopper configured to receive the output signal and process the output signal, wherein the first chopper outputs a chopper output signal in which the undesired high-frequency components are down-converted to a lower frequency and up-converted to a higher frequency; a low-pass filter configured to pass the undesired high-frequency components down-converted to a lower frequency while filtering out the undesired high-frequency components up-converted to a higher frequency; a second chopper configured to up-convert the undesired high-frequency components down-converted to a lower frequency by the first chopper back to their original high frequency; and a transistor circuit coupled between the second chopper and ground, wherein the transistor circuit is driven by the down-converted undesired high-frequency components of the output signal passed through the low-pass filter, such that the transistor circuit removes those up-converted undesired high-frequency components from the input signal through the second chopper. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram of a known receiving chain of a vehicle-mounted radar system including a voltage gain amplifier.

[0015] Figure 2 is a schematic diagram of a voltage gain amplifier disclosed herein, which can be used with Figure 1 Used together with the vehicle radar system.

[0016] Figure 3 is a schematic diagram of another embodiment of the voltage gain amplifier disclosed herein, which can be used with Figure 1 Used together with the vehicle radar system.

[0017] Figure 4 It is compared in terms of frequency Figures 2 to 3 A graph of the response of a voltage gain amplifier of FIG. 1 and the response of a known prior art voltage gain amplifier.

[0018] Figure 5 is similar to Figure 2 Schematic diagram of an embodiment of a voltage gain amplifier, but using field effect transistors instead of bipolar junction transistors.

[0019] Figure 6 is similar to Figure 3 A schematic diagram of an embodiment of a voltage gain amplifier, but with PNP transistors instead of NPN transistors. DETAILED DESCRIPTION

[0020] The following disclosure enables one skilled in the art to make and use the subject matter disclosed herein. The general principles described herein may be applied to embodiments and applications other than those described in detail above without departing from the spirit and scope of the present disclosure. The present disclosure is not intended to be limited to the embodiments shown, but is to be given the widest scope consistent with the principles and features disclosed or suggested herein. Note that, for example, any resistor shown as an adjustable resistor may be a group of selectable resistors or may be adjusted by any other suitable means.

[0021] Now first refer to Figure 2 To describe the Figure 1 The structure and operation of the voltage gain amplifier (VGA) 15 used in the reception chain 1 of FIG. In particular, the structure will be described first, and then the operation will be described.

[0022] VGA 15 is composed of a differential pair of NPN bipolar junction transistors NP1 and NP2. The first amplifier 23 receives a differential input signal Vinp+Vicm at its non-inverting input, has its inverting input coupled to the emitter of transistor NP1, and provides its output to the base of transistor NP1. Similarly, the second amplifier 26 receives a differential input signal Vinm+Vicm at its non-inverting input, has its inverting input coupled to the emitter of transistor NP2, and provides its output to the base of transistor NP2. Two adjustable resistors Rs are connected in series between the emitters of transistors NP1 and NP2, with an input common-mode voltage Vicm formed at the center tap between resistors Rs. The DC gain of VGA 15 is Rd / Rs, so the gain of VGA 15 can be changed by varying Rs.

[0023] Current source 22 is coupled to the emitter of transistor NP1 and sinks current I1 therefrom. An adjustable resistor Rz, configured as capacitor Cz, and an NMOS transistor are coupled in series between the base of transistor NP1 and ground. Capacitor C1 is coupled between the base of transistor NP1 and ground. Capacitor Cs (representing the input capacitance of the differential amplifier) ​​is illustratively coupled between the inverting terminal of amplifier 23 and ground. Current source 21 is coupled between the collector of transistor NP1 and power supply voltage Vdd and supplies current I1+I2 / 2. Capacitor C1 is utilized to stabilize amplifier 23.

[0024] Similarly, current source 25 is coupled to the emitter of transistor NP2 and also sinks current I1 therefrom. An adjustable resistor Rz, configured as capacitor Cz, and an NMOS transistor are coupled in series between the base of transistor NP2 and ground, and capacitor C1 is coupled between the base of transistor NP1 and ground. Capacitor Cs (representing the input capacitance of the differential amplifier) ​​is illustratively coupled between the inverting terminal of amplifier 26 and ground. Current source 24 is coupled between the collector of transistor NP2 and power supply voltage Vdd and provides current I1+I2 / 2. Capacitor C1 is utilized to stabilize amplifier 26.

[0025] VGA 15 also includes a second differential pair of NPN bipolar junction transistors NP3 and NP4. The emitters of transistors NP3 and NP4 are coupled to tail current source 28, which sinks current I2. The collector of transistor NP3 is coupled to the collector of transistor NP1 and the non-inverting terminal of amplifier 27. The base of transistor NP3 is coupled to the non-inverting output of amplifier 27 via capacitor C1. The collector of transistor NP4 is coupled to the collector of transistor NP2 and to the inverting terminal of amplifier 27 to receive output voltage Voutp. The base of transistor NP3 is coupled to the inverting output of amplifier 27 via capacitor C1 to receive output voltage Voutn. Resistor R1 is coupled in series between the bases of transistors NP3 and NP4, with output common-mode voltage Vocm formed at the center tap of resistor R1. Resistor R1 and capacitor C1 form a high-pass filter. An adjustable resistor Rd is coupled between the inverting input and the non-inverting output of the amplifier 27 , and another adjustable resistor Rd is coupled between the non-inverting input and the inverting output of the amplifier 27 .

[0026] In operation, amplifiers 23 and 26 increase the transconductance of transistors NP1 and NP2. Resistor Rz and capacitor Cz form a pole (zero in the input network) in the transfer function, while capacitors Cs and Rs form a zero in the transfer function. Transistors NP1 and NP2 produce the following gain due to the differential current generated by resistor Rs flowing through resistor Rd:

[0027]

[0028] Note that in the above equation, Cd represents the load capacitance at the output of VGA 15. The resistance values ​​of Rz and Rs track each other over PVT variations because they are formed with the same technology (integrated into the same substrate using the same technology). Similarly, Cz will generally track the gate-source capacitance of transistors NP1 and NP2. This tracking eliminates the problem of gain peaking because the pole The term cancels out the zero point (1+sCs*Rs).

[0029] If it is desired to increase gain by reducing Rs, then Rz is reduced accordingly according to the calibration function to maintain pole-to-zero cancellation and the corresponding gain peaking cancellation. Similarly, if it is desired to increase gain by increasing Rd, then after setting the value of Rs, Rz is increased to move the zero in the input network closer to the mid-frequency to remove the gain droop effect caused by Rd*Cd.

[0030] To provide the desired 72 dB of attenuation, the capacitance value of capacitor C1 and the resistance value of resistor R1 are selected based on the expected location of the aliasing band (and can be fine-tuned for accuracy). Thus, in the example shown, C1 and R1 are selected so as to filter frequencies above 75 MHz from the input of the differential amplifier formed by transistors NP3 and NP4. Thus, if the differential signal represented by Voutp and Voutn has a component with a frequency of 75 MHz or higher, that component will be removed from the input of amplifier 27 by the differential amplifier formed by transistors NP3 and NP4, and ultimately from the differential signal represented by Voutp and Voutn. In other words, for the purpose of having only the high-frequency components of the output signal represented by Voutp and Voutn drive the gate of the differential amplifier formed by transistors NP3 and NP4, resistor R1 and capacitor C1 form a high-pass filter, such that the differential amplifier effectively acts as a low-pass filter, removing signal components above the set high-pass filter frequency (here, as an example, 75 MHz) from the output signal represented by Voutp and Voutn.

[0031] The reason for using this feedback loop to perform low pass filtering is that if a capacitor is placed in parallel with resistor Rd to perform the desired filtering, the resulting pole will change as Rd changes, thereby changing the gain of VGA 15.

[0032] Therefore, this design of the VGA not only eliminates the gain peaking problem of the prior art, but also achieves 72dB of attenuation in the aliasing band from 75MHz to 100MHz.

[0033] It should be understood here that the bandwidth of the amplifier formed by transistors NP3 and NP4 is 75 MHz to 100 MHz (thus, equal to the bandwidth of the aliasing band).

[0034] Now refer to Figure 3 Described is a variation of VGA 15' that not only eliminates the high frequency gain peak, but also provides the desired attenuation of the output signals Voutp and Voutn at 75 MHz. VGA 15' has the same Figure 2The VGA 15 has the same structure as the VGA 15, except for the connection with transistors NP3 and NP4. Here, a 100 MHz chopper 31 (the frequency of the chopper 32 is 100 MHz to match the frequency of the ADC 17) is coupled between the collector of transistor NP3 and the collector of transistor NP1, and is coupled between the collector of transistor NP4 and the collector of transistor NP3.

[0035] Furthermore, here, the filter between the output of amplifier 27 and the input of the differential amplifier formed by transistors NP3 and NP4 is different from the filter in VGA 15 because it is a low-pass filter. Indeed, capacitor C3 is coupled between the bases of transistors NP3 and NP4. Resistor R3 is coupled between the base of transistor NP4 and a 100 MHz chopper 32 (the frequency of chopper 32 is 100 MHz to match the frequency of ADC 17), and another resistor R3 is coupled between the base of transistor NP3 and chopper 32. Chopper 32 is coupled between resistor R3 and the inverting output of amplifier 27, and between resistor R3 and the non-inverting output of amplifier 27.

[0036] Note that the differential amplifier formed by transistors NP3 and NP4 has a bandwidth greater than 75 MHz because the signal driving its inputs will have a frequency of at least 75 MHz. Choppers 31 and 32 are used to reduce this bandwidth. The high-frequency components of Voutp and Voutn at 75 MHz are therefore chopped down to 25 MHz and 125 MHz by chopper 32. The low-pass filter formed by resistor R3 and capacitor C3 filters the signal component at 125 MHz, so the bases of transistors NP3 and NP4 only receive the 25 MHz signal component. Chopper 31 converts the frequency of the signal received by transistors NP3 and NP4 back to 75 MHz to 100 MHz, which is the bandwidth of the aliasing band.

[0037] Therefore, in Figure 3 In the embodiment of Figure 3 The bandwidth of the differential amplifier formed by transistors NP3 and NP4 in the embodiment is 0 MHz to 25 MHz, instead of Figure 3 The transistors NP3 and NP4 in the embodiment form a differential amplifier with a bandwidth of 75MHz to 100MHz.

[0038] exist Figure 4 The robust performance of VGA 15' and VGA 15 can be seen in the graphs of , where it can be seen that the prior art gain peaking is eliminated and the desired attenuation of 72dB in the aliasing band is achieved (and actually exceeded) since the attenuation in the aliasing band is 78dB. Figure 4 What can be noticed from the graph is that the gain remains relatively flat and varies by less than 0.5dB.

[0039] In the above description, a 25MHz IF bandwidth and a 100MHz sampling frequency are used as examples. The selection of the IF bandwidth and sampling frequency results in an aliasing band of 75MHz to 100MHz and a desired attenuation of 72dB. Similarly, the chopper frequency is derived from the aliasing band frequency. It should be understood that these values ​​are for illustrative purposes only, and any IF bandwidth and sampling frequency can be used. The desired attenuation level and chopper frequency can be adjusted accordingly based on the IF bandwidth and sampling frequency.

[0040] It should be understood that although the exemplary voltage gain amplifiers illustrated and described above have utilized bipolar junction transistors, field effect transistors could be used instead. Figure 5 VGA 15" with Figure 2 Compared to the VGA 15 shown above, the transistors configured as capacitor Cz' are n-channel transistors, n-channel transistors MN1 and MN2 replace NPN transistors NP1 and NP2, and n-channel transistors MN3 and MN4 replace NPN transistors NP3 and NP4. The operating principle of VGA 15' remains the same as that of the aforementioned VGA 15.

[0041] Similarly, it should be understood that although the exemplary voltage gain amplifiers shown and described have utilized NPN bipolar junction transistors, they could instead utilize PNP bipolar junction transistors. Figure 6 VGA 15"' with Figure 3comparisons, it can be seen that NPN transistors NP1 and NP2 are replaced with PNP transistors PN1 and PN2, and NPN transistors NP3 and NP4 are replaced with PNP transistors PN3 and PN4. In addition, note that capacitor Cs is coupled between the inverting terminal of amplifier 23 and Vdd, capacitor Cl is coupled between the output terminal of amplifier 23 and Vdd, and adjustable resistor Rz and transistor configured as capacitor Cz are coupled in series between the output terminal of amplifier 23 and Vdd. In addition, note that current II from current source 22 is provided to the emitter of PNP transistor PN1, and current II + I2 / 2 from current source 21 is absorbed from the collector of PNP transistor PN1 to ground. Similarly, note that capacitor Cs is coupled between the inverting terminal of amplifier 26 and Vdd, capacitor Cl is coupled between the output terminal of amplifier 26 and Vdd, and adjustable resistor Rz and transistor configured as capacitor Cz are coupled in series between the output terminal of amplifier 26 and Vdd. In addition, note that current II from current source 25 is provided to the emitter of PNP transistor PN2, and current II + I2 / 2 from current source 24 is absorbed from the collector of PNP transistor PN2 to ground. The operation of VGA 15”’ is still the same as the operation of VGA 15’ described above.

[0042] While the present disclosure has been described with respect to a limited number of embodiments, those skilled in the art will appreciate that other embodiments can be devised which do not depart from the scope of the present disclosure disclosed herein. Accordingly, the scope of the present disclosure should only be limited by the claims appended hereto.

Claims

1. A circuit comprising: an amplifier having an input to receive an input signal, and the amplifier generating an output signal at an output, wherein the output signal includes a desired low frequency component and an undesired high frequency component; a high-pass filter receiving the output signal and configured to filter out the desired low-frequency components and pass the undesired high-frequency components; as well as a transistor circuit coupled between the input of the amplifier and ground, wherein the transistor circuit is driven by the undesired high frequency components of the output signal passed through the high pass filter such that the transistor circuit removes those undesired high frequency components from the input signal, wherein the input signal is a differential input signal consisting of a first differential input signal and a second differential input signal; wherein the output signal is a differential output signal composed of a first differential output signal and a second differential output signal, the first differential output signal and the second differential output signal including the desired low-frequency component and the undesired high-frequency component; wherein the amplifier has a first input for receiving the first differential input signal and a second input for receiving the second differential input signal, and the amplifier has a first output for outputting the first differential output signal and a second output for outputting the second differential output signal; wherein the transistor circuit comprises a differential amplifier formed by a first transistor and a second transistor, the first transistor and the second transistor having their first conduction terminals coupled to the first output and the second output of the amplifier, respectively, having their second conduction terminals coupled to a tail node, and having a control terminal; and The high-pass filter includes a filter resistor coupled between the control terminal of the first transistor and the control terminal of the second transistor, a first filter capacitor coupled between the control terminal of the first transistor and the first output of the amplifier, and a second filter capacitor coupled between the control terminal of the second transistor and the second output of the amplifier.

2. The circuit of claim 1 , wherein the differential amplifier comprises: a first NPN transistor having a collector coupled to the first input of the amplifier, an emitter coupled to the tail node, and a base coupled to the first output of the amplifier through the first filter capacitor; a second NPN transistor having a collector coupled to the second input of the amplifier, an emitter coupled to the tail node, and a base coupled to the second output of the amplifier through the second filter capacitor; as well as The filter resistor is coupled between the base of the first NPN transistor and the base of the second NPN transistor.

3. The circuit of claim 1 , wherein the differential amplifier comprises: a first n-channel transistor having a drain coupled to the first input of the amplifier, a source coupled to the tail node, and a gate coupled to the first output of the amplifier through the first filter capacitor; a second n-channel transistor having a drain coupled to the second input of the amplifier, a source coupled to the tail node, and a gate coupled to the second output of the amplifier through the second filter capacitor; as well as The filter resistor is coupled between the gate of the first n-channel transistor and the gate of the second n-channel transistor. The circuit of claim 1 , wherein the tail node is coupled to ground through a current source.

5. The circuit according to claim 1 , further comprising: an input differential amplifier formed by a first input transistor and a second input transistor having first conduction terminals thereof generating the first differential input signal and the second differential input signal, respectively, having second conduction terminals thereof coupled to the tail, and having control terminals thereof coupled to receive the first input signal and the second input signal, respectively.

6. The circuit according to claim 5, further comprising: A first tunable RC circuit is coupled between the control terminal of the first input transistor and ground, and a second tunable RC circuit is coupled between the control terminal of the second input transistor and ground.

7. The circuit of claim 5, further comprising a first amplifier providing the first input signal and a second amplifier providing the second input signal.

8. A circuit comprising: an amplifier having an input to receive an input signal, and the amplifier generating an output signal at an output, wherein the output signal includes an undesirable high frequency component; a first chopper configured to receive the output signal and process the output signal, wherein the first chopper outputs a chopper output signal in which the undesired high frequency component is down-converted to a lower frequency and up-converted to a higher frequency; a low-pass filter configured to pass the undesired high-frequency components down-converted to the lower frequency while filtering out the undesired high-frequency components up-converted to the higher frequency; a second chopper configured to up-convert the undesired high frequency component down-converted to the lower frequency by the first chopper back to its original high frequency; as well as a transistor circuit coupled to the second chopper, wherein the transistor circuit is driven by the down-converted undesired high-frequency components of the output signal passed through the low-pass filter, such that the transistor circuit removes those up-converted undesired high-frequency components from the input signal through the second chopper.

9. The circuit according to claim 8, wherein the input signal is a differential input signal consisting of a first differential input signal and a second differential input signal; wherein the output signal is a differential output signal consisting of a first differential output signal and a second differential output signal, the first differential output signal and the second differential output signal including the undesired high frequency component; wherein the amplifier has a first input for receiving the first differential input signal and a second input for receiving the second differential input signal, and the amplifier has a first output for outputting the first differential output signal and a second output for outputting the second differential output signal; wherein the transistor circuit comprises a differential amplifier formed by a first transistor and a second transistor, the first transistor and the second transistor having their first conduction terminals coupled to the first input and the second input of the amplifier, respectively, via the second chopper, having their second conduction terminals coupled to a tail node, and having a control terminal; and The low-pass filter includes a first filter resistor coupled between the first chopper and the control terminal of the first transistor, a second filter resistor coupled between the first chopper and the control terminal of the second transistor, and a filter capacitor coupled between the control terminal of the first transistor and the control terminal of the second transistor.

10. The circuit of claim 9, wherein the differential amplifier comprises: a first NPN transistor having a collector coupled to the first input of the amplifier through the second chopper, an emitter coupled to the tail node, and a base coupled to the first chopper through a first filter capacitor; a second NPN transistor having a collector coupled to the second input of the amplifier through the second chopper, an emitter coupled to the tail node, and a base coupled to the first chopper through a second filter capacitor; and The filter resistor is coupled between the base of the first NPN transistor and the base of the second NPN transistor.

11. The circuit of claim 9, wherein the tail node is coupled to ground through a current source.

12. The circuit of claim 9, wherein the tail node is coupled to a supply voltage through a current source.

13. The circuit of claim 9, further comprising: an input differential amplifier formed by a first input transistor and a second input transistor having first conduction terminals thereof generating the first differential input signal and the second differential input signal, respectively, having second conduction terminals thereof coupled to the tail, and having control terminals thereof coupled to receive the first input signal and the second input signal, respectively.

14. The circuit of claim 13 , further comprising: A first tunable RC circuit is coupled between the control terminal of the first input transistor and ground, and a second tunable RC circuit is coupled between the control terminal of the second input transistor and ground.

15. The circuit of claim 13, further comprising a first amplifier providing the first input signal and a second amplifier providing the second input signal.

16. The circuit of claim 9, further comprising: an input differential amplifier formed by a first input transistor and a second input transistor, the first input transistor and the second input transistor having their second conduction terminals generating the first differential input signal and the second differential input signal, respectively, having their first conduction terminals coupled to the tail, and having their control terminals coupled to receive the first input signal and the second input signal, respectively.

17. The circuit of claim 16, further comprising: A first tunable RC circuit is coupled between the control terminal of the first input transistor and a supply voltage, and a second tunable RC circuit is coupled between the control terminal of the second input transistor and a supply voltage.

18. A voltage gain amplifier comprising: A first differential amplifier comprising: a first NPN transistor having a collector coupled to the first output node, an emitter coupled to the first tail current source, and a base; a second NPN transistor having a collector coupled to the second output node, an emitter coupled to the second tail current source, and a base; a resistor coupled between the emitter of the first NPN transistor and the emitter of the second NPN transistor; a first input amplifier having a non-inverting input coupled to a first differential input voltage, an inverting input coupled to ground, and an output coupled to the base of the first NPN transistor; a first resistor and a first capacitor coupled in series between the base of the first NPN transistor and ground; a second input amplifier having a non-inverting input coupled to the second differential input voltage, an inverting input coupled to ground, and an output coupled to the base of the second NPN transistor; a second resistor and a second capacitor coupled in series between the base of the second NPN transistor and ground; a two-terminal differential amplifier having a non-inverting input coupled to the first output node, an inverting input coupled to the second output node, a non-inverting output coupled to the inverting input through a first feedback resistor, and an inverting output coupled to the non-inverting input through a second feedback resistor; and a low-pass filter circuit, coupled between the non-inverting output and the inverting output of the two-terminal differential amplifier and the inverting output and the non-inverting output of the two-terminal differential amplifier, respectively; wherein a resistance of the first resistor is substantially equal to a resistance coupled between an emitter of the first NPN transistor and an emitter of the second NPN transistor, and wherein a capacitance of the first capacitor is substantially equal to an input capacitance of the first differential amplifier; wherein a resistance of the second resistor is substantially equal to a resistance coupled between an emitter of the first NPN transistor and an emitter of the second NPN transistor, and wherein a capacitance of the second capacitor is substantially equal to an input capacitance of the first differential amplifier; and The first differential input voltage and the second differential input voltage represent input signals having an intermediate frequency, and the low-pass filter circuit is configured to filter out aliasing bandwidth associated with the intermediate frequency from the first output node and the second output node without changing poles and zeros of a transfer function of the voltage gain amplifier.

19. The voltage gain amplifier according to claim 18, wherein the low-pass filter loop comprises: a high-pass filter configured to pass through signal components output by the two-ended differential amplifier within the aliasing bandwidth and to block components output by the two-ended differential amplifier within the intermediate frequency bandwidth; as well as A second differential amplifier is configured to receive the output of the high-pass filter as an input, such that the second differential amplifier removes the signal component passed by the high-pass filter from the first output node and the second output node.

20. The voltage gain amplifier according to claim 19, The second differential amplifier comprises: a third NPN transistor having a collector coupled to the first output node, an emitter coupled to a tail current source, and a base coupled to the non-inverting output of the two-terminal differential amplifier through a first filter capacitor; a fourth NPN transistor having a collector coupled to the second output node, an emitter coupled to a tail current source, and a base coupled to the inverting output of the two-terminal differential amplifier via a second filter capacitor; as well as A filter resistor is coupled between the base of the third NPN transistor and the base of the fourth NPN transistor.

21. The voltage gain amplifier of claim 20 , wherein the first differential amplifier comprises an active load coupled between a power supply voltage and the first output node and the second output node, wherein the active load comprises a first current source coupled between the power supply voltage and the first output node and a second current source coupled between the power supply voltage and the second output node; wherein, The first tail current source and the second tail current source each sink a first current; wherein the tail current source of the second differential amplifier sinks a second current; and wherein the first current source provides a third current equal to the sum of half the second current and the first current, and the second current source provides the third current.

22. The voltage gain amplifier of claim 18, further comprising: a first chopper configured to down-convert a signal component within the aliasing bandwidth output by the two-terminal differential amplifier to a lower frequency bandwidth; a low-pass filter configured to pass a low-frequency component output by the first chopper to an input of a second differential amplifier, the second differential amplifier configured to sink a current including the low-frequency component output by the first chopper; as well as The second chopper is configured to up-convert the low-frequency component of the current absorbed by the second differential amplifier so as to remove the signal component within the aliasing bandwidth output by the double-ended differential amplifier from the first output node and the second output node.

23. The voltage gain amplifier of claim 22, wherein the second differential amplifier comprises: a third NPN transistor having a collector coupled to the first output node, an emitter coupled to a tail current source, and a base coupled to the non-inverting output of the two-terminal differential amplifier through a first filter resistor; a fourth NPN transistor having a collector coupled to the second output node, an emitter coupled to a tail current source, and a base coupled to the inverting output of the two-terminal differential amplifier through a second filter resistor; as well as A capacitor and a resistor are coupled between the base of the third NPN transistor and the base of the fourth NPN transistor.

24. The voltage gain amplifier of claim 23 , wherein the first differential amplifier comprises an active load coupled between a power supply voltage and the first output node and the second output node, wherein the active load comprises a first current source coupled between the power supply voltage and the first output node and a second current source coupled between the power supply voltage and the second output node; wherein, The first tail current source and the second tail current source each sink a first current; wherein the tail current source of the second differential amplifier sinks a second current; and wherein the first current source provides a third current equal to the sum of half the second current and the first current, and the second current source provides the third current.

25. The voltage gain amplifier of claim 18, wherein the first capacitor and the second capacitor are formed by MOSFETs configured as transistors.

26. The voltage gain amplifier of claim 18, wherein the first differential amplifier comprises an active load coupled between a supply voltage and the first and second output nodes.

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