Low Voltage Differential Signaling Driver

Abstract

A low-voltage differential driver includes an output driver configured to provide an output between a first output node and a second output node. The output driver includes a current source, a first branch, and a second branch. The current source is configured to provide a source current. The current source is connected to a parallel connection of the first branch and the second branch connected between an upper node and a lower node. The first branch includes a first switch, a second switch, and the first output node therebetween. The second branch parallel to the first branch includes a third switch, a fourth switch, and the second output node therebetween. The first switch and the second switch are controlled by a first switch circuit and a second switch circuit respectively, and the first switch circuit and the second switch circuit form a first driver. The third switch and the fourth switch are controlled by a third switch circuit and a fourth switch circuit respectively, and the third switch circuit and the fourth switch circuit form a second driver. Each of the first to fourth switch circuits is connected between the upper node and the lower node.

Description

Technical Field

[0001] The present invention relates to a Low Voltage Differential Signaling (LVDS) driver. Background Art

[0002] LVDS transmission has the advantages of low voltage, low power consumption, and noise immunity. Figure 1 The circuit diagram of an LVDS transmission system is shown. The LVDS transmission system 100 includes a driver 102 and a receiver 104. The driver 102 includes a current source 106, and first to fourth transistors 108, 110, 112, 114. The current source 106 provides a current which, according to the TIA-EIA0-644-A-2001 standard, is preferably 3.5 mA. The first transistor 108 and the second transistor 110 are connected in series between the current source 106 and the ground. The third transistor 112 and the fourth transistor 114 are connected in series between the current source 106 and the ground.

[0003] The first transistor 108 and the fourth transistor 114 turn on in response to a first input signal applied to their gate (control) terminals. The second transistor 110 and the third transistor 114 turn on in response to a second input signal applied to their gate (control) terminals. The driver 102 provides output signals at a first node 116 between the first transistor 108 and the second transistor 110 and at a second node 118 between the third transistor 112 and the fourth transistor 114.

[0004] The receiver 104 includes a termination resistor 120 and a comparator 122. The comparator 122 has a negative input terminal and a positive input terminal, and each of the negative input terminal and the positive input terminal is coupled to a corresponding one of the first node 116 and the second node 118 of the driver 102. The resistor 120 is coupled between the negative input terminal and the positive input terminal of the comparator 122. The resistor 120 has a resistance value preferably of 100 ohms. The comparator 122 is configured to have a high DC input impedance, so that the current of the output signal transmitted from the driver 102 mainly flows through the termination resistor 120, and causes a voltage difference at the input terminals of the comparator 122. As described, this voltage difference is approximately 350 mV.

[0005] As the current polarity of the output signal of the driver 102 changes due to the switching of the first to fourth transistors 108 to 114, the polarity of the voltage difference at the input terminals of the comparator 122 flips, causing the logical state of the output of the comparator 122 to change.

[0006] LVDS transmission makes the processing of signals focus on the voltage difference at the input end of comparator 122, such as 350 mV in this example. Accordingly, LVDS transmission is highly efficient and reliable. As the critical dimension (CD) of manufacturing transistors is reduced to 14 nm and then to 7 nm, the supply voltage is reduced to 1.8 V or lower. The above poses challenges for transistors to meet the requirements of LVDS. Summary of the Invention

[0007] This Summary of the Invention is provided to introduce a selected simplified portion of the concepts described in detail in the following Detailed Description. This Summary of the Invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0008] According to one embodiment, a low-voltage differential driver includes:

[0009] An output driver configured to provide an output between a first output node and a second output node, wherein the output driver includes:

[0010] A current source configured to provide a source current and connected in parallel with a first branch and a second branch connected between an upper node and a lower node;

[0011] The first branch includes a first switch, a second switch, and a first output node therebetween; and

[0012] A second branch in parallel with the first branch, the second branch includes a third switch, a fourth switch, and a second output node therebetween; wherein

[0013] The first switch and the second switch are controlled by a first switch circuit and a second switch circuit respectively, and the first switch circuit and the second switch circuit form a first driver;

[0014] The third switch and the fourth switch are controlled by a third switch circuit and a fourth switch circuit respectively, and the third switch circuit and the fourth switch circuit form a second driver; and wherein

[0015] Each of the first to fourth switch circuits is connected between the upper node and the lower node.

[0016] In one or more embodiments:

[0017] The first branch further includes a first voltage drop element connected between the first switch and the second switch;

[0018] The second branch further includes a second voltage drop element connected between the third switch and the fourth switch.

[0019] In one or more embodiments, the first voltage drop element and the second voltage drop element are each a PMOS transistor connected as a diode.

[0020] In one or more embodiments, the output driver further includes a termination resistor connected between the first output node and the second output node.

[0021] In one or more embodiments, the first switching circuit of the first driver includes:

[0022] A first PMOS transistor having a source terminal, a gate terminal, and a drain terminal; the source terminal of the first PMOS transistor is connected to the upper node, the gate terminal of the first PMOS transistor is connected to receive an input signal, and the drain terminal of the first PMOS transistor is connected to the control terminal of the first switch;

[0023] A first NMOS transistor having a drain terminal, a gate terminal, and a source terminal; the drain terminal of the first NMOS transistor is connected to the drain terminal of the first PMOS transistor, the gate terminal of the first NMOS transistor is connected to the gate terminal of the first PMOS transistor and receives the input signal, and the source terminal of the first NMOS transistor is connected to the lower node; and

[0024] A circuit connected as a diode that operates to receive the inverse signal of the input signal and provide a first switching signal to the first switch.

[0025] In one or more embodiments, the circuit connected as a diode includes:

[0026] A second PMOS transistor having a gate terminal, a source terminal, and a drain terminal, the gate terminal of the second PMOS transistor is connected to receive the inverse signal of the input signal, and the source terminal of the second PMOS transistor is connected to the upper node;

[0027] A second NMOS transistor having a gate terminal, a drain terminal, and a source terminal, the gate terminal of the second NMOS transistor is connected to the gate terminal of the second PMOS transistor and receives the inverse signal of the input signal, the drain terminal of the second NMOS transistor is connected to the drain terminal of the second PMOS transistor, and the source terminal of the second NMOS transistor is connected to the control terminal of the first switch; and

[0028] A third PMOS transistor having a gate terminal, a source terminal, and a drain terminal, the gate terminal of the third PMOS transistor is connected to the drain terminals of the second PMOS transistor and the second NMOS transistor, the source terminal of the third PMOS transistor is connected to the upper node, and the drain terminal of the third PMOS transistor is connected to the control terminal of the first switch.

[0029] In one or more embodiments, the second switching circuit of the first driver includes:

[0030] A first PMOS transistor having a source terminal, a gate terminal, and a drain terminal, wherein the source terminal of the first PMOS transistor is connected to an upper node, the gate terminal of the first PMOS transistor is connected to receive an input signal, and the drain of the first PMOS transistor is connected to the control terminal of a second switch;

[0031] A first NMOS transistor having a drain terminal, a gate terminal, and a source terminal, wherein the drain terminal of the first NMOS transistor is connected to the drain terminal of the first PMOS transistor, the gate terminal of the first NMOS transistor is connected to receive an input signal, and the source terminal of the first NMOS transistor is connected to a lower node; and

[0032] A circuit connected as a diode, operative to receive an inverted signal of the input signal and to provide a second switch signal to the second switch.

[0033] In one or more embodiments, the circuit connected as a diode includes:

[0034] A second PMOS transistor having a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal of the second PMOS transistor is connected to receive an inverted signal of the input signal, and the source terminal of the second PMOS transistor is connected to the control terminal of the second switch;

[0035] A second NMOS transistor having a gate terminal, a drain terminal, and a source terminal, wherein the gate terminal of the second NMOS transistor is connected to the gate terminal of the second PMOS transistor and to receive an inverted signal of the input signal, the drain terminal of the second NMOS transistor is connected to the drain terminal of the second PMOS transistor, and the source terminal of the second NMOS transistor is connected to the lower node; and

[0036] A third NMOS transistor having a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal of the third NMOS transistor is connected to the drain terminals of the second PMOS transistor and the second NMOS transistor, the source terminal of the third NMOS transistor is connected to the lower node, and the drain terminal of the third NMOS transistor is connected to the control terminal of the second switch.

[0037] In one or more embodiments, the third switch circuit of the second driver includes:

[0038] A first PMOS transistor having a source terminal, a gate terminal, and a drain terminal, wherein the source terminal of the first PMOS transistor is connected to an upper node, the gate terminal of the first PMOS transistor is connected to receive an inverted signal of the input signal, and the drain terminal of the first PMOS transistor is connected to the control terminal of a third switch;

[0039] A first NMOS transistor having a drain terminal, a gate terminal, and a source terminal, wherein the drain terminal of the first NMOS transistor is connected to the drain terminal of a first PMOS transistor, the gate terminal of the first NMOS transistor is connected to the gate terminal of the first PMOS transistor and receives an inverted signal of an input signal, and the source terminal of the first NMOS transistor is connected to a low node; and

[0040] A circuit connected as a diode, operative to receive an input signal and to provide a third switching signal to a third switch.

[0041] In one or more embodiments, the circuit connected as a diode includes:

[0042] A second PMOS transistor having a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal of the second PMOS transistor is connected to receive the input signal, and the source terminal of the second PMOS transistor is connected to a high node;

[0043] A second NMOS transistor having a gate terminal, a drain terminal, and a source terminal, wherein the gate terminal of the second NMOS transistor is connected to the gate terminal of the second PMOS transistor and receives the input signal, the drain terminal of the second NMOS transistor is connected to the drain terminal of the second PMOS transistor, and the source terminal of the second NMOS transistor is connected to a control terminal of a third switch; and

[0044] A third PMOS transistor having a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal of the third PMOS transistor is connected to the drains of the second PMOS transistor and the second NMOS transistor, the source terminal of the third PMOS transistor is connected to the high node, and the drain terminal of the third PMOS transistor is connected to the control terminal of the third switch.

[0045] In one or more embodiments, the fourth switching circuit of the second driver includes:

[0046] A first PMOS transistor having a source terminal, a gate terminal, and a drain terminal, wherein the source terminal of the first PMOS transistor is connected to the high node, the gate terminal of the first PMOS transistor is connected to receive an inverted signal of the input signal, and the drain terminal of the first PMOS transistor is connected to a control terminal of a fourth switch;

[0047] A first NMOS transistor having a drain terminal, a gate terminal, and a source terminal, wherein the drain terminal of the first NMOS transistor is connected to the drain terminal of the first PMOS transistor, the gate terminal of the first NMOS transistor is connected to receive an inverted signal of the input signal, and the source terminal of the first NMOS transistor is connected to the low node; and

[0048] A circuit connected as a diode, operative to receive the input signal and to provide a fourth switching signal to the fourth switch.

[0049] In one or more embodiments, a circuit connected as a diode includes:

[0050] A second PMOS transistor having a gate terminal, a source terminal, and a drain terminal, the gate terminal of the second PMOS transistor being connected to receive an input signal, and the source terminal of the second PMOS transistor being connected to the control terminal of a fourth switch;

[0051] A second NMOS transistor having a gate terminal, a drain terminal, and a source terminal, the gate terminal of the second NMOS transistor being connected to the gate terminal of the second PMOS transistor and receiving the input signal, the drain terminal of the second NMOS transistor being connected to the drain terminal of the second PMOS transistor, and the source terminal of the second NMOS transistor being connected to a low node; and

[0052] A third NMOS transistor having a gate terminal, a source terminal, and a drain terminal, the gate terminal of the third NMOS transistor being connected to the drain terminals of the second PMOS transistor and the second NMOS transistor, the source terminal of the third NMOS transistor being connected to the low node, and the drain terminal of the third NMOS transistor being connected to the control terminal of the fourth switch.

[0053] In one or more embodiments,

[0054] The first switch and the third switch are PMOS transistors; and

[0055] The second switch and the fourth switch are NMOS transistors.

[0056] According to one embodiment, a low voltage differential driver includes:

[0057] An output driver, including:

[0058] A current source configured to provide a source current;

[0059] A first switch and a second switch connected in series between the current source and a second voltage, wherein the first switch and the second switch are alternately closed, and a differential signal driven by the current source flows through a first node between the first switch and the second switch; and

[0060] A third switch and a fourth switch connected in series between the current source and the second voltage, wherein the third switch and the fourth switch are alternately closed, and the differential signal flows through a second node between the third switch and the fourth switch;

[0061] A first pre-driver connected between the current source and the second voltage, configured to receive an input signal, and generate a first switch signal and a second switch signal, the first switch signal and the second switch signal being respectively provided to the control terminals of the first switch and the second switch of the output driver; and

[0062] Second pre-driver. Connected between a current source and a second voltage, configured to receive an input signal, and generate a third switching signal and a fourth switching signal, the third switching signal and the fourth switching signal are respectively provided to the control terminals of the third switch and the fourth switch of the output driver.

[0063] In one or more embodiments, the output driver further includes:

[0064] A first voltage drop element, connected between a first node and a second switch, the first voltage drop element causes the series connection of the first switch and the second switch to operate in a first voltage range between a first voltage and a second voltage, the first voltage range being smaller than a second voltage range between the supply voltage provided to the current source and the ground level;

[0065] A second voltage drop element, connected between a second node and a fourth switch, the second voltage drop element causes the series connection of the third switch and the fourth switch to operate in the first voltage range.

[0066] In one or more embodiments, the first voltage drop element and the second voltage drop element are PMOS transistors connected as diodes.

[0067] In one or more embodiments, the first pre-driver includes:

[0068] A first PMOS transistor, having a gate terminal configured to receive an input signal, a source terminal connected to the current source, and a drain terminal connected to the first switch;

[0069] A first NMOS transistor, having a gate terminal connected to the gate terminal of the first PMOS transistor and configured to receive an input signal, a source terminal connected to the second voltage, and a drain terminal connected to the drain terminal of the first PMOS transistor;

[0070] A second PMOS transistor, having a gate terminal configured to receive the inverted signal of the input signal, a source terminal connected to the current source, and a drain terminal;

[0071] A second NMOS transistor, having a gate terminal connected to the gate terminal of the second PMOS transistor and configured to receive the inverted signal of the input signal, a source terminal connected to the drain terminals of the first PMOS transistor and the first NMOS transistor, and a drain terminal connected to the drain terminal of the second PMOS transistor; and

[0072] A third PMOS transistor, having a gate terminal connected to the drain terminals of the second PMOS transistor and the second NMOS transistor, a source terminal connected to the current source, and a drain terminal connected to the first switch to provide a first switching signal.

[0073] In one or more embodiments, the first pre-driver includes:

[0074] A first PMOS transistor having a gate terminal configured to receive an input signal, a source terminal connected to a current source, and a drain terminal connected to a second switch;

[0075] A first NMOS transistor having a gate terminal connected to the gate terminal of the first PMOS transistor and configured to receive an input signal, a source terminal connected to a second voltage, and a drain terminal connected to the drain terminal of the first PMOS transistor;

[0076] A second PMOS transistor having a gate terminal configured to receive an inverted signal of the input signal, a source terminal connected to the drain terminals of the first PMOS transistor and the first NMOS transistor, and a drain terminal;

[0077] A second NMOS transistor having a gate terminal connected to the gate terminal of the second PMOS transistor and configured to receive an inverted signal of the input signal, a source terminal connected to a second voltage, and a drain terminal connected to the drain terminal of the second PMOS transistor; and

[0078] A third NMOS transistor having a gate terminal connected to the drain terminals of the second PMOS transistor and the second NMOS transistor, a source terminal connected to a second voltage, and a drain terminal connected to the second switch to provide a second switch signal.

[0079] In one or more embodiments, the second pre-driver includes:

[0080] A first PMOS transistor having a gate terminal configured to receive an inverted signal of the input signal, a source terminal connected to a current source, and a drain terminal connected to a third switch;

[0081] A first NMOS transistor having a gate terminal connected to the gate terminal of the first PMOS transistor and configured to receive an inverted signal of the input signal, a source terminal connected to a second voltage, and a drain terminal connected to the drain terminal of the first PMOS transistor;

[0082] A second PMOS transistor having a gate terminal configured to receive the input signal, a source terminal connected to a current source, and a drain terminal;

[0083] A second NMOS transistor having a gate terminal connected to the gate terminal of the second PMOS transistor and configured to receive the input signal, a source terminal connected to the drain terminals of the first PMOS transistor and the first NMOS transistor, and a drain terminal connected to the drain terminal of the second PMOS transistor; and

[0084] A third PMOS transistor having a gate terminal connected to the drains of the second PMOS transistor and the second NMOS transistor, a source terminal connected to a current source, and a drain terminal connected to a third switch to provide a third switching signal.

[0085] In one or more embodiments, the second pre-driver includes:

[0086] A first PMOS transistor having a gate terminal configured to receive an inverted signal of an input signal, a source terminal connected to a current source, and a drain terminal connected to a fourth switch;

[0087] A first NMOS transistor having a gate terminal connected to the gate terminal of the first PMOS transistor and receiving the inverted signal of the input signal, a source terminal connected to a second voltage, and a drain terminal connected to the drain terminal of the first PMOS transistor;

[0088] A second PMOS transistor having a gate terminal configured to receive the input signal, a source terminal connected to the drain terminals of the first PMOS transistor and the first NMOS transistor, and a drain terminal;

[0089] A second NMOS transistor having a gate terminal connected to the gate terminal of the second PMOS transistor and configured to receive the input signal, a source terminal connected to the second voltage, and a drain terminal connected to the drain terminal of the second PMOS transistor; and

[0090] A third NMOS transistor having a gate terminal connected to the drains of the second PMOS transistor and the second NMOS transistor, a source terminal connected to the second voltage, and a drain terminal connected to a fourth switch to provide a fourth switching signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0091] To enable the foregoing content of the present invention to be understood in a more specific manner, a further detailed description of the present invention may be obtained with reference to the embodiments, some of which are shown by the accompanying drawings. The accompanying drawings only show typical embodiments of the present invention, and since the present invention may have other equally effective embodiments, the accompanying drawings should not be construed as limiting the scope of the present invention. The drawings are drawn for ease of understanding rather than for measuring the present invention. For those skilled in the art, the benefits of the claimed inventive subject matter will be readily understood upon reading this description and in conjunction with the accompanying drawings. In the drawings, like reference numerals are used to indicate like elements, and:

[0092] Figure 1 is a circuit diagram of a low voltage differential signal transmission system;

[0093] Figure 2 is a block diagram of a current mode low voltage differential signal driver according to one embodiment;

[0094] Figure 3 is Figure 2 a detailed circuit diagram of a current-mode low-voltage differential signal driver; and

[0095] Figure 4 is according to an embodiment of Figure 2 and Figure 3 a schematic diagram of the switching signal and output signal of the driver of Detailed Embodiments

[0096] Figure 2 is a block diagram of a current-mode low-voltage differential signal driver according to an embodiment of the present invention. The low-voltage differential signal (LVDS) driver 200 includes an output driver 202, a first driver 206 or a first pre-driver 206, and a second driver 210 or a second pre-driver 210. The output driver 202 includes a current source 220 that operates at a supply voltage V DDA and provides a source current similarly to the current source 106 in Figure 1 . According to the standard TIA-EIA0-644-A-2001, the source current is 3.5 mA. Specifically, the current source 220 can be implemented as a PMOS transistor having a gate terminal that receives a bias signal P _bias , a source terminal connected to receive the supply voltage VDDA, and a drain terminal that provides the source current.

[0097] and Figure 1Similarly, the output driver 202 in this embodiment includes a first branch 222 and a second branch 224 connected in parallel. Specifically, the first branch 222 includes a first switch 226 and a second switch 228 connected in series. The differential signal driven by the current source 220 flows through the first node 230 between the first switch 226 and the second switch 228. In this embodiment, the first switch 226 is a PMOS transistor and the second switch 228 is an NMOS transistor. In other embodiments, other switching elements may also be applicable. As described, the first switch 226 and the second switch 228 are alternately closed under the control of the switching signals provided to the gate terminals of the transistors 226, 228. The first switching signal pp is provided to the gate terminal (control terminal) of the PMOS transistor 226 to turn on / off the PMOS transistor 226, and the second switching signal pn is provided to the gate or control terminal of the NMOS transistor 228 to turn on / off the NMOS transistor 228. The first driver 206 includes a first switching circuit 260 and a second switching circuit 262. The first switching circuit 260 receives the input signal IN and the inverted signal IN_B of the input signal, and provides the first switching signal pp to the first switch 226 of the output driver 202. The second switching circuit 262 receives the input signal IN and the inverted signal IN_B of the input signal, and provides the second switching signal pn to the second switch 228 of the output driver 202.

[0098] Specifically, the first switch 226 has a gate or control terminal that receives the first switching signal pp, a source terminal that is connected to the current source 220 through the supply node 232 to receive the source current, and a drain terminal that is connected to the first node 230. The supply node 232 has a first voltage level p_out. The second switch 228 has a gate or control terminal that receives the second switching signal pn, a drain terminal that is coupled to the first node 230, and a source terminal that is connected to the ground node 234. The coupling between the drain terminal of the second switch 228 and the first node 230 can be a direct connection or can be through another element 242 that will be described in detail later.

[0099] According to one or more embodiments, the ground node 234 is connected to the ground level through the feedback transistor N FB and the feedback transistor N FB is an NMOS transistor that receives the feedback signal N _FB as a control signal. The feedback signal N _FB can be extracted from the differential signal provided by the output driver 202, which causes the drain terminal of the feedback transistor N FB connected to the ground node 234 to have a second voltage level n_out. In one or more embodiments, the bias transistor N BIASIt can also be connected between the ground node 234 and the ground level. As shown in the figure, the bias transistor N BIAS is an NMOS transistor, which has a gate terminal receiving a bias control signal N _BIAS , a drain terminal connected to the ground node 234, and a source terminal connected to the ground level. The bias transistor N BIAS can be used to further adjust the second voltage level n_out on the ground node 234 and release a constant ground current of about 1 mA to prevent the common-mode feedback loop of the output driver 202 from entering an infinite loop when the first voltage level p_out on the supply node 232 and the second voltage level n_out on the ground node 234 are close enough to each other.

[0100] Similarly, the second branch 224 includes a third switch 236 and a fourth switch 238 connected in series. The differential signal flows through the second node 240 between the third switch 236 and the fourth switch 238. In this embodiment, the third switch 236 is a PMOS transistor and the fourth switch 239 is an NMOS transistor. In other embodiments, other switching elements can also be applicable. The third switch 236 and the fourth switch 238 are controlled to alternately close. The third switch signal np is provided to the gate or control terminal of the PMOS transistor 236 to turn on / off the PMOS transistor 236, and the fourth switch signal nn is provided to the gate or control terminal of the NMOS transistor 238 to turn on / off the NMOS transistor 238. The second driver 210 includes a third switch circuit 212 and a fourth switch circuit 214. The third switch circuit 212 receives the input signal IN and the inverted signal IN_B of the input signal, and provides the third switch signal np to the third switch 236 of the output driver 202. The fourth switch circuit 214 receives the input signal IN and the inverted signal IN B of the input signal, and provides the fourth switch signal nn to the fourth switch 238 of the output driver 202.

[0101] Specifically, the third switch 236 has a gate or control terminal receiving the third switch signal np, a source terminal connected to the supply node 232, and a drain terminal connected to the second node 240. The fourth switch 238 has a gate or control terminal receiving the fourth switch signal nn, a drain terminal coupled to the second node 240, and a source terminal connected to the ground node 234. The coupling between the drain terminal of the fourth switch 238 and the second node 240 can be a direct connection or through additional elements 244 to be described in detail below.

[0102] During operation, the differential signal driven by the current source 220 flows through the first node 230, Figure 2 not shown in but related to Figure 1a termination resistor similar to the termination resistor 120 in [[ ]], and a second node 240, and a voltage difference appears between the first node 230 and the second node 240. Since the termination resistor typically has a resistance value of 100 ohms, the voltage difference between the first node 230 and the second node 240 is about 350 mV. Since each switch of the output driver 202 has a negligibly small drain-source voltage drop in the on state, the voltage difference between the first voltage level p_out on the supply node 232 and the second voltage level n_out on the ground node 234 is also approximately 350 mV. To further distinguish the voltage difference of about 350 mV from the threshold voltage of the switching transistor, the output driver 202 may further include a first voltage drop element 242 connected between the first node 230 and the second switch 228, and a second voltage drop element 244 connected between the second node 240 and the fourth switch 238.

[0103] Now refer to Figure 3 , which shows the first to fourth switch circuits 260, 262, 212, 214, and the first and second voltage drop elements 242, 244. As shown, the first voltage drop element 242 may be a PMOS transistor connected as a diode, whose gate terminal is connected to the drain terminal and to the drain terminal of the second switch 228, and whose source terminal is connected to the first node 230. Similarly, the second voltage drop element 244 may be a PMOS transistor connected as a diode, whose gate terminal is connected to the drain terminal and to the drain terminal of the fourth switch 238, and whose source terminal is connected to the second node 240. The first voltage drop element 242 and the second voltage drop element 244 increase the voltage difference between the voltage level on the first node 230 and the voltage level on the second node 240, so a value is added to the voltage difference between the first voltage level p_out on the supply node 232 and the second voltage level n_out on the ground node 234, making it reach about 800 mV to 900 mV. As is known, the threshold voltage of a transistor is defined as the voltage difference between the voltage levels applied to the gate terminal and the source terminal of the transistor. When the source terminal voltage approaches the threshold voltage, it becomes difficult to switch the transistor by applying a gate voltage signal to the gate terminal. The increased voltage difference brought about by the voltage drop elements 242 and 244 can enhance the switching of the transistors of the LVDS driver 200. In addition, the first and second voltage drop elements 242, 244 also enable the first voltage level p_out and the second voltage level n_out to vary with different manufacturing processes, so as to stabilize the output impedance of the first pre-driver 206 and the second pre-driver 210 operating at the first and second voltage levels.

[0104] The first pre-driver 206 and the second pre-driver 210 are connected in parallel with the first branch 222 and the second branch 224 between the supply node 232 and the ground node 234 to operate in a voltage range between the first voltage level p_out and the second voltage level n_out. By Figure 2 and Figure 3 It can be understood that the voltage range between the first voltage level p_out and the second voltage level n_out is smaller than the voltage range between the supply voltage VDDA and the ground level. As described, the common-mode voltage of the required differential signal is 1.2V, which further requires the supply voltage VDDA to be typically 1.8V, or at least 1.62V (10% down from 1.8V). However, process improvements and scaling have led to a reduction in device size and a decrease in the maximum tolerable voltage, such as the threshold voltage V of the transistor th . Supplying the devices of the LVDS driver 200 with a reduced voltage range between the first voltage level p_out at the supply node 232 and the second voltage level n_out at the ground node 234 enables devices manufactured in an advanced process, such as a 14-nanometer FinFET process, to operate and reduces power consumption and leakage.

[0105] As described, both the first pre-driver 206 and the second pre-driver 210 receive the input signal IN and the inverted signal IN_B of the input signal. The inverted signal IN_B of the input signal can be provided, for example, by using a single-ended to differential signal generator from the input signal. As Figure 3 shown, the first to fourth switch circuits 260, 262, 212, 214 all operate in the voltage range between the first voltage level p_out and the second voltage level n_out. Since the first pre-driver 206 and the second pre-driver 210 have a symmetric structure, only the first switch circuit 260 and the second switch circuit 262 of the first pre-driver 206 will be described hereafter.

[0106] The first switching circuit 260 includes a first PMOS transistor 264, a first NMOS transistor 266, a second PMOS transistor 268, a second NMOS transistor 270, and a third PMOS transistor 272. The first PMOS transistor 264 has a gate or control terminal connected to receive an input signal IN, a source terminal connected to a current source 220 to be coupled to a first voltage level p_out, and a drain terminal connected to the gate or control terminal of a first switch 226 to provide a first switching signal pp. The first NMOS transistor 266 has a gate terminal connected to the gate terminal of the first PMOS transistor 264 and a gate (control) terminal to receive the input signal IN, a source terminal coupled to a second voltage level n_out, and a drain terminal. The drain terminal of the first NMOS transistor 266 is connected to the drain terminal of the first PMOS transistor 264 and the gate or control terminal of the first switch 226. The first PMOS transistor 264 and the first NMOS transistor 266 are connected as an inverter that receives the input signal IN and provides an inverter signal with respect to the input signal IN as the first switching signal pp provided to the first switch 226.

[0107] The second PMOS transistor 268 of the first switching circuit 260 has a gate or control terminal connected to receive an inverted signal IN_B of the input signal, a source terminal connected to the current source 220 to be coupled to the first voltage level p_out, and a drain terminal. The second NMOS transistor 270 of the first switching circuit 260 has a gate (control) terminal connected to the second PMOS transistor 268 and to receive the inverted signal IN_B of the input signal, a source terminal connected to the drain terminals of the PMOS transistor 264 and the first NMOS transistor 266, and a drain terminal connected to the drain terminal of the second PMOS transistor 268. The third PMOS transistor 272 of the first switching circuit 260 has a gate (control) terminal connected to the drain terminals of the second PMOS transistor 268 and the second NMOS transistor 270, a source terminal coupled to the first voltage level p_out, and a drain terminal connected to the gate (control) terminal of the first switch 226 to provide the first switching signal pp. The second PMOS transistor 268, the second NMOS transistor 270, and the third PMOS transistor of the first switching circuit 260 are connected as a diode circuit that receives the inverted signal IN_B of the input signal and provides the first switching signal pp to the first switch 226.

[0108] Similarly to the first switch 260, the second switch 262 also includes a first PMOS transistor 274 and a first NMOS transistor 276 connected as an inverter between a first voltage level p_out and a second voltage level n_out. The first PMOS transistor 274 and the first NMOS transistor 276 each receive an input signal IN at their gate terminals, and provide a second switching signal pn to the gate or control terminal of the second switch 228 at their drain terminals. The source terminal of the first PMOS transistor 274 of the second switch 262 is connected to the first voltage level p_out, and the source terminal of the first NMOS transistor 276 of the second switching circuit 262 is connected to the second voltage level n_out.

[0109] Further, the second switching circuit 262 also includes a diode circuit that receives an inverted signal IN_B of the input signal, and provides the second switching signal pn to the second switch 228. Different from the diode circuit of the first switching circuit 260, the diode circuit of the second switching circuit 262 includes a second PMOS transistor 278, a second NMOS transistor 280, and a third NMOS transistor 282. The second PMOS transistor 278 of the second switching circuit 262 has a gate or control terminal connected to receive the inverted signal IN_B of the input signal, a source terminal connected to the drain terminals of the first PMOS transistor 274 and the first NMOS transistor 276, and a drain terminal. The second NMOS transistor 280 of the second switching circuit 262 has a gate or control terminal connected to the gate (control) terminal of the second PMOS transistor 278 and receiving the inverted signal IN_B of the input signal, a source terminal coupled to the second voltage level n_out, and a drain terminal, and the drain terminal of the second NMOS transistor 280 is connected to the drain terminal of the second PMOS transistor 278 of the second switching circuit 262. The third NMOS transistor 282 of the second switching circuit 262 has a gate terminal, a source terminal, and a drain terminal; wherein the gate terminal is connected to the drain terminals of the second PMOS transistor 278 and the second NMOS transistor 280, the source terminal is connected to the second voltage level n_out, and the drain terminal is connected to the gate or control terminal of the second switch 228 and provides the second switching signal pn.

[0110] The third switching circuit 212 of the second pre-driver 210 is configured similarly to the first switching circuit 260 of the first pre-driver 206, however, the PMOS and NMOS transistors connected as an inverter receive the inverted signal IN_B of the input signal, and the diode circuit receives the input signal IN. The fourth switching circuit 214 of the second pre-driver 210 is configured similarly to the second switching circuit 262 of the first pre-driver 206, except that the PMOS and NMOS transistors connected as an inverter receive the inverted signal IN_B of the input signal, and the diode circuit receives the input signal IN.

[0111] The input signal IN and the inverted signal IN_B of the input signal are supplied to the first pre-driver 206 and the second pre-driver 210, so that the first switch 226 and the second switch 228 of the first branch 222 are alternately closed, and the third switch 236 and the fourth switch 238 are alternately closed. Specifically, when the first switch 226 and the fourth switch 238 are closed and the second switch 228 and the third switch 236 are open, the source current driven by the current source 220 will flow through the first switch 226, the first node 230, the terminal resistor ( Figure 2 not shown in the figure), the second node 240, and the fourth switch 238. When the first switch 226 and the fourth switch 238 are open and the second switch 228 and the third switch 236 are closed, the source current driven by the current source 220 will flow through the third switch 236, the second node 240, the terminal resistor, the first node 230, and the second switch 228.

[0112] The first switch 226 and the second switch 228 of the first branch 222 in the switch output driver 202 are described herein. The switching actions of the third switch 236 and the fourth switch 238 in the second branch 224 are similar to those of the first branch 222. Figure 4 is a schematic diagram showing the first to fourth switch signals of the switches applied to the Figure 3 output driver based on the input signal IN and the inverted signal IN_B of the input signal, and the output of the output driver. Figure 4 The illustration in the figure will be described in detail for the first pre-driver 206, that is, the first switch signal pp identified as 302 and the second switch signal pn identified as 304. The input signal IN and the inverted signal IN_B of the input signal typically swing within a voltage range of 0 to 1.8V, which is significantly greater than the first to fourth switch signals.

[0113] In the first branch 222 of the output driver 202, the first switch 226 and the second switch 228 are preferably not closed simultaneously to avoid significant leakage. To close the second switch 228, the second switch signal pn needs to increase until the threshold voltage V of the second switch 228, that is, the NMOS transistor thn . At the same time, the first switch signal pp applied to the first switch 226 also increases to turn off the PMOS transistor 226. As Figure 4As shown, both the first switching signal pp and the second switching signal pn increase. To increase the first switching signal pp and the second switching signal pn, the input signal IN decreases while the inverted signal IN_B of the input signal increases. For the first switching circuit 260 of the first pre-driver 206, when the input signal IN drops to the threshold voltage of the first NMOS transistor 266, the first NMOS transistor 266 will be turned off, causing the first switching signal pp provided at the drain terminal of the first NMOS transistor 266 to be pulled up by the diode circuit as the inverted signal IN_B of the input signal increases. For the diode circuit, as the inverted signal IN_B of the input signal increases, the second NMOS transistor 270 is turned on to pull down the voltage at the gate terminal of the third PMOS transistor 272, thereby switching the third PMOS transistor 272 to the on state. The turned-on third PMOS transistor 272 provides the first switching signal pp with an increasing voltage level at its drain terminal. Furthermore, when the increase exceeds the threshold voltage V thp of the first switch 226, the first switch 226 is turned off.

[0114] Similarly, in the second switching circuit 262, the increase in the inverted signal IN_B of the input signal applied to the diode circuit of the second switching circuit turns on the second NMOS transistor 280 and turns off the third NMOS transistor 282, causing the second switching signal pn to be pulled up by the first PMOS transistor 274. The decrease in the input signal IN operates to turn on the first PMOS transistor when it drops below the threshold voltage of the first PMOS transistor 274, thereby pulling up the second switching signal pn provided at the drain of the first PMOS transistor 274. From Figure 4 this, it can be seen that as the first switching signal pp and the second switching signal pn rise, the output 310 of the first node 230 decreases from the first voltage level p_out downward, gradually decreasing past the common-mode voltage V_cm until the second voltage level n_out. On the other side of the LVDS driver 200, the decrease in the input signal IN and the increase in the inverted signal IN_B of the input signal together pull down the third switching signal np labeled 306 and the fourth switching signal nn labeled 308. The decreasing third switching signal np turns on the PMOS transistor 236, and the decreasing fourth switching signal nn turns off the NMOS transistor 238. Therefore, the output 312 at the second node 240 increases from the second voltage level n_out until the first voltage level p_out.

[0115] Thereafter, after the output 312 at the second node 240 is fully established, the input signal IN starts to rise to turn on the first switch 226 and turn off the second switch 228. The increase in the input signal IN turns on the first NMOS transistor 276 of the second switch circuit 262 and pulls down the second switch signal pn until it is lower than the threshold voltage V of the second switch 228. thn As a result, the second switch 228 is turned off. The input signal IN provided at the gate terminal of the first NMOS transistor 266 of the first switch circuit 260 increases beyond the threshold voltage of the first NMOS transistor 266 to turn on the first NMOS transistor 266, and pulls down the first switch signal pp provided at the drain terminal of the first NMOS transistor 266 to the second voltage level n_out. The voltage level of the first switch signal pp is lower than the threshold voltage V of the first switch 226. thp This will turn on the first switch 226.

[0116] It should be understood that the switch circuits 212, 214, 260, 262 determine the switching rate of the gate signals applied to the corresponding switches. Therefore, the switching rates of the switch signals pp, pn, np, nn are configurable according to the configuration of the devices in the switch circuits, such as the sizes of the first NMOS transistor 266 of the first switch circuit 260 and the first PMOS transistor 274 of the second switch circuit 260. Figure 4 The dashed lines in show the switch signals with controlled switching rates and the output signals at the first node 230 and the second node 240. Return to reference Figure 2 and Figure 3 , in one or more embodiments, as shown, the on-die termination resistor 246 can be connected between the first node 230 and the second node 240. The on-die termination resistor 246 is controlled by the enable signal odt_en to be coupled in the output driver 202 in high-speed mode. The on-die termination resistor 246 is locally connected in the output driver 202 when it is enabled to improve the transmission of the output LVDS signal, with smaller signal delay and enhanced performance.

[0117] Specifically shown examples are referred to herein for describing various exemplary embodiments. The examples of the examples are selected to assist those skilled in the art in forming a clear understanding of the embodiments and implementing them. However, the scope of systems, structures, and devices that can be constructed to include one or more embodiments, and the scope of methods implemented according to one or more embodiments, are not limited by the exemplary examples shown. On the contrary, those skilled in the art can understand based on this specification that many other configurations, structures, and methods can be implemented according to the embodiments.

[0118] It should be understood that, with respect to the various positional indications used in the foregoing description of the present invention, such as top, bottom, upper, lower, etc., those indications are given only with reference to the corresponding drawings, and when the orientation of the device changes during manufacturing or operation, other positional relationships may instead be present. As described above, those positional relationships are described only for clarity and are not restrictive.

[0119] The foregoing description of the present specification is with reference to specific embodiments and specific drawings, but the present invention should not be limited thereto and should be given by the claims. The described drawings are all exemplary and not restrictive. In the drawings, for illustrative purposes, the dimensions of the various elements may be enlarged and may not be drawn to a specific scale. The present specification should also include discontinuous changes in the tolerances and properties of the various elements and the manner of operation. It should also include various weakened embodiments of the present invention.

[0120] The term "comprising" as used in this specification and the claims does not exclude other elements or steps. Unless otherwise specified, when using the singular form such as "a", "an" to refer to a definite or indefinite element, the plural of that element should be included. Thus, the term "comprising" should not be construed as limited to the items listed thereafter and should not be construed as excluding other elements or steps; the scope of the description "the device comprises items A and B" should not be limited to a device that only includes elements A and B. This description means that, with respect to this specification, only elements A and B of the device are relevant. Although coupling generally includes inductive connection and connection generally means connection through, for example, wires, the terms "connected", "coupled", "coupling" as used herein all indicate that there is an electrical connection between the coupled or connected elements and do not mean that there are no intermediate elements therebetween. When describing transistors and their connections, the terms gate, drain, and source are interchangeable with gate electrode, drain electrode, source electrode and gate terminal, drain terminal, source terminal.

[0121] Those skilled in the art can make various specific changes without departing from the scope of the claims of the present invention.

Claims

1. A low-voltage differential driver, characterized in that, Comprising: An output driver configured to provide an output between a first output node and a second output node, wherein the output driver comprises: A current source configured to provide a source current and connected in parallel with a first branch and a second branch connected between an upper node and a lower node; The first branch includes a first switch, a second switch, and a first output node therebetween; and A second branch parallel to the first branch, the second branch includes a third switch, a fourth switch, and a second output node therebetween; wherein The first switch and the second switch are controlled by a first switch circuit and a second switch circuit respectively, and the first switch circuit and the second switch circuit form a first driver; The third switch and the fourth switch are controlled by a third switch circuit and a fourth switch circuit respectively, and the third switch circuit and the fourth switch circuit form a second driver; and wherein: Each of the first to fourth switch circuits is connected between the upper node and the lower node; The first branch further includes a first voltage drop element connected between the first switch and the second switch, and the first voltage drop element is a PMOS transistor connected as a diode; The second branch further includes a second voltage drop element connected between the third switch and the fourth switch, and the second voltage drop element is a PMOS transistor connected as a diode.

2. The driver according to claim 1, characterized in that: The output driver further includes a termination resistor connected between the first output node and the second output node.

3. The driver according to claim 1, characterized in that, The first switch circuit of the first driver includes: A first PMOS transistor having a source terminal, a gate terminal, and a drain terminal; the source terminal of the first PMOS transistor is connected to the upper node, the gate terminal of the first PMOS transistor is connected to receive an input signal, and the drain terminal of the first PMOS transistor is connected to the control terminal of the first switch; A first NMOS transistor having a drain terminal, a gate terminal, and a source terminal; the drain terminal of the first NMOS transistor is connected to the drain terminal of the first PMOS transistor, the gate terminal of the first NMOS transistor is connected to the gate terminal of the first PMOS transistor and receives the input signal, and the source terminal of the first NMOS transistor is connected to the low node; and A circuit connected as a diode, operating to receive the inverse signal of the input signal and provide a first switch signal to the first switch.

4. The driver according to claim 1, characterized in that, The second switch circuit of the first driver includes: A first PMOS transistor having a source terminal, a gate terminal, and a drain terminal, the source terminal of the first PMOS transistor is connected to the upper node, the gate terminal of the first PMOS transistor is connected to receive the input signal, and the drain of the first PMOS transistor is connected to the control terminal of the second switch; A first NMOS transistor having a drain terminal, a gate terminal, and a source terminal, the drain terminal of the first NMOS transistor is connected to the drain terminal of the first PMOS transistor, the gate terminal of the first NMOS transistor is connected to receive the input signal, and the source terminal of the first NMOS transistor is connected to the low node; and A circuit connected as a diode, operating to receive the inverse signal of the input signal and provide a second switch signal to the second switch.

5. The driver according to claim 1, characterized in that, The third switch circuit of the second driver includes: A first PMOS transistor having a source terminal, a gate terminal, and a drain terminal, wherein the source terminal of the first PMOS transistor is connected to an upper node, the gate terminal of the first PMOS transistor is connected to receive an inverted signal of an input signal, and the drain terminal of the first PMOS transistor is connected to a control terminal of a third switch; A first NMOS transistor having a drain terminal, a gate terminal, and a source terminal, wherein the drain terminal of the first NMOS transistor is connected to the drain terminal of the first PMOS transistor, the gate terminal of the first NMOS transistor is connected to the gate terminal of the first PMOS transistor and receives the inverted signal of the input signal, and the source terminal of the first NMOS transistor is connected to a lower node; and A circuit connected as a diode, operative to receive the input signal and provide a third switch signal to the third switch.

6. The driver according to claim 1, wherein The fourth switching circuit of the second driver includes: A first PMOS transistor having a source terminal, a gate terminal, and a drain terminal, wherein the source terminal of the first PMOS transistor is connected to the upper node, the gate terminal of the first PMOS transistor is connected to receive the inverted signal of the input signal, and the drain terminal of the first PMOS transistor is connected to a control terminal of a fourth switch; A first NMOS transistor having a drain terminal, a gate terminal, and a source terminal, wherein the drain terminal of the first NMOS transistor is connected to the drain terminal of the first PMOS transistor, the gate terminal of the first NMOS transistor is connected to receive the inverted signal of the input signal, and the source terminal of the first NMOS transistor is connected to the lower node; and A circuit connected as a diode, operative to receive the input signal and provide a fourth switch signal to the fourth switch.

7. A low-voltage differential driver, characterized in that, Comprising: An output driver, comprising: A current source configured to provide a source current; A first switch and a second switch connected in series between the current source and a second voltage, wherein the first switch and the second switch are alternately closed, and a differential signal driven by the current source flows through a first node between the first switch and the second switch; and A third switch and a fourth switch connected in series between the current source and the second voltage, wherein the third switch and the fourth switch are alternately closed, and the differential signal flows through a second node between the third switch and the fourth switch; A first pre-driver connected between the current source and the second voltage, configured to receive the input signal and generate a first switch signal and a second switch signal, the first switch signal and the second switch signal being respectively provided to control terminals of the first switch and the second switch of the output driver; and A second pre-driver connected between the current source and the second voltage, configured to receive the input signal and generate a third switch signal and a fourth switch signal, the third switch signal and the fourth switch signal being respectively provided to control terminals of the third switch and the fourth switch of the output driver; The output driver further includes: A first voltage drop element connected between the first node and the second switch, the first voltage drop element causing the series connection of the first switch and the second switch to operate in a first voltage range between a first voltage and a second voltage, the first voltage range being less than a second voltage range between a supply voltage provided to the current source and a ground level, the first voltage drop element being a PMOS transistor connected as a diode; A second voltage drop element is connected between the second node and the fourth switch. The second voltage drop element causes the series connection of the third switch and the fourth switch to operate within a first voltage range. The second voltage drop element is a PMOS transistor connected as a diode.

Images