Display device and method of manufacturing the same

Abstract

A display device and a manufacturing method thereof are disclosed. The display device can include a display panel; and an anti-reflection layer disposed on the display panel, the display panel including a first area defined with a first alignment mark, a curved area extending from the first area, and a second area extending from the curved area. It can be that a second alignment mark defined in the anti-reflection layer overlaps the second area when viewed on a plane.

Description

TECHNICAL FIELD

[0001] The present application relates to a display device and a manufacturing method thereof. BACKGROUND

[0002] Generally, electronic devices such as a smart phone, a digital camera, a notebook computer, a navigator, and a smart TV, etc. that provide an image to a user include a display device for displaying an image. The display device generates an image and provides the generated image to the user through a display screen.

[0003] Recently, as the technology of the display device is developed, a display device including a flexible display panel is developed. The display panel includes a plurality of pixels that display an image and a driving chip for driving the pixels. The pixels are disposed in a display area of the display panel, and the driving chip is disposed in a non-display area of the display panel surrounding the display area. A bending portion is defined between the driving chip and the display area, and the bending portion is bent so that the driving chip is disposed under the display panel. SUMMARY

[0004] An object of the present application is to provide a display device in which a bending area of a display panel can be bent to have a predetermined curvature and a manufacturing method thereof.

[0005] A display device according to an embodiment of the present application can include a display panel, and an anti-reflection layer disposed on the display panel, the display panel including a first area in which a first alignment mark is defined, a bending area extending from the first area, and a second area extending from the bending area. It can be that a second alignment mark defined in the anti-reflection layer overlaps the second area when viewed in a planar view.

[0006] A manufacturing method of a display device according to an embodiment of the present application can include a step of preparing a display panel including a first area in which a first alignment mark is defined, a bending area extending from the first area, and a second area extending from the bending area, a step of providing an anti-reflection layer on the display panel, a step of providing a driving IC spaced apart from the anti-reflection layer on the second area, a step of irradiating a laser to a portion of the anti-reflection layer that overlaps the second area when viewed in a planar view to form a second alignment mark, and a step of providing a cover tape on the second area to cover the driving IC. It can be that the cover tape is disposed on the anti-reflection layer disposed on the second area, and the cover tape does not overlap the second alignment mark when viewed in the planar view.

[0007] (EFFECTS OF THE INVENTION)

[0008] According to embodiments of the present application, a first alignment mark can be defined on a display panel, and a second alignment mark can be defined on an anti-reflection layer disposed on the display panel. When a bending area of the display panel is bent, the second alignment mark is aligned with the first alignment mark, so that the bending area can be bent to have a predetermined curvature. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a perspective view of a display apparatus according to embodiments of the present application.

[0010] Figure 2 is Figure 1 is a plan view of the display apparatus shown in FIG. 1.

[0011] Figure 3 is an enlarged view of any one of the pixels shown in FIG. 1. Figure 2

[0012] Figure 4 is Figure 2 is a sectional view taken along line I-I' shown in FIG. 1.

[0013] Figure 5 is an enlarged view of the second area adjacent to the bending area shown in FIG. 1. Figure 4

[0014] Figure 6 is a view showing a structure of an anti-reflection layer disposed on the second area shown in FIG. 1. Figure 5

[0015] is a view showing the first alignment mark defined on the display panel and the second alignment mark defined on the anti-reflection layer shown in FIG. 1, in a plan view. Figure 7 Figure 4 is a view showing a bending state of the bending area shown in FIG. 1.

[0016] Figure 8 Figure 4 is a view showing the bending area shown in FIG. 1, in a plan view.

[0017] Figure 9 is a view showing the bending area and the second area shown in FIG. 1, in a plan view. Figure 8

[0018] Figures 10 to 15 is a view for explaining a manufacturing method of a display apparatus according to embodiments of the present application.

[0019] Figure 16 is a view showing first and second alignment marks according to another embodiment of the present application.

[0020] (REFERENCE NUMERALS)

[0021] DD: display apparatus DP: display panel ​​​​​

[0022] ISP: input sensing section RPL: antireflection layer

[0023] WIN: window DDV: data driving section

[0024] CTP: cap tape AMK1, AMK2: first and second alignment marks

[0025] AA1, AA2: first and second areas BA: bending area

[0026] HC: hard coat layer PFM: polarizing film DETAILED DESCRIPTION

[0027] In the present specification, when referring to a certain constituent element (or area, layer, portion, etc.) "on", "connected to", or "bonded to" another constituent element, it means that the certain constituent element can be directly disposed / connected / bonded to the other constituent element, or a third constituent element can be disposed between them.

[0028] The same reference numerals refer to the same constituent elements. In addition, in the drawings, the thickness, proportions, and dimensions of the constituent elements are exaggerated for the effect of the technical content.

[0029] "and / or" includes all combinations of the relevant constituents defined thereby.

[0030] The first, second, and the like terms can be used to describe various constituent elements, but the constituent elements are not limited by the terms. The terms are used only for the purpose of distinguishing one constituent element from other constituent elements. For example, a first constituent element can be named a second constituent element, and similarly, a second constituent element can be named a first constituent element, without departing from the scope of the present application. Singular expressions include plural expressions unless clearly indicated to the contrary.

[0031] In addition, the terms "lower", "lower side", "upper", "upper side", and the like are used to describe the relative relationship of the constituent elements shown in the drawings. The terms are relative concepts, and are described based on the direction indicated in the drawings.

[0032] All terms used in the present specification, including technical and scientific terms, have the same meanings that are commonly understood by those skilled in the art to which the present application pertains. In addition, terms such as those defined in a generally used dictionary are to be interpreted to have the same meanings as those in the context of relevant technology, unless explicitly defined in various ways. Unless explicitly so defined in various ways, all terms used herein, including technical and scientific terms, have the same meanings as those that are commonly understood by those skilled in the art to which the present application pertains.

[0033] The terms "comprising" or "including" or "having" are to be construed as specifying the presence of stated features, numbers, steps, operations, constituents, components, or combinations thereof, and do not preclude the presence or addition of one or more other features, numbers, steps, operations, constituents, components, or combinations thereof.

[0034] Hereinafter, an embodiment of the present application will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 is a perspective view of a display device according to an embodiment of the present application.

[0036] Referring to Figure 1 The display device DD according to the embodiment of the present application can have a square shape having a long side extending in a first direction DR1 and having a short side extending in a second direction DR2 crossing the first direction DR1. However, it is not limited thereto, and the display device DD can have various shapes such as a circular shape or a polygonal shape.

[0037] Hereinafter, a direction substantially perpendicularly crossing a plane defined by the first direction DR1 and the second direction DR2 will be defined as a third direction DR3. Also, in the present specification, a meaning observed in a plane will be defined as a state observed from the third direction DR3.

[0038] A top surface of the display device DD can be defined as a display surface DS, and can have a plane defined by the first direction DR1 and the second direction DR2. An image IM generated in the display device DD through the display surface DS can be provided to a user.

[0039] The display surface DS can include a display area DA and a non-display area NDA surrounding the display area DA. It can be that the display area DA displays an image and the non-display area NDA does not display an image. The non-display area NDA can surround the display area DA, and define a bezel of the display device DD printed in a predetermined color.

[0040] The display device DD can be used for a large electronic device such as a television, a monitor, or an outdoor advertising board. Also, the display device DD can be used for a small or medium electronic device such as a personal computer, a notebook computer, a personal digital terminal, a car navigation device, a game machine, a smart phone, a tablet computer, or a camera. However, these are merely presented as exemplary embodiments, and can be used for other electronic devices as long as the concept of the present application is not exceeded.

[0041] Figure 2 is a plan view of a display device shown in Figure 1

[0042] Referring to Figure 2 ​The display device DD can include a display panel DP, a scan driver SDV, a data driver DDV, an emission driver EDV, a cover tape CTP, a printed circuit board PCB, and a timing controller T-CON.

[0043] The display panel DP according to an embodiment of the disclosure can be a light emitting type display panel, which is not particularly limited. For example, the display panel DP can be an organic light emitting display panel or a quantum dot light emitting display panel. The light emitting layer of the organic light emitting display panel can include an organic light emitting substance. The light emitting layer of the quantum dot light emitting display panel can include quantum dots, quantum rods, or the like. Hereinafter, the display panel DP is described as an organic light emitting display panel.

[0044] The display panel DP can be a flexible display panel. For example, the display panel DP can include a plurality of electronic elements disposed on a flexible substrate. The display panel DP can be longer in the first direction DR1 than in the second direction DR2. The display panel DP can have a plane defined by the first direction DR1 and the second direction DR2.

[0045] The display panel DP can include a first area AA1, a second area AA2, and a bending area BA disposed between the first area AA1 and the second area AA2. It can be that the first area AA1, the bending area BA, and the second area AA2 are aligned in the first direction DR1, and the bending area BA extends in the second direction DR2. It can be that the bending area BA extends from the first area AA1 in the first direction DR1, and the second area AA2 extends from the bending area BA in the first direction DR1.

[0046] The first area AA1 can have long sides extending in the first direction DR1 and opposite each other in the second direction DR2. The length of the bending area BA and the second area AA2 can be less than the length of the first area AA1, with reference to the second direction DR2.

[0047] The first area AA1 can include a display area DA and a non-display area NDA surrounding the display area DA. The non-display area NDA can surround the display area DA. It can be that the display area DA displays an image, and the non-display area NDA does not display an image. The second area AA2 and the bending area BA can not display an image.

[0048] The display panel DP can include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to ELm, a first control line CSL1, a second control line CSL2, a first power line PL1, a second power line PL2, a plurality of connection lines CNL, and a plurality of pads PD. m and n are natural numbers. The pixels PX can be arranged in the display area DA and connected to the scan lines SL1 to SLm, the data lines DL1 to DLn, and the emission lines EL1 to ELm.

[0049] The scan driving portion SDV and the emission driving portion EDV can be arranged in the non-display area NDA. The scan driving portion SDV and the emission driving portion EDV can be arranged in the non-display area NDA adjacent to the long side of the first area AA1. The data driving portion DDV can be arranged in the second area AA2.

[0050] The data driving portion DDV can be manufactured in an integrated circuit chip form and mounted on the second area AA2. The data driving portion DDV can be defined as a driving IC. The cover tape CTP can be arranged on the second area AA2 to cover the data driving portion DDV.

[0051] The scan lines SL1 to SLm can extend in the second direction DR2 and be connected to the scan driving portion SDV. The data lines DL1 to DLn can extend in the first direction DR1 and be connected to the data driving portion DDV via the bending area BA. The emission lines EL1 to ELm can extend in the second direction DR2 and be connected to the emission driving portion EDV.

[0052] The first power line PL1 can extend in the first direction DR1 and be arranged in the non-display area NDA. The first power line PL1 can be arranged between the display area DA and the emission driving portion EDV. However, the first power line PL1 can also be arranged between the display area DA and the scan driving portion SDV.

[0053] The first power line PL1 can extend to the second area AA2 via the bending area BA. When viewed in plan, the first power line PL1 can extend toward the lower end of the second area AA2. The first power line PL1 can receive a first voltage.

[0054] The second power line PL2 can be arranged in the non-display area NDA facing the second area AA2 and in the non-display area NDA adjacent to the long side of the first area AA1 with the display area DA in between. The second power line PL2 can be arranged in the periphery of the scan driving portion SDV and the emission driving portion EDV.

[0055] The second power line PL2 can extend into the second region AA2 via the bending region BA. The second power line PL2 extends in the first direction DR1 with the data drive unit DDV positioned in the middle of the second region AA2. When viewed in a plane, the second power line PL2 can extend towards the lower end of the second region AA2.

[0056] The second power line PL2 can receive a second voltage with a level lower than the first voltage. Although the connection is not illustrated for ease of explanation, the second power line PL2 may extend to the display area DA and connect to the pixel PX, with the second voltage provided to the pixel PX through the second power line PL2.

[0057] The connecting line CNL can extend in the second direction DR2 and be aligned in the first direction DR1. The connecting line CNL can be connected to the first power line PL1 and the pixel PX. A first voltage can be applied to the pixel PX through the interconnected first power line PL1 and connecting line CNL.

[0058] The first control line CSL1 can be connected to the scan driver unit SDV and extends towards the lower end of the second region AA2 via the curved region BA. The second control line CSL2 can be connected to the light emission driver unit EDV and extends towards the lower end of the second region AA2 via the curved region BA. The data driver unit DDV can be disposed between the first control line CSL1 and the second control line CSL2.

[0059] When viewed in a plane, the pad PD can be configured adjacent to the lower end of the second region AA2. The data driver DDV, the first power line PL1, the second power line PL2, the first control line CSL1, and the second control line CSL2 can be connected to the pad PD.

[0060] Data lines DL1 to DLn can be connected to their corresponding pads PD via the data driver unit DDV. For example, data lines DL1 to DLn can be connected to the data driver unit DDV, and the data driver unit DDV can be connected to the pads PD corresponding to the data lines DL1 to DLn respectively.

[0061] Multiple first alignment marks AMK1 can be defined on the display panel DP. The first alignment marks AMK1 can be defined in the non-display area NDA. Multiple second alignment marks AMK2 can be defined on the second area AA2 of the display panel DP. The more specific structure of the first alignment marks AMK1 and the second alignment marks AMK2 is described below. Figures 4 to 7 Detailed explanation follows.

[0062] The printed circuit board (PCB) can be connected to the pads (PD). The timing controller (T-CON) can be configured on the PCB. The timing controller (T-CON) can be manufactured as an integrated circuit chip and mounted on the PCB. The timing controller (T-CON) can be connected to the pads (PD) via the PCB.

[0063] Although not shown in the figure, the display device DD may also include a voltage generating unit for generating a first voltage and a second voltage. The voltage generating unit may be connected to pads PD that are connected to the first power line PL1 and the second power line PL2.

[0064] The timing controller T-CON can control the operation of the scan driver unit (SDV), the data driver unit (DDV), and the light emission driver unit (EDV). The timing controller T-CON can generate scan control signals, data control signals, and light emission control signals in response to control signals received from external sources.

[0065] The scan control signal can be provided to the scan driver unit (SDV) via the first control line CSL1. The light emission control signal can be provided to the light emission driver unit (EDV) via the second control line CSL2. The data control signal can be provided to the data driver unit (DDV). The timing controller can receive image signals from the outside and convert the image signal data format to match the interface specifications of the data driver unit (DDV) before providing it to the data driver unit (DDV).

[0066] The scan drive unit (SDV) can generate multiple scan signals in response to scan control signals. These scan signals can be applied to pixels PX via scan lines SL1 to SLm. The scan signals can be applied to pixels PX sequentially.

[0067] The data driving unit (DDV) can generate multiple data voltages corresponding to the image signal in response to a data control signal. These data voltages can be applied to pixel PX via data lines DL1 to DLn. The light emission driving unit (EDV) can generate multiple light emission signals in response to a light emission control signal. These light emission signals can be applied to pixel PX via light emission lines EL1 to Elm.

[0068] A pixel (PX) can receive a data voltage in response to a scan signal. A pixel (PX) can also emit light of a brightness corresponding to the data voltage in response to a light emission signal, thereby displaying an image. The emission time of the pixel (PX) can be controlled by the light emission signal.

[0069] Figure 3 This is an illustrative example. Figure 2 A cross-section of any pixel shown in the figure.

[0070] Reference Figure 3The pixel (PX) can be configured on the substrate (SUB) and includes a transistor (TR) and a light-emitting element (OLED). The light-emitting element (OLED) can include a first electrode (AE), a second electrode (CE), a hole control layer (HCL), an electron control layer (ECL), and a light-emitting layer (EML). The first electrode (AE) can be an anode electrode, and the second electrode (CE) can be a cathode electrode.

[0071] The transistor TR and the light-emitting element OLED can be disposed on the substrate SUB. Although a transistor TR is illustrated illustratively, in practice, the pixel PX may include multiple transistors for driving the light-emitting element OLED and at least one capacitor.

[0072] The display area DA may include the light-emitting area PA corresponding to the pixel PX and the non-light-emitting area NPA surrounding the light-emitting area PA. The light-emitting element OLED may be configured in the light-emitting area PA.

[0073] The substrate SUB may include a flexible plastic substrate. For example, the substrate SUB may contain transparent polyimide (PI). A buffer layer BFL, which is an inorganic layer, may be disposed on the substrate SUB. A semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may contain polycrystalline silicon. However, it is not limited to this; the semiconductor pattern may also contain amorphous silicon or metal oxide.

[0074] The electrical properties of a semiconductor pattern can differ depending on whether it is doped or not. A semiconductor pattern can include doped and undoped regions. Doped regions can be doped with N-type or P-type dopants. Doped regions have higher conductivity than undoped regions and can essentially function as the source and drain electrodes of a transistor (TR). Undoped regions can essentially function as the active region (or channel) of a transistor.

[0075] The source (S), active region (A), and drain (D) of transistor TR can be formed from a semiconductor pattern. A first insulating layer (INS1) can be disposed on the semiconductor pattern. The gate (G) of transistor TR can be disposed on the first insulating layer (INS1). A second insulating layer (INS2) can be disposed on the gate (G). A third insulating layer (INS3) can be disposed on the second insulating layer (INS2).

[0076] The connecting electrode CNE can be configured between the transistor TR and the light-emitting element OLED to connect the transistor TR and the light-emitting element OLED. The connecting electrode CNE may include a first connecting electrode CNE1 and a second connecting electrode CNE2.

[0077] The first connecting electrode CNE1 can be disposed on the third insulating layer INS3 and connected to the drain electrode D through a first contact hole CH1 defined in the first insulating layer INS1 to the third insulating layer INS3. A fourth insulating layer INS4 can be disposed on the first connecting electrode CNE1. A fifth insulating layer INS5 can be disposed on the fourth insulating layer INS4.

[0078] The second connecting electrode CNE2 can be disposed on the fifth insulating layer INS5. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through the second contact hole CH2 defined in the fifth insulating layer INS5. A sixth insulating layer INS6 can be disposed on the second connecting electrode CNE2. The first insulating layer INS1 to the sixth insulating layer INS6 can be inorganic or organic layers.

[0079] A first electrode AE ​​can be disposed on the sixth insulating layer INS6. The first electrode AE ​​can be connected to the second connecting electrode CNE2 through a third contact hole CH3 defined in the sixth insulating layer INS6. A pixel defining film PDL can be disposed on the first electrode AE ​​and the sixth insulating layer INS6 to expose a predetermined portion of the first electrode AE. An opening PX_OP for exposing a predetermined portion of the first electrode AE ​​can be defined in the pixel defining film PDL.

[0080] The hole control layer HCL can be disposed on the first electrode AE ​​and the pixel defining film PDL. The hole control layer HCL can be disposed together on the light-emitting region PA and the non-light-emitting region NPA. The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0081] The emissive layer EML can be configured on the hole control layer HCL. The emissive layer EML can be configured in the region corresponding to the opening PX_OP. The emissive layer EML can contain organic and / or inorganic materials. The emissive layer EML can generate any of the following light: red, green, and blue.

[0082] An electronic control layer (ECL) can be disposed on both the light-emitting layer (EML) and the hole control layer (HCL). The ECL can also be disposed together in both the light-emitting region (PA) and the non-light-emitting region (NPA). The ECL may include an electron transport layer and an electron injection layer.

[0083] The second electrode CE can be disposed on the electronic control layer ECL. The second electrode CE can also be disposed together on the pixel PX. The layer from the buffer layer BFL to the light-emitting element OLED can be defined as the pixel layer PXL.

[0084] A thin-film encapsulation layer (TFE) can be disposed on an OLED light-emitting element. The TFE can be disposed on a second electrode (CE) and cover a pixel (PX). The TFE may include a first encapsulation layer (EN1) disposed on the second electrode (CE), a second encapsulation layer (EN2) disposed on the first encapsulation layer (EN1), and a third encapsulation layer (EN3) disposed on the second encapsulation layer (EN2).

[0085] The first encapsulation layer EN1 and the third encapsulation layer EN3 can be inorganic layers, while the second encapsulation layer EN2 can be an organic layer. The first encapsulation layer EN1 and the third encapsulation layer EN3 can protect the pixel PX from moisture / oxygen. The second encapsulation layer EN2 can protect the pixel PX from foreign matter such as dust particles.

[0086] Alternatively, a first voltage can be applied to the first electrode AE ​​via a transistor TR, and a second voltage with a lower level than the first voltage can be applied to the second electrode CE. Holes and electrons injected into the light-emitting layer EML recombine to form excitons, and the light-emitting element OLED emits light as the excitons transition to the ground state.

[0087] Figure 4 yes Figure 2 The cross-sectional view of line I-I' is shown in the figure. Figure 5 Is with Figure 4 The diagram shows a plane of the second region adjacent to the curved region. Figure 6 It shows the configuration in Figure 5 The diagram shows the structure of the anti-reflective layer on the second region.

[0088] Reference Figure 4 The display device DD may include a display panel DP, a panel protective film PPF, an input sensing unit ISP, an anti-reflective layer RPL, a window WIN, a first adhesive layer AL1, a second adhesive layer AL2, a third adhesive layer AL3, a data driving unit DDV, a printed circuit board PCB, a timing controller T-CON, and a cover strip CTP.

[0089] The panel protective film PPF can be configured under the display panel DP. The panel protective film PPF can contain a flexible plastic material. For example, the panel protective film PPF can contain polyethylene terephthalate (PET).

[0090] The panel protective film PPF can define an opening OP that overlaps with the curved area BA. For example, the panel protective film PPF can be disposed under the first area AA1 and the second area AA2, but not under the curved area BA.

[0091] A first adhesive layer AL1 can be disposed between the display panel DP and the panel protective film PPF. The first adhesive layer AL1 can be disposed under the first region AA1 and the second region AA2, but not under the bending region BA. The display panel DP and the panel protective film PPF can be bonded to each other through the first adhesive layer AL1.

[0092] The pixel layer PXL can be disposed on the substrate SUB. The pixel layer PXL can be disposed in the first region AA1 of the display panel DP. The pixel layer PXL can overlap the display region DA. In the first region AA1, a thin film encapsulation layer TFE can be disposed on the pixel layer PXL.

[0093] The input sensing unit ISP can be disposed on the display panel DP. The input sensing unit ISP can be directly disposed on the first region AA1 of the display panel DP. The input sensing unit ISP can also be directly manufactured on the thin-film encapsulation layer TFE during the manufacturing of the display device DD. However, it is not limited to this; the input sensing unit ISP can also be manufactured as a panel separate from the display panel DP, attached to the display panel DP via an adhesive layer.

[0094] The input sensing unit (ISP) can sense external inputs such as user touch and convert them into input signals, which are then provided to the display panel (DP). The ISP may include multiple sensing units (not shown) for sensing external inputs. These sensing units can sense external inputs capacitively. The display panel (DP) can receive the input signals from the ISP and generate an image corresponding to the input signals.

[0095] An anti-reflective layer RPL can be disposed on the input sensing unit ISP. The anti-reflective layer RPL reduces the reflectivity of external light incident from the display device DD toward the display panel DP. For example, the anti-reflective layer RPL may include a polarizing film capable of reducing the reflectivity of external light, the polarizing film including a phase retarder and / or a polarizer. The anti-reflective layer RPL can be defined as a polarizing layer.

[0096] A second adhesive layer AL2 can be disposed between the anti-reflective layer RPL and the input sensing unit ISP. The anti-reflective layer RPL and the input sensing unit ISP can be bonded to each other through the second adhesive layer AL2.

[0097] A window WIN can be configured on the anti-reflective layer RPL. The window WIN can be made of plastic or glass. The window WIN can protect the display panel DP, the input sensor ISP, and the anti-reflective layer RPL from external scratches and impacts. The window WIN can be configured on the first area AA1 and the curved area BA.

[0098] A third adhesive layer AL3 can be configured between the window WIN and the anti-reflective layer RPL. The window WIN and the anti-reflective layer RPL can be bonded to each other through the third adhesive layer AL3.

[0099] The first adhesive layer AL1 to the third adhesive layer AL3 may include transparent adhesive layers such as pressure-sensitive adhesive (PSA) or optically clear adhesive (OCA).

[0100] An anti-reflective layer RPL can be disposed on the first region AA1, the curved region BA, and the second region AA2. The anti-reflective layer RPL can be disposed on the first region AA1 between the input sensing unit ISP and the window WIN, and extend on the curved region BA and the second region AA2. The anti-reflective layer RPL can extend to a portion of the second region AA2 adjacent to the curved region BA.

[0101] The second adhesive layer AL2 can be disposed on the first region AA1 between the input sensing unit ISP and the anti-reflective layer RPL, and extend towards the curved region BA and the second region AA2. The second adhesive layer AL2 can be disposed between the anti-reflective layer RPL and the curved region BA, and between the anti-reflective layer RPL and the second region AA2. The anti-reflective layer RPL can be attached to the curved region BA and the second region AA2 through the second adhesive layer AL2.

[0102] Although not illustrated, lines can be arranged on the substrate SUB within the curved region BA. These lines may include the aforementioned data lines DL1-DLn, the first control line CSL1, the second control line CSL2, the first power line PL1, and the second power line PL2. The lines can extend from the pixel layer PXL through the curved region BA to the second region AA2.

[0103] The anti-reflective layer RPL can be configured on the line in the bending region BA and the second region AA2 to protect the line. The anti-reflective layer RPL supplements the rigidity of the bending region BA, preventing cracking when the bending region BA is bent. The anti-reflective layer RPL protects the bending region BA from external impacts.

[0104] The data drive unit (DDV) can be configured on the second region AA2. The data drive unit (DDV) can be configured separately from the anti-reflective layer (RPL). A printed circuit board (PCB) can be configured on one side of the second region AA2. The timing controller (T-CON) can be configured on the PCB. The data drive unit (DDV) can be configured on the second region AA2 between the PCB and the anti-reflective layer (RPL).

[0105] The cover tape CTP can be disposed on the second region AA2 to cover the data drive unit DDV. The cover tape CTP can be disposed on a portion of the printed circuit board (PCB) disposed on the second region AA2. The cover tape CTP can be disposed on a portion of the anti-reflective layer RPL disposed on the second region AA2. The cover tape CTP may include an insulating tape containing organic materials.

[0106] The first alignment mark AMK1 can be defined in the first region AA1. The second alignment mark AMK2 can be defined in the anti-reflective layer RPL. The second alignment mark AMK2 can also be defined in a portion of the anti-reflective layer RPL disposed on the second region AA2. Therefore, when viewed in a plane, the second alignment mark AMK2 can overlap the second region AA2.

[0107] The first alignment mark AMK1 and the second alignment mark AMK2 may be adjacent to the curved region BA. The curved region BA may be configured between the first alignment mark AMK1 and the second alignment mark AMK2.

[0108] The first alignment mark AMK1 can be configured with... Figure 3 The transistor TR shown is on the same layer as the conductive pattern. The conductive pattern may include a metal pattern forming the gate G and a semiconductor pattern forming the source S and drain D. However, it is not limited thereto; the first alignment mark AMK1 may also be disposed on the same layer as the metal pattern forming the connection electrode CNE. The first alignment mark AMK1 may be formed by simultaneously patterning with the conductive pattern using the same material.

[0109] Reference Figure 4 as well as Figure 5 The second alignment mark AMK2 can be defined on the top of the anti-reflective layer RPL. For example, the second alignment mark AMK2 can be formed by recessing the upper portion of the anti-reflective layer RPL downwards to a predetermined depth. That is, the second alignment mark AMK2 can be formed by intaglio engraving. However, this is illustrative, and the second alignment mark AMK2 can also be formed on the anti-reflective layer RPL by relief engraving.

[0110] Reference Figure 6 The anti-reflective layer RPL may include a polarizing film PFM that reduces the reflectivity of external light and a hard coating HC disposed on the polarizing film PFM. The hard coating HC defines the upper part of the anti-reflective layer RPL. The polarizing film PFM may include a phase retarder and / or a polarizer to reduce the reflectivity of external light. The hard coating HC protects the polarizing film PFM from external scratches and impacts.

[0111] The second alignment mark AMK2 can be defined on the hard coating HC. The second alignment mark AMK2 can be defined by removing a predetermined portion of the hard coating HC.

[0112] The functions of the first alignment mark AMK1 and the second alignment mark AMK2 are explained in detail below.

[0113] Figure 7 It is shown on a plane. Figure 4 The diagram shows a first alignment mark defined on the display panel and a second alignment mark defined on the anti-reflective layer.

[0114] Reference Figure 7 The first alignment mark AMK1 may have a different shape than the second alignment mark AMK2. For example, the first alignment mark AMK1 may have a triangular or groove shape, but its shape is not limited to these. Similarly, the second alignment mark AMK2 may have an "L" shape or a cross shape, but its shape is not limited to these.

[0115] When viewed in a flat plane, the cover tape CTP may not overlap with the second alignment mark AMK2. The cover tape CTP may protrude toward the curved area BA. The protrusion PRT of the cover tape CTP protruding toward the curved area BA may be positioned between the second alignment marks AMK2 without overlapping them.

[0116] The first alignment mark AMK1 and the second alignment mark AMK2 can be configured to be adjacent to the curved region BA, with the curved region BA positioned in the middle. The first alignment mark AMK1 can be configured adjacent to both sides of the first region AA1, which is opposite to each other in the second direction DR2, but the configuration position of the first alignment mark AMK1 is not limited to this. The second alignment mark AMK2 can be configured adjacent to both sides of the second region AA2, which is opposite to each other in the second direction DR2, but the configuration position of the second alignment mark AMK2 is not limited to this.

[0117] Figure 8 It is shown Figure 4 The diagram shows the bending state of the bending region. Figure 9 Observing on a plane Figure 8 The diagram shows the curved region and the second region.

[0118] Illustratively, Figure 9 This is shown as a view upwards from below the display device DD. That is, Figure 9 The image shows the state behind the display panel DP, where the second area AA2 is configured. Additionally, in... Figure 9 The printed circuit board (PCB) and the timing controller (T-CON) are omitted.

[0119] Reference Figure 8 The curved region BA can be bent into a second region AA2 disposed below the first region AA1. Therefore, the data driver unit DDV can be disposed below the first region AA1.

[0120] The bending region BA can be bent into an outward protrusion towards the display panel DP. The bending region BA can be bent into a predetermined curvature. The data drive unit DDV can... Figure 8 It is configured under the second region AA2.

[0121] Reference Figure 9 Alternatively, the second region AA2 can be positioned below the first region AA1, and when viewed in a plane, the second alignment mark AMK2 can be adjacent to the first alignment mark AMK1. The first alignment mark AMK1 and the second alignment mark AMK2 can be aligned in the second direction DR2. When viewed in a plane, the first alignment mark AMK1 can be adjacent to the two sides of the second region AA2 that are opposite to each other in the second direction DR2.

[0122] The first alignment mark AMK1 and the second alignment mark AMK2 can be aligned such that the curved region BA has a predetermined curvature. For example, the curved region BA is curved, and when viewed in a plane, the first alignment mark AMK1 and the second alignment mark AMK2 can be aligned with horizontal lines HL1, HL2 parallel to the second direction DR2. In such a case, when viewed from the second direction DR2, the first alignment mark AMK1 and the second alignment mark AMK2 can overlap each other with the horizontal lines HL1, HL2 as the center.

[0123] When viewed in a plane, the second alignment mark AMK2 can be aligned with the first alignment mark AMK1, spaced apart by a predetermined distance DT in the second direction DR2. In this case, the two sides of the second region AA2 extending towards the first direction DR1 can be configured parallel to the first direction DR1 without distortion. As described above, when the first alignment mark AMK1 and the second alignment mark AMK2 are aligned with each other, the curved region BA can be curved to have a desired curvature.

[0124] When the first alignment mark AMK1 and the second alignment mark AMK2 are not aligned with the horizontal lines HL1 and HL2, the second alignment mark AMK2 may be configured in a position that is more aligned than the horizontal lines HL1 and HL2. Figure 7 The location shown is further to the right. In such a case, the curved region BA is more curved, and the curved region BA may not be curved to the desired curvature.

[0125] When the first alignment mark AMK1 and the second alignment mark AMK2 are not aligned with the horizontal lines HL1 and HL2, the second alignment mark AMK2 may be configured in a position that is more aligned than the horizontal lines HL1 and HL2.Figure 7 The position shown is further to the left. In such a case, the curved region BA is bent less, and the curved region BA may not be bent to the desired curvature.

[0126] When the second alignment mark AMK2 is not separated from the first alignment mark AMK1 by a predetermined distance DT in the second direction DR2, the two sides of the second region AA2 extending towards the first direction DR1 may be configured to be twisted relative to the first direction DR1. Therefore, the curved region BA may not be curved to have the desired curvature.

[0127] In an embodiment of the invention, when the curved region BA is bent, the first alignment mark AMK1 defined in the display panel DP and the second alignment mark AMK2 defined in the anti-reflective layer RPL are aligned with each other, and the curved region BA can be bent to have a desired curvature.

[0128] Figures 10 to 15 This is a diagram illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0129] Reference Figure 10 A display panel DP, defined by a first alignment mark AMK1, can be prepared. An anti-reflective layer RPL can be provided on the display panel DP, the RPL being disposed on a first region AA1 and extending towards a curved region BA and a second region AA2. A panel protective film PPF, defining an opening OP, can be provided beneath the display panel DP.

[0130] Reference Figure 11 A data drive unit (DDV) can be provided on the second area AA2. Additionally, a printed circuit board (PCB) with a timing controller (T-CON) mounted on it can be provided on the second area AA2.

[0131] Reference Figure 12 as well as Figure 13 When viewed on a plane, a laser beam (LAR) can be shone onto the portion of the antireflective layer RPL that overlaps with the second region AA2. The laser beam (LAR) can shine from above the antireflective layer RPL towards the top of the antireflective layer RPL.

[0132] The second alignment mark AMK2 can be defined on the antireflective layer RPL by using a laser beam LAR. For example, the second alignment mark AMK2 can be defined on the hard coating HC by removing a predetermined portion of the hard coating HC by using a laser beam LAR. Therefore, the second alignment mark AMK2 can be defined on top of the antireflective layer RPL.

[0133] Reference Figure 14Alternatively, a window WIN can be provided on the anti-reflective layer RPL, and a cover strip CTP can be provided on the second region AA2. The window WIN can be attached to the anti-reflective layer RPL via a third adhesive layer AL3. The cover strip CTP can be configured on the second region AA2 on both the data drive unit DDV and the anti-reflective layer RPL.

[0134] Reference Figure 15 The curved region BA can be bent into a second region AA2 positioned below the first region AA1. When the curved region BA is bent, the second alignment mark AMK2 can be aligned with the first alignment mark AMK1. The alignment method of the first alignment mark AMK1 and the second alignment mark AMK2 is as described above.

[0135] During the bending process of the bending region BA, the second alignment mark AMK2 and the first alignment mark AMK1 can be aligned with each other while viewed from below the display device DD. The second alignment mark AMK2 may not be defined in the anti-reflective layer RPL, but rather in the second region AA2 of the display panel DP disposed above the anti-reflective layer RPL. When viewed from below the display device DD, the second alignment mark defined in the second region AA2 of the display panel DP can be obscured by the anti-reflective layer RPL and is not visible from the outside.

[0136] Reference Figure 9 as well as Figure 15 In an embodiment of the present invention, the second alignment mark AMK2 is defined in the anti-reflective layer RPL, so that the second alignment mark AMK2 can be easily seen from the outside when viewed from below the display device DD.

[0137] When viewed from below the display device DD upwards, the first alignment mark AMK1 is as follows: Figure 9 As shown, it is not obscured by the anti-reflective layer RPL and is therefore easily visible. Therefore, during the bending process in the bending region BA, the second alignment mark AMK2 can be easily aligned with the first alignment mark AMK1.

[0138] Figure 16 This is a diagram illustrating the first and second alignment marks according to another embodiment of the present invention.

[0139] Illustratively, Figure 16 Shown as with Figure 7 The corresponding floor plan.

[0140] Reference Figure 16 ,and Figure 7Unlike the first alignment mark AMK1 and the second alignment mark AMK2 shown, the first alignment mark AMK1_1 can have the same shape as the second alignment mark AMK2_1. Example, the first alignment mark AMK1_1, arranged adjacent to both sides of the first region AA1 opposite to each other in the second direction DR2, can have a symmetrical shape. Similarly, the second alignment mark AMK2_1, arranged adjacent to both sides of the second region AA2 opposite to each other in the second direction DR2, can have a symmetrical shape.

[0141] The above description, with reference to embodiments, demonstrates that those skilled in the art will understand that various modifications and alterations can be made to the present invention without departing from the concept and scope of the invention as set forth in the claims. Furthermore, the embodiments disclosed herein are not intended to limit the technical concept of the invention; rather, it should be understood that all technical concepts within the scope of the claims and their equivalents are included within the scope of the claims.

Claims

1. A display device, wherein, include: Display panel; as well as An anti-reflective layer is disposed on the display panel. The display panel includes: The first region is defined by the first alignment mark; A curved region extending from the first region; and The second region extends from the curved region. The anti-reflective layer extends from the first region to the curved region and the second region, overlapping with the first region, the curved region, and the second region. When viewed on a plane, the second alignment mark defined in the anti-reflective layer overlaps with the second region.

2. The display device according to claim 1, wherein, The second alignment mark is defined on the top of the antireflective layer. The first alignment mark and the second alignment mark are adjacent to the curved region. The first alignment mark has a different shape than the second alignment mark.

3. The display device according to claim 1, wherein, The anti-reflective layer includes: Polarizing film; and A hard coating is disposed on the polarizing film. The second alignment mark is defined within the hard coating.

4. The display device according to claim 1, wherein, The first region includes: Display area, including pixels; and The non-display area is located around the display area. The first alignment mark is defined in the non-display area.

5. The display device according to claim 4, wherein, The pixels include: transistors; and The light-emitting element is connected to the transistor. The first alignment mark is disposed on the same layer as the conductive pattern of the transistor. The first alignment mark and the conductive pattern are simultaneously patterned using the same material.

6. The display device according to claim 1, wherein, The display device further includes: The driver IC is disposed on the second region, spaced apart from the antireflective layer; and A cover strip is disposed on the second region to cover the driver IC. The cover strip is disposed on the antireflective layer disposed on the second region. When viewed on the plane, the cover strip does not overlap with the second alignment mark.

7. The display device according to claim 1, wherein, The first region, the curved region, and the second region are arranged in a first direction, and the curved region extends in a second direction that intersects the first direction.

8. The display device according to claim 7, wherein, The first alignment mark is provided in multiple forms, and the multiple first alignment marks are arranged adjacent to the two sides of the first region that are opposite to each other in the second direction. The second alignment mark is provided as a plurality of such marks, which are arranged adjacent to the two sides of the second region that are opposite to each other in the second direction.

9. The display device according to claim 7, wherein, The curved region is curved, and the second region is positioned below the first region. When viewed on the plane, the second alignment mark is adjacent to the first alignment mark. When viewed on the plane, the first alignment mark and the second alignment mark are aligned with a horizontal line parallel to the second direction, and the second alignment mark is spaced a predetermined distance from the first alignment mark in the second direction.

10. The display device according to claim 1, wherein, The display device further includes: A panel protective film is disposed under the display panel and defines an opening that overlaps with the curved area; The input sensing unit is directly disposed on the first region; and A window is configured on the input sensing unit. The anti-reflective layer is disposed on the first region between the input sensing unit and the window and extends onto the curved region and the second region.

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