Light emitting diode package and display device including the same

Abstract

A light emitting diode (LED) package includes: a first LED pixel, which includes a plurality of first LED chips; and a first pixel driver integrated circuit, which is used to drive the first LED chips according to an active matrix (AM) mode using an entire first frame period, wherein the first pixel driver integrated circuit includes: a first storage area, which is configured to store first frame data of each first LED chip; a second storage area, which is configured to store duty cycle compensation data of each first LED chip; a pulse width modulation (PWM) data calculator, which is configured to perform arithmetic operations on the first frame data and the duty cycle compensation data to generate PWM data; and a PWM data generator, which is configured to adjust the emission duty cycle based on the PWM data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0076757 filed on June 23, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Methods, devices, and systems consistent with example embodiments relate to a light emitting diode (LED) package and a display device including the LED package, and more particularly, to an LED package including a pixel driving integrated circuit and a display device including the LED package. Background Art

[0004] In addition to being used as a light source for lighting devices, LEDs are also used as light sources for various electronic products. In particular, LEDs are widely used as light sources for various display devices included in televisions (TVs), mobile phones, personal computers (PCs), notebook PCs, tablet PCs, wearable devices, electronic signs, and the like.

[0005] In the prior art, a display device including a liquid crystal display panel and a backlight has been used. However, recently, an LED display including three small LED chips constituting one pixel has been proposed. LED displays do not require a separate backlight, so compared with liquid crystal display (LCD) devices, LED displays are easy to highly integrate and have better light efficiency. In addition, by changing the arrangement of the LED chips, the aspect ratio of the screen can be freely selected and a large area screen can be implemented, thereby providing various types of display devices. Summary of the Invention

[0006] Example embodiments provide a light emitting diode (LED) package and a display apparatus including the same, in which reliability of operation is improved even when a low-brightness operation is performed and brightness non-uniformity is prevented, thereby achieving excellent screen quality.

[0007] According to one aspect of an exemplary embodiment, an LED package includes: a first LED pixel including a plurality of first LED chips; and a first pixel driver integrated circuit configured to drive the plurality of first LED chips according to an active matrix (AM) mode using an entire first frame period. The first pixel driver integrated circuit includes: a first storage area configured to store first frame data for each of the plurality of first LED chips; a second storage area configured to store duty cycle compensation data for each of the plurality of first LED chips; a pulse width modulation (PWM) data calculator configured to perform an arithmetic operation on the first frame data provided from the first storage area and the duty cycle compensation data provided from the second storage area to generate PWM data; and a PWM data generator configured to adjust an emission duty cycle based on the PWM data.

[0008] According to one aspect of another exemplary embodiment, an LED package includes: a first LED pixel including a plurality of first LED chips; a first pixel driver integrated circuit configured to drive the plurality of first LED chips based on an AM PWM mode, the AM PWM mode controlling the time when a driving current is applied to the plurality of first LED chips in a first frame period; and a package substrate on which the plurality of first LED chips and the first pixel driver integrated circuit are disposed. The first pixel driver integrated circuit includes: a deserializer configured to receive serial data from an external controller, extract and store first frame data of each of the plurality of first LED chips from the serial data, and provide the first frame data; a first storage area configured to store the first frame data provided from the deserializer; a second storage area configured to store duty cycle compensation data for each of the plurality of first LED chips; a PWM data calculator configured to perform an arithmetic operation on the first frame data provided from the first storage area and the duty cycle compensation data provided from the second storage area to generate PWM data; and a constant current generator configured to generate a constant current based on a power supply voltage. a reference current; a PWM data generator configured to generate a plurality of first driving currents applied to the plurality of first LED chips based on a clock signal, a PWM clock signal, the PWM data provided from the PWM data calculator, and the reference current provided from the constant current generator; a data input pad configured to receive the serial data; a data output pad configured to output data other than the first frame data in the serial data; a power supply pad configured to receive the power supply voltage; a first clock pad configured to receive the clock signal; a second clock pad configured to receive the PWM clock signal; and a ground pad connected to the plurality of first LED chips.

[0009] According to one aspect of another exemplary embodiment, a display device includes: a printed circuit board; a plurality of light emitting diode (LED) packages disposed on a first surface of the printed circuit board; and a controller disposed on a second surface of the printed circuit board opposite to the first surface, the controller being configured to control driving of the plurality of LED packages. Each of the plurality of LED packages includes: a first LED pixel including a plurality of first LED chips; and a first pixel driver integrated circuit configured to drive the plurality of first LED chips based on an active matrix (AM) mode using an entire first frame period. The first pixel driver integrated circuit includes: a first storage area configured to store first frame data for each of the plurality of first LED chips; a second storage area configured to store duty cycle compensation data for each of the plurality of first LED chips; a pulse width modulation (PWM) data calculator configured to perform an arithmetic operation on the first frame data provided from the first storage area and the duty cycle compensation data provided from the second storage area to generate PWM data; and a PWM data generator configured to adjust an emission duty cycle based on the PWM data. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features will become more apparent from the following description of example embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1 is a perspective view illustrating a light emitting diode (LED) package according to example embodiments;

[0012] Figure 2 is used to describe Figure 1 A circuit diagram of a pixel driver integrated circuit;

[0013] Figures 3 to 5 、 Figure 6A 、 Figure 6B 、 Figure 6C and Figure 6D is used to describe Figure 2 A diagram illustrating the operation of a pixel driver integrated circuit;

[0014] Figure 7 is a circuit diagram for describing a pixel driving integrated circuit according to an example embodiment;

[0015] Figure 8 is a circuit diagram for describing a pixel driving integrated circuit according to an example embodiment;

[0016] Figure 9 is a circuit diagram for describing a pixel driving integrated circuit according to an example embodiment;

[0017] Figure 10 is a circuit diagram for describing a pixel driving integrated circuit according to an example embodiment;

[0018] Figure 11 is a perspective view showing an LED package according to an example embodiment;

[0019] Figure 12 is a perspective view showing an LED package according to an example embodiment;

[0020] Figure 13 is a perspective view showing an LED package according to an example embodiment;

[0021] Figure 14 is a perspective view for describing a display device according to an example embodiment;

[0022] Figure 15 It shows Figure 14 an enlarged plan view of a region CX1; and

[0023] Figure 16 yes Figure 14 A cross-sectional view of a display device. DETAILED DESCRIPTION

[0024] Figure 1 is a perspective view illustrating a light emitting diode (LED) package 1000 according to example embodiments.

[0025] Reference Figure 1 , the LED package 1000 may include an LED pixel and a pixel driver integrated circuit 300. The LED pixel may include a plurality of LED chips 200 mounted on the pixel driver integrated circuit 300, and the LED chips 200 and the pixel driver integrated circuit 300 may be mounted on the package substrate 100. External connection terminals 400 such as solder or bumps may be connected to the lower portion of the package substrate 100, and a sealing member 500 covering the LED chips 200 and the pixel driver integrated circuit 300 may also be provided.

[0026] In some example embodiments, the LED chip 200 may include first to third LED chips 210 to 230 disposed on the pixel driver integrated circuit 300, and the first to third LED chips 210 to 230 may emit light having different colors. For example, the first LED chip 210 may emit red light, the second LED chip 220 may emit green light, and the third LED chip 230 may emit blue light. In this case, the LED package 1000 may be a red, blue, and green (RGB) package for full color.

[0027] In some example embodiments, the first to third LED chips 210 to 230 may emit light of the same color. For example, each of the first to third LED chips 210 to 230 may be an LED chip emitting white light. In this case, the LED package 1000 may be a multi-white package for vivid colors.

[0028] In some other example embodiments, the color of light emitted from the first to third LED chips 210 to 230 may further include at least one of various colors (eg, cyan, yellow, and magenta).

[0029] The LED chip 200 may be disposed on a top surface of the pixel driving integrated circuit 300 , and thus, light emitted from the LED chip 200 may not be blocked by the pixel driving integrated circuit 300 .

[0030] The pixel driver integrated circuit 300 can be disposed below the LED chip 200 and can drive the LED chip 200 based on an active matrix (AM) mode. Here, the AM mode refers to an addressing method applied to a flat panel display device. In a display device driven based on the AM mode, each pixel may include a storage element (e.g., a capacitor) for driving the corresponding pixel and a transistor programmable for each signal. The pixels included in one scan line can be programmed in a specific time (frame time / number of scan lines) based on an external signal. Moreover, the capacitor included in each pixel can maintain the voltage of the corresponding pixel, and therefore, each pixel can continuously emit light at other times of the frame. In the process of displaying a moving image by using a display device, the motion can be cut at specific time intervals and can be displayed continuously, and in this case, the time interval corresponding to one scene can be referred to as a frame time.

[0031] The pixel driver integrated circuit 300 can drive the LED chip 200 based on a multi-mode pulse width modulation (PWM) mode. The pixel driver integrated circuit 300 can adjust the pulse width (i.e., the application time of the driving current) of the driving current flowing through the LED chip 200 during one frame period to control the brightness of the LED chip 200.

[0032] The pixel driver integrated circuit 300 can drive the LED chips 200 by performing a duty cycle compensation operation that compensates for the brightness characteristics of each LED chip 200. For example, the duty cycle compensation operation can be performed using one of a first mode and a second mode. The first mode can be a mode for performing a multiplication operation on the first frame data of each LED chip 200 and the duty cycle compensation data of each LED chip 200, and the second mode can be a mode for performing an addition operation on the first frame data of each LED chip 200 and the duty cycle compensation data of each LED chip 200.

[0033] In an example embodiment, a duty cycle compensation operation may be performed by using one of a first mode and a second mode based on duty cycle compensation data obtained according to the brightness characteristic value of each LED chip 200. For example, when one of the LED chips 200 has a brightness lower than the target brightness, the duty cycle compensation data may include duty cycle compensation information for the first mode (i.e., multiplication operation). When one of the LED chips 200 has a low brightness of low grayscale or has an abnormal turn-on problem such as flickering, the duty cycle compensation data may include duty cycle compensation information for the second mode (i.e., addition operation). 6A to 6D A method of calculating duty ratio compensation data based on the brightness characteristic value of each LED chip 200 is described in detail.

[0034] In an example embodiment, the duty cycle compensation operation may be performed on all of the first to third LED chips 210 to 230 by using the first mode. In other example embodiments, the duty cycle compensation operation may be performed on all of the first to second LED chips 210 and 220 by using the first mode, and the duty cycle compensation operation may be performed on the third LED chip 230 by using the second mode. In other example embodiments, the duty cycle compensation operation may be performed on all of the first to third LED chips 210 and 230 by using the first mode, and the duty cycle compensation operation may be performed on the second LED chip 220 by using the second mode. Figures 3 to 5 and 6A to 6D A driving method based on the duty ratio compensation operation of the pixel driving integrated circuit 300 is described in detail.

[0035] The pixel driver integrated circuit 300 may be electrically connected to the package substrate 100 on the package substrate 100. For example, various wiring structures including through silicon vias (TSVs) may be provided in the pixel driver integrated circuit 300. The pixel driver integrated circuit 300 may be configured to be electrically connected to the package substrate 100 through connection terminals such as solder or conductive bumps. The pixel driver integrated circuit 300 may include a plurality of pads for connecting the package substrate 100 to the pixel driver integrated circuit 300. The plurality of pads may be provided on the bottom surface of the pixel driver integrated circuit 300. The plurality of pads may include a data input pad 311 (see Figure 2 ), data output pad 312 (see Figure 2 ), power supply pad 313 (see Figure 2 ), multiple clock pads 314 and 315 (see Figure 2 ), and ground pad 316 (see Figure 2 ).

[0036] exist Figure 1 In an exemplary embodiment, the LED chip 200 may be implemented as a flip chip type. Specifically, the LED chip 200 may be connected to the pixel driver integrated circuit 300 via at least one electrode. Furthermore, the pixel driver integrated circuit 300 below the LED chip 200 may include at least one pad for electrically connecting to the LED chip 200. The LED chip 200 may be electrically connected to the pixel driver integrated circuit 300 via a conductive adhesive material such as a eutectic metal, paste, or solder.

[0037] The LED chip 200 and the pixel driving integrated circuit 300 may be mounted on the package substrate 100 and may be connected to the external printed circuit board (PCB) 1300 (see FIG. Figure 16 ) and external controller 1400 (see Figure 16 ) communication.

[0038] The package substrate 100 may include a plurality of pads for electrical connection to the pixel driver integrated circuit 300. The plurality of pads of the package substrate 100 may include data input pads, clock pads, power pads, data output pads, and ground pads, and may be disposed between the package substrate 100 and the pixel driver integrated circuit 300 so as not to be exposed. An adhesive member such as epoxy resin, silicone resin, acrylate, or solder paste may be disposed between the pixel driver integrated circuit 300 and the package substrate 100 to secure the plurality of pads therebetween.

[0039] The LED chip 200 and the pixel driver integrated circuit 300 can be fixed on the package substrate 100 by a light-transmitting sealing member 500. The sealing member 500 can include epoxy resin and silicone resin. The sealing member 500 can also include a filler, such as fused quartz or carbon black.

[0040] According to example embodiments, the pixel driver integrated circuit 300 may perform a duty cycle compensation operation by multiplication or addition based on the brightness characteristic value of each of the first to third LED chips 210 to 230. Therefore, even when the first to third LED chips 210 to 230 have different brightness characteristic values, light having uniform brightness may be emitted from the LED package 1000. In other words, in terms of binning of the LED chips 200, even when the LED package 1000 is manufactured by using LED chips 200 having relatively large brightness deviations, the LED package 1000 may emit light having good quality (or uniform brightness), thereby reducing the manufacturing cost of the LED package 1000. Furthermore, the LED package 1000 may enable a display device to display an image in which brightness deviations are compensated in grayscale. Therefore, the LED package 1000 may improve image quality and may prevent flickering at low grayscales, thereby increasing the reliability of the operation of the display device including the LED package 1000.

[0041] Figure 2 is used to describe Figure 1 1 is a circuit diagram of a pixel driving integrated circuit 300.

[0042] Reference Figure 2 The pixel driving integrated circuit 300 may include a plurality of pads 311 to 316 , a deserializer 320 , a first storage area 330 , a second storage area 340 , a PWM data calculator 350 , a constant current generator 360 , and a PWM data generator 370 .

[0043] The deserializer 320 can receive data from the external controller 1400 (see Figure 16 ) receives the serial data SDAT, extracts and stores the first frame data of the LED chip 200 from the serial data SDAT, and distributes and outputs the frame data.

[0044] In some example embodiments, the first frame data may include a plurality of pieces of frame data DFR1, DFR2, and DFR3 of the LED chip 200, and control data CONT for controlling the PWM data generator 370. The control data CONT may include command and clock matching data. For example, the plurality of pieces of frame data DFR1, DFR2, and DFR3 may include grayscale data of an image signal and may further include additional grayscale data for correcting undesirable low efficiency and / or wavelength shift of a particular pixel.

[0045] The deserializer 320 can output the serial data SDAT' except the frame data corresponding to the corresponding pixel driving integrated circuit 300 in the serial data SDAT without separate processing. The serial data SDAT' can be output through the data output pad 312 and can be provided to the subsequent LED package (for example, the LED package of the next scan line). In the display device 2000 (see Figure 14 ), a plurality of LED packages may be serially connected to each other, and serial data SDAT corresponding to one frame period may include a plurality of pieces of frame data of the plurality of LED packages.

[0046] For example, the LED packages of the first scan line can obtain only their frame data and output other data to the LED packages of the second scan line, and the LED packages of the second scan line can obtain only their frame data and output other data to the LED packages of the third scan line. In this way, the LED packages of the first to last scan lines can each obtain their frame data.

[0047] The first storage area 330 may store a plurality of pieces of frame data DFR1, DFR2, and DFR3, which are data for respectively driving the first to third LED chips 210 to 230. The first storage area 330 may store the plurality of pieces of frame data DFR1, DFR2, and DFR3 provided from the deserializer 320, and may output the plurality of pieces of frame data DFR1, DFR2, and DFR3 to the PWM data calculator 350.

[0048] In example embodiments, the first storage area 330 may be implemented in the form of a latch, a register, or a buffer, and may include at least one of a volatile memory, such as a static random access memory (SRAM) and a dynamic random access memory (DRAM), and a non-volatile memory, such as an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano-floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), and a ferroelectric random access memory (FRAM).

[0049] The second storage area 340 may store a plurality of duty cycle compensation data DCC1, DCC2, and DCC3, each including a duty cycle compensation coefficient of the first to third LED chips 210 to 230, and may output the plurality of duty cycle compensation data DCC1, DCC2, and DCC3 to the PWM data calculator 350. The plurality of duty cycle compensation data DCC1, DCC2, and DCC3 may include duty cycle compensation coefficients a1, a2, and a3 calculated based on the brightness characteristic values ​​of the first to third LED chips 210 to 230, respectively (see FIG. Figure 4 In addition, the plurality of duty cycle compensation data DCC1, DCC2, and DCC3 may include information for determining a mode (eg, a first mode or a second mode) of a duty cycle compensation operation calculated based on the brightness characteristic values ​​of the first to third LED chips 210 to 230.

[0050] In example embodiments, the second storage area 340 may be implemented in the form of a latch, a register, or a buffer, and may include at least one of a volatile memory such as SRAM and DRAM and a nonvolatile memory such as EEPROM, flash memory, PRAM, RRAM, NFGM, PoRAM, MRAM, and FRAM.

[0051] The PWM data calculator 350 may perform a duty cycle compensation operation based on the plurality of pieces of frame data DFR1, DFR2, and DFR3 provided from the first storage area 330 and the plurality of pieces of duty cycle compensation data DCC1, DCC2, and DCC3 provided from the second storage area 340 to generate a plurality of pieces of PWM data DCP1, DCP2, and DCP3, and may output the plurality of pieces of PWM data DCP1, DCP2, and DCP3 to the PWM data generator 370.

[0052] In an example embodiment, the PWM data calculator 350 may include a first calculator 352 and a second calculator 354. The PWM data calculator 350 may perform a duty cycle compensation operation based on one of a first mode and a second mode. The first mode may be an operation mode in which a multiplication operation is performed on the plurality of pieces of frame data DFR1, DFR2, and DFR3 provided from the first storage area 330 and the plurality of pieces of duty cycle compensation data DCC1, DCC2, and DCC3 provided from the second storage area 340. The first mode may be performed by the first calculator 352, which may include a shifter for the multiplication operation. The second mode may be an operation mode in which an addition operation is performed on the plurality of pieces of frame data DFR1, DFR2, and DFR3 provided from the first storage area 330 and the plurality of pieces of duty cycle compensation data DCC1, DCC2, and DCC3 provided from the second storage area 340. The second mode may be performed by the second calculator 354, which may include an adder for the addition operation.

[0053] For example, the plurality of duty cycle compensation data DCC1, DCC2, and DCC3 provided from the second storage area 340 to the PWM data calculator 350 may include k bits (where k is a natural number of 4 or greater) of data. The plurality of duty cycle compensation data DCC1, DCC2, and DCC3 may include 1 bit of data for selecting a mode from the first mode and the second mode and k-1 bits of data indicating a duty cycle compensation coefficient based on the brightness characteristic value of the LED chip 200. Here, the 1 bit of data for selecting a mode from the first mode and the second mode may be referred to as a mode selection bit MDS (see Figure 4 ).

[0054] For example, the duty cycle compensation data DCC1 for the first LED chip 210 may include a mode selection bit MDS (e.g., data “0”) indicating a first mode of duty cycle compensation operation, and in this case, the first calculator 352 of the PWM data calculator 350 may perform a multiplication operation on the frame data DFR1 provided from the first storage area 330 and the duty cycle compensation data DCC1 provided from the second storage area 340 to generate PWM data DCP1, and may output the PWM data DCP1 to the PWM data generator 370.

[0055] For example, the duty cycle compensation data DCC2 for the second LED chip 220 may include a mode selection bit MDS (e.g., data “1”) indicating a second mode of duty cycle compensation operation, and in this case, the second calculator 354 of the PWM data calculator 350 may perform an addition operation on the frame data DFR2 provided from the first storage area 330 and the duty cycle compensation data DCC2 provided from the second storage area 340 to generate PWM data DCP2, and may output the PWM data DCP2 to the PWM data generator 370.

[0056] The constant current generator 360 may receive the power supply voltage VDD through the power supply pad 313 and may generate a reference current based on the power supply voltage VDD. For example, the constant current generator 360 may include a current mirror.

[0057] The PWM data generator 370 can generate multiple driving currents DI1, DI2 and DI3 applied to the first LED chip 210 to the third LED chip 230 based on the following: the clock signal CLK received through the first clock pad 314, the PWM clock signal PCLK received through the second clock pad 315, the control data CONT provided from the deserializer 320, the multiple PWM data DCP1, DCP2 and DCP3 provided from the PWM data calculator 350, and the reference current provided from the constant current generator 360.

[0058] The driving currents DI1, DI2, and DI3 may be generated based on a PWM pattern. For example, the pulse width (e.g., the application time of the driving current DI1) applied to the first LED chip 210 may be adjusted based on the PWM data DCP1, the pulse width of the driving current DI2 applied to the second LED chip 220 may be adjusted based on the PWM data DCP2, and the pulse width of the driving current DI3 applied to the third LED chip 230 may be adjusted based on the PWM data DCP3.

[0059] For example, the clock signal CLK for driving the PWM data generator 370 may have a first frequency, and the PWM clock signal PCLK for modulating PWM may have a second frequency higher than the first frequency to precisely adjust the pulse widths of the driving currents DI1 , DI2 , and DI3 .

[0060] In some example embodiments, the unit emission time of each of the first to third LED chips 210 to 230 may be equal to or greater than the period of the PWM clock signal PCLK. In some example embodiments, the unit emission time of each of the first to third LED chips 210 to 230 may be N times (where N is an integer of 2 or greater) the period of the PWM clock signal PCLK. For example, the unit emission time of each of the first to third LED chips 210 to 230 may be a multiple of the period of the PWM clock signal PCLK.

[0061] Each of the first to third LED chips 210 to 230 may include an anode electrode receiving a corresponding one of the driving currents DI1, DI2, and DI3 from the PWM data generator 370 and a cathode electrode connected to a ground pad 316 providing a ground voltage GND.

[0062] Figures 3 to 5 and 6A to 6D is used to describe Figure 2 A diagram of the operation of a pixel driver integrated circuit.

[0063] Figure 3 is a timing diagram showing data D_STG1 stored in the first storage area 330 , data D_STG2 stored in the second storage area 340 , and data D_PDG stored in the PWM data generator 370 in one frame period of the pixel driving integrated circuit 300 .

[0064] Reference Figure 2 and Figure 3 , the pixel driving integrated circuit 300 can drive the first LED chip 210 to the third LED chip 230 in the AM mode that fully uses one frame period. The pixel driving integrated circuit 300 can perform a duty cycle compensation operation based on the data D_STG1 stored in the first storage area 330 and the data D_STG2 stored in the second storage area 340 in the first frame period FR1, the second frame period FR2, and the third frame period FR3 that are sequentially connected to each other to calculate the data D_PDG stored in the PWM data generator 370.

[0065] For example, the first to third frame periods FR1 , FR2 , and FR3 may each include an initial period FRI, a transmission period FRE, and a reset period FRS.

[0066] In the first frame period FR1, during the emission period FRE, the pixel driver integrated circuit 300 may receive and distribute the first frame data D_FR1, and the first storage area 330 may store the first frame data D_FR1. In addition, during the emission period FRE, the second storage area 340 may store the duty cycle compensation data DCC_FR1 for each of the first to third LED chips 210 to 230. During the first frame period FR1, the PWM data generator 370 may not generate a driving current, and therefore, the first to third LED chips 210 to 230 may not emit light. For example, the PWM data generator 370 may not generate the data D_PDG during the first frame period FR1.

[0067] In the second frame period FR2 after the first frame period FR1, during the initial period FRI, the first frame data D_FR1 stored in the first storage area 330 can be provided to the PWM data calculator 350, and the duty cycle compensation data DCC_FR1 stored in the second storage area 340 can be provided to the PWM data calculator 350. The PWM data calculator 350 can perform a duty cycle compensation operation on the first frame data D_FR1 and the duty cycle compensation data DCC_FR1 (for example, the first calculator 352 can perform a multiplication operation, or the second calculator 354 can perform an addition operation). Therefore, the PWM data generator 370 can generate a driving current DI_FR1 based on the result obtained by performing the duty cycle compensation operation. During the emission period FRE of the second frame period FR2, the first to third LED chips 210 to 230 can emit light based on the driving current DI_FR1.

[0068] In the second frame period FR2, during the emission period FRE, the pixel driver integrated circuit 300 may receive and distribute the second frame data D_FR2, and the first storage area 330 may store the second frame data D_FR2. In the third frame period FR3 following the second frame period FR2, during the initial period FRI, the PWM data calculator 350 may perform a duty cycle compensation operation (e.g., the first calculator 352 may perform a multiplication operation, or the second calculator 354 may perform an addition operation) on the second frame data D_FR2 stored in the first storage area 330 and the duty cycle compensation data DCC_FR2 stored in the second storage area 340. Thus, the PWM data generator 370 may generate a driving current DI_FR2 based on the result obtained by performing the duty cycle compensation operation. During the emission period FRE of the third frame period FR3, the first to third LED chips 210 to 230 may emit light based on the driving current DI_FR2. Likewise, during the emission period FRE of the third frame period FR3 , the pixel driving integrated circuit 300 may receive and distribute third frame data D_FR3 , the first storage area 330 may store the third frame data D_FR3 , and the second storage area 340 may store duty cycle compensation data DCC_FR3 .

[0069] Figure 4 is a diagram illustrating the configuration of each of a plurality of pieces of duty ratio compensation data DCC1 , DCC2 , and DCC3 .

[0070] Reference Figure 4 The plurality of duty cycle compensation data DCC1, DCC2, and DCC3 provided from the second storage area 340 to the PWM data calculator 350 may include k bits of data (where k is a natural number of 4 or greater). The plurality of duty cycle compensation data DCC1, DCC2, and DCC3 may include 1 bit of data for selecting a mode from the first mode and the second mode and k-1 bits of data including a duty cycle compensation coefficient based on the brightness characteristic value of the LED chip 200. Here, the 1 bit of data for selecting a mode from the first mode and the second mode may be referred to as a mode selection bit MDS.

[0071] like Figure 4 As shown, when the plurality of pieces of duty cycle compensation data DCC1, DCC2, and DCC3 include 5-bit data, each of the plurality of pieces of duty cycle compensation data DCC1, DCC2, and DCC3 may include 1-bit data corresponding to the mode selection bit MDS and 4-bit data corresponding to the duty cycle compensation coefficients a1, a2, and a3. However, the number of bits of the mode selection bit MDS is not limited to Figure 4The figure shows that the mode selection bit MDS can be implemented with 2 bits or more. In addition, the number of bits of the duty cycle compensation coefficients a1, a2 and a3 is not limited to Figure 4 , and the duty cycle compensation coefficients a1, a2, and a3 can each be implemented with fewer bits or more bits.

[0072] Figure 5 is a timing diagram illustrating a plurality of driving currents DI1 , DI2 , and DI3 applied to the first to third LED chips 210 to 230 .

[0073] Reference Figure 5 , the driving current DI1 applied to the first LED chip 210 may have a first level I1 and a first pulse width W1F, the driving current DI2 applied to the second LED chip 220 may have a second level I2 and a second pulse width W2F, and the driving current DI3 applied to the third LED chip 230 may have a third level I3 and a third pulse width W3F. As the width of the driving current increases, the LED chip 200 may emit light with a higher grayscale (or brightness).

[0074] The driving current DI1 applied to the first LED chip 210 may have a first level I1 and a first pulse width W1F, so that the first LED chip 210 may emit light during a first time period corresponding to the first pulse width W1F. For example, the first pulse width W1F may be a pulse width (application time) obtained by multiplying the first input pulse width W1I by the first duty cycle compensation coefficient a1. For example, the frame data DFR1 stored in the first storage area 330 may include information about the first input pulse width W1I, and the duty cycle compensation data DCC1 stored in the second storage area 340 may include information about the first duty cycle compensation coefficient a1 and information about the multiplication operation. When the first LED chip 210 has a brightness characteristic lower than the target brightness, the first duty cycle compensation coefficient a1 may have a value greater than 1. Therefore, the first LED chip 210 can emit light for a first period corresponding to the first pulse width W1F obtained by multiplying the first duty cycle compensation coefficient a1 of the first LED chip 210 and the first input pulse width W1I, and the first LED chip 210 can have a brightness corresponding to (or similar to) the target brightness. Since the first duty cycle compensation coefficient a1 has a value greater than 1, the first pulse width W1F can be wider than the first input pulse width W1I, and the first LED chip 210 can be compensated to have a relatively brighter brightness.

[0075] Similarly, the driving current DI2 applied to the second LED chip 220 may have a second level I2 and a second pulse width W2F, and thus the second LED chip 220 may emit light during a second time period corresponding to the second pulse width W2F. For example, the second pulse width W2F may be a pulse width (application time) obtained by performing an addition operation on the second input pulse width W2I and the second duty cycle compensation coefficient a2. For example, the frame data DFR2 stored in the first storage area 330 may include information about the second input pulse width W2I, and the duty cycle compensation data DCC2 stored in the second storage area 340 may include information about the second duty cycle compensation coefficient a2 and information about the addition operation. The second LED chip 220 may be configured such that when a flicker phenomenon such as unstable flicker occurs in the second LED chip 220 at low grayscale, duty cycle compensation is performed based on the second duty cycle compensation coefficient a2 and the addition operation. Therefore, the second LED chip 220 can emit light in a second time period corresponding to the second pulse width W2F obtained by performing an addition operation on the second duty cycle compensation coefficient a2 of the second LED chip 220 and the second input pulse width W2I, and the second LED chip 220 can have a brightness corresponding to (or similar to) the target brightness, and unstable flickering at low grayscales can be prevented. Since the second duty cycle compensation coefficient a2 is added to the second input pulse width W2I, the second pulse width W2F can be wider than the second input pulse width W2I, and the second LED chip 220 can be compensated to have a relatively brighter brightness.

[0076] Similarly, the driving current DI3 applied to the third LED chip 230 may have a third level I3 and a third pulse width W3F, and thus the third LED chip 230 may emit light during a third time period corresponding to the third pulse width W3F. For example, the third pulse width W3F may be a pulse width (application time) obtained by multiplying the third input pulse width W3I by the third duty cycle compensation coefficient a3. For example, the frame data DFR3 stored in the first storage area 330 may include information about the third input pulse width W3I, and the duty cycle compensation data DCC3 stored in the second storage area 340 may include information about the third duty cycle compensation coefficient a3 and information about the multiplication operation. When the third LED chip 230 has a brightness characteristic higher than the target brightness, the third duty cycle compensation coefficient a3 may have a value less than 1. Therefore, the third LED chip 230 can emit light in a third period corresponding to the third pulse width W3F obtained by multiplying the third duty cycle compensation coefficient a3 of the third LED chip 230 and the third input pulse width W3I, and the third LED chip 230 can have a brightness corresponding to (or similar to) the target brightness. Since the third duty cycle compensation coefficient a3 has a value less than 1, the third pulse width W3F can be narrower than the third input pulse width W3I, and the third LED chip 230 can be compensated to have a relatively darker brightness.

[0077] In an embodiment, the first level I1, the second level I2, and the third level I3 may be the same. Due to the process distribution and the wavelength difference between the emitted light, the first LED chip 210 to the third LED chip 230 may have different brightness characteristics with respect to the forward voltage Vf and the current, and may have different wavelength offsets. Therefore, it may be difficult to apply a PWM mode that controls the level of the current to adjust the grayscale, and when a PWM mode that controls the emission time to adjust the grayscale is applied in a state where the level of the current is fixed, the wavelength offset caused by the input current or problems such as distribution and low efficiency caused by low current can be prevented, and the emission efficiency can be improved. However, the example embodiment is not limited thereto, and in other example embodiments, the pixel driver integrated circuit 300 may further include a current regulator and may be configured so that at least one of the first level I1, the second level I2, and the third level I3 has a different value.

[0078] Figure 6A is a flowchart illustrating a method of determining duty cycle compensation data according to example embodiments. Figure 6B is used to describe Figure 6A Schematic diagram of the multiplication operation method. Figure 6C is used to describe Figure 6A Schematic diagram of the addition operation method. Figure 6D It is shown in Figure 6A Schematic diagram of duty cycle compensation data obtained in each operation. In detail, 6A to 6D An exemplary method of determining duty cycle compensation data for generating a plurality of duty cycle compensation data DCC1 , DCC2 and DCC3 for the first to third LED chips 210 to 230 stored in the second storage area 340 of the pixel driving integrated circuit 300 is schematically illustrated.

[0079] Reference 6A to 6D , in operation S110 , the LED chip 200 may be turned on with an initial duty cycle.

[0080] In operation S120, the brightness of light emitted from the LED chip 200 may be measured. A measured brightness LMk0 may be obtained for each LED chip 200. For example, measured brightness LM10, LM20, and LM30 of the first to third LED chips 210 to 230 may be obtained.

[0081] In an example embodiment, Figure 6B As shown, the measured brightness LMk0 of each LED chip 200 can be obtained by scanning the pulse width of the driving current applied to the LED chip 120 (or the application time of the driving current). For example, by gradually increasing the pulse width (or application time) of the driving current applied to the LED chip 200, the emission intensity of each pulse width can be measured.

[0082] In operation S130, a duty cycle multiplication compensation coefficient axk may be calculated based on a ratio of the target brightness LMT to the measured brightness LMk0 of each LED chip 200. For example, a first duty cycle multiplication compensation coefficient ax1, a second duty cycle multiplication compensation coefficient ax2, and a third duty cycle multiplication compensation coefficient ax3 may be calculated based on a ratio of the target brightness LMT to each of the measured brightnesses LM10, LM20, and LM30 of the first to third LED chips 210 to 230.

[0083] In an example embodiment, in the case where the brightness is measured by scanning the pulse width of the driving current applied to the LED chip 200, the duty ratio multiplication compensation coefficient axk may be calculated based on the following Equation 1:

[0084] axk=S_LMT / S_LMk0 (Equation 1)

[0085] In Equation 1, axk may represent a duty cycle multiplication compensation coefficient of the kth LED chip, S_LMk0 may represent a slope of measured brightness of the kth LED chip with respect to pulse width, and S_LMT may represent a slope of target brightness with respect to pulse width.

[0086] For example, when the slope S_LMk0 of the measured brightness LMk0 of each LED chip 200 is less than the slope S_LMT of the target brightness LMT, the duty ratio multiplication compensation coefficient axk may have a value greater than 1. When the slope S_LMk0 of the measured brightness LMk0 of each LED chip 200 is greater than the slope S_LMT of the target brightness LMT, the duty ratio multiplication compensation coefficient axk may have a value less than 1.

[0087] according to Figure 5 In the example embodiment shown in the timing diagram of FIG, the slope S_LM10 of the measured brightness LM10 of the first LED chip 210 may be less than the slope S_LMT of the target brightness LMT, and the first duty cycle multiplication compensation coefficient ax1 may have a value greater than 1. The slope S_LM20 of the measured brightness LM20 of the second LED chip 220 may be less than the slope S_LMT of the target brightness LMT, and the second duty cycle multiplication compensation coefficient ax2 may have a value greater than 1. In addition, the slope S_LM30 of the measured brightness LM30 of the third LED chip 230 may be greater than the slope S_LMT of the target brightness LMT, and the third duty cycle multiplication compensation coefficient ax3 may have a value less than 1.

[0088] In operation S140, the LED chip 200 may be turned on at a compensated duty cycle. The compensated duty cycle may have a value obtained by multiplying the initial duty cycle and the duty cycle multiplication compensation coefficient axk. For example, when the duty cycle multiplication compensation coefficient axk is greater than 1, the compensated duty cycle may be greater than the initial duty cycle, and when the duty cycle multiplication compensation coefficient axk is less than 1, the compensated duty cycle may be less than the initial duty cycle.

[0089] In operation S150, the brightness of light emitted from each LED chip 200 may be measured, and a first measured brightness LMk1 of each LED chip 200 may be obtained. For example, first measured brightness LM11, LM21, and LM31 of the first to third LED chips 210 to 230 may be obtained.

[0090] In operation S160, the brightness difference between the first measured brightness LMk1 and the target brightness LMT of each LED chip 200 may be compared with a brightness deviation reference value LMS. In example embodiments, the brightness deviation reference value LMS may include about 10% or less, about 5% or less, about 3% or less, about 2% or less, or about 1% or less of the target brightness LMT, but is not limited thereto, and the brightness deviation reference value LMS may vary based on the characteristics required for the application including the LED package 1000.

[0091] For example, when the brightness difference between the first measured brightness LMk1 of each LED chip 200 and the target brightness LMT is equal to or less than the brightness deviation reference value LMS, the duty ratio multiplication compensation coefficient axk may be stored in the second storage area 340 in operation S170.

[0092] For example, when the brightness difference between the first measured brightness LMk1 of each LED chip 200 and the target brightness LMT is greater than the brightness deviation reference value LMS, an additional operation can be performed on the duty cycle addition compensation coefficient ayk according to the brightness difference between the measured brightness LMk0 of each LED chip 200 and the target brightness LMT in operation S180.

[0093] The duty ratio addition compensation coefficient ayk may correspond to a difference between the target luminance LMT and the measured luminance LMk0. The duty ratio addition compensation coefficient ayk may be a compensation coefficient for performing an addition operation on the duty ratio.

[0094] In example embodiments, in the case where the brightness is measured by scanning the pulse width of the driving current applied to the LED chip 200, the duty cycle addition compensation coefficient ayk may be determined as an arithmetic mean of brightness difference values ​​between the target brightness LMT and the measured brightness LMk0 of the LED chip 200 obtained at a plurality of sampling points P1, P2, . . . , and Pn (e.g., obtained at a plurality of pulse widths), and the duty cycle addition compensation coefficient ayk may be calculated based on the following Equation 2:

[0095] ayk=(ΔLM1+ΔLM2+...+ΔLMn) / n (Equation 2)

[0096] In Equation 2, ayk may represent a duty cycle additive compensation coefficient of the kth LED chip, n may represent the number of sampling points (e.g., n may be 3 to 10), ΔLM1 may represent a difference between the target brightness and the measured brightness at the first sampling point P1, ΔLM2 may represent a difference between the target brightness and the measured brightness at the second sampling point P2, and ΔLMn may represent a difference between the target brightness and the measured brightness at the nth sampling point Pn.

[0097] Subsequently, in operation S140, the LED chip 200 may be turned on with the additionally calculated compensated duty cycle. The additionally calculated compensated duty cycle may have a value obtained by performing an addition operation on the initial duty cycle and the duty cycle addition compensation coefficient ayk.

[0098] In operation S150, the brightness of light emitted from each LED chip 200 may be measured. A second measured brightness LMk2 of each LED chip 200 may be obtained.

[0099] In operation S160, the brightness difference between the second measured brightness LMk2 of each LED chip 200 and the target brightness LMT may be compared with the brightness deviation reference value LMS. For example, when the brightness difference between the second measured brightness LMk2 of each LED chip 200 and the target brightness LMT is equal to or less than the brightness deviation reference value LMS, the duty cycle addition compensation coefficient ayk may be stored in the second storage area 340 in operation S170.

[0100] according to Figure 5 In the example embodiment shown in the timing diagram of FIG, the first LED chip 210 and the third LED chip 230 may store the first duty cycle multiplication compensation coefficient ax1 and the third duty cycle multiplication compensation coefficient ax3 obtained according to the ratio of the target brightness LMT to the measured brightnesses LM10 and LM30 in the second storage area 340, and the second LED chip 220 may store the second duty cycle addition compensation coefficient ay2 obtained by an additional operation according to the difference between the measured brightness LM20 and the target brightness LMT in the second storage area 340. That is, the first duty cycle compensation coefficient a1 may correspond to the value of the first duty cycle multiplication compensation coefficient ax1, the second duty cycle compensation coefficient a2 may correspond to the value of the second duty cycle addition compensation coefficient ay2, and the third duty cycle compensation coefficient a3 may correspond to the value of the third duty cycle multiplication compensation coefficient ax3.

[0101] In this case, the plurality of duty cycle compensation data DCC1 and DCC3 of the first LED chip 210 and the third LED chip 230 may each include 1-bit data for performing a duty cycle compensation operation based on a first mode corresponding to a multiplication operation (e.g., the mode selection bit MDS is “0”). The duty cycle compensation data DCC2 of the second LED chip 220 may include 1-bit data for performing a duty cycle compensation operation based on a second mode corresponding to an addition operation (e.g., the mode selection bit MDS is “1”).

[0102] For example, the duty cycle compensation data DCC1 of the first LED chip 210 may include k bits, which may include a mode selection bit MDS (e.g., data “0”) for selecting the first mode and k-1 bits of data including a first duty cycle compensation coefficient a1 based on the brightness characteristic value of the first LED chip 210. The duty cycle compensation data DCC2 of the second LED chip 220 may include k bits, which may include a mode selection bit MDS (e.g., data “1”) for selecting the second mode and k-1 bits of data including a second duty cycle compensation coefficient a2 based on the brightness characteristic value of the second LED chip 220. The duty cycle compensation data DCC3 of the third LED chip 230 may include k bits, which may include a mode selection bit MDS (e.g., data “0”) for selecting the first mode and k-1 bits of data including a third duty cycle compensation coefficient a3 based on the brightness characteristic value of the third LED chip 230.

[0103] exist Figures 4 to 6D , an example embodiment has been described in which a first mode of duty cycle compensation operation corresponding to a multiplication operation is performed on the first LED chip 210 and the third LED chip 230, and a second mode of duty cycle compensation operation corresponding to an addition operation is performed on the second LED chip 220. However, example embodiments are not limited thereto, and in other example embodiments, various combinations of performing the duty cycle compensation operation in one of the first mode and the second mode may be implemented.

[0104] When the duty cycle compensation coefficients a1, a2, and a3 of all pixels are calculated, the compensation method may end.

[0105] The method of determining the plurality of pieces of duty cycle compensation data DCC1, DCC2, and DCC3 according to example embodiments may be performed during the process of manufacturing the LED package 1000. In this case, the plurality of pieces of duty cycle compensation data DCC1, DCC2, and DCC3 of the first to third LED chips 210 to 230 may be determined during the process of manufacturing the LED package 1000 and may be stored in the second storage area 340, and the plurality of duty cycle-compensated driving currents DI1, DI2, and DI3 in which the duty cycles have been compensated based on the plurality of pieces of duty cycle compensation data DCC1, DCC2, and DCC3 stored in the second storage area 340 may be applied to the first to third LED chips 210 to 230 during the process of performing the operation of the first to third LED chips 210 to 230. In other example embodiments, the method of determining the plurality of duty cycle compensation data DCC1, DCC2, and DCC3 may be periodically performed during the operation of the LED package 1000, and the newly determined duty cycle compensation coefficients a1, a2, and a3 may be stored again in the second storage area 340.

[0106] Typically, in a passive matrix (PM) mode, N LED packages (where N is an integer of 2 or greater) can be connected in series with each other and can be driven by one integrated circuit. One frame period is divided into N divided periods, and one LED package is driven during one divided period. In this case, in a low grayscale period, a flickering phenomenon may occur when flickering occurs before sufficient voltage is applied to the LED chip. In addition, an afterimage phenomenon or a ghosting phenomenon occurs, in which parasitic capacitance existing in the LED package due to flickering between pixels causes the previous pixel to re-emit light vaguely.

[0107] On the other hand, in the AM mode according to the exemplary embodiment, each LED package can include a pixel driver integrated circuit. Therefore, even when N LED packages are connected in series, each LED package can be driven by using the entire frame period. Therefore, compared to the passive matrix mode, the on-time of each LED package can be increased, and thus, the aforementioned flicker phenomenon can be prevented. In addition, the emission operation of the current frame can be performed based on the frame data of the previous frame, and the reset period FRS can be between adjacent frame periods, thereby preventing the aforementioned ghosting phenomenon.

[0108] Furthermore, in the LED package 1000 according to the exemplary embodiment, the pixel driver integrated circuit 300 can perform a duty cycle compensation operation through a multiplication operation or an addition operation based on the brightness characteristic value of each of the first to third LED chips 210 to 230. Therefore, even when the first to third LED chips 210 to 230 have different brightness characteristic values, light having uniform brightness can be emitted from the LED package 1000. In other words, with respect to the binning of the LED chips 200, even when the LED package 1000 is manufactured using LED chips 200 having relatively large brightness deviations, the LED package 1000 can emit light having uniform brightness, thereby reducing the manufacturing cost of the LED package 1000. Furthermore, the LED package 1000 can enable a display device to display an image in grayscale that compensates for brightness deviations. Therefore, the LED package 1000 can improve image quality and prevent flickering at low grayscales, thereby increasing the reliability of the operation of a display device including the LED package 1000.

[0109] Figure 7 is a circuit diagram for describing a pixel driving integrated circuit 300A according to an example embodiment. Figure 7 In, with Figures 1 to 6D Like reference numerals refer to like elements.

[0110] Reference Figure 7 The pixel driver integrated circuit 300A may further include a detector 380. When an electrical defect occurs in at least one of the first to third LED chips 210 to 230, the detector 380 may detect the electrical defect and generate a fault detection signal FDS. For example, the electrical defect may include an undesirable short circuit or open circuit between the first to third LED chips 210 to 230 and the pixel driver integrated circuit 300A.

[0111] In some example embodiments, the fault detection signal FDS may be fed back to an external controller ( Figure 16 In this case, the external controller may limit driving of the first to third LED chips 210 to 230 based on the fault detection signal FDS. The pixel driver integrated circuit 300A may further include a feedback pad for providing the fault detection signal FDS to the external controller.

[0112] In some other example embodiments, the fault detection signal FDS may be fed back to the first storage block 330 , and the first storage block 330 may limit (eg, mask) driving of the first to third LED chips 210 to 230 based on the fault detection signal FDS.

[0113] In some other example embodiments, the fault detection signal FDS may be fed back to the PWM data generator 370 , and the PWM data generator 370 may limit (eg, mask) driving of the first to third LED chips 210 to 230 based on the fault detection signal FDS.

[0114] Figure 8 is a circuit diagram for describing a pixel driving integrated circuit 300B according to example embodiments.

[0115] Reference Figure 8 The pixel driving integrated circuit 300B may further include a clock generator 385, and the first clock pad 314 may be omitted (see Figure 2 ) and the second clock pad 315 (see Figure 2 ).

[0116] The frame data distributed by the deserializer 320 may further include clock data CCON. The clock generator 385 may generate a clock signal CLK and a PWM clock signal PCLK based on the clock data CCON.

[0117] Figure 9 is a circuit diagram for describing a pixel driving integrated circuit 300C according to example embodiments.

[0118] Reference Figure 9 The pixel driving integrated circuit 300C may further include an oscillator 390, and the second clock pad 315 may be omitted (see Figure 2 ).

[0119] The oscillator 390 may generate the PWM clock signal PCLK based on the clock signal CLK received through the first clock pad 314. For example, the oscillator 390 may include a ring oscillator, an RC oscillator, a crystal oscillator, or a temperature compensated crystal oscillator, but is not limited thereto.

[0120] Figure 10 is a circuit diagram for describing a pixel driving integrated circuit 300D according to example embodiments.

[0121] Reference Figure 10 , the pixel driver integrated circuit 300D may include an electrostatic discharge (ESD) protection circuit 395. The ESD protection circuit 395 may be connected to the power supply pad 313. When an ESD event occurs, the ESD protection circuit 395 may protect the components of the pixel driver integrated circuit 300D from a large amount of charge flowing from the outside. In other example embodiments, the ESD protection circuit 395 may also be connected to the ground pad 316.

[0122] The pixel driving integrated circuit 300D may further include an ESD protection circuit connected to at least one of the data input pad 311 , the data output pad 312 , the first clock pad 314 , and the second clock pad 315 .

[0123] Figure 11 is a perspective view illustrating an LED package 1001 according to example embodiments.

[0124] Reference Figure 11 The LED package 1001 may include a package substrate 101 , first to third LED chips 210 to 230 , a pixel driving integrated circuit 301 , external connection terminals 400 , a plurality of bonding wires 420 , and a sealing member 500 .

[0125] The package substrate 101 and the pixel driver integrated circuit 301 may be connected to each other in a wire bonding manner using a plurality of bonding wires 420. The package substrate 101 may include a plurality of pads 111 to 116 that are electrically connected to the plurality of pads 311 to 316 of the pixel driver integrated circuit 301 and are horizontally spaced apart from the pixel driver integrated circuit 301. The plurality of pads 111 to 116 may include a data input pad 111, a data output pad 112, a power supply pad 113, a plurality of clock pads 114 and 115, and a ground pad 116.

[0126] The pixel driver integrated circuit 301 may include a plurality of pads 311 to 316 that are electrically connected to the package substrate 101 and are disposed on a top surface (i.e., a surface opposite to a surface facing the package substrate 101) of the pixel driver integrated circuit 301. For example, the plurality of pads 311 to 316 may include a data input pad 311, a data output pad 312, a power supply pad 313, a plurality of clock pads 314 and 315, and a ground pad 316. The plurality of pads 111 to 116 of the package substrate 101 may be connected to the plurality of pads 311 to 316 of the pixel driver integrated circuit 301 via a plurality of bonding wires 420.

[0127] Figure 12 is a perspective view illustrating an LED package 1002 according to example embodiments.

[0128] Reference Figure 12 The LED package 1002 may include a package substrate 102 , a first LED chip 212 , a second LED chip 222 , and a third LED chip 232 , a pixel driving integrated circuit 302 , an external connection terminal 400 , a plurality of bonding wires 420 and 430 , and a sealing member 500 .

[0129] The package substrate 102 and the pixel driver integrated circuit 302 may be connected to each other by wire bonding using a plurality of bonding wires 420 and 430. The first LED chip 212, the second LED chip 222, and the third LED chip 232 may include epitaxial chips (i.e., non-flip chips), and therefore, the first LED chip 212, the second LED chip 222, and the third LED chip 232 may be connected to the pixel driver integrated circuit 302 by bonding wires.

[0130] The package substrate 102 may be Figure 11 The package substrate 101 is substantially the same as that of FIG. 1 , and therefore, repeated description thereof is omitted.

[0131] The pixel driver integrated circuit 302 may further include a first solder pad 318A, a second solder pad 318B, and a third solder pad 318C for electrically connecting to the first LED chip 212, the second LED chip 222, and the third LED chip 232. A bonding wire 420 may be used to electrically connect the package substrate 102 to the pixel driver integrated circuit 302. A bonding wire 430 may be used to electrically connect the first LED chip 212, the second LED chip 222, and the third LED chip 232 to the pixel driver integrated circuit 302. Specifically, the bonding wire 430 may connect the first LED chip 212, the second LED chip 222, and the third LED chip 232 to the first solder pad 318A, the second solder pad 318B, and the third solder pad 318C, respectively.

[0132] Figure 13 is a perspective view illustrating an LED package 1003 according to example embodiments.

[0133] Reference Figure 13 The LED package 1003 may include a plurality of LED chips 203A, 203B, 203C, and 203D and a plurality of pixel driving integrated circuits 303A, 303B, 303C, and 303D, and may further include a package substrate 103 , a sealing member 503 , and a plurality of bonding wires 420 .

[0134] With a device in which one LED pixel and one pixel driver integrated circuit 300 are provided on one package substrate 100 Figure 1 The single structure of the LED package 1000 is different. Figure 13 In the LED package 1003, a plurality of LED pixels and a plurality of pixel driver integrated circuits 303A, 303B, 303C and 303D may be provided on one package substrate 103. Figure 13In the exemplary embodiment, a 4-in-1 structure is shown in which four LED pixels are provided on one package substrate 103. However, the exemplary embodiment is not limited thereto, and an M-in-1 structure in which M LED pixels are provided on one package substrate (where M is a natural number of 2 or greater) may be widely applied.

[0135] like Figure 13 As shown, by using the connection wiring 140 included in the package substrate 103, the data output terminal of the pixel driver integrated circuit 303A can be connected to the data input terminal of the pixel driver integrated circuit 303B, and the data output terminal of the pixel driver integrated circuit 303C can be connected to the data input terminal of the pixel driver integrated circuit 303D. As described above, since the four-in-one structure is applied, the number of lower pins of the package substrate 103 can be reduced, and thus, high-speed processing of high-resolution data can be achieved.

[0136] Figure 14 is a perspective view for describing a display apparatus 2000 according to an example embodiment. Figure 15 It shows Figure 14 An enlarged plan view of area CX1. Figure 16 yes Figure 14 sectional view of a display device 2000.

[0137] Reference Figures 14 to 16 , the display device 2000 may include an LED module 1200 including a plurality of LED packages 1100 , a PCB 1300 , and a controller 1400 .

[0138] The PCB 1300 may be referred to as a module board, and may include complex internal wiring for connecting the plurality of LED packages 1100 to the controller 1400 .

[0139] A plurality of LED packages 1100 may be provided on a first surface of the PCB 1300 and may include Figures 1 to 13 One of the LED packages 1000, 1001, 1002, and 1003 shown. Each of the plurality of LED packages 1100 may constitute one pixel of the display device 2000, and the plurality of LED packages 1100 may be arranged to constitute rows and columns in the X and Y directions on the PCB 1300. Figure 14 , a case where the display device 2000 includes a plurality of LED packages 1100 arranged in a 15×15 matrix is ​​shown, but example embodiments are not limited thereto. The display device 2000 may include a plurality of LED packages arranged differently based on a resolution to be achieved (e.g., 1024×768, 1920×1080, etc.).

[0140] The controller 1400 may be provided on a second surface of the PCB 1300 opposite to the first surface, and may control driving of the plurality of LED packages 1100. For example, the controller 1400 may provide signals and power for driving a pixel driving integrated circuit included in each of the plurality of LED packages 1100. Figure 14 , only one controller 1400 is shown, but example embodiments are not limited thereto, and a plurality of controllers may be provided on the second surface of the PCB 1300. The number of controllers may be determined based on the total number of LED packages 1100 and the number of LED packages driven by one controller 1400.

[0141] like Figure 15 As shown, the display device 2000 may further include a first partition wall structure 1210 that defines an area of ​​the PCB 1300 where the plurality of LED packages 1100 are disposed. Furthermore, each of the plurality of LED packages 1100 may be disposed to be surrounded by a second partition wall structure 1220. Each of the plurality of LED packages 1100 may be electrically isolated by the second partition wall structure 1220 and may be independently driven as a separate pixel. In some example embodiments, the first partition wall structure 1210 and the second partition wall structure 1220 may each include a black matrix, but are not limited thereto.

[0142] like Figure 16 As shown, the LED packages 1100 arranged in the same row or column can be connected to each other in series through the wiring 1310 of the PCB 1300. Therefore, each LED package 1100 can obtain only the frame data of the LED package 1100 among the multiple serial data transmitted from the controller 1400, and can transmit other data to the next LED package.

[0143] While aspects of the example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A light emitting diode package, comprising: A first light-emitting diode pixel includes a plurality of first light-emitting diode chips; as well as a first pixel driving integrated circuit configured to drive the plurality of first light emitting diode chips based on an active matrix mode using an entire first frame period, Wherein, the first pixel driving integrated circuit includes: a first storage area configured to store first frame data of each of the plurality of first light emitting diode chips; a second storage area configured to store duty cycle compensation data of each of the plurality of first light emitting diode chips; a pulse width modulation data calculator configured to perform an arithmetic operation on the first frame data provided from the first storage area and the duty ratio compensation data provided from the second storage area to generate pulse width modulation data; and a pulse width modulation data generator configured to adjust a transmission duty cycle based on the pulse width modulation data, The pulse width modulation data calculator is configured to perform a multiplication operation on the first frame data and the duty cycle compensation data in a first mode, and to perform an addition operation on the first frame data and the duty cycle compensation data in a second mode.

2. The light emitting diode package according to claim 1, wherein The first pixel driver integrated circuit further includes: a deserializer configured to receive serial data from an external controller, extract and store first frame data of each of the plurality of first light emitting diode chips from the serial data, and provide the first frame data to the first storage area; and a constant current generator configured to generate a reference current based on a power supply voltage, and The PWM data generator is configured to provide a plurality of first driving currents to the plurality of first LED chips based on a clock signal, a PWM clock signal, the PWM data, and the reference current provided from the constant current generator.

3. The light emitting diode package according to claim 1, wherein The duty cycle compensation data includes k-bit data, wherein k is a natural number of 4 or greater. wherein the first bit of the duty cycle compensation data indicates one of the first mode and the second mode, and The k-1 bit of the duty cycle compensation data indicates a duty cycle compensation coefficient based on a brightness characteristic value of a corresponding light emitting diode chip among the plurality of first light emitting diode chips.

4. The light emitting diode package according to claim 2, wherein The first pixel driving integrated circuit is configured as: During the first frame period, receiving the first frame data and providing the first frame data to the first storage area, and During a second frame period following the first frame period, one of the first mode and the second mode is used to generate the plurality of first drive currents based on the pulse width modulation data calculated by performing an arithmetic operation on the first frame data provided from the first storage area and the duty ratio compensation data provided from the second storage area, and second frame data is received and provided to the first storage area.

5. The light emitting diode package according to claim 2, wherein The first pixel driving integrated circuit further includes a detector configured to detect an electrical defect based on an electrical defect occurring in at least one of the plurality of first light emitting diode chips and generate a failure detection signal. The light emitting diode package according to claim 5 , wherein: The fault detection signal is provided to the external controller, and Wherein, driving of the plurality of first light emitting diode chips is limited based on the fault detection signal.

7. The light emitting diode package according to claim 5, wherein: The fault detection signal is provided to any one of the first storage area and the pulse width modulation data generator or any combination of the first storage area and the pulse width modulation data generator, and Wherein, driving of the plurality of first light emitting diode chips is limited based on the fault detection signal.

8. The light emitting diode package according to claim 2, wherein: The first pixel driver integrated circuit further includes: a data input pad configured to receive the serial data; a data output pad configured to output data in the serial data except the first frame data; a power supply pad configured to receive the power supply voltage; a first clock pad configured to receive the clock signal; a second clock pad configured to receive the pulse width modulated clock signal; and A ground pad is connected to the plurality of first light emitting diode chips.

9. The light emitting diode package according to claim 8, further comprising: An electrostatic discharge protection circuit is connected to the power supply pad.

10. The light emitting diode package according to claim 2, wherein The first pixel driving integrated circuit further includes an oscillator configured to generate the pulse width modulation clock signal based on the clock signal. The light emitting diode package according to claim 10 , wherein: The first pixel driver integrated circuit further includes: a data input pad configured to receive the serial data; a data output pad configured to output data in the serial data except the first frame data; a power supply pad configured to receive the power supply voltage; a first clock pad configured to receive the clock signal; and A ground pad is connected to the plurality of first light emitting diode chips.

12. The light emitting diode package according to claim 2, wherein: The first frame data also includes clock data, and The first pixel driving integrated circuit further includes a clock generator, and the clock generator is configured to generate the clock signal and the pulse width modulation clock signal based on the clock data.

13. The light emitting diode package according to claim 12, wherein: The first pixel driver integrated circuit further includes: a data input pad configured to receive the serial data; a data output pad configured to output data in the serial data except the first frame data; a power supply pad configured to receive the power supply voltage; and A ground pad is connected to the plurality of first light emitting diode chips.

14. The light emitting diode package according to claim 1, further comprising: a package substrate, disposed below the first pixel driver integrated circuit; wherein the first pixel driver integrated circuit is connected to the package substrate via at least one first bonding wire, and The plurality of first light-emitting diode chips are directly connected to the first pixel driving integrated circuit via at least one second bonding wire.

15. The light emitting diode package according to claim 1, further comprising: a package substrate disposed below the first pixel driver integrated circuit, The plurality of first light-emitting diode chips are directly connected to the first pixel driver integrated circuit through at least one electrode, and the first pixel driver integrated circuit is connected to the package substrate through at least one conductive bump.

16. The light emitting diode package according to claim 1, further comprising: a second light-emitting diode pixel comprising a plurality of second light-emitting diode chips; as well as a second pixel driving integrated circuit configured to drive the plurality of second light emitting diode chips based on the active matrix mode, Wherein, the second pixel driving integrated circuit includes: a third storage area configured to store second frame data of each of the plurality of second light emitting diode chips; a fourth storage area configured to store duty cycle compensation data of each of the plurality of second light emitting diode chips; a pulse width modulation data calculator configured to perform an arithmetic operation on the second frame data provided from the third storage area and the duty ratio compensation data provided from the fourth storage area to generate pulse width modulation data; and A pulse width modulation data generator is configured to adjust a transmission duty cycle based on the pulse width modulation data.

17. The light emitting diode package according to claim 16, further comprising: a package substrate disposed below the first pixel driver integrated circuit and the second pixel driver integrated circuit, The package substrate, the plurality of first light emitting diode chips, the first pixel driver integrated circuit, the plurality of second light emitting diode chips and the second pixel driver integrated circuit are fixed by a sealing member.

18. A light emitting diode package, comprising: A first light-emitting diode pixel includes a plurality of first light-emitting diode chips; a first pixel driver integrated circuit configured to drive the plurality of first light emitting diode chips based on an active matrix pulse width modulation mode, the active matrix pulse width modulation mode controlling a time when a driving current is applied to the plurality of first light emitting diode chips in a first frame period; as well as a package substrate on which the plurality of first light-emitting diode chips and the first pixel driver integrated circuit are disposed, Wherein, the first pixel driving integrated circuit includes: a deserializer configured to receive serial data from an external controller, extract and store first frame data of each of the plurality of first light emitting diode chips from the serial data, and provide the first frame data; a first storage area configured to store the first frame data provided from the deserializer; a second storage area configured to store duty cycle compensation data of each of the plurality of first light emitting diode chips; a pulse width modulation data calculator configured to perform an arithmetic operation on the first frame data provided from the first storage area and the duty ratio compensation data provided from the second storage area to generate pulse width modulation data; a constant current generator configured to generate a reference current based on a power supply voltage; a pulse width modulation data generator configured to generate a plurality of first driving currents applied to the plurality of first light emitting diode chips based on a clock signal, a pulse width modulation clock signal, the pulse width modulation data provided from the pulse width modulation data calculator, and the reference current provided from the constant current generator; a data input pad configured to receive the serial data; a data output pad configured to output data in the serial data except the first frame data; a power supply pad configured to receive the power supply voltage; a first clock pad configured to receive the clock signal; a second clock pad configured to receive the pulse width modulated clock signal; and a ground pad connected to the plurality of first light emitting diode chips, The pulse width modulation data calculator is configured to perform a multiplication operation on the first frame data and the duty cycle compensation data in a first mode, and to perform an addition operation on the first frame data and the duty cycle compensation data in a second mode.

19. A display device comprising: printed circuit boards; a plurality of light emitting diode packages disposed on a first surface of the printed circuit board; as well as a controller disposed on a second surface of the printed circuit board opposite to the first surface, the controller being configured to control driving of the plurality of light emitting diode packages, Wherein, each of the plurality of light emitting diode packages comprises: A first light-emitting diode pixel includes a plurality of first light-emitting diode chips; and a first pixel driving integrated circuit configured to drive the plurality of first light emitting diode chips based on an active matrix mode using an entire first frame period, and Wherein, the first pixel driving integrated circuit includes: a first storage area configured to store first frame data of each of the plurality of first light emitting diode chips; a second storage area configured to store duty cycle compensation data of each of the plurality of first light emitting diode chips; a pulse width modulation data calculator configured to perform an arithmetic operation on the first frame data provided from the first storage area and the duty ratio compensation data provided from the second storage area to generate pulse width modulation data; and a pulse width modulation data generator configured to adjust a transmission duty cycle based on the pulse width modulation data, The pulse width modulation data calculator is configured to perform a multiplication operation on the first frame data and the duty cycle compensation data in a first mode, and to perform an addition operation on the first frame data and the duty cycle compensation data in a second mode.

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