Drive circuit, active matrix substrate, and display device

Abstract

To provide a drive circuit, an active matrix substrate, and a display device capable of reducing a withstand voltage required for a transistor and reducing a speed of deterioration of the transistor.SOLUTION: The unit circuit 1a of the gate driving circuit includes a transistor T2 to which a set signal is input and a transistor T3 to which a reset signal is input. At least one of the transistors T2 and T3 includes a first channel C1 and a second channel C2. The length C2 of the second channel L2 is larger than the length L1 of the first channel, or the length C2 of the second channel T2 is smaller than the length T2 of the first channel, or the mobility of the second layer of the transistor well is lower than the mobility of the first layer of the transistor well.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to a drive circuit, an active matrix substrate, and a display device. [Background technology]

[0002] The shift register described in Patent Document 1 includes a plurality of unit circuits. Each of the plurality of unit circuits includes a node, a first transistor, a second transistor, and a third transistor. A set signal is supplied to the gate terminal of the first transistor. A node is connected to the source terminal of the first transistor. A power supply potential higher than the low-level potential of the set signal is supplied to the drain terminal of the first transistor. A node is connected to the gate terminal of the second transistor. A gate bus line is connected to the source terminal of the second transistor. A clock signal is supplied to the drain terminal of the second transistor. A reset signal is supplied to the gate terminal of the third transistor. A node is connected to the source terminal of the third transistor. A power supply potential higher than the low-level potential of the reset signal is supplied to the drain terminal of the third transistor. Furthermore, only the first transistor of the first to third transistors has a tandem structure. A tandem structure is a structure in which a first channel overlapping with the first gate electrode and a second channel overlapping with the second gate electrode are provided in a semiconductor disposed between the source terminal and the drain terminal. The dimensions (length and width) of the first channel are equal to the dimensions (length and width) of the second channel, and the semiconductor material constituting the first channel is equal to the semiconductor material constituting the second channel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 1,183,0454 Summary of the Invention [Problem to be solved by the invention]

[0004] Because a tandem structure has the same function as a structure in which multiple transistors are connected in series, the voltage applied per channel (source-drain voltage) in the first transistor described in Patent Document 1 is reduced. Here, the dimensions (length and width) of the first channel described in Patent Document 1 are equal to the dimensions (length and width) of the second channel, and the semiconductor material constituting the first channel is equal to the semiconductor material constituting the second channel. However, the inventors of the present application discovered that when a potential difference is actually generated between the source terminal and drain terminal of the first transistor, the source-drain voltage (potential difference between both ends) of the first channel differs from the source-drain voltage (potential difference between both ends) of the second channel. Therefore, even when the first transistor has a tandem structure, the source-drain voltage of one of the first and second channels becomes large, which necessitates a higher breakdown voltage for the first transistor and causes accelerated degradation of the first transistor.

[0005] Therefore, the present disclosure has been made to solve the above-mentioned problems, and aims to provide a drive circuit, an active matrix substrate, and a display device that can reduce the breakdown voltage required of a transistor and slow the rate of deterioration of the transistor. [Means for solving the problem]

[0006] In order to solve the above problem, a drive circuit according to a first aspect is a drive circuit which is composed of a plurality of stages and supplies a drive signal to a group of scanning signal lines in response to an input of a clock signal, the drive circuit including a unit circuit which constitutes one of the plurality of stages and outputs the drive signal to any one of the scanning signal lines of the group of scanning signal lines, the unit circuit including a node, a first transistor which outputs the drive signal to the scanning signal line, the first transistor having a gate electrode connected to the node, a source electrode of the first transistor to which the clock signal is applied, and a drain electrode of the first transistor connected to the scanning signal line, a second transistor to which a set signal for the unit circuit is input, the set signal is input to a gate electrode of the second transistor, and a drain electrode of the second transistor connected to the node, and a third transistor to which a reset signal for the unit circuit is input, the reset signal is input to a gate electrode of the third transistor, and a drain electrode of the third transistor connected to the node. at least one of the second transistor and the third transistor has a first semiconductor portion connected to a drain electrode of at least one of the second transistor and the third transistor and a second semiconductor portion connected to a source electrode of at least one of the second transistor and the third transistor, a gate electrode of at least one of the second transistor and the third transistor has a first gate portion overlapping the first semiconductor portion and a second gate portion overlapping the second semiconductor portion, at least one of the second transistor and the third transistor includes a first channel which is a portion of the first semiconductor portion overlapping with the first gate portion and a second channel which is a portion of the second semiconductor portion overlapping with the second gate portion,The length of the second channel in the second direction is smaller than the length of the first channel in the second direction, or the mobility of electrons or holes in the second semiconductor portion is lower than the mobility of electrons or holes in the first semiconductor portion.

[0007] An active matrix substrate according to a second aspect includes the drive circuit according to the first aspect and a substrate on which the drive circuit is arranged.

[0008] A display device according to a third aspect includes the drive circuit according to the first aspect, a substrate on which the drive circuit is arranged, and a counter substrate arranged opposite to the substrate. [Effects of the Invention]

[0009] According to the above configuration, it is possible to reduce the breakdown voltage required of the transistor and to slow down the rate of deterioration of the transistor. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing the configuration of a display device 100 according to the first embodiment. [Figure 2] FIG. 2 is a block diagram showing the internal configuration of the display panel 10. As shown in FIG. [Figure 3] 3 is a schematic diagram showing the arrangement of the common electrode, and FIG. 4 is a cross-sectional view showing the configuration of the display unit 2. [Figure 4] FIG. 4 is a cross-sectional view showing the configuration of the display unit 2. As shown in FIG. [Figure 5] FIG. 5 is a diagram showing the configuration of the gate drive circuit 1. As shown in FIG. [Figure 6] FIG. 6 is a circuit diagram showing the configuration of the unit circuit 1a. [Figure 7] FIG. 7 is a cross-sectional view showing the structure of the transistors T2 and T3 according to the first embodiment. [Figure 8] FIG. 8 is a plan view schematically showing the structure of the transistors T2 and T3 according to the first embodiment. [Figure 9]FIG. 9 is a timing chart for explaining the relationship between each terminal of the unit circuit 1a and the potential during the display period according to the first embodiment. [Figure 10] FIG. 10 is a timing chart for explaining the relationship between each terminal of the unit circuit 1a and the potential in a period including the point at which the touch detection period TP and the display period switch over according to the first embodiment. [Figure 11] FIG. 11 is a circuit diagram showing the configuration of a gate drive circuit 201 according to the second embodiment. [Figure 12] FIG. 12 is a cross-sectional view showing the structure of the transistors T202 and T203 according to the second embodiment. [Figure 13] FIG. 13 is a plan view schematically showing the structure of the transistors T202 and T203 according to the second embodiment. [Figure 14] FIG. 14 is a diagram for explaining the configuration of the transistor Tc according to the first comparative example. [Figure 15] FIG. 15 is a diagram showing measurement results for explaining the comparison results between the first example, the second example, the first comparative example, and the second comparative example. [Figure 16] FIG. 16 is a circuit diagram showing the configuration of a gate drive circuit 301 according to the third embodiment. [Figure 17] FIG. 17 is a plan view schematically showing the structure of the transistors T302 and T303 according to the third embodiment. [Figure 18] FIG. 18 is a cross-sectional view showing the structure of the transistors T321 and T331 according to the third embodiment, taken along A1-A1 in FIG. [Figure 19] FIG. 19 is a cross-sectional view showing the structure of the transistors T322 and T332 according to the third embodiment, taken along line A2-A2 in FIG. [Figure 20] 20, 22, 24, 26, 28, and 30 are cross-sectional views showing the configuration of a transistor T321 in the transistor T302 according to the third embodiment. [Figure 21] FIG. 21 is a cross-sectional view showing the configuration of a transistor T322 in the transistor T302 according to the third embodiment. [Figure 22] FIG. 22 is a cross-sectional view showing the configuration of a transistor T321 in the transistor T302 according to the third embodiment. [Figure 23] FIG. 23 is a cross-sectional view showing the configuration of a transistor T322 in the transistor T302 according to the third embodiment. [Figure 24] FIG. 24 is a cross-sectional view showing the configuration of a transistor T321 in the transistor T302 according to the third embodiment. [Figure 25] FIG. 25 is a cross-sectional view showing the configuration of a transistor T322 in the transistor T302 according to the third embodiment. [Figure 26] FIG. 26 is a cross-sectional view showing the configuration of a transistor T321 in the transistor T302 according to the third embodiment. [Figure 27] FIG. 27 is a cross-sectional view showing the configuration of a transistor T322 in the transistor T302 according to the third embodiment. [Figure 28] FIG. 28 is a cross-sectional view showing the configuration of a transistor T321 in the transistor T302 according to the third embodiment. [Figure 29] FIG. 29 is a cross-sectional view showing the configuration of a transistor T322 in the transistor T302 according to the third embodiment. [Figure 30] FIG. 30 is a cross-sectional view showing the configuration of a transistor T321 in the transistor T302 according to the third embodiment. [Figure 31] FIG. 31 is a cross-sectional view showing the configuration of a transistor T322 in the transistor T302 according to the third embodiment. [Figure 32] FIG. 32 is a diagram showing the configuration of a transistor T402 according to a modification of the first to third embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The present disclosure is not limited to the following embodiments, and appropriate design modifications can be made within the scope of the configuration of the present disclosure. In the following description, the same reference numerals are used in common between different drawings for identical parts or parts having similar functions, and repeated description thereof will be omitted. The configurations described in the embodiments and modifications may be combined or modified as appropriate within the scope of the gist of the present disclosure. To facilitate understanding of the description, the drawings referred to below show simplified or schematic configurations, and some components may be omitted.

[0012] [First embodiment] (Overall configuration of the display device) Fig. 1 is a block diagram showing the configuration of a display device 100 in a first embodiment. Fig. 2 is a block diagram showing the internal configuration of a display panel 10. Fig. 3 is a schematic diagram showing the arrangement of a common electrode. Fig. 4 is a cross-sectional view showing the configuration of a display unit 2.

[0013] The display device 100 according to the first embodiment is configured as a display device with a touch panel. As shown in FIG. 1, the display device 100 includes a display panel 10 (touch panel) and a control board 20. The display panel 10 and the control board 20 are connected via a flexible printed circuit board or the like. The display panel 10 includes a gate drive circuit 1, a display section 2 which is an area where an image is displayed, and a source drive circuit 3. The control board 20 is provided with a timing controller 4, a power supply circuit 5, and a level shifter circuit 6.

[0014] 1, the timing controller 4 receives timing signals (horizontal synchronization signal, vertical synchronization signal, data enable signal, etc.) and video signals, and generates a digital video signal DV, a source start pulse signal SSP, a source clock signal SCK, a gate start pulse signal GSPa, and a gate clock signal GCKa based on the received signals. The timing controller 4 transmits the digital video signal DV, the source start pulse signal SSP, and the source clock signal SCK to the source driver circuit 3. The timing controller 4 also transmits the gate start pulse signal GSPa and the gate clock signal GCKa to the level shifter circuit 6.

[0015] The power supply circuit 5 generates a gate-on voltage VGH and a gate-off voltage VGL based on power input from an external power supply or a battery (not shown). The gate-on voltage VGH and the gate-off voltage VGL are DC voltages having a constant level (voltage value). The power supply circuit 5 inputs the generated gate-on voltage VGH and gate-off voltage VGL to the level shifter circuit 6.

[0016] Based on the gate-on voltage VGH and the gate-off voltage VGL, the level shifter circuit 6 generates clock signals GCK1 and GCK2 and a VTP signal that has the same potential (hereinafter referred to as "High level") as the gate-on voltage VGH during a touch detection period, which is a period for detecting a touch by a pointer, and has the same potential (hereinafter referred to as "Low level") as the gate-off voltage VGL during periods other than the touch detection period, which includes the display period. The level shifter circuit 6 inputs the generated signals to the gate drive circuit 1. The clock signal GCK2 is a signal whose phase is shifted by 180 degrees from the clock signal GCK1. The timing controller 4 performs processing that repeats the display period and the touch detection period in a time-division manner.

[0017] 2, the gate drive circuit 1 is disposed on one side of the display unit 2. The gate drive circuit 1 is a gate driver on array (GOA) formed on an active matrix substrate 41 (see FIG. 4) of the display panel 10.

[0018] The display panel 10 is provided with a plurality of gate lines 11 constituting a group of scanning signal lines connected to a gate drive circuit 1, and a plurality of source lines 12 constituting a group of source signal lines connected to a source drive circuit 3. The plurality of gate lines 11 and the plurality of source lines 12 are arranged to intersect with each other, and pixels are arranged in each region defined by the plurality of gate lines 11 and the plurality of source lines 12. The plurality of pixels are arranged in a matrix on the display panel 10.

[0019] 2, each pixel includes a pixel transistor 13 and a pixel electrode 14. A gate electrode of the pixel transistor 13 is connected to a gate line 11. A source electrode of the pixel transistor 13 is connected to a source line 12. A drain electrode of the pixel transistor 13 is connected to the pixel electrode 14.

[0020] When the pixel transistor 13 is turned on by a drive signal (gate signal) supplied via the gate line 11, the source signal supplied via the source line 12 is written to (charged into) the pixel electrode 14. This forms an electric field between the pixel electrode 14 and a common electrode 15 disposed opposite the pixel electrode 14.

[0021] As shown in FIG. 3, the plurality of common electrodes 15 are arranged, for example, in a matrix. The touch detection control circuit 7 is connected to each of the plurality of common electrodes 15 via wiring 16. The capacitance of the common electrode 15 changes due to capacitive coupling with a pointer. The touch detection control circuit 7 supplies touch drive signals (pulse signals) to the plurality of common electrodes 15 during a touch detection period TP (see FIG. 8). The waveform of the pulse signal changes depending on the magnitude of the capacitance of the common electrode 15. The touch detection control circuit 7 detects a touch by a pointer (touched position) based on the waveform of the pulse signal from the common electrode 15. In other words, the common electrode 15 also serves as a touch detection electrode. The display panel 10 is a self-capacitance touch panel. However, the present invention is not limited to this example, and the display panel 10 may be configured as a mutual capacitance touch panel.

[0022] 4, the display unit 2 includes an active matrix substrate 41, a counter substrate 42 disposed opposite the active matrix substrate 41, and a liquid crystal layer 43 disposed between the active matrix substrate 41 and the counter substrate 42. The liquid crystal layer 43 is driven by an electric field generated between the pixel electrodes 14 and the common electrode 15, and displays an image on the display panel 10.

[0023] (Configuration of gate drive circuit 1) Fig. 5 is a diagram showing the configuration of the gate drive circuit 1. Fig. 6 is a circuit diagram showing the configuration of a unit circuit 1a.

[0024] As shown in Fig. 5, the gate drive circuit 1 is made up of multiple stages and includes a shift register circuit that sequentially supplies drive signals to gate lines 11 (G) in response to input of clock signals GCK1 and GCK2. The gate drive circuit 1 comprises multiple unit circuits 1a that constitute one of the multiple stages and output drive signals to the connected gate lines 11. The number of unit circuits 1a is the same as the number of gate lines 11. Fig. 5 shows some (four) of the multiple unit circuits 1a.

[0025] The unit circuit 1a receives clock signals GCK1 and GCK2 and a VTP signal from the level shifter circuit 6. The drive signal output from the terminal OUT of the unit circuit 1a in the previous stage (the stage immediately before in the example of FIG. 5) is input to the terminal S of the unit circuit 1a as a set signal. The drive signal output from the terminal OUT of the unit circuit 1a in the subsequent stage (the stage immediately after in the example of FIG. 5) is input to the terminal R of the unit circuit 1a as a reset signal. As a result, when a gate start pulse signal is input as a set signal from the level shifter circuit 6 to the unit circuit 1a in the first stage, drive signals are output to the gate line 11 in sequence up to the unit circuit 1a in the final stage.

[0026] 6, the unit circuit 1a includes transistors T1 to T3, a capacitor Cbst, and a node N. The node N connects the transistors T1 to T3 and the capacitor Cbst.

[0027] The transistor T1 is a transistor for outputting a drive signal to the gate line 11 connected to the unit circuit 1a. The transistor T1 outputs the drive signal to the gate line 11 in response to a clock signal GCK1 (or clock signal GCK2) input to the terminal GCK. The bootstrap capacitor Cbst is a capacitor for turning on the transistor T1 by an increased potential due to charging.

[0028] The gate electrode of the transistor T1 is connected to the node N. The source electrode of the transistor T1 is connected to the terminal GCK. The drain electrode of the transistor T1 is connected to the terminal OUT from which the drive signal is output. One end of the bootstrap capacitor Cbst is connected to the gate electrode of the transistor T1, and the other end of the bootstrap capacitor Cbst is connected to the drain electrode of the transistor T1.

[0029] The transistor T2 is a transistor for increasing (charging) the potential of the node N in response to the input of a set signal. The gate electrode and source electrode of the transistor T2 are connected to the terminal S to which the set signal is input. The drain electrode of the transistor T2 is connected to the node N.

[0030] The transistor T3 is a transistor for decreasing (discharging) the potential of the node N in response to the input of a reset signal. The gate electrode of the transistor T3 is connected to the terminal R to which the reset signal is input. The source electrode of the transistor T3 is connected to the terminal VTP to which the VTP signal is input. The drain electrode of the transistor T3 is connected to the node N.

[0031] The semiconductor layers of the transistors T1 to T3 contain an oxide semiconductor. The oxide semiconductor can be an In-Ga-Zn-O-based oxide semiconductor that is crystalline. This makes it possible to reduce power consumption, increase driving speed, and achieve higher resolution compared to when each transistor is made of amorphous silicon.

[0032] FIG. 7 is a cross-sectional view showing the structures of transistors T2 and T3 according to the first embodiment. Since transistor T3 has the same configuration as transistor T2, the configuration of transistor T2 will be described below, and a description of the configuration of transistor T3 will be omitted. Transistor T2 includes a substrate 51, a conductor layer 52, a first insulating layer 53, a semiconductor layer 54, a second insulating layer 55, a first gate electrode 56a, a second gate electrode 56b, a third insulating layer 57, a drain electrode 58a, and a source electrode 58b. The conductor layer 52, the first insulating layer 53, the semiconductor layer 54, the second insulating layer 55, the first gate electrode 56a, the second gate electrode 56b, the third insulating layer 57, the drain electrode 58a, and the source electrode 58b are stacked in this order on the substrate 51. Transistor T2 is a top-gate transistor.

[0033] 7, the normal direction of the transistor T2 is defined as the Z1 direction, and the opposite direction to the Z1 direction is defined as the Z2 direction. The direction from the drain electrode 58a to the source electrode 58b is defined as the X1 direction, and the opposite direction to the X1 direction is defined as the X2 direction. The direction perpendicular to the X1 direction in a plan view is defined as the Y1 direction, and the opposite direction to the Y1 direction is defined as the Y2 direction.

[0034] The substrate 51 is a substrate containing glass and / or resin. The conductor layer 52 is made of a metal (e.g., copper, silver, gold, etc.). The conductor layer 52 may be made of a transparent electrode (e.g., ITO: indium tin oxide). The first insulating layer 53, the second insulating layer 55, and the third insulating layer 57 are made of, for example, an inorganic material or an organic material and have insulating properties. The first gate electrode 56a, the second gate electrode 56b, the drain electrode 58a, and the source electrode 58b are made of a metal (e.g., copper, silver, gold, etc.). The first gate electrode 56a, the second gate electrode 56b, the drain electrode 58a, and the source electrode 58b may be made of a transparent electrode (e.g., ITO).

[0035] 8 is a plan view schematically illustrating the structures of transistors T2 and T3 according to the first embodiment. As shown in FIG. 8, the first gate electrode 56a of the transistor T2 is disposed closer to the drain electrode 58a than the second gate electrode 56b. The second gate electrode 56b of the transistor T2 is disposed closer to the source electrode 58b than the first gate electrode 56a.

[0036] As shown in FIG. 8, the semiconductor layer 54 includes a first semiconductor portion 54a and a second semiconductor portion 54b. The first semiconductor portion 54a is connected to a drain electrode 58a connected to a node N (a portion having a high potential). The second semiconductor portion 54b is connected to a source electrode 58b having a potential equal to or lower than the potential of the node N. A portion of the first gate electrode 56a overlaps the first semiconductor portion 54a in a planar view. A portion of the second gate electrode 56b overlaps the second semiconductor portion 54b in a planar view. The first semiconductor portion 54a includes a first channel C1 that overlaps with the first gate electrode 56a. The second semiconductor portion 54b includes a second channel C2 that overlaps with the second gate electrode 56b. The transistor T2 also includes a connection portion 56c that connects the first gate electrode 56a and the second gate electrode 56b at a position that does not overlap with the semiconductor layer 54 in a planar view. As a result, as shown in Figure 6, the transistor T2 can be regarded as a series connection of a transistor T21 having a first channel C1 and a transistor T22 having a second channel C2. That is, the transistor T2 has a tandem structure. The transistor T3 can be regarded as a series connection of a transistor T31 having a first channel C1 and a transistor T32 having a second channel C2. That is, the transistor T3 has a tandem structure.

[0037] In the first embodiment, as shown in FIG. 8 , the length L2 of the second channel C2 in the X1 direction is greater than the length L1 of the first channel C1 in the X1 direction. In the first embodiment, the length L2 of the second gate electrode 56b is greater than the length L1 of the first gate electrode 56a, so that the transistor T2 is configured such that the length L2 of the second channel C2 is greater than the length of the first channel C1. The width W1 of the second channel C2 in the Y1 direction is equal to the length W1 of the first channel C1 in the Y1 direction. This increases the source-drain voltage Vds of the second channel C2, thereby reducing the source-drain voltage of the first channel C1. As a result, the breakdown voltage required of the transistors T2 and T3 can be reduced, and the rate of degradation of the transistors T2 and T3 can be reduced.

[0038] (Operation of the unit circuit 1a according to the first embodiment) Fig. 9 is a timing chart for explaining the relationship between each terminal of the unit circuit 1a and the potential during the display period according to the first embodiment. Fig. 10 is a timing chart for explaining the relationship between each terminal of the unit circuit 1a and the potential during the period including the point of time when the touch detection period TP and the display period switch according to the first embodiment.

[0039] As shown in Fig. 9, a clock signal GCK1 or GCK2 is input to the terminal GCK of the unit circuit 1a. For example, as shown in Fig. 5, a clock signal GCK1 is input to the terminal GCK of the odd-numbered unit circuit 1a, and a clock signal GCK2 is input to the terminal GCK of the even-numbered unit circuit 1a. Here, in Figs. 9 and 10, a low-level voltage state is indicated as "L," and a high-level voltage state is indicated as "H." Furthermore, a voltage state higher than the high level is indicated as "HH."

[0040] At time t1, when a set signal is input to terminal S (when the voltage becomes "H"), node N is charged from "L" to "H". Then, at time t2, when the potential of terminal GCK becomes "H", the potential of node N rises from "H" to "HH". As a result, the potential of terminal OUT becomes "H", a gate signal is output, a set signal is input to the unit circuit 1a of the next stage, and a reset signal is input to the unit circuit 1a of the previous stage. At time t3, when a reset signal is input to terminal R (when the voltage becomes "H"), node N is discharged from "HH" to "H", and at time t4, node N is discharged from "H" to "L".

[0041] 10, during the touch detection period TP, the input of the clock signals GCK1 and GCK2 is stopped, while the VTP signal is input to the terminal VTP. At time t11, a set signal is input to the terminal S of the unit circuit 1a. Then, at time t12, the VTP signal is input to the terminal VTP (the VTP signal becomes "H"), and the potential of the node N is maintained at "H" until time t13 when the VTP signal becomes "L". Then, at time t13, the clock signal GCK1 or GCK2 is input to the terminal GCK, and the potential of the terminal GCK becomes "H", and the potential of the node N becomes "HH", the potential of the terminal OUT becomes "H", and a gate signal is output. Then, at time t14, a reset signal is input to the terminal R (the voltage becomes "H"), and the node N is discharged from "HH" to "H", and at time t15, the node N is discharged from "H" to "L".

[0042] [Second embodiment] Next, the configuration of a gate drive circuit 201 according to the second embodiment will be described with reference to Figures 11 to 13. In the transistors T202 and T203 of the second embodiment, the width W2 of the second channel C12 is smaller than the width W1 of the first channel C1. Note that the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and their description will be omitted.

[0043] Fig. 11 is a circuit diagram showing the configuration of a gate drive circuit 201 according to the second embodiment. As shown in Fig. 11, the gate drive circuit 201 according to the second embodiment includes a unit circuit 201a. The unit circuit 201a includes transistors T202 and T203. The transistor T202 is configured by connecting in series a transistor T21 having a first channel C1 and a transistor T222 having a second channel C12 (see Fig. 13). The transistor T203 is configured by connecting in series a transistor T31 having a first channel C1 and a transistor T232 having a second channel C12 (see Fig. 13).

[0044] FIG. 12 is a cross-sectional view showing the structures of transistors T202 and T203 according to the second embodiment. FIG. 13 is a plan view showing the structures of transistors T202 and T203 according to the second embodiment. The transistor T203 has a similar configuration to the transistor T202, and therefore a description thereof will be omitted. As shown in FIG. 12, the transistor T202 includes a first gate electrode 56a, a second gate electrode 256b, and a semiconductor layer 254.

[0045] 13, the semiconductor layer 254 includes a first semiconductor portion 254a connected to the drain electrode 58a and a second semiconductor portion 254b connected to the source electrode 58b. A portion of the second gate electrode 256b overlaps the second semiconductor portion 254b in a planar view. The second semiconductor portion 254b includes a second channel C12 that overlaps with the second gate electrode 256b.

[0046] In the second embodiment, the width W2 of the second channel C12 is smaller than the width W1 of the first channel C1. The length L3 of the second channel C12 is equal to the length L1 of the first channel C1. In the second embodiment, the width W2 of the second semiconductor portion 254b is smaller than the width W1 of the first semiconductor portion 254a, and thus the transistor T202 is configured so that the width W2 of the second channel C12 is smaller than the width W1 of the first channel C1. This increases the source-drain voltage Vds of the second channel C12, thereby reducing the source-drain voltage of the first channel C1. As a result, the breakdown voltage required of the transistors T202 and T203 can be reduced, and the rate of degradation of the transistors T202 and T203 can be reduced.

[0047] [Comparison with comparative examples] Next, with reference to Figures 14 and 15, we will explain the results of comparing an example of the first embodiment (hereinafter referred to as the "first example"), an example of the second embodiment (hereinafter referred to as the "second example"), and two comparative examples (first comparative example and second comparative example).

[0048] 14 is a diagram illustrating the configuration of a transistor Tc according to a first comparative example. The transistor Tc has a first channel C1c and a second channel C2c in a region where the semiconductor layer 1054 and the gate electrode 1056 overlap. The width W1 and length L1 of the first channel C1c are equal to the width W1 and length L1 of the second channel C2c, respectively.

[0049] Furthermore, in the transistor according to the second comparative example, although not shown, the length of the first channel is longer than the length of the second channel, and the width of the first channel is equal to the width of the second channel.

[0050] The first example is the transistor T2 according to the first embodiment, and the second example is the transistor T202 according to the second embodiment.

[0051] 15 shows measurement results for explaining the comparison results between Example 1, Example 2, Comparative Example 1, and Comparative Example 2. With 30 V applied to the drain electrode of each transistor in Example 1, Example 2, Comparative Example 1, and Comparative Example 2, and 0 V applied to the source electrode, voltages of 0 V to 28 V were sequentially applied to the gate electrode, and the source-drain voltage Vds in the second channel was measured.

[0052] 15, the maximum value of Vds in the first comparative example was 4.2 V, and Vds in the second comparative example was 2.8 V. In other words, the source-drain voltage Vds in the first channel can be said to be the difference between the source-drain voltage Vds in the second channel and 30 V, so the source-drain voltage Vds in the first channel in the first comparative example was 25.8 V, and the source-drain voltage Vds in the first channel in the second comparative example was 27.2 V.

[0053] As shown in FIG. 15, the maximum value of Vds in the first embodiment and the second embodiment were both 6.5 V. That is, the source-drain voltage Vds in the first channel in the first embodiment and the source-drain voltage Vds in the first channel in the second embodiment were 23.5 V. As a result, it was found that the first embodiment and the second embodiment can reduce the source-drain voltage Vds in the first channel more than the first and second comparative examples. The withstand voltage required for transistors T2 and T3 in the first embodiment and transistors T202 and T203 in the second embodiment can be reduced, and the rate of degradation of these transistors can be slowed.

[0054] [Third embodiment] Next, the configuration of a gate drive circuit 301 according to the third embodiment will be described with reference to Figures 16 to 18. In the transistor T302 of the third embodiment, the mobility of electrons or holes in the second semiconductor layer 354b is lower than the mobility in the first semiconductor layer 354a. Note that the same components as in the first embodiment are denoted by the same reference numerals as in the first embodiment, and description thereof will be omitted.

[0055] Fig. 16 is a circuit diagram showing the configuration of a gate drive circuit 301 according to the third embodiment. As shown in Fig. 16, the gate drive circuit 301 according to the third embodiment includes a unit circuit 301a. The unit circuit 301a includes transistors T302 and T303. The transistor T302 is configured by connecting in series a transistor T321 having a first channel C21 (see Fig. 17) and a transistor T322 having a second channel C22 (see Fig. 13). The transistor T303 is configured by connecting in series a transistor T331 having a first channel C21 and a transistor T332 having a second channel C32.

[0056] Fig. 17 is a plan view schematically showing the structures of transistors T302 and T303 according to the third embodiment. Fig. 18 is a cross-sectional view showing the structures of transistors T321 and T331 according to the third embodiment, taken along A1-A1 in Fig. 17. Fig. 19 is a cross-sectional view showing the structures of transistors T322 and T332 according to the third embodiment, taken along A2-A2 in Fig. 17. Note that the transistor T303 has a similar configuration to the transistor T302, and therefore a description thereof will be omitted.

[0057] 17, the transistor T302 includes a conductor layer 352, a first gate electrode 356a, a second gate electrode 356b, a first semiconductor layer 354a, a second semiconductor layer 354b, and a connection electrode 358c. The first gate electrode 356a overlaps the first semiconductor layer 354a. The second gate electrode 356b overlaps the second semiconductor layer 354b. The first gate electrode 356a is connected to the second gate electrode 356b by a connection portion 356c.

[0058] The length L1 of the first channel C21, which is a region of the first semiconductor layer 354a overlapping with the first gate electrode 356a, is equal to the length L3 of the second channel C22, which is a region of the second semiconductor layer 354b overlapping with the second gate electrode 356b. The width W1 of the first channel C21 is equal to the width W3 of the second channel C22.

[0059] In the third embodiment, the mobility of electrons or holes in the second semiconductor layer 354b is lower than that of the first semiconductor layer 354a. For example, the first semiconductor layer 354a and the second semiconductor layer 354b are both made of an In-Ga-Zn-O oxide semiconductor. However, the impurity concentration and / or crystallinity of the material of the second semiconductor layer 354b differ from those of the material of the first semiconductor layer 354a, so that the second semiconductor layer 354b has a lower mobility than that of the first semiconductor layer 354a. When changing the impurity concentration, for example, an impurity doping step for changing the mobility may be performed in at least one of the steps of forming the first semiconductor layer 354a and forming the second semiconductor layer 354b. Alternatively, the mobility of the second semiconductor layer 354b may be reduced by forming the first semiconductor layer 354a from an In-Ga-Zn-O-based oxide semiconductor and the second semiconductor layer 354b from Si. Since the mobility of the second semiconductor layer 354b is lower than that of the first semiconductor layer 354a, the source-drain voltage Vds of the second channel C22 can be increased, thereby reducing the source-drain voltage of the first channel C21. As a result, the breakdown voltage required of the transistors T302 and T303 can be reduced, and the rate of degradation of the transistors T302 and T303 can be reduced.

[0060] The connection electrode 358c is disposed across the first semiconductor layer 354a and the second semiconductor layer 354b, and is a conductor that connects the first semiconductor layer 354a and the second semiconductor layer 354b. The connection electrode 358c is formed, for example, from the same material as the drain electrode 58a. The connection electrode 358c is formed, for example, in the same layer as the drain electrode 58a.

[0061] 18 and 19, the first semiconductor layer 354a and the second semiconductor layer 354b are formed in different layers. For example, the first semiconductor layer 354a is formed in a layer above the layer in which the second semiconductor layer 354b is formed. This makes it possible to easily change the material of the first semiconductor layer 354a and the material of the second semiconductor layer 354b.

[0062] (Method for manufacturing the transistor T302 according to the third embodiment) Next, a method for manufacturing the transistor T302 according to the third embodiment will be described with reference to Figures 17 to 31. Figures 20, 22, 24, 26, 28, and 30 are cross-sectional views showing the configuration of a transistor T321 in the transistor T302. Figures 21, 23, 25, 27, 29, and 31 are cross-sectional views showing the configuration of a transistor T322 in the transistor T302.

[0063] 20 and 21, a conductor layer 352 is formed on a substrate 51. Then, as shown in FIGS. 22 and 23, a first insulating layer 53 is formed to cover the conductor layer 352. Then, as shown in FIG. 23, a second semiconductor layer 354b is formed on the first insulating layer 53 in a region of the transistor T302 that will become the transistor T322.

[0064] 24 and 25, an insulating layer 355b is formed to cover the second semiconductor layer 354b. Then, as shown in Fig. 24, a first semiconductor layer 354a is formed on the insulating layer 355b in a region of the transistor T302 that will become the transistor T321.

[0065] 26 and 27, an insulating layer 355a is formed to cover the first semiconductor layer 354a. Then, as shown in Fig. 26, a first gate electrode 356a is formed on the insulating layer 355a in a region of the transistor T302 that will become the transistor T321. Furthermore, a second gate electrode 356b is formed on the insulating layer 355a in a region of the transistor T302 that will become the transistor T322.

[0066] Then, as shown in Fig. 28, part of the insulating layer 355a is removed so as to expose the first semiconductor layer 354a. Furthermore, as shown in Fig. 29, part of the insulating layer 355a is removed so as to expose the second semiconductor layer 354b.

[0067] Then, as shown in FIGS. 30 and 31, a third insulating layer 57 is formed to cover the first gate electrode 356a, the second gate electrode 356b, the first semiconductor layer 354a, and the second semiconductor layer 354b.

[0068] 18 and 19, contact holes are formed at a position in the X2 direction as viewed from the first gate electrode 356a, between the first gate electrode 356a and the second gate electrode 356b, and at a position in the X1 direction as viewed from the second gate electrode 356b. A drain electrode 58a is formed in the contact hole formed at a position in the X2 direction as viewed from the first gate electrode 356a. A connection electrode 358c is formed in the contact hole formed between the first gate electrode 356a and the second gate electrode 356b. A source electrode 58b is formed in a contact hole formed at a position in the X1 direction as viewed from the second gate electrode 356b. In this manner, the transistor T302 is manufactured.

[0069] [Variations] Although the embodiments of the present invention have been described above, the above-described embodiments are merely examples for carrying out the invention. Therefore, the present invention is not limited to the above-described embodiments, and can be modified as appropriate within the scope of the spirit of the invention. Modifications of the above-described embodiments will be described below.

[0070] (1) In the first to third embodiments, the display device is configured as a liquid crystal display device, but the present disclosure is not limited to this. For example, the display device may be configured as an organic EL display device, a micro LED display device, or the like.

[0071] (2) In the first to third embodiments, the length of the second channel of both the transistor receiving the set signal and the transistor receiving the reset signal in the unit circuit is made longer than the length of the first channel, the width of the second channel is made smaller than the width of the first channel, or the mobility of the second semiconductor layer is made smaller than the mobility of the first semiconductor layer. However, the present disclosure is not limited to this. That is, the length of the second channel of only one of the transistor receiving the set signal and the transistor receiving the reset signal may be made longer than the length of the first channel, the width of the second channel may be made smaller than the width of the first channel, or the mobility of the second semiconductor layer may be made smaller than the mobility of the first semiconductor layer.

[0072] (3) In the first to third embodiments, examples have been shown in which the transistors are configured to have a tandem structure in which two transistors are connected in series within the transistor, but the present disclosure is not limited to this. As in the modified transistor T402 shown in FIG. 32, the transistors may be configured to have a structure in which three transistors (T412 to T414) are connected in series, or a structure in which four or more transistors are connected in series. In this case, the length of the channel (second channel) of at least the transistor on the lowest potential side (source electrode side) of the three (or four or more) transistors is longer than the length of the channel (first channel) of the transistor on the highest potential side (drain electrode side), or the width of the second channel is smaller than the width of the first channel, or the mobility of the transistor on the lowest potential side is smaller than the mobility of the transistor on the highest potential side.

[0073] (4) In the first to third embodiments, an example was shown in which the clock signal has two phases, GCK1 and GCK2, but the present disclosure is not limited to this. The clock signal may have two phases (single phase or three or more phases).

[0074] (5) In the first to third embodiments, the transistor includes a crystalline In-Ga-Zn-O oxide semiconductor, but the present disclosure is not limited to this. The transistor may include an amorphous In-Ga-Zn-O oxide semiconductor, an oxide semiconductor other than In-Ga-Zn-O, or silicon.

[0075] (6) In the first to third embodiments, examples have been shown in which the bootstrap capacitor Cbst is provided in the unit circuit, but the present disclosure is not limited to this. If the bootstrap operation can be performed by the capacitance of the transistor T1, the bootstrap capacitor does not need to be provided in the unit circuit.

[0076] The above-described configuration can also be explained as follows.

[0077] A drive circuit according to a first configuration is a drive circuit composed of a plurality of stages, which supplies a drive signal to a group of scanning signal lines in response to an input of a clock signal, and includes a unit circuit which constitutes one of the plurality of stages and outputs the drive signal to any one of the scanning signal lines of the group of scanning signal lines, the unit circuit including a node, a first transistor which outputs the drive signal to the scanning signal line, the first transistor having a gate electrode connected to the node, a source electrode of the first transistor to which the clock signal is applied, and a drain electrode of the first transistor connected to the scanning signal line, a second transistor to which a set signal for the unit circuit is input, the set signal is input to a gate electrode of the second transistor, and a drain electrode of the second transistor connected to the node, and a third transistor to which a reset signal for the unit circuit is input, the reset signal is input to a gate electrode of the third transistor, and a drain electrode of the third transistor connected to the node, and the second transistor at least one of the second transistor and the third transistor has a first semiconductor portion connected to a drain electrode of at least one of the second transistor and the third transistor, and a second semiconductor portion connected to a source electrode of at least one of the second transistor and the third transistor, a gate electrode of at least one of the second transistor and the third transistor has a first gate portion overlapping the first semiconductor portion and a second gate portion overlapping the second semiconductor portion, at least one of the second transistor and the third transistor includes a first channel which is a portion of the first semiconductor portion overlapping with the first gate portion, and a second channel which is a portion of the second semiconductor portion overlapping with the second gate portion,The length in the second direction is shorter than that of the first channel, or the mobility of electrons or holes in the second semiconductor portion is lower than that of electrons or holes in the first semiconductor portion (first configuration).

[0078] Here, when the dimensions (length and width) of the first channel are equal to the dimensions (length and width) of the second channel and the material (mobility) of the first semiconductor portion is equal to the material (mobility) of the second semiconductor portion, the source-drain voltage of the first channel is larger than the source-drain voltage of the second channel. In contrast, in the first configuration described above, when the length of the second channel in the first direction is larger than the length of the first channel in the first direction, or when the length of the second channel in the second direction is smaller than the length of the first channel in the second direction, the source-drain voltage of the second channel can be increased, thereby preventing the source-drain voltage of the first channel from becoming too large. As a result, the breakdown voltage required of the second transistor or the third transistor can be reduced, and the rate of degradation of the second transistor or the third transistor can be reduced.

[0079] Furthermore, in the first configuration, when the mobility of electrons or holes in the second semiconductor portion is lower than that of electrons or holes in the first semiconductor portion, the source-drain voltage of the second channel can be increased, thereby preventing the source-drain voltage of the first channel from becoming too high. As a result, the breakdown voltage required of the second transistor or the third transistor can be reduced, and the rate of degradation of the second transistor or the third transistor can be slowed.

[0080] In the first configuration, the length of the second gate portion in the first direction may be greater than the length of the first gate portion in the first direction, so that the length of the second channel in the first direction may be greater than the length of the first channel in the first direction (second configuration).

[0081] According to the second configuration, the length of the second channel in the first direction can be configured to be greater than the length of the first channel in the first direction.

[0082] In the first or second configuration, the length of the second semiconductor portion in the second direction may be smaller than the length of the first semiconductor portion in the second direction, so that the length of the second channel in the second direction is smaller than the length of the first channel in the second direction (third configuration).

[0083] According to the third configuration, the length of the second channel in the second direction can be configured to be smaller than the length of the first channel in the second direction.

[0084] In any one of the first to third configurations, at least one of the second transistor and the third transistor may include a first semiconductor layer in which the first semiconductor portion is formed, and a second semiconductor layer in which the second semiconductor portion is formed, the second semiconductor layer being a layer different from the first semiconductor layer. The mobility of electrons or holes in the second semiconductor portion may be lower than the mobility of electrons or holes in the first semiconductor portion (fourth configuration).

[0085] According to the fourth configuration, the material of the second semiconductor portion can be easily made different from the material of the first semiconductor portion, compared to when the layer in which the first semiconductor portion is formed and the layer in which the second semiconductor portion is formed are the same layer.

[0086] An active matrix substrate according to a fifth configuration includes a drive circuit according to any one of the first to fourth configurations and a substrate on which the drive circuit is arranged (fifth configuration).

[0087] According to the fifth configuration, it is possible to provide an active matrix substrate that can reduce the breakdown voltage required for the transistors and slow down the rate of deterioration of the transistors.

[0088] A display device according to a sixth configuration includes a drive circuit according to any one of the first to fourth configurations, a substrate on which the drive circuit is arranged, and an opposing substrate arranged opposite the substrate (sixth configuration).

[0089] According to the sixth configuration, it is possible to provide a display device that can reduce the breakdown voltage required for the transistor and slow down the rate of deterioration of the transistor. [Explanation of symbols]

[0090] 1: gate drive circuit, 1a: unit circuit, 2: display unit, 3: source drive circuit, 4: timing controller, 5: power supply circuit, 6: level shifter circuit, 7: touch detection control circuit, 10: display panel, 11: gate line, 12: source line, 13: pixel transistor, 14: pixel electrode, 15: common electrode, 16: wiring, 20: control substrate, 41: active matrix substrate, 42: opposing substrate, 43: liquid crystal layer, 51: substrate, 52: conductor layer, 53: first insulating layer, 54: semiconductor layer, 54a: first semiconductor portion, 54b: second semiconductor portion, 55: second insulating layer, 56: second gate electrode, 56a: first gate electrode, 56b: second gate electrode, 56c: connecting portion, 57: third insulating layer, 58a: drain electrode, 58b: source electrode, 100: display device, 201: gate drive circuit, 201a: unit circuit, 254: semiconductor layer, 254a: first semiconductor portion, 254b: second semiconductor portion, 256b: second gate electrode, 301: gate drive circuit, 301a: unit circuit, 352: conductor layer, 354a: first semiconductor layer, 354b: second semiconductor layer, 355a: insulating layer, 355b: insulating layer, 356a: first gate electrode, 356b: second gate electrode, 356c: connecting portion, 358c: connection electrode, 1054: semiconductor layer, 1056: gate electrode, C1: first channel, C12: second channel, C1c: first channel, C2: second channel, C21: first channel, C22: second channel, C2c: second channel, C32: second channel, Cbst: bootstrap capacitor, DV: digital video signal, GCK: terminal, GCK1: clock signal, GCK2: clock signal, GCKa: gate clock signal, GSPa: gate start pulse signal, N: node, OUT: terminal, R: terminal, S: terminal, SCK: source clock signal, S SP: source start pulse signal, T1: transistor, T2: transistor, T202: transistor, T203: transistor, T21: transistor, T22: transistor, T222: transistor, T232: transistor, T3: transistor, T302: transistor, T303: transistor, T31: transistor, T32: transistor, T321: transistor, T322: transistor, T331: transistor, T332: transistor, T402: transistor, TFT: pixel, TP: touch detection period, Tc: transistor,VGH: Gate on voltage, VGL: Gate off voltage, VTP: Terminal, Vds: Drain voltage

Claims

1. A driving circuit that is made up of a plurality of stages and that supplies driving signals to a group of scanning signal lines in response to an input of a clock signal, a unit circuit that configures one of the plurality of stages and outputs the drive signal to any one of the scanning signal lines of the scanning signal line group; The unit circuit comprises: a node; a first transistor that outputs the drive signal to the scanning signal line, the first transistor having a gate electrode connected to the node, a source electrode of the first transistor to which the clock signal is applied, and a drain electrode of the first transistor connected to the scanning signal line; a second transistor to which a set signal for the unit circuit is input, the set signal being input to a gate electrode of the second transistor and a drain electrode of the second transistor being connected to the node; a third transistor to which a reset signal for the unit circuit is input, the reset signal being input to a gate electrode of the third transistor and having a drain electrode connected to the node; At least one of the second transistor and the third transistor is a first semiconductor portion connected to a drain electrode of at least one of the second transistor and the third transistor; a second semiconductor portion connected to a source electrode of at least one of the second transistor and the third transistor; The gate electrode of at least one of the second transistor and the third transistor is a first gate portion overlying the first semiconductor portion; a second gate portion overlapping the second semiconductor portion; At least one of the second transistor and the third transistor is a first channel that is a portion of the first semiconductor portion that overlaps with the first gate portion; a second channel that is a portion of the second semiconductor portion that overlaps with the second gate portion, When a direction from the drain electrode to the source electrode in a plan view is defined as a first direction and a direction perpendicular to the first direction is defined as a second direction, The length of the second channel in the first direction is greater than the length of the first channel in the first direction, or The length of the second channel in the second direction is smaller than the length of the first channel in the second direction, or A drive circuit, wherein the mobility of electrons or holes in the second semiconductor portion is lower than the mobility of electrons or holes in the first semiconductor portion.

2. 2. The driving circuit of claim 1, wherein the length of the second gate portion in the first direction is greater than the length of the first gate portion in the first direction, such that the length of the second channel in the first direction is greater than the length of the first channel in the first direction.

3. 2. The driving circuit of claim 1, wherein the length of the second semiconductor portion in the second direction is smaller than the length of the first semiconductor portion in the second direction, such that the length of the second channel in the second direction is smaller than the length of the first channel in the second direction.

4. At least one of the second transistor and the third transistor is a first semiconductor layer in which the first semiconductor portion is formed; a second semiconductor layer in which the second semiconductor portion is formed and which is a layer different from the first semiconductor layer; The drive circuit according to claim 1 , wherein the mobility of electrons or holes in the second semiconductor portion is lower than the mobility of electrons or holes in the first semiconductor portion.

5. A drive circuit according to any one of claims 1 to 4; a substrate on which the drive circuit is arranged.

6. A drive circuit according to any one of claims 1 to 4; a substrate on which the drive circuit is arranged; a counter substrate disposed opposite the substrate.

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