Display panel and display device
By introducing a pull-down capacitor into the gate drive circuit, the problem that the pull-down sustaining module cannot simultaneously maintain low leakage current and low potential is solved, thus achieving stable display of the display panel.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGZHOU CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
- Filing Date
- 2024-12-31
- Publication Date
- 2026-06-05
AI Technical Summary
The pull-down sustaining module in the existing gate drive circuit cannot simultaneously achieve low leakage current and low potential sustaining capability, resulting in display abnormalities.
A pull-down capacitor is set in the gate drive circuit to electrically connect the first node and the second node to the plate of the pull-down capacitor. The pull-down capacitor improves the ability to maintain a low potential and reduces the channel width of the transistor to reduce leakage current.
This improves the low leakage current and low potential maintenance capability of the gate drive circuit, reduces leakage current, and ensures the stability and reliability of the display.
Smart Images
Figure CN119516931B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology
[0002] GOA (Gate On Array) technology refers to a driving method that scans the gate row by row by fabricating the gate row scan drive signal on the array substrate. Because GOA technology eliminates the need for gate driver chips and circuit boards, saving space and enabling narrow bezels, it is widely used in display panels. Existing gate driver circuits use pull-down sustaining modules to maintain the pull-down state of the output and nodes. To improve the pull-down speed, the channel width of the transistors in the pull-down sustaining module is increased. However, in practical use, it has been found that the larger channel width of the transistors in the pull-down sustaining module leads to severe leakage current. When the nodes in the gate driver circuit output a high potential, the leakage current prevents the nodes from maintaining the high potential, causing the gate driver circuit to fail to output scan signals normally, resulting in display abnormalities. Conversely, reducing the channel width of the transistors in the pull-down sustaining module results in poor pull-down sustaining performance.
[0003] Therefore, existing gate drive circuits have a technical problem where the pull-down sustaining module cannot simultaneously achieve low leakage current and low potential sustaining capability. Summary of the Invention
[0004] This application provides a levitation motor that improves the safety of the levitation motor and at least partially solves the above-mentioned technical problems.
[0005] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, the display panel comprising: a plurality of cascaded gate driving circuits, each of the gate driving circuits comprising:
[0006] A pull-up module is electrically connected to the first node. The pull-up module is configured to connect the clock signal line to the signal output terminal of the gate drive circuit of this stage according to the potential of the first node, or to disconnect the electrical connection between the clock signal line and the signal output terminal.
[0007] The pull-down sustaining module is electrically connected to the first node and the low-potential power supply terminal;
[0008] An inverting module, one end of which is electrically connected to the first node, and the other end of which is electrically connected to the pull-down sustaining module at the second node, wherein the inverting module is configured to control the pull-down sustaining module to connect the low-potential power supply terminal to the first node or disconnect the electrical connection between the low-potential power supply terminal and the first node according to the potential of the first node.
[0009] The gate drive circuit further includes a pull-down capacitor, at least one of the first node and the second node is electrically connected to the first plate of the pull-down capacitor, and the second plate of the pull-down capacitor is electrically connected to the low-potential power supply terminal.
[0010] According to a second aspect of this application, a display device is provided, the display device including a display panel as described in any of the above embodiments.
[0011] This application provides a display panel and a display device. The display panel includes a gate driving circuit. By setting a pull-down capacitor in the gate driving circuit, at least one of the first node and the second node is electrically connected to the first plate of the pull-down capacitor, and the second plate of the pull-down capacitor is electrically connected to a low-potential power supply terminal. By setting a pull-down capacitor between at least one of the first node and the second node and the low-potential power supply terminal, the ability to maintain the first node and / or the second node at a low potential can be improved, as well as the ability to maintain other nodes and signal output terminals at a low potential. This improves the pull-down speed and the ability to maintain a low potential. Furthermore, since the pull-down capacitor increases the pull-down maintenance capability, the channel width of the transistors in the pull-down maintenance module and the inverting module can be appropriately reduced, thereby reducing leakage current. This balances the low leakage current and low potential maintenance capability of the gate driving circuit.
[0012] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description
[0013] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0014] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.
[0015] Figure 1 A circuit diagram of the gate driving circuit of a comparative display device provided in an embodiment of this application.
[0016] Figure 2 This is a schematic diagram illustrating the division of a frame time under different touch methods provided in the embodiments of this application.
[0017] Figure 3 The contrast display device provided in the embodiments of this application adopts Figure 2 A timing diagram showing a display error occurred when using one of the touch methods.
[0018] Figure 4 This is a plan view of the display panel provided in an embodiment of this application.
[0019] Figure 5 This is a first circuit diagram of a gate drive circuit provided in an embodiment of this application.
[0020] Figure 6 This is a second circuit diagram of the gate drive circuit provided in an embodiment of this application.
[0021] Figure 7 This is a third circuit diagram of the gate drive circuit provided in the embodiments of this application.
[0022] Figure 8 This is a first cross-sectional schematic diagram of a display panel provided in an embodiment of this application.
[0023] Figure 9 This is a schematic diagram of a first type of stacking of a display panel provided in an embodiment of this application.
[0024] Figure 10 for Figure 9 An exploded view of the gate layer and active layer of the display panel.
[0025] Figure 11 for Figure 9 An exploded view of the source / drain layer and pixel conductive layer of the display panel.
[0026] Figure 12 This is a second cross-sectional schematic diagram of the display panel provided in an embodiment of this application.
[0027] Figure 13 This is a schematic diagram of a second type of stacking of a display panel provided in an embodiment of this application.
[0028] Figure 14 for Figure 13 An exploded view of the gate layer and active layer of the display panel.
[0029] Figure 15 for Figure 13 An exploded view of the source / drain layer and pixel conductive layer of the display panel. Detailed Implementation
[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.
[0031] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "electrical connection" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or connections that allow for communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0032] To illustrate the principle behind the technical problem of this application, a contrast display device is provided. It should be understood that this contrast display device cannot be considered prior art in the embodiments of this application. Figure 1 As shown, a gate driving circuit in a contrast display device includes a first transistor T11a, a second transistor T21a, a third transistor T32a, a fourth transistor T42a, and a capacitor Cba. The gate and first electrode of the first transistor T11a are connected to the output terminal G(N-1)a of the previous stage gate driving circuit. The second electrode of the first transistor T11a, the gate of the second transistor T21a, one plate of the capacitor Cba, and the second electrode of the fourth transistor T42a are connected to a first point Qa. The first electrode of the second transistor T21a is connected to the clock line CKa. The second electrode of the second transistor T21a, the other plate of the capacitor Cba, and the second electrode of the third transistor T32a are connected to the output terminal G(N)a of the current stage gate driving circuit. The gates of the third transistor T32a and the fourth transistor T42a are connected to a second point Ka or a third point Pa. The first electrodes of the third transistor T32a and the fourth transistor T42a are connected to the low potential line VSSa. In this circuit, the third transistor T32a is used to maintain the output terminal G(N)a at a low potential, and the fourth transistor T42a is used to maintain the first point Qa at a low potential. Testing of this gate drive circuit revealed that the larger the channel width of the third transistor T32a and the fourth transistor T42a, the better their ability to maintain a low potential.
[0033] Meanwhile, in order to achieve touch functionality, display devices divide a frame into a display time period D and a touch time period T, such as... Figure 2 As shown, Figure 2(a) in the diagram is a time division diagram of a frame when there is no touch. Figure 2 As can be seen in (a), a frame can be divided into a display time period D and a blank time period B. Figure 2 (b) in the diagram is a time division diagram of a frame when there is touch input. Figure 2 As can be seen in (b), touch will occur during a blank time period B within one frame. This scheme is compared to Figure 2 (a) in the text can be considered as simply extending the blank time period B. Figure 2 (c) in the diagram is another time division diagram for a frame when there is touch input. Figure 2 As can be seen in (c), a frame is divided into multiple display time periods D and multiple touch time periods T. Different touch electrodes are scanned in different time periods, thereby achieving multiple reporting points within a frame and realizing high-frequency touch.
[0034] In comparison display devices adopted Figure 2 When using touch mode (c), a relatively long touch time period exists between adjacent display time periods. During this period, the gate drive circuit needs to be paused, and the potential of the first point Qa needs to be maintained at a high potential. However, in actual use, it was found that the first point Qa cannot maintain a high potential under high temperature environments. Figure 3 As shown, during the touch duration T, the potential of the first point Qa should remain high, but it cannot, causing abnormal signals output to the scan line Gate and resulting in display abnormalities. Testing of the gate drive circuit revealed that this was due to the large channel widths of the second transistor T21a, the third transistor T32a, and the fourth transistor T42a, leading to significant leakage. Therefore, the existing gate drive circuit suffers from a technical problem where the pull-down sustaining module cannot simultaneously achieve low leakage and low potential sustaining capabilities.
[0035] This application provides a display panel and a display device to solve the above-mentioned technical problems.
[0036] Figure 4 This is a plan view of the display panel provided in an embodiment of this application. Figure 5 This is a first circuit diagram of a gate drive circuit provided in an embodiment of this application. Figure 6 This is a second circuit diagram of the gate drive circuit provided in an embodiment of this application. Figure 7 This is a third circuit diagram of the gate drive circuit provided in the embodiments of this application. Figure 8 This is a first cross-sectional schematic diagram of a display panel provided in an embodiment of this application. Figure 9 This is a schematic diagram of a first type of stacking of a display panel provided in an embodiment of this application. Figure 10 for Figure 9 An exploded view of the gate layer and active layer of the display panel in the image; Figure 10 (a) in the middle is Figure 9 An exploded view of the gate layer of the display panel; Figure 10 (b) in the middle is Figure 9 An exploded view of the active layer of the display panel. Figure 11 for Figure 9 An exploded view of the source / drain layer and pixel conductive layer of the display panel in the image; Figure 11 (a) in the middle is Figure 9 An exploded view of the source and drain layers of the display panel in the image; Figure 11 (b) in the middle is Figure 9 An exploded view of the pixel conductive layer of the display panel. Figure 12 This is a second cross-sectional schematic diagram of the display panel provided in an embodiment of this application. Figure 13 This is a schematic diagram of a second type of stacking of a display panel provided in an embodiment of this application. Figure 14 for Figure 13 An exploded view of the gate layer and active layer of the display panel in the image; Figure 14 (a) in the middle is Figure 13 An exploded view of the gate layer of the display panel; Figure 14 (b) in the middle is Figure 13 An exploded view of the active layer of the display panel. Figure 15 for Figure 13 An exploded view of the source / drain layer and pixel conductive layer of the display panel in the image; Figure 15 (a) in the middle is Figure 13 An exploded view of the source and drain layers of the display panel in the image; Figure 15 (b) in the middle is Figure 13 An exploded view of the pixel conductive layer of the display panel.
[0037] like Figures 4 to 15As shown, this application embodiment provides a display panel 1, which includes multiple cascaded gate driving circuits 21. Each gate driving circuit 21 includes a pull-up module 211, a pull-down sustaining module 212, and an inverting module 213. The pull-up module 211 is electrically connected to a first node Q. The pull-up module 211 is configured to connect the clock signal line CK to the signal output terminal G(N) of the gate driving circuit 21 at this stage according to the potential of the first node Q, or to disconnect the clock signal line CK from the signal output terminal G(N). Electrical connection; the pull-down sustaining module 212 is electrically connected to the first node Q and the low-potential power supply terminal VSS; one end of the inverting module 213 is electrically connected to the first node Q, and the other end of the inverting module 213 is connected to the pull-down sustaining module 212 at the second node K. The inverting module 213 is configured to control the pull-down sustaining module 212 to connect the low-potential power supply terminal VSS to the first node Q, or to disconnect the electrical connection between the low-potential power supply terminal VSS and the first node Q, according to the potential of the first node Q.
[0038] The gate drive circuit 21 further includes a pull-down capacitor 214, at least one of the first node Q and the second node K is electrically connected to the first plate of the pull-down capacitor 214, and the second plate of the pull-down capacitor 214 is electrically connected to the low-potential power supply terminal VSS.
[0039] This application provides a display panel including a gate driving circuit. By setting a pull-down capacitor in the gate driving circuit, at least one of the first node Q and the second node K is electrically connected to the first plate of the pull-down capacitor, and the second plate of the pull-down capacitor is electrically connected to a low-potential power supply terminal. By setting a pull-down capacitor between at least one of the first node Q and the second node K and the low-potential power supply terminal, the ability to maintain the first node Q and / or the second node K at a low potential can be improved, as well as the ability to maintain other nodes and signal output terminals at a low potential. This improves the pull-down speed and the ability to maintain a low potential. Furthermore, since the pull-down capacitor increases the pull-down maintenance capability, the channel width of the transistors in the pull-down maintenance module and the inverting module can be appropriately reduced, thereby reducing leakage current. This balances the low leakage current and low potential maintenance capability of the gate driving circuit.
[0040] Specifically, it is understandable that due to the overlap between the gate and source (or drain) of each transistor, a capacitance is formed between them. Through testing, this application's embodiments have found that the larger the channel width of the transistor in the pull-down sustaining module, the more severe the leakage current under high-temperature conditions. Conversely, the smaller the capacitance formed between the gate and source (or drain) of the transistor in the pull-down sustaining module, the more severe the leakage current under high-temperature conditions. Furthermore, it was found that the smaller the proportion of the capacitance formed between the gate and source of the transistor in the pull-up sustaining module to the total capacitance (the sum of all capacitances in the circuit), the smaller the leakage current. Therefore, it can be seen that increasing the channel width of the transistor in the pull-down sustaining module can improve forward bias resistance and accelerate pull-down speed, but it will lead to severe leakage current. Increasing the capacitance formed between the gate and source of the transistor in the pull-down sustaining module can reduce leakage current, and decreasing the proportion of the capacitance formed between the gate and source of the transistor in the pull-up sustaining module to the total capacitance (the sum of all capacitances in the circuit) can reduce leakage current. However, in related technologies, since each transistor is set independently, reducing the channel width of each transistor will lead to a decrease in the capacitance between its gate and source. Therefore, in this embodiment, at least one pull-down capacitor is provided to distinguish the pull-down capacitor from the capacitance formed by the gate and source of the transistor. This allows the capacitance of the pull-down capacitor and the channel width of the transistor to be designed independently. This enables the pull-down speed to be accelerated and the performance of maintaining a low potential to be improved by using the pull-down capacitor. By adjusting the channel width of the transistor, leakage current is reduced, thereby balancing the low leakage current and low potential maintenance capability of the gate drive circuit.
[0041] Specifically, it can be understood that the pull-down capacitor added in the embodiments of this application can be regarded as being in series with the capacitance formed by the gate and source of each transistor. When the two are regarded as a whole, it is equivalent to increasing the capacitance formed by the gate and source of the transistor. Since the size of the pull-down capacitor can be adjusted, it is equivalent to realizing the separation design of the capacitance formed by the gate and source of the transistor from the channel width of the transistor. The two can be designed independently, thereby taking into account both the relatively small channel width and the relatively large capacitance, thus taking into account the low leakage current and low potential maintenance capability of the gate drive circuit.
[0042] Specifically, such as Figure 4 As shown, the non-display area 102 can be arranged around the display area 101, but the embodiments of this application are not limited to this. The non-display area 102 can be arranged on both sides or three sides of the display area 101, and the non-display area 102 can be bent to the back side of the display panel. The non-display area 102 may include gate driving circuit areas 102a located on both sides of the display area 101. The gate driving circuit can be arranged in the gate driving circuit setting area, but the embodiments of this application are not limited to this. The gate driving circuit area can be arranged on one side of the display area. Correspondingly, the gate driving circuit is arranged on one side of the display area.
[0043] Specifically, the non-display area 102 may also include a binding area (not shown).
[0044] In some embodiments, such as Figure 5 As shown, the first plate of the pull-down capacitor 214 is electrically connected to the second node K, and the second plate of the pull-down capacitor 214 is electrically connected to the low-potential power supply terminal VSS. By electrically connecting the first plate of the pull-down capacitor to the second node K and the second plate of the pull-down capacitor to the low-potential power supply terminal, the pull-down speed of the first node Q and the signal output terminal can be accelerated. Correspondingly, the channel width of the transistor in the pull-down sustaining module can be reduced, the risk of leakage current can be reduced, and the high-potential stability of the first node Q and the signal output terminal can be improved.
[0045] In some embodiments, such as Figure 6 As shown, the first plate of the pull-down capacitor 214 is electrically connected to the first node Q, and the second plate of the pull-down capacitor 214 is electrically connected to the low-potential power supply terminal VSS. By electrically connecting the first plate of the pull-down capacitor to the first node Q and the second plate of the pull-down capacitor to the low-potential power supply terminal, the pull-down speed of the second node K and the third node can be accelerated, and correspondingly, the channel width of the transistor in the inverting module can be reduced, thereby improving the high-potential stability of the second node K and the third node.
[0046] Specifically, considering that the inverting module is connected to the pull-down sustaining module, the stability of the inverting module directly affects the stability of the pull-down sustaining module, thereby indirectly affecting the display effect. Therefore, in this embodiment, by electrically connecting the first plate of the pull-down capacitor to the first node Q and the second plate of the pull-down capacitor to the low-potential power supply terminal, the pull-down speed of the second node K and the third node can be accelerated through the pull-down capacitor, thereby improving the ability of the inverting module to maintain a low potential. Correspondingly, the channel width of the transistor in the inverting module can be reduced, leakage current can be reduced, and display abnormalities can be avoided.
[0047] In some embodiments, such as Figure 7As shown, the pull-down capacitor 214 includes a first sub-capacitor Cqt and a second sub-capacitor Ckt. The first plate of the first sub-capacitor Cqt is electrically connected to the first node Q, and the second plate of the first sub-capacitor Cqt is electrically connected to the low-potential power supply terminal VSS. The first plate of the second sub-capacitor Ckt is electrically connected to the second node K, and the second plate of the second sub-capacitor Ckt is electrically connected to the low-potential power supply terminal VSS. By electrically connecting the first plate of the first sub-capacitor Cqt to the first node Q and the second plate of the first sub-capacitor Cqt to the low-potential power supply terminal, the pull-down speed of the second node K and the third node can be accelerated through the first sub-capacitor Cqt, and correspondingly, the channel width of the transistor in the inverting module can be reduced, thereby improving the high-potential stability of the second node K and the third node. By electrically connecting the first plate of the second sub-capacitor Ckt to the second node K and the second plate of the second sub-capacitor Ckt to the low-potential power supply terminal, the pull-down speed of the first node Q and the signal output terminal can be accelerated through the second sub-capacitor Ckt. Correspondingly, the channel width of the transistor in the pull-down sustaining module can be reduced, the risk of leakage current can be reduced, and the high-potential stability of the first node Q and the signal output terminal can be improved.
[0048] In some embodiments, such as Figures 5 to 7 As shown, the pull-down sustaining module 212 includes a first pull-down sustaining transistor T32 and a second pull-down sustaining transistor T42. The gate of the first pull-down sustaining transistor T32 is electrically connected to the second node K, the first electrode of the first pull-down sustaining transistor T32 is electrically connected to the low-potential power supply terminal VSS, and the second electrode of the first pull-down sustaining transistor T32 is electrically connected to the signal output terminal G(N). The gate of the second pull-down sustaining transistor T42 is electrically connected to the second node K, the first electrode of the second pull-down sustaining transistor T42 is electrically connected to the low-potential power supply terminal VSS, and the second electrode of the second pull-down sustaining transistor T42 is electrically connected to the first node Q.
[0049] In this circuit, the first plate of the second sub-capacitor Ckt is electrically connected to the gate of the first pull-down sustaining transistor T32 and the gate of the second pull-down sustaining transistor T42. By configuring the first pull-down sustaining transistor T32 and the second pull-down sustaining transistor T42, the second electrode of the first pull-down sustaining transistor T32 is connected to the signal output terminal, and the second electrode of the second pull-down sustaining transistor T42 is connected to the first node Q. This allows the first pull-down sustaining transistor T32 and the second pull-down sustaining transistor T42 to control the signal output terminal and the first node Q to maintain a low potential, ensuring the normal operation of the gate drive circuit. Furthermore, the electrical connection between the first plate of the second sub-capacitor Ckt and the gates of the first pull-down sustaining transistor T32 and the second pull-down sustaining transistor T42 accelerates the pull-down speed of the first node Q and the signal output terminal, correspondingly reducing the channel width of the first pull-down sustaining transistor T32 and the second pull-down sustaining transistor T42, thereby reducing leakage current and balancing the low leakage current and low potential maintenance capability of the gate drive circuit.
[0050] In some embodiments, such as Figures 5 to 7 As shown, the inverting module 213 includes a first inverting transistor T51, a second inverting transistor T52, a third inverting transistor T53, and a fourth inverting transistor T54. The gate of the first inverting transistor T51 is electrically connected to the high-potential power supply terminal VGH, and the first electrode of the first inverting transistor T51 is electrically connected to the high-potential power supply terminal VGH. The gate of the second inverting transistor T52 is electrically connected to the first node Q, the first electrode of the second inverting transistor T52 is electrically connected to the low-potential power supply terminal VSS, and the second electrode of the second inverting transistor T52 is electrically connected to the second electrode of the first inverting transistor T51. The gate of the third inverting transistor T53 is electrically connected to the second electrode of the first inverting transistor T51 at the third node P; the first electrode of the third inverting transistor T53 is electrically connected to the high-potential power supply terminal VGH; the second electrode of the third inverting transistor T53 is electrically connected to the pull-down sustaining module 212 at the second node K; the gate of the fourth inverting transistor T54 is electrically connected to the first node Q; the first electrode of the fourth inverting transistor T54 is electrically connected to the low-potential power supply terminal VSS; the second electrode of the fourth inverting transistor T54 is electrically connected to the second node K.
[0051] In this circuit, the first plate of the first sub-capacitor Cqt is electrically connected to the gate of the second inverting transistor T52 and the gate of the fourth inverting transistor T54. By electrically connecting the first plate of the first sub-capacitor Cqt to the gate of the second inverting transistor T52 and the gate of the fourth inverting transistor T54, the pull-down speed of the second node K and the third node can be accelerated, thereby reducing the channel width of the second inverting transistor T52 and the fourth inverting transistor T54, thus reducing leakage current and balancing the low leakage current and low potential maintenance capability of the gate drive circuit.
[0052] In some embodiments, such as Figures 7 to 15 As shown, the display panel 1 includes a substrate 311, a gate layer 312, and a source / drain layer 315. The gate layer 312 is disposed on one side of the substrate 311, and includes the gate T32G of the first pull-down sustaining transistor T32, the gate T42G of the second pull-down sustaining transistor T42, the gate T52G of the second inverting transistor T52, the gate T54G of the fourth inverting transistor T54, the first electrode Cqt1 of the first sub-capacitor Cqt, and the first electrode of the second sub-capacitor Ckt. Plate Ckt1; Source-drain layer 315 is disposed on the side of the gate layer 312 away from the substrate 311, and the source-drain layer 315 includes the first electrode T32S of the first pull-down sustaining transistor T32, the first electrode T42S of the second pull-down sustaining transistor T42, the first electrode T52S of the second inverting transistor T52, the first electrode T54S of the fourth inverting transistor T54, the second plate Cqt2 of the first sub-capacitor Cqt, and the second plate Ckt2 of the second sub-capacitor Ckt;
[0053] Wherein, the gate T32G of the first pull-down sustaining transistor T32, the gate T42G of the second pull-down sustaining transistor T42, and the first plate Ckt1 of the second sub-capacitor Ckt are connected, and the first electrode T32S of the first pull-down sustaining transistor T32, the first electrode T42S of the second pull-down sustaining transistor T42, and the second plate Ckt2 of the second sub-capacitor Ckt are connected;
[0054] And / or, the gate T52G of the second inverting transistor T52, the gate T54G of the fourth inverting transistor T54, and the first plate Cqt1 of the first sub-capacitor Cqt are connected, and the first electrode T52S of the second inverting transistor T52, the first electrode T54S of the fourth inverting transistor T54, and the second plate Ckt2 of the first sub-capacitor CqtCkt are connected.
[0055] Specifically, only the gate T32G of the first pull-down sustaining transistor T32, the gate T42G of the second pull-down sustaining transistor T42, and the first plate Ckt1 of the second sub-capacitor Ckt can be connected, and the first electrode T32S of the first pull-down sustaining transistor T32, the first electrode T42S of the second pull-down sustaining transistor T42, and the second plate Ckt2 of the second sub-capacitor Ckt can be connected. Therefore, when adding the second sub-capacitor Ckt, the gates of the first pull-down sustaining transistor T32 and T42, and the first plate of the second sub-capacitor Ckt can be combined, as can the first electrodes of the first pull-down sustaining transistor T32 and T42, and the second plate of the second sub-capacitor Ckt. This reduces the bezel size, improving space utilization and reducing the bezel size while increasing the second sub-capacitor Ckt. The design of the second inverting transistor T52, the fourth inverting transistor T54, and the first sub-capacitor Cqt is not limited.
[0056] Specifically, only the gate T52G of the second inverting transistor T52, the gate T54G of the fourth inverting transistor T54, and the first plate Cqt1 of the first sub-capacitor Cqt can be connected, and the first electrode T52S of the second inverting transistor T52, the first electrode T54S of the fourth inverting transistor T54, and the second plate Ckt2 of the first sub-capacitor CqtCkt can be connected. Therefore, when adding the first sub-capacitor Cqt, the gates of the second inverting transistor T52 and the fourth inverting transistor T54, and the first plate of the first sub-capacitor Cqt can be combined, and the first electrodes of the second inverting transistor T52 and the fourth inverting transistor T54, and the second plate of the first sub-capacitor Cqt can be combined, thereby reducing the bezel size and improving space utilization while increasing the first sub-capacitor Cqt. The design of the first pull-down holding transistor T32, the second pull-down holding transistor T42, and the second sub-capacitor Ckt is not limited.
[0057] Specifically, the gate T32G of the first pull-down sustaining transistor T32, the gate T42G of the second pull-down sustaining transistor T42, and the first plate Ckt1 of the second sub-capacitor Ckt can be connected, and the first electrode T32S of the first pull-down sustaining transistor T32, the first electrode T42S of the second pull-down sustaining transistor T42, and the second plate Ckt2 of the second sub-capacitor Ckt can be connected; and the gate T52G of the second inverting transistor T52, the gate T54G of the fourth inverting transistor T54, and the first plate Cqt1 of the first sub-capacitor Cqt can be connected, and the first electrode T52S of the second inverting transistor T52, the first electrode T54S of the fourth inverting transistor T54, and the second plate Ckt2 of the first sub-capacitor CqtCkt can be connected. Therefore, when adding the first sub-capacitor Cqt and the second sub-capacitor Ckt, the gates of the first pull-down holding transistor T32, the second pull-down holding transistor T42, and the first plate of the second sub-capacitor Ckt can be combined. The gates of the second inverting transistor T52, the fourth inverting transistor T54, and the first plate of the first sub-capacitor Cqt can be combined. The first electrode of the first pull-down holding transistor T32, the first electrode of the second pull-down holding transistor T42, and the second plate of the second sub-capacitor Ckt can be combined. The first electrode of the second inverting transistor T52, the first electrode of the fourth inverting transistor T54, and the second plate of the first sub-capacitor Cqt can be combined. This reduces the bezel size and improves space utilization while increasing the first sub-capacitor Cqt and the second sub-capacitor Ckt.
[0058] Specifically, such as Figure 8 , Figure 12 As shown, the display panel 1 also includes a gate insulating layer 313, an active layer 314, an interlayer insulating layer 316, and a pixel conductive layer 317. The gate insulating layer 313 can be disposed on the side of the gate layer 312 away from the substrate 311. The active layer 314 is disposed between the gate insulating layer 313 and the source / drain layer 315. The interlayer insulating layer 316 is disposed on the side of the source / drain layer 315 away from the active layer. The pixel conductive layer 317 is disposed on the side of the interlayer insulating layer 316 away from the source / drain layer 315.
[0059] In some embodiments, such as Figures 8 to 15As shown, the first electrode T32S of the first pull-down holding transistor T32 includes a first branch electrode 411 and a second branch electrode 412. The first branch electrode 411 and the second branch electrode 412 are arranged along the first direction X. The length L1 of the first branch electrode 411 in the second direction Y is greater than the length L2 of the second branch electrode 412 in the second direction Y. The second plate Ckt2 of the second sub-capacitor Ckt and the portion of the first branch electrode 411 that extends beyond the second branch electrode 412 are arranged along the first direction X.
[0060] In the second direction Y, the second electrode Ckt2 of the second sub-capacitor Ckt is located between the second branch electrode 412 and the first electrode T42S of the second pull-down sustaining transistor T42. The angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees. By making the first electrode of the first pull-down sustaining transistor T32 include a first branch electrode and a second branch electrode, with the length of the first branch electrode being greater than the length of the second branch electrode, and the second electrode of the second sub-capacitor Ckt and the portion of the first branch electrode extending beyond the second branch electrode being arranged along the first direction, and the second electrode of the second sub-capacitor Ckt being located between the second branch electrode and the first electrode of the second pull-down sustaining transistor T42, it is possible to shorten the portion of the second branch electrode in the first electrode of the first pull-down sustaining transistor T32 and use this portion as the second electrode of the second sub-capacitor Ckt. This reduces the channel width of the transistor while increasing the second sub-capacitor Ckt, thereby improving the electrical performance of the display panel, increasing space utilization, and reducing the bezel size.
[0061] Specifically, it can be seen that the connection point (i.e., the first node Q) between the gate of the fourth inverting transistor T54 and the second electrode of the second pull-down holding transistor T42 is correspondingly set with the first branch electrode, and the first electrode of the second pull-down holding transistor T42 is correspondingly set with the second branch electrode. Furthermore, the connection point between the gate of the fourth inverting transistor T54 and the second electrode of the second pull-down holding transistor T42 is set along the first direction with the first electrode of the second pull-down holding transistor T42. This can improve space utilization, appropriately reduce the channel width of the second pull-down holding transistor T42, and improve the electrical performance of the display panel while improving space utilization and reducing the bezel size.
[0062] In some embodiments, such as Figures 8 to 15As shown, the second plate Cqt2 of the first sub-capacitor Cqt is located between the first electrode T52S of the second inverting transistor T52 and the first electrode T54S of the fourth inverting transistor T54. By placing the second plate of the first sub-capacitor Cqt between the first electrode of the second inverting transistor T52 and the first electrode of the fourth inverting transistor T54, the second plate of the first sub-capacitor Cqt can be formed using the gap between the first electrodes of the second inverting transistor T52 and the first electrode of the fourth inverting transistor T54. This improves the electrical performance of the display panel while increasing space utilization and reducing the bezel size.
[0063] Specifically, it can be seen that in the second direction, the length of the first electrode of the fourth inverter transistor T54 is greater than the length of the first electrode of the second inverter transistor T52. The connection between the second electrode of the second inverter transistor T52 and the gate of the third inverter transistor (i.e., the third node P) is correspondingly set with the portion of the first electrode of the fourth inverter transistor T54 that extends beyond the first electrode of the second inverter transistor T52, thereby improving space utilization and reducing the bezel size.
[0064] Specifically, it is understood that, compared to setting each transistor independently, the embodiments of this application, by adding pull-down capacitors, can improve the electrical performance of the display panel while increasing space utilization and reducing the bezel by adjusting the connection relationship and position of each transistor.
[0065] Specifically, such as Figure 8 , Figure 9 , Figure 10 As shown, in Figure 10 As shown in (a), the gate layer 312 includes the gate T32G of the first pull-down sustaining transistor T32, the gate T42G of the second pull-down sustaining transistor T42, the gate T52G of the second inverting transistor T52, the gate T53G of the third inverting transistor T53, the gate T54G of the fourth inverting transistor T54, the first plate Cqt1 of the first sub-capacitor Cqt, and the first plate Ckt1 of the second sub-capacitor Ckt. It is understood that the gate layer also includes the gates of other transistors. Figure 10 (a) is not shown.
[0066] Specifically, such as Figure 8 , Figure 9 , Figure 10 As shown, in Figure 10As can be seen in (b), the active layer 314 includes the active portion T32A of the first pull-down sustaining transistor T32, the active portion T42A of the second pull-down sustaining transistor T42, the active portion T52A of the second inverting transistor T52, the active portion T53A of the third inverting transistor T53, and the active portion T54A of the fourth inverting transistor T54. It can be understood that the active layer also includes the active portions of other transistors. Figure 10 (b) is not shown.
[0067] Specifically, it can be understood that the gate of each transistor is set to correspond to the active part of each transistor.
[0068] Specifically, such as Figure 8 , Figure 9 , Figure 11 As shown, in Figure 11 As shown in (a), the source-drain layer 315 includes the first electrode T32S of the first pull-down sustaining transistor T32, the second electrode T32D of the first pull-down sustaining transistor T32, the first electrode T42S of the second pull-down sustaining transistor T42, the second electrode T42D of the second pull-down sustaining transistor T42, the first electrode T52S of the second inverting transistor T52, the second electrode T52D of the second inverting transistor T52, the first electrode T53S of the third inverting transistor T53, the second electrode T53D of the third inverting transistor T53, the first electrode T54S of the fourth inverting transistor T54, the second electrode T54D of the fourth inverting transistor T54, the second electrode Cqt2 of the first sub-capacitor Cqt, and the second electrode Ckt2 of the second sub-capacitor Ckt. It can be understood that the source-drain layer also includes the first and second electrodes of other transistors. Figure 11 (a) is not shown.
[0069] Specifically, such as Figure 8 , Figure 9 , Figure 11 As shown, in Figure 11As shown in (b), the pixel conductive layer 317 may include a first connection portion K1, a second connection portion K2, a third connection portion K3, and a fourth connection portion K4. The first connection portion K1 passes through the via 301 and connects to the gate T32G of the first pull-down holding transistor T32 and the second electrode T53D of the third inverting transistor T53. The second connection portion K2 passes through the via 301 and connects to the second electrode T42D of the second pull-down holding transistor T42 and the gate T54G of the fourth inverting transistor T54. The third connection portion K3 passes through the via 301 and connects to the second electrode T52D of the second inverting transistor T52 and the gate T53G of the third inverting transistor T53. The fourth connection portion K4 passes through the via 301 and connects to the first electrode T53S of the third inverting transistor T53. It is understood that the pixel conductive layer also includes other connection portions. Figure 11 (b) is not shown.
[0070] Specifically, in the embodiments of this application, the film layer for via setting is not limited, and it is understood that the positions of the vias through which different connection parts pass can be different, and the same connection part can pass through multiple vias. The via can be a via that connects the pixel conductive layer to the gate layer, or a via that connects the pixel conductive layer to the source and drain layers.
[0071] In some embodiments, such as Figures 12 to 15 As shown, the display panel 1 further includes a pixel conductive layer 317, which is disposed on the side of the source-drain layer 315 away from the gate layer 312.
[0072] The pixel conductive layer 317 is electrically connected to at least one of the gates of the first pull-down sustaining transistor T32, the second pull-down sustaining transistor T42, the second inverting transistor T52, and the fourth inverting transistor T54. By electrically connecting the pixel conductive layer to at least one of the gates of the first pull-down sustaining transistor T32, the second pull-down sustaining transistor T42, the second inverting transistor T52, and the fourth inverting transistor T54, the control capability of each transistor can be increased, and the capacitance of the pull-down capacitor can be increased, thereby increasing the pull-down sustaining capability.
[0073] Specifically, the pixel conductive layer can be electrically connected to at least one of the first node Q and the second node K, so that the pixel conductive layer is equivalent to having another capacitor connected in series with the pull-down capacitor, thereby increasing the pull-down holding capability, improving the control capability of the transistor, and reducing leakage current.
[0074] Specifically, the pixel conductive layer can be connected to the first node Q, or it can be connected to the second node K. Alternatively, the pixel conductive layer can consist of two parts, one part connected to the first node Q and the other part connected to the second node K.
[0075] Specifically, the pixel conductive layer can be connected to one, two, three, or four of the gates of the first pull-down sustaining transistor T32, the second pull-down sustaining transistor T42, the second inverting transistor T52, and the fourth inverting transistor T54. When the pixel conductive layer is connected to the gates of multiple transistors, multiple transparent conductive portions can be provided to prevent signal crosstalk.
[0076] In some embodiments, such as Figures 12 to 15 As shown, the pixel conductive layer 317 includes a first transparent conductive portion 317a and a second transparent conductive portion 317b. The first transparent conductive portion 317a is connected to the gate of the first pull-down sustaining transistor T32 and the gate of the second pull-down sustaining transistor T42, and the second transparent conductive portion 317b is connected to the gate of the second inverting transistor T52 and the gate of the fourth inverting transistor T54. By including the first transparent conductive portion and the second transparent conductive portion in the pixel conductive layer, and connecting the first transparent conductive portion to the gate of the first pull-down sustaining transistor T32 and the gate of the second pull-down sustaining transistor T42, and connecting the second transparent conductive portion to the gate of the second inverting transistor T52 and the gate of the fourth inverting transistor T54, the first sub-capacitor Cqt and the second sub-capacitor Ckt can be increased, thereby further improving the pull-down sustaining capability, increasing the gate control capability of each transistor, and reducing leakage current.
[0077] Specifically, such as Figure 12 , Figure 13 , Figure 14 As shown, in Figure 14 As shown in (a), the gate layer 312 includes the gate T32G of the first pull-down sustaining transistor T32, the gate T42G of the second pull-down sustaining transistor T42, the gate T52G of the second inverting transistor T52, the gate T53G of the third inverting transistor T53, the gate T54G of the fourth inverting transistor T54, the first plate Cqt1 of the first sub-capacitor Cqt, and the first plate Ckt1 of the second sub-capacitor Ckt. It is understood that the gate layer also includes the gates of other transistors. Figure 14 (a) is not shown.
[0078] Specifically, such as Figure 12 , Figure 13 , Figure 14 As shown, in Figure 14As can be seen in (b), the active layer 314 includes the active portion T32A of the first pull-down sustaining transistor T32, the active portion T42A of the second pull-down sustaining transistor T42, the active portion T52A of the second inverting transistor T52, the active portion T53A of the third inverting transistor T53, and the active portion T54A of the fourth inverting transistor T54. It can be understood that the active layer also includes the active portions of other transistors. Figure 14 (b) is not shown.
[0079] Specifically, it can be understood that the gate of each transistor is set to correspond to the active part of each transistor.
[0080] Specifically, such as Figure 12 , Figure 13 , Figure 15 As shown, in Figure 15 As shown in (a), the source-drain layer 315 includes the first electrode T32S of the first pull-down sustaining transistor T32, the second electrode T32D of the first pull-down sustaining transistor T32, the first electrode T42S of the second pull-down sustaining transistor T42, the second electrode T42D of the second pull-down sustaining transistor T42, the first electrode T52S of the second inverting transistor T52, the second electrode T52D of the second inverting transistor T52, the first electrode T53S of the third inverting transistor T53, the second electrode T53D of the third inverting transistor T53, the first electrode T54S of the fourth inverting transistor T54, the second electrode T54D of the fourth inverting transistor T54, the second electrode Cqt2 of the first sub-capacitor Cqt, and the second electrode Ckt2 of the second sub-capacitor Ckt. It can be understood that the source-drain layer also includes the first and second electrodes of other transistors. Figure 11 (a) is not shown.
[0081] Specifically, such as Figure 12 , Figure 13 , Figure 15 As shown, in Figure 15As shown in (b), the pixel conductive layer 317 may include a first transparent conductive portion 317a, a second transparent conductive portion 317b, a third connecting portion K3, and a fourth connecting portion K4. The first transparent conductive portion 317a passes through the via 301 and connects to the gate T32G of the first pull-down holding transistor T32 and the second electrode T53D of the third inverting transistor T53. The projection of the first transparent conductive portion on the substrate may coincide with the projection of the gate of the first pull-down holding transistor T32, the gate of the second pull-down holding transistor T42, and the second sub-capacitor Ckt on the substrate. The second transparent conductive portion... 317b passes through via 301 to connect the second electrode T42D of the second pull-down holding transistor T42 and the gate T54G of the fourth inverting transistor T54. The second transparent conductive portion can overlap with the presence of the gate of the second inverting transistor T52, the gate of the fourth inverting transistor T54, and the first sub-capacitor Cqt on the substrate. The third connection portion K3 passes through via 301 to connect the second electrode T52D of the second inverting transistor T52 and the gate T53G of the third inverting transistor T53. The fourth connection portion K4 passes through via 301 to connect the first electrode T53S of the third inverting transistor T53. It is understood that the pixel conductive layer also includes other connection portions. Figure 15 (b) is not shown.
[0082] Specifically, it is understandable that, depending on the film layer design of the display panel, the pixel conductive layer can be set in the same layer as the pixel electrode, in the same layer as the common electrode, or independently.
[0083] In some embodiments, such as Figures 5 to 7 As shown, the gate driving circuit 21 further includes:
[0084] Pull-up control module 215 includes pull-up control transistor T11, the gate of pull-up control transistor T11 and the first electrode of pull-up control transistor T11 are configured to receive pull-up control signal, and the second electrode of pull-up control transistor T11 is electrically connected to the first node Q.
[0085] The pull-down module 216 includes a first pull-down transistor T31 and a second pull-down transistor T41. The gate of the first pull-down transistor T31 is configured to receive a first pull-down control signal. The first electrode of the first pull-down transistor T31 is electrically connected to the low-potential power supply terminal VSS, and the second electrode of the first pull-down transistor T31 is electrically connected to the signal output terminal G(N). The gate of the second pull-down transistor T41 is configured to receive a second pull-down control signal. The first electrode of the second pull-down transistor T41 is electrically connected to the low-potential power supply terminal VSS, and the second electrode of the second pull-down transistor T41 is electrically connected to the first node Q.
[0086] The reset module 217 includes a first reset transistor TrG and a second reset transistor TrQ. The gate of the first reset transistor TrG is connected to the reset signal line Rst, the first electrode of the first reset transistor TrG is electrically connected to the low-potential power supply terminal VSS, and the second electrode of the first reset transistor TrG is electrically connected to the signal output terminal G(N). The gate of the second reset transistor TrQ is connected to the reset signal line Rst, the first electrode of the second reset transistor TrQ is electrically connected to the low-potential power supply terminal VSS, and the second electrode of the second reset transistor TrQ is electrically connected to the first node Q.
[0087] A storage capacitor Cbt is provided, with one plate of the storage capacitor Cbt electrically connected to the first node Q, and the other plate of the storage capacitor Cbt electrically connected to the signal output terminal G(N).
[0088] Specifically, such as Figures 5 to 7 As shown, the pull-up module 211 includes a pull-up transistor T21. The gate of the pull-up transistor T21 is electrically connected to the first node Q. The first electrode of the pull-up transistor T21 is connected to the clock signal line CK. The second electrode of the pull-up transistor T21 is connected to the signal output terminal G(N).
[0089] Specifically, the display panel 1 includes multiple cascaded gate drive circuits 21. The gate of the pull-up control transistor T11 in the first-stage gate drive circuit 21 can be connected to the start signal line STV. The gate of the pull-up control transistor T11 in the other stages of the gate drive circuit 21 can be connected to the signal output terminal G(N-3) of the first three stages of the gate drive circuit 21. N is greater than or equal to 4, and N is an integer.
[0090] Specifically, the gate of the first pull-down transistor T31 in this stage gate drive circuit can be connected to the signal output terminal G(N+4) in the fourth stage gate drive circuit below, and the gate of the second pull-down transistor T41 in this stage gate drive circuit can be connected to the signal output terminal G(N+6) in the sixth stage gate drive circuit below.
[0091] Specifically, the embodiments of this application illustrate the signal lines or signal terminals connected to the gates of each transistor. It is understood that the embodiments of this application are not limited to this. For example, the gate of the first pull-down transistor T31 in this stage gate driving circuit can be connected to the signal output terminal G(N+2) in the next two stage gate driving circuits. Different connection methods are possible without affecting the display, which will not be elaborated here.
[0092] Specifically, each transistor in the embodiments of this application can be a silicon semiconductor transistor (e.g., a low-temperature polycrystalline silicon thin-film transistor) to reduce power consumption. However, the embodiments of this application are not limited to this. Each transistor can be an oxide semiconductor transistor (e.g., an indium gallium zinc oxide thin-film transistor), or some transistors can be silicon semiconductor transistors (e.g., low-temperature polycrystalline silicon thin-film transistors) and some transistors can be oxide semiconductor transistors (e.g., indium gallium zinc oxide thin-film transistors).
[0093] Specifically, each transistor in the embodiments of this application can be an N-type transistor.
[0094] Specifically, the first electrode can be the source and the second electrode can be the drain; or the first electrode can be the drain and the second electrode can be the source.
[0095] Specifically, it is understood that, since the gate drive circuit in the embodiments of this application adds a pull-down capacitor, even if the dimensions of the pull-down transistor (including the length and width of its gate, the length and width of its source, the length and width of its drain, etc.) remain unchanged, the ratio of the capacitance formed by the gate and source of the pull-down transistor to the total capacitance will inevitably decrease, thereby reducing leakage current.
[0096] Specifically, it is understood that the above embodiments, in order to illustrate the specific design of each structure, have divided a structure. It is also understood that, without considering the influence of factors such as impedance, multiple structures with different labels are actually multiple parts of a single structure. The signals on this structure are the same and can be named with the same label. For example, the first electrode of the first pull-down sustaining transistor T32, the second electrode of the second pull-down sustaining transistor T42, and the second plate of the second sub-capacitor Ckt are actually three parts of the same structure. The first branch electrode and the second branch electrode are derived from the parts of this structure corresponding to the first pull-down sustaining transistor T32. In other words, the above structures transmit the same signal and can be labeled with the same number. Similarly, other similar designs can be found in the above description.
[0097] Specifically, the above embodiments have described some embodiments of the display panel from the aspects of circuit and film layer. It is understood that when there is no conflict between the embodiments, the embodiments can be combined, separated, or separated and then combined. For example, the first plate of the pull-down capacitor 214 is electrically connected to the second node K, the second plate of the pull-down capacitor 214 is electrically connected to the low potential power supply terminal VSS, the pull-down sustaining module 212 includes a first pull-down sustaining transistor T32 and a second pull-down sustaining transistor T42, the gate of the first pull-down sustaining transistor T32 is electrically connected to the second node K, and the first pull-down sustaining transistor... The first electrode of T32 is electrically connected to the low-potential power supply terminal VSS, and the second electrode of the first pull-down sustaining transistor T32 is electrically connected to the signal output terminal G(N); the gate of the second pull-down sustaining transistor T42 is electrically connected to the second node K, the first electrode of the second pull-down sustaining transistor T42 is electrically connected to the low-potential power supply terminal VSS, and the second electrode of the second pull-down sustaining transistor T42 is electrically connected to the first node Q; wherein, the first plate of the pull-down capacitor 214 is electrically connected to the gate of the first pull-down sustaining transistor T32 and the gate of the second pull-down sustaining transistor T42. Alternatively, the first plate of the pull-down capacitor 214 is electrically connected to the second node K, and the second plate of the pull-down capacitor 214 is electrically connected to the low-potential power supply terminal VSS. The display panel 1 includes a substrate 311, a gate layer 312, and a source-drain layer 315. The gate layer 312 is disposed on one side of the substrate 311 and includes the gate of the first pull-down sustaining transistor T32, the gate of the second pull-down sustaining transistor T42, and the first plate of the pull-down capacitor. The source-drain layer 315 is disposed away from the gate layer 312. On one side of the substrate 311, the source-drain layer 315 includes a first electrode of the first pull-down sustaining transistor T32, a first electrode of the second pull-down sustaining transistor T42, and a second electrode of the pull-down capacitor 214; wherein the gate of the first pull-down sustaining transistor T32, the gate of the second pull-down sustaining transistor T42, and the first electrode of the pull-down capacitor are connected, and the first electrode of the first pull-down sustaining transistor T32, the first electrode of the second pull-down sustaining transistor T42, and the second electrode of the pull-down capacitor 214 are connected.
[0098] Meanwhile, this application provides a display device, which includes a display panel as described in any of the above embodiments.
[0099] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0100] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0101] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.
[0102] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A display panel, characterized in that, The system includes multiple cascaded gate drive circuits, each of which includes: A pull-up module is electrically connected to the first node. The pull-up module is configured to connect the clock signal line to the signal output terminal of the gate drive circuit of this stage according to the potential of the first node, or to disconnect the electrical connection between the clock signal line and the signal output terminal. The pull-down sustaining module is electrically connected to the first node and the low-potential power supply terminal; An inverting module, one end of which is electrically connected to the first node, and the other end of which is electrically connected to the pull-down sustaining module at the second node, wherein the inverting module is configured to control the pull-down sustaining module to connect the low-potential power supply terminal to the first node or disconnect the electrical connection between the low-potential power supply terminal and the first node according to the potential of the first node. The gate drive circuit further includes a pull-down capacitor, at least one of the first node and the second node is electrically connected to the first plate of the pull-down capacitor, and the second plate of the pull-down capacitor is electrically connected to the low-potential power supply terminal. The pull-down capacitor includes a first sub-capacitor and a second sub-capacitor. The first plate of the first sub-capacitor is electrically connected to the first node, and the second plate of the first sub-capacitor is electrically connected to the low-potential power supply terminal. The first plate of the second sub-capacitor is electrically connected to the second node, and the second plate of the second sub-capacitor is electrically connected to the low-potential power supply terminal. The pull-down sustaining module includes a first pull-down sustaining transistor and a second pull-down sustaining transistor. The gate of the first pull-down sustaining transistor is electrically connected to the second node, the first electrode of the first pull-down sustaining transistor is electrically connected to the low-potential power supply terminal, and the second electrode of the first pull-down sustaining transistor is electrically connected to the signal output terminal. The gate of the second pull-down sustaining transistor is electrically connected to the second node, the first electrode of the second pull-down sustaining transistor is electrically connected to the low-potential power supply terminal, and the second electrode of the second pull-down sustaining transistor is electrically connected to the first node. The first plate of the second sub-capacitor is electrically connected to the gates of both the first and second pull-down sustaining transistors. The inverting module includes a first inverting transistor, a second inverting transistor, a third inverting transistor, and a fourth inverting transistor. The gate of the first inverting transistor is electrically connected to a high-potential power supply terminal, and its first electrode is also electrically connected to the high-potential power supply terminal. The gate of the second inverting transistor is electrically connected to the first node, its first electrode is electrically connected to the low-potential power supply terminal, and its second electrode is electrically connected to the second electrode of the first inverting transistor at a third node. The gate of the third inverting transistor is electrically connected to the second electrode of the first inverting transistor at the third node, its first electrode is electrically connected to the high-potential power supply terminal, and its second electrode is electrically connected to the pull-down sustaining module at the second node. The gate of the fourth inverting transistor is electrically connected to the first node, its first electrode is electrically connected to the low-potential power supply terminal, and its second electrode is electrically connected to the second node. The first plate of the first sub-capacitor is electrically connected to the gates of the second and fourth inverting transistors. The display panel includes a substrate, a gate layer, and a source / drain layer. The gate layer is disposed on one side of the substrate and includes the gate of the first pull-down sustaining transistor, the gate of the second pull-down sustaining transistor, the gate of the second inverting transistor, the gate of the fourth inverting transistor, the first electrode of the first sub-capacitor, and the first electrode of the second sub-capacitor. The source / drain layer is disposed on the side of the gate layer away from the substrate and includes the first electrode of the first pull-down sustaining transistor, the first electrode of the second pull-down sustaining transistor, the first electrode of the second inverting transistor, the first electrode of the fourth inverting transistor, the second electrode of the first sub-capacitor, and the second electrode of the second sub-capacitor. Wherein, the gate of the first pull-down sustaining transistor, the gate of the second pull-down sustaining transistor, and the first plate of the second sub-capacitor are connected, and the first electrode of the first pull-down sustaining transistor, the first electrode of the second pull-down sustaining transistor, and the second plate of the second sub-capacitor are connected; And / or, the gate of the second inverting transistor, the gate of the fourth inverting transistor, and the first plate of the first sub-capacitor are connected, and the first electrode of the second inverting transistor, the first electrode of the fourth inverting transistor, and the second plate of the first sub-capacitor are connected.
2. The display panel according to claim 1, characterized in that, The first electrode of the first pull-down sustaining transistor includes a first branch electrode and a second branch electrode. The first branch electrode and the second branch electrode are arranged along a first direction. The length of the first branch electrode in the second direction is greater than the length of the second branch electrode in the second direction. The second plate of the second sub-capacitor and the portion of the first branch electrode that extends beyond the second branch electrode are arranged along the first direction. In the second direction, the second plate of the second sub-capacitor is located between the second branch electrode and the first electrode of the second pull-down sustaining transistor; the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.
3. The display panel according to claim 1, characterized in that, The second plate of the first sub-capacitor is located between the first electrode of the second inverting transistor and the first electrode of the fourth inverting transistor.
4. The display panel according to claim 1, characterized in that, The display panel further includes a pixel conductive layer, which is disposed on the side of the source / drain layer away from the gate layer; The pixel conductive layer is electrically connected to at least one of the gates of the first pull-down sustaining transistor, the second pull-down sustaining transistor, the second inverting transistor, and the fourth inverting transistor.
5. The display panel according to claim 4, characterized in that, The pixel conductive layer includes a first transparent conductive portion and a second transparent conductive portion. The first transparent conductive portion is connected to the gate of the first pull-down sustaining transistor and the gate of the second pull-down sustaining transistor, and the second transparent conductive portion is connected to the gate of the second inverting transistor and the gate of the fourth inverting transistor.
6. The display panel according to any one of claims 1 to 5, characterized in that, The gate driving circuit further includes: A pull-up control module includes a pull-up control transistor, wherein the gate and a first electrode of the pull-up control transistor are configured to receive a pull-up control signal, and a second electrode of the pull-up control transistor is electrically connected to the first node. A pull-down module includes a first pull-down transistor and a second pull-down transistor. The gate of the first pull-down transistor is configured to receive a first pull-down control signal. The first electrode of the first pull-down transistor is electrically connected to the low-potential power supply terminal, and the second electrode of the first pull-down transistor is electrically connected to the signal output terminal. The gate of the second pull-down transistor is configured to receive a second pull-down control signal. The first electrode of the second pull-down transistor is electrically connected to the low-potential power supply terminal, and the second electrode of the second pull-down transistor is electrically connected to the first node. A reset module includes a first reset transistor and a second reset transistor. The gate of the first reset transistor is connected to a reset signal line, the first electrode of the first reset transistor is electrically connected to the low-potential power supply terminal, and the second electrode of the first reset transistor is electrically connected to the signal output terminal. The gate of the second reset transistor is connected to a reset signal line, the first electrode of the second reset transistor is electrically connected to the low-potential power supply terminal, and the second electrode of the second reset transistor is electrically connected to the first node. A storage capacitor, one plate of which is electrically connected to the first node, and the other plate of which is electrically connected to the signal output terminal.
7. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 6.