Gate driver and display device including the same

Abstract

The present invention relates to a gate driver and a display device including the same. The display device includes gate lines and pixels connected to the gate lines. The display device includes stages providing gate signals to the gate lines and first and second gate power lines transmitting a first voltage to the stages. A first stage among the stages includes a first node controller and a first output unit. The first node controller is connected to the second gate power line and controls a voltage of a first control node. The first output unit is connected to the first gate power line and outputs the first voltage of the first gate power line as the gate signal in response to the voltage of the first control node.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0068442, filed on June 5, 2020, and all benefits derived from that application, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure generally relates to gate drivers and display devices including such gate drivers. Background Technology

[0003] Display devices typically include a data driver, a gate driver, and pixels. The data driver provides data signals to the pixels via data lines. The gate driver generates gate signals using an externally supplied gate power supply and a clock signal, and sequentially provides these gate signals to the pixels via gate lines. For example, the gate driver outputs a gate power supply as a gate signal with an on level in response to a clock signal. Each pixel in the display can receive a corresponding data signal in response to the gate signal and emit light accordingly.

[0004] In a display device, when a gate signal is supplied to a gate line, fluctuations may occur in the gate power supply as the line capacitance of the gate line is charged. Since the gate signal is output sequentially, periodic fluctuations (or ripples) may occur in the gate power supply that forms the basis of the gate signal, and fluctuations may also occur in the gate signal generated based on the gate power supply.

[0005] A pixel receiving a data signal at a moment when fluctuations occur in the grating signal may emit light with a different brightness than a pixel receiving a data signal at a moment when no fluctuations occur in the grating signal. That is, a brightness difference may occur due to fluctuations in the grating signal. Summary of the Invention

[0006] The embodiments provide a display device capable of reducing or preventing brightness differences caused by fluctuations in the gate signal.

[0007] According to embodiments of this disclosure, a display device includes: a first gate power line, a second gate power line, and a third gate power line, each of which is applied with a first voltage, wherein the first, second, and third gate power lines extend to be spaced apart from each other; and a first gate driver including multiple stages for outputting multiple gate signals. In such an embodiment, each of the first and second stages includes a capacitor and multiple transistors connected to each other, and the first and second stages have identical structures. In such an embodiment, a first electrode of a first transistor in the first stage is connected to the first gate power line, a second electrode of the first transistor in the first stage is connected to an output terminal of the first stage, a first electrode of a first transistor in the second stage is connected to the second gate power line, and a second electrode of the first transistor in the second stage is connected to an output terminal of the second stage.

[0008] In an embodiment, each of the first and second stages may further include a second transistor, the second transistor including a first electrode connected to a third gate power line.

[0009] In one embodiment, the display device may further include a reference gate power line. In such an embodiment, the first stage may further include a pull-down transistor, which includes a first electrode connected to an output terminal and a second electrode connected to the reference gate power line.

[0010] In an embodiment, the display device may further include a first clock signal line, a second clock signal line, and a start signal line. In such an embodiment, the first stage may further include: a zeroth transistor, including a first electrode, a second electrode connected to a start signal line or an output unit of a previous stage, and a gate electrode connected to a first clock signal line; a third transistor, including a first electrode connected to a second electrode of a second transistor, a second electrode connected to a second clock signal line, and a gate electrode connected to a gate electrode of a pull-down transistor; a fourth transistor, including a first electrode connected to a gate electrode of a second transistor, a second electrode connected to a first clock signal line, and a gate electrode connected to a second electrode of the zeroth transistor; a fifth transistor, including a first electrode connected to a first electrode of the fourth transistor, a second electrode connected to a reference gate power line, and a gate electrode connected to the first clock signal line; a first coupling transistor, including a first electrode and a second electrode connected to a first electrode of the fifth transistor, and a gate electrode connected to a reference gate power line; a coupling capacitor, including a first electrode and a second electrode connected to a second electrode of the first coupling transistor; a sixth transistor, including a first electrode connected to a gate electrode of the first transistor, a second electrode connected to a second electrode of the coupling capacitor, and a gate electrode connected to a second clock signal line; and a seventh transistor, including a first electrode connected to a second electrode of the coupling capacitor, a second electrode connected to a second clock signal line, and a gate electrode connected to a first electrode of the coupling capacitor.

[0011] In an embodiment, the first stage may further include: a capacitor including a first electrode connected to a second electrode of a second transistor and a second electrode connected to a gate electrode of a third transistor; and a second coupling transistor including a first electrode connected to a second electrode of a zeroth transistor, a second electrode connected to a gate electrode of a pull-down transistor, and a gate electrode connected to a reference gate power line.

[0012] In an embodiment, the first stage may further include: an eighth transistor, including a first electrode connected to a first gate power line, a second electrode connected to a gate electrode of the first transistor, and a gate electrode connected to a second electrode of a zeroth transistor; and a first capacitor, including a first electrode connected to the first gate power line and a second electrode connected to a gate electrode of the first transistor.

[0013] In an embodiment, the first stage may further include a reset transistor, which includes a first electrode connected to a first gate power line, a second electrode connected to a second electrode of a zeroth transistor, and a gate electrode connected to the reset line.

[0014] In an embodiment, the first stage may further include: an eighth transistor, including a first electrode connected to a third gate power line, a second electrode connected to a gate electrode of the first transistor, and a gate electrode connected to a second electrode of the zeroth transistor; and a first capacitor, including a first electrode connected to the first gate power line and a second electrode connected to a gate electrode of the first transistor.

[0015] In an embodiment, the first stage may further include: a first auxiliary transistor, including a first electrode, a second electrode, and a gate electrode connected to a start signal line or an output unit of a previous stage; a second auxiliary transistor, including a first electrode connected to the second electrode of the first auxiliary transistor, a second electrode connected to the gate electrode of a third transistor, and a gate electrode connected to a reference gate power line; and a third auxiliary transistor, including a first electrode connected to the gate electrode of the third transistor, a second electrode connected to the gate electrode of a pull-down transistor, and a gate electrode connected to the gate electrode of the third transistor.

[0016] In an embodiment, the first stage may further include: an eighth transistor, including a first electrode connected to a third gate power line, a second electrode connected to a gate electrode of the first transistor, and a gate electrode connected to a second electrode of the zeroth transistor; and a first capacitor, including a first electrode connected to the first gate power line and a second electrode connected to a gate electrode of the first transistor.

[0017] In an embodiment, the display device may further include a second gate driver comprising multiple stages of outputting multiple gate signals, wherein a first gate power line, a second gate power line, and a third gate power line may extend from the first gate driver to the second gate driver along the edge of the display device.

[0018] In one embodiment, one end of the first gate power line, the second gate power line, and the third gate power line may be connected to each other.

[0019] According to another embodiment of this disclosure, a display device includes: a display unit including a plurality of gate lines and a plurality of pixels connected to the plurality of gate lines; and a first gate driver including a plurality of stages for providing a plurality of gate signals to the plurality of gate lines and a plurality of gate power lines for transmitting a first voltage to the plurality of stages. In such an embodiment, the first stage among the plurality of stages includes: a first node controller connected to a second gate power line among the plurality of gate power lines, wherein the first node controller can control the voltage of a first control node; and a first output unit connected to the first gate power line among the plurality of gate power lines, wherein the first output unit can output a first voltage of the first gate power line as a gate signal in response to the voltage of the first control node. In such an embodiment, substantially the same voltage is applied to the first gate power line and the second gate power line.

[0020] In an embodiment, the output terminal of the first stage can be connected to two or more of the multiple gate lines.

[0021] In an embodiment, a second stage adjacent to the first stage among a plurality of stages may include: a second node controller connected to the first gate power line, wherein the second node controller can control the voltage of the first control node in the second stage; and a second output unit connected to the second gate power line, wherein the second output unit can output a first voltage of the second gate power line as a gate signal in response to the voltage of the first control node in the second stage.

[0022] In one embodiment, the display device may further include a reference gate power line that is different from the gate power line. In such an embodiment, the first output unit may include: a pull-up transistor including a first electrode connected to the first gate power line, a second electrode connected to an output terminal, and a gate electrode connected to a first control node; and a pull-down transistor including a first electrode connected to the output terminal, a second electrode connected to the reference gate power line, and a gate electrode connected to a second control node.

[0023] In an embodiment, the display device may further include a first clock signal line, a second clock signal line, and a start signal line. In such an embodiment, the first node controller may include: a first transistor including a first electrode, a second electrode connected to a start signal line or an output unit of a previous stage, and a gate electrode connected to a first clock signal line; a second transistor including a first electrode, a second electrode, and a gate electrode connected to a second gate power line; a third transistor including a first electrode connected to the second electrode of the second transistor, a second electrode connected to the second clock signal line, and a gate electrode connected to a second control node; a fourth transistor including a first electrode connected to the gate electrode of the second transistor, a second electrode connected to the first clock signal line, and a gate electrode connected to the second electrode of the first transistor; a fifth transistor including a first electrode connected to the first electrode of the fourth transistor, a second electrode connected to a reference gate power line, and a gate electrode connected to the first clock signal line; a first coupling transistor including a first electrode and a second electrode connected to the first electrode of the fifth transistor, and a gate electrode connected to the reference gate power line; a coupling capacitor including a first electrode and a second electrode connected to the second electrode of the first coupling transistor; a sixth transistor including a first electrode connected to the first control node, a second electrode connected to the second electrode of the coupling capacitor, and a gate electrode connected to the second clock signal line; and a seventh transistor including a first electrode connected to the second electrode of the coupling capacitor, a second electrode connected to the second clock signal line, and a gate electrode connected to the first electrode of the coupling capacitor.

[0024] In an embodiment, the first node controller may further include: a capacitor including a first electrode connected to a second electrode of a second transistor and a second electrode connected to a gate electrode of a third transistor; and a second coupling transistor including a first electrode connected to a second electrode of the first transistor, a second electrode connected to a second control node, and a gate electrode connected to a reference gate power line.

[0025] In an embodiment, the first stage may further include: an eighth transistor, including a first electrode connected to a first gate power line, a second electrode connected to a first control node, and a gate electrode connected to the second electrode of the first transistor; and a first capacitor, including a first electrode connected to the first gate power line and a second electrode connected to the first control node.

[0026] In an embodiment, the first stage may further include a reset transistor, which includes a first electrode connected to a first gate power line, a second electrode connected to a second electrode of the first transistor, and a gate electrode connected to the reset line.

[0027] In an embodiment, the first stage may further include: an eighth transistor, including a first electrode connected to a second gate power line, a second electrode connected to a first control node, and a gate electrode connected to the second electrode of the first transistor; and a first capacitor, including a first electrode connected to the first gate power line and a second electrode connected to the first control node.

[0028] In an embodiment, the first node controller may further include: a first auxiliary transistor, including a first electrode, a second electrode, and a gate electrode connected to a start signal line or an output unit of a previous stage; a second auxiliary transistor, including a first electrode connected to the second electrode of the first auxiliary transistor, a second electrode connected to the gate electrode of a third transistor, and a gate electrode connected to a reference gate power line; and a third auxiliary transistor, including a first electrode connected to the gate electrode of the third transistor, a second electrode connected to the second control node, and a gate electrode connected to the gate electrode of the third transistor.

[0029] In an embodiment, the first stage may further include: an eighth transistor, including a first electrode connected to a second gate power line, a second electrode connected to a first control node, and a gate electrode connected to the second electrode of the first transistor; and a first capacitor, including a first electrode connected to the first gate power line and a second electrode connected to the first control node.

[0030] In one embodiment, multiple gate power lines may be separated from each other in the first gate driver and connected to each other outside the first gate driver.

[0031] In one embodiment, the display device may further include a second gate driver that provides a plurality of gate signals to a plurality of gate lines. In such an embodiment, a first gate driver may be arranged on one side of the display unit, and a second gate driver may be arranged on the other side of the display unit. In such an embodiment, gate power lines may extend from the first gate driver to the second gate driver along the edge of the display unit.

[0032] In one embodiment, each of the plurality of stages may include a first power input terminal and a second power input terminal. In such an embodiment, the first power input terminals of the odd-numbered stages and the second power input terminals of the even-numbered stages may be connected to a first gate power line, and the second power input terminals of the odd-numbered stages and the first power input terminals of the even-numbered stages may be connected to a second gate power line.

[0033] In one embodiment, the display device may further include a first clock signal line and a second clock signal line. In such an embodiment, each of the plurality of stages may further include a first clock input terminal and a second clock input terminal. In such an embodiment, the first clock input terminals of the odd-numbered stages and the second clock input terminals of the even-numbered stages may be connected to the first clock signal line, and the second clock input terminals of the odd-numbered stages and the first clock input terminals of the even-numbered stages may be connected to the second clock signal line.

[0034] In an embodiment, a second stage adjacent to the first stage among a plurality of stages includes: a second node controller connected to a second gate power line, wherein the second node controller can control the voltage of a first control node in the second stage; and a second output unit connected to a third gate power line among a plurality of gate power lines, wherein the second output unit can output a first voltage of the third gate power line as a gate signal in response to the voltage of the first control node in the second stage.

[0035] In such an embodiment, substantially the same voltage can be applied to the first gate power line, the second gate power line, and the third gate power line.

[0036] In one embodiment, each of the plurality of stages may include a first power input terminal and a second power input terminal. In such an embodiment, the second power input terminal of each of the plurality of stages may be connected to a second gate power line. In such an embodiment, the first power input terminals of the odd-numbered stages may be connected to a first gate power line, and the first power input terminals of the even-numbered stages may be connected to a third gate power line.

[0037] In an embodiment, the first stage may further include: an eighth transistor, including a first electrode connected to a second gate power line and a second electrode connected to a first control node; and a first capacitor, including a first electrode connected to a first gate power line and a second electrode connected to a first control node.

[0038] In an embodiment, the first stage may further include: an eighth transistor, including a first electrode connected to a first gate power line and a second electrode connected to a first control node; and a first capacitor, including a first electrode connected to a first gate power line and a second electrode connected to a first control node.

[0039] In an embodiment, the display device may further include a first clock signal line, a second clock signal line, a start signal line, and a reference gate power line different from the gate power line. In such an embodiment, the first node controller may include: a first transistor including a first electrode, a second electrode connected to the start signal line or the output unit of a previous stage, and a gate electrode connected to the first clock signal line; a second transistor including a first electrode, a second electrode, and a gate electrode connected to the second gate power line; a third transistor including a first electrode connected to the second electrode of the second transistor, a second electrode connected to the second clock signal line, and a gate electrode connected to the second control node; a first auxiliary transistor including a first electrode, a second electrode connected to the start signal line or the output unit of a previous stage, and a gate electrode connected to the first clock signal line; a second auxiliary transistor including a first electrode connected to the second electrode of the first auxiliary transistor, a second electrode connected to the gate electrode of the third transistor, and a gate electrode connected to the reference gate power line; and a third auxiliary transistor including a first electrode connected to the gate electrode of the third transistor, a second electrode connected to the second control node, and a gate electrode connected to the gate electrode of the third transistor.

[0040] In an embodiment, the first stage may further include: an eighth transistor, including a first electrode connected to a second gate power line, a second electrode connected to a first control node, and a gate electrode connected to the second electrode of the first transistor; and a first capacitor, including a first electrode connected to the first gate power line and a second electrode connected to the first control node.

[0041] In one embodiment, the first gate power line, the second gate power line, and the third gate power line may be separated from each other in the first gate driver and connected to each other outside the first gate driver.

[0042] According to another embodiment of this disclosure, a display device includes: a substrate including a display area, a non-display area, and a pad area separated from each other; a plurality of gate lines and a plurality of pixels disposed on the substrate in the display area, wherein the plurality of pixels are connected to the plurality of gate lines; a gate driver disposed on the substrate in the non-display area, wherein the gate driver includes a plurality of stages connected to the plurality of gate lines; gate power pads disposed on the substrate in the pad area; and a plurality of gate power lines disposed on the substrate, wherein the plurality of gate power lines connect the gate power pads to the plurality of stages. In such an embodiment, the plurality of gate power lines are separated from each other in the non-display area and connected to each other in the pad area.

[0043] In an embodiment, each of the multiple stages may be connected to two or more of the multiple gate lines.

[0044] In one embodiment, each of the plurality of stages may include a first power input terminal and a second power input terminal. In such an embodiment, the first power input terminals of the odd-numbered stages and the second power input terminals of the even-numbered stages may be connected to a first grid power line among a plurality of grid power lines, and the second power input terminals of the odd-numbered stages and the first power input terminals of the even-numbered stages may be connected to a second grid power line among a plurality of grid power lines.

[0045] In one embodiment, each of the plurality of stages may include a first power input terminal and a second power input terminal. The second power input terminal of each of the plurality of stages may be connected to a second gate power line among the plurality of gate power lines. In such an embodiment, the first power input terminals of the odd-numbered stages may be connected to a first gate power line among the plurality of gate power lines, and the first power input terminals of the even-numbered stages may be connected to a third gate power line among the plurality of gate power lines.

[0046] According to another embodiment of this disclosure, the display device includes: multiple stages for providing multiple gate signals to multiple gate lines; and multiple gate power lines for transmitting a first voltage to the multiple stages, wherein the first voltage is a DC voltage. In such an embodiment, the first stage of the multiple stages includes: a first node controller connected to a second gate power line among the multiple gate power lines, wherein the first node controller controls the voltage of a first control node; and a first output unit connected to the first gate power line among the multiple gate power lines, wherein the first output unit outputs the first voltage of the first gate power line as a gate signal in response to the voltage of the first control node. In such an embodiment, substantially the same voltage is applied to the first gate power line and the second gate power line. Attached Figure Description

[0047] The above and other features of the invention will become more apparent from the accompanying drawings, which describe embodiments of the invention in a further detailed manner with reference to the drawings, in which:

[0048] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0049] Figure 2A and Figure 2B It is a diagram. Figure 1 A plan view of an embodiment of the display device shown;

[0050] Figure 3 It is a diagram. Figure 2A A circuit diagram of an embodiment of pixels included in the display device shown;

[0051] Figure 4 It is a diagram. Figure 2A and Figure 2B A diagram showing an embodiment of a compensation gate driver included in the display device;

[0052] Figure 5 It is a diagram. Figure 4 The circuit diagram shows an embodiment of the first compensation stage and the second compensation stage included in the compensated gate driver shown.

[0053] Figure 6 It is a diagram. Figure 5 Waveform diagram of an embodiment of the signal in the first compensation stage shown;

[0054] Figure 7A It is a diagram. Figure 2A A diagram showing an embodiment of a gate driver included in a display device;

[0055] Figure 7B It is a diagram. Figure 7A Waveform diagram of an embodiment of the signal in the gate driver shown;

[0056] Figure 8 It is a diagram. Figure 7A Waveform diagram of a comparative example of the signal in the gate driver shown;

[0057] Figure 9 It is a diagram. Figure 4 Circuit diagram of alternative embodiments of the first and second compensation stages included in the compensated gate driver shown;

[0058] Figure 10 It is a diagram. Figure 4 A circuit diagram of another alternative embodiment of the first and second compensation stages included in the compensated gate driver shown;

[0059] Figure 11 It is a diagram. Figure 4A circuit diagram of yet another alternative embodiment of the first and second compensation stages included in the compensated gate driver shown.

[0060] Figure 12A , Figure 12B , Figure 12C and Figure 12D It is a diagram. Figure 1 Plan view of alternative embodiments of the display device shown;

[0061] Figure 13 It is a diagram. Figures 12A to 12D A diagram showing an embodiment of a compensation gate driver included in the display device;

[0062] Figure 14 It is a diagram. Figure 13 The circuit diagram shown illustrates an embodiment of the first and second compensation stages included in the compensated gate driver; and

[0063] Figure 15 , Figure 16 and Figure 17 It is a diagram. Figure 13 The circuit diagrams shown are of various embodiments of the first compensation stage and the second compensation stage included in the compensated gate driver. Detailed Implementation

[0064] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals throughout refer to the same elements.

[0065] It will be understood that when a component is referred to as being "on" another component, the component can be directly "on" the other component, or there can be an intermediate component between the component and the other component. Conversely, when a component is referred to as being "directly" "on" another component, there is no intermediate component.

[0066] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, without departing from the teachings herein, “first element,” “first component,” “first area,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second area, second layer, or second part.

[0067] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “the,” and “at least one” do not refer to a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” is not to be construed as limiting “a.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the items listed. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0068] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another as illustrated in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to cover different orientations of the device. For example, if a device in one of the drawings is flipped, an element described as being “below” the other elements will be oriented as being “above” the other elements. Thus, depending on the specific orientation of the drawing, the term “below” can cover both “below” and “above” orientations. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” the other elements will be oriented as being “above” the other elements. Thus, the terms “below” and “under” can cover both “above” and “below” orientations.

[0069] Considering the measurements discussed and the errors associated with the measurement of a specific quantity (i.e., limitations of the measurement system), the terms "approximately" or "about" as used herein include the stated values ​​and mean within an acceptable deviation of the specific values ​​as determined by one of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated values.

[0070] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having meanings consistent with their meanings in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein. Furthermore, for better understanding and ease of description, the dimensions and thicknesses of each component illustrated in the accompanying drawings are shown arbitrarily, and this disclosure is not limited thereto.

[0071] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0072] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0073] refer to Figure 1 An embodiment of the display device DD may include a timing controller TC, a data driver DDV, a gate driver GDV, and a display unit DP (or display panel). In such an embodiment, the display device DD may further include a power supply PS.

[0074] The timing controller (TC) can receive external input signals from an external source (e.g., an external processor). These external input signals may include vertical synchronization signals, horizontal synchronization signals, data enable signals, image data (e.g., RGB data), and clock signals.

[0075] The vertical synchronization signal may include multiple pulses. At the moment each pulse is generated, a previous frame period may end and a current frame period may begin. The interval between adjacent pulses in the vertical synchronization signal may correspond to a frame period. The horizontal synchronization signal may include multiple pulses. At the moment each pulse is generated, a previous horizontal period may end and a current horizontal period may begin. The interval between adjacent pulses in the horizontal synchronization signal may correspond to a horizontal period. A data enable signal may indicate that RGB data is supplied during a horizontal period. In one embodiment, for example, the RGB data corresponding to the data enable signal may be supplied in pixel rows during the horizontal period (e.g., supplied to pixels connected to the same write gate).

[0076] The timing controller TC can generate grayscale values ​​based on RGB data to correspond to the specifications of the display device DD. In one embodiment, for example, the grayscale value may refer to RGB data reconstructed to correspond to the resolution of the display unit DP, etc.

[0077] In an embodiment, the timing controller TC can generate control signals for the data driver DDV and the gate driver GDV based on external input signals to correspond to the specifications of the display device DD.

[0078] The data driver DDV can generate a data voltage (or data signal) using grayscale values ​​and control signals received from the timing controller TC, and supply the data voltage to data lines DL1, DL2, ..., DLm. Here, m can be a positive integer. In one embodiment, for example, the data driver DDV can sample grayscale values ​​using a clock signal to generate a data voltage corresponding to the grayscale values, and supply the data voltage to data lines DL1, DL2, ..., DLm in pixel rows.

[0079] The gate driver GDV can receive control signals from the timing controller TC, generate gate signals based on the control signals, and provide the gate signals to the gate lines GWL1, GCL1, GBL1, GIL1, EML1, ..., GWLn, GCLn, GBLn, GILn, and EMLn. Here, n is a positive integer.

[0080] In an embodiment, the gate driver GDV receives a gate power voltage (e.g., a voltage with a logic high level) from the power supply PS via the gate power line VGHL, and provides a gate signal with pulses of the gate power voltage to gate lines GWL1, GCL1, GBL1, GIL1, EML1, ..., GWLn, GCLn, GBLn, GILn, and EMLn (e.g., compensating gate lines GCL1, ..., and GCLn). The gate power voltage supplied via the gate power line VGHL is in direct current ("DC") form and may have the same voltage level.

[0081] Please refer to later Figure 2A , Figure 2B and Figure 5 The configuration of the gate driver GDV is described in more detail.

[0082] The display unit DP includes pixels. In one embodiment, for example, the pixel PXLnm can be connected to the corresponding data line DLm, the corresponding write gate line GWLn, the corresponding compensation gate line GCLn, the corresponding bypass gate line GBLn, the corresponding initialization gate line GILn, and the corresponding emit gate line EMLn.

[0083] The power supply PS can supply the gate voltage to the gate driver GDV through the gate power line VGHL.

[0084] In one embodiment, the power supply PS can be implemented as a separate integrated circuit, but this disclosure is not limited thereto. In an alternative embodiment, for example, the power supply PS together with the data driver DDV can be implemented as a single integrated circuit. In such an embodiment, the gate power voltage can be supplied from the data driver DDV to the gate driver GDV.

[0085] Figure 2A and Figure 2BIt is a diagram. Figure 1 A plan view of an embodiment of the display device shown. Figure 2A and Figure 2B The diagram below briefly illustrates a display device DD based on a gate driver GDV.

[0086] In the embodiment, reference Figure 1 and Figure 2A The display device may include a substrate SUB.

[0087] The substrate SUB may include a display area A_DP and a non-display area located on at least one side of the display area A_DP. The non-display area may include a pad area A_PD and a gate circuit area A_GDV (or a first gate circuit area). The display area A_DP, the pad area A_PD, and the gate circuit area A_GDV may be distinguishable from each other. In one embodiment, for example, the pad area A_PD may be located below the display area A_DP, and the gate circuit area A_GDV may be located to the left of the display area A_DP.

[0088] Data lines DL1, ..., and DLm, gate lines GWLn, GCLn, GBLn, GILn, and EMLn, and pixel PXLnm can be arranged or provided in the display area A_DP of the substrate SUB. The display area A_DP of the substrate SUB can correspond to the above reference. Figure 1 The description refers to the display unit DP.

[0089] Pads PD_D1, ..., PD_Dm, PD_GC and PD_GW can be arranged in the pad area A_PD on the substrate SUB.

[0090] Data pads PD_D1, ..., and PD_Dm can be connected to data lines DL1, ..., and DLm, respectively. Data lines DL1, ..., and DLm can be connected to the data drive DDV (see data pads PD_D1, ..., and PD_Dm) via data pads PD_D1, ..., and PD_Dm. Figure 1 ).

[0091] The first gate power pad PD_GC can be connected to the gate power line. In one embodiment, for example, as... Figure 2A As shown, the first gate power pad PD_GC can be connected to the first gate power line VGHL1 and the second gate power line VGHL2. The first gate power line VGHL1 and the second gate power line VGHL2 can be arranged or provided in the non-display area of ​​the substrate SUB, connected to each other in the pad area A_PD, and arranged to be separated from each other in the non-display area outside the pad area A_PD. In an embodiment, the first gate power line VGHL1 and the second gate power line VGHL2 are connected to, as shown... Figure 2AThe first gate power pad PD_GC is illustrated in the figure, but this disclosure is not limited thereto. In an alternative embodiment, for example, when the size of the pad region A_PD is sufficiently large, the first gate power line VGHL1 and the second gate power line VGHL2 can be connected to different power pads, and the same gate power voltage can be applied to the first gate power line VGHL1 and the second gate power line VGHL2 through different power pads. The first gate power pad PD_GC can be connected to the power supply PS (see [reference]). Figure 1 Furthermore, the gate power voltage (e.g., a voltage with a logic high level) can be applied from the power supply PS to the first gate power pad PD_GC.

[0092] The second gate power pad PD_GW can be connected to the write gate power line VGHL_GW and the emit gate power line VGHL_EM. The write gate power line VGHL_GW and the emit gate power line VGHL_EM can be arranged or provided in the non-display area of ​​the substrate SUB and connected to each other in the pad area A_PD. The write gate power line VGHL_GW and the emit gate power line VGHL_EM can be separated from the first gate power line VGHL1 and the second gate power line VGHL2. The second gate power pad PD_GW can be connected to the power supply PS (see...). Figure 1 Furthermore, a gate power voltage (e.g., a voltage with a logic high level) can be applied from the power supply PS to the second gate power pad PD_GW. The voltage level of the gate power voltage applied to the second gate power pad PD_GW can be equal to the voltage level of the gate power voltage applied to the first gate power pad PD_GC, but this disclosure is not limited thereto.

[0093] The gate driver GDV can be formed or arranged in the gate circuit region A_GDV of the substrate SUB.

[0094] The gate driver GDV may include a write gate driver GWDV, a compensation gate driver GCDV (or a first compensation gate driver), and a transmit driver EMDV. The gate circuit region A_GDV of the substrate SUB may include a write gate circuit region A_GWDV, a compensation gate circuit region A_GCDV (or a first compensation gate circuit region), and a transmit circuit region A_EMDV that are distinct from each other, and the write gate driver GWDV, the compensation gate driver GCDV, and the transmit driver EMDV may be arranged or formed in the write gate circuit region A_GWDV, the compensation gate circuit region A_GCDV, and the transmit circuit region A_EMDV, respectively.

[0095] In this embodiment, the write gate driver (GWDV) can be closest to the display unit (DP), the compensation gate driver (GCDV) can be further away from the display unit (DP) than the write gate driver (GWDV), and the transmit driver (EMDV) can be further away from the display unit (DP) than the compensation gate driver (GCDV). (See reference later.) Figure 7B In more detail, since the pulse width of the write gate signal is the smallest, the write gate signal generated by the write gate driver GWDV is most sensitive to resistor-capacitor (“RC”) delay, and since the pulse width of the transmit gate signal is the largest, the transmit gate signal generated by the transmit driver EMDV is least sensitive to RC delay.

[0096] The write gate driver GWDV can be in the form of a shift register and includes multiple write stages. The write gate driver GWDV (or write stages) can be connected to the write gate power line VGHL_GW. The write stages can respond to input from the timing controller TC (see...). Figure 1 Upon receiving a write start signal, write gate signals with on-level (e.g., logic low) are sequentially generated. These on-level write gate signals can be provided to the corresponding write gate lines GWL1, ..., and GWLn (see...). Figure 1 In an embodiment, the write gate signal is used as a bypass gate signal and may also be provided to bypass gate lines GBL1, ..., and GBLn (see...). Figure 1 In one embodiment, for example, a write gate signal generated after a write gate signal applied to write gate line GWLn (i.e., a subsequent write gate signal) may be provided to bypass gate line GBLn as a bypass gate signal. However, this disclosure is not limited thereto. In an alternative embodiment, for example, a write gate signal applied to write gate line GWLn may be provided to bypass gate line GBLn as a bypass gate signal.

[0097] The compensated gate driver GCDV (or initialized gate driver) can be in the form of a shift register and includes multiple compensation stages (or initialization stages). The compensated gate driver GCDV (or each compensation stage in the compensation stage) can be connected to a first gate power line VGHL1 and a second gate power line VGHL2. The compensation stages can respond to input from the timing controller TC (see...). Figure 1 The compensation gate signals are sequentially generated with on-level (e.g., logic high level) in response to the received compensation start signal (or initialization start signal). In one embodiment, for example, each compensation stage in the compensation stage may output one of a first gate power voltage in the first gate power line VGHL1 and a second gate power voltage in the second gate power line VGHL2 as a pulse of the corresponding compensation gate signal. The compensation gate signals may be provided to the corresponding compensation gate lines GCL1, ..., GCLn respectively (see...). Figure 1In one embodiment, for example, the odd-numbered compensation stage in the compensation stage can output the first gate voltage in the first gate power line VGHL1 as a compensation gate signal, and the even-numbered compensation stage in the compensation stage can output the second gate voltage in the second gate power line VGHL2 as a compensation gate signal. Therefore, a drop (or fluctuation) in the second gate voltage (i.e., the second gate voltage in the second gate power line VGHL2) generated when the even-numbered compensation stage outputs the compensation gate signal can have no effect on the first gate voltage in the first gate power line VGHL1. In such an embodiment, although the same gate voltage is applied to both the odd-numbered and even-numbered compensation stages, the first gate power line VGHL1 and the second gate power line VGHL2 used to transmit the gate voltage are separated from each other. In this embodiment, the first gate power line VGHL1 and the second gate power line VGHL2 are connected to each other in the pad region A_PD, such that the drop in the second gate power voltage in the second gate power line VGHL2 is reduced as it passes through the pad region A_PD (i.e., the voltage drop path is lengthened, and an RC delay occurs in the voltage drop due to the capacitance corresponding to this path), and is quickly recovered or charged by the gate power voltage applied to the first gate power pad PD_GC. Therefore, the duration of the ripple of the gate power voltage (i.e., each of the first and second gate power voltages) is increased, and the ripple and brightness difference of the compensated gate signal caused by the ripple of the gate power voltage can be reduced. (Refer to...) Figure 7B This embodiment, in which the ripple and brightness difference of the compensated gate signal are reduced, is described in detail.

[0098] In this embodiment, the compensation gate signal is used as the initialization gate signal, and the compensation gate signal with an on level can also be provided to the corresponding initialization gate lines GIL1, ..., GILn (see...). Figure 1 In one embodiment, for example, a compensation gate signal generated before the compensation gate signal applied to the compensation gate line GCLn (i.e., the previous compensation gate signal) can be provided to the initialization gate line GILn as an initialization gate signal.

[0099] The transmit driver EMDV can be in the form of a shift register and includes multiple transmit stages. The transmit driver EMDV (or transmit stages) can be connected to the transmit gate power line VGHL_EM. The transmit stages can respond to signals from the timing controller TC (see...). Figure 1 The system receives a transmit start signal and sequentially generates transmit gate signals with cutoff levels. Transmit gate signals with cutoff levels (e.g., logic high) can be provided to the corresponding transmit gate lines EML1, ..., EMLn (see...). Figure 1 In one embodiment, for example, the transmitter stage may output the gate power voltage applied to the transmitter gate power line VGHL_EM as a pulse of the transmitter gate signal.

[0100] In an embodiment, such as Figure 2A As shown, the compensation gate driver GCDV can be arranged on one side (e.g., the left side) of the display unit DP, but this disclosure is not limited thereto.

[0101] In alternative embodiments, such as Figure 2B As shown, the substrate SUB may further include a second compensation gate circuit region A_GCDV2 located on the opposite side (e.g., the right side) of the display region A_DP, and a second compensation gate driver GCDV2 may be formed or disposed in the second compensation gate circuit region A_GCDV2. The second compensation gate driver GCDV2 may be included in the gate driver GDV.

[0102] Each of the first gate power line VGHL1' and the second gate power line VGHL2' can extend upwards along the edge of the display area A_DP to the second compensation gate circuit area A_GCDV2. In such an embodiment, as referenced above... Figure 2A As described, the first gate power line VGHL1' and the second gate power line VGHL2' can be connected to each other in the pad area A_PD. The first gate power line VGHL1' and the second gate power line VGHL2' can be unconnected to each other in a non-display area other than the pad area A_PD, and can be arranged to be separated from each other. In such an embodiment, as... Figure 2B As shown, one end of the first gate power line VGHL1' and the second gate power line VGHL2' can be connected to the first gate power pad PD_GC provided in the pad area A_PD, and one end of the first gate power line VGHL1' and the second gate power line VGHL2' can be connected to the third gate power pad PD_GC2 provided in the pad area A_PD.

[0103] Apart from its placement, the second compensation gate driver GCDV2 can be substantially the same as or similar to the compensation gate driver GCDV (or the first compensation gate driver) described above.

[0104] In an embodiment, the second compensated gate driver GCDV2 may be in the form of a shift register and includes multiple compensation stages (or initialization stages). The second compensated gate driver GCDV2 (or each compensation stage in the compensation stages) may be connected to the first gate power line VGHL1' and the second gate power line VGHL2'. The compensation stages may respond to input from the timing controller TC (see...). Figure 1 The compensation gate signal, having an on-state level (e.g., logic high level), is sequentially generated by the received compensation start signal (or initialization start signal). The compensation gate signal generated by the second compensation gate driver GCDV2 can be provided to the corresponding compensation gate lines GCL1, ..., GCLn (see...). Figure 1).

[0105] Compensation gate lines GCL1, ..., and GCLn (see...) Figure 1 The compensation gate signal can be connected to the compensation gate driver GCDV (or the first compensation gate driver) and the second compensation gate driver GCDV2, and the compensation gate signal can be applied to the compensation gate lines GCL1, ..., GCLn from opposite sides of the display unit DP. Therefore, the RC delay of the compensation gate signal can be minimized.

[0106] In this embodiment, the compensation gate signal generated by the second compensation gate driver GCDV2 is used as the initialization gate signal, and can also be provided to the corresponding initialization gate lines GIL1, ..., GILn (see...). Figure 1 ).

[0107] In an embodiment, such as Figure 2B As shown, only the second compensated gate driver GCDV2 can be arranged to the right of the display area A_DP, but this disclosure is not limited thereto. In an alternative embodiment, for example, the second write gate driver and the second transmit driver can be further arranged to the right of the display area A_DP. In such an embodiment, the RC delay of the write gate signal and the RC delay of the transmit gate signal can be minimized.

[0108] In the embodiments, as referenced Figure 2A and Figure 2B The described display device DD includes a first gate power line VGHL1 and a second gate power line VGHL2 (or a first gate power line VGHL1' and a second gate power line VGHL2') connected to a compensation gate driver GCDV (or each compensation stage in the compensation stage). The first gate power line VGHL1 and the second gate power line VGHL2 are connected to each other in a pad area A_PD and are arranged to be separated from each other in a non-display area other than the pad area A_PD.

[0109] Figure 3 It is a diagram. Figure 2A The circuit diagram shows an embodiment of the pixels included in the display device. Figure 2A The pixels included in the display device DD shown are substantially the same or similar to each other, and therefore, for ease of description, only pixel PXLnm will be described in detail below.

[0110] refer to Figure 3 The pixel PXLnm may include thin-film transistors (e.g., first transistor M1 to seventh transistor M7), storage capacitor Cst, and light-emitting diode LD (or light-emitting device).

[0111] In such an embodiment, the first electrode of the first thin-film transistor M1 can be connected to the second node N2, the second electrode of the first thin-film transistor M1 can be connected to the third node N3, and the gate electrode of the first thin-film transistor M1 can be connected to the first node N1. The first thin-film transistor M1 can be referred to as a driving transistor.

[0112] The first thin-film transistor M1 can control the amount of current flowing from the first power line VDD through the light-emitting diode LD to the second power line VSS based on the voltage of the first node N1.

[0113] The first electrode of the second thin-film transistor M2 can be connected to the data line DLm, the second electrode of the second thin-film transistor M2 can be connected to the first electrode (or the second node N2) of the first thin-film transistor M1, and the gate electrode of the second thin-film transistor M2 can be connected to the write gate line GWLn. The second thin-film transistor M2 can be referred to as a switching transistor.

[0114] The second thin-film transistor M2 can be turned on when the write gate signal is supplied to the write gate line GWLn, so as to electrically connect the data line DLm and the first electrode of the first thin-film transistor M1.

[0115] The first electrode of the third thin-film transistor M3 can be connected to the gate electrode (or the first node N1) of the first thin-film transistor M1, the second electrode of the third thin-film transistor M3 can be connected to the second electrode (or the third node N3) of the first thin-film transistor M1, and the gate electrode of the third thin-film transistor M3 can be connected to the compensation gate line GCLn. The third thin-film transistor M3 can be referred to as a compensation transistor.

[0116] The third thin-film transistor M3 can be turned on when the compensation gate signal is supplied to the compensation gate line GCLn, so as to electrically connect the first node N1 and the third node N3. Therefore, when the third thin-film transistor M3 is turned on, the first thin-film transistor M1 can be connected in the form of a diode.

[0117] The first electrode of the fourth thin-film transistor M4 can be connected to the gate electrode (or the first node N1) of the first thin-film transistor M1, the second electrode of the fourth thin-film transistor M4 can be connected to the first initialization line VINTL1, and the gate electrode of the fourth thin-film transistor M4 can be connected to the initialization gate line GILn. The fourth thin-film transistor M4 can be referred to as the initialization transistor.

[0118] The fourth thin-film transistor M4 can be turned on when the initialization gate signal is supplied to the initialization gate line GILn to connect the first node N1 to the first initialization line VINTL1.

[0119] The first electrode of the fifth thin-film transistor M5 can be connected to the first power supply line VDD, the second electrode of the fifth thin-film transistor M5 can be connected to the first electrode (or the second node N2) of the first thin-film transistor M1, and the gate electrode of the fifth thin-film transistor M5 can be connected to the emitter gate line EMLn. The fifth thin-film transistor M5 can be referred to as the first emitter transistor.

[0120] The first electrode of the sixth thin-film transistor M6 can be connected to the second electrode (or third node N3) of the first thin-film transistor M1, the second electrode of the sixth thin-film transistor M6 can be connected to the anode (or anode electrode) of the light-emitting diode LD, and the gate electrode of the sixth thin-film transistor M6 can be connected to the emitter gate line EMLn. The sixth thin-film transistor M6 can be referred to as the second emitter transistor.

[0121] The fifth thin-film transistor M5 and the sixth thin-film transistor M6 can be turned off when an emitter gate signal with a cutoff level is supplied to the emitter gate line EMLn, and turned on when an emitter gate signal with a conduction level is supplied to the emitter gate line EMLn.

[0122] The first electrode of the seventh thin-film transistor M7 can be connected to the anode of the light-emitting diode LD, the second electrode of the seventh thin-film transistor M7 can be connected to the second initialization line VINTL2, and the gate electrode of the seventh thin-film transistor M7 can be connected to the bypass gate line GBLn. The seventh thin-film transistor M7 can be referred to as a bypass transistor.

[0123] The seventh thin-film transistor M7 can be turned on when the bypass gate signal is supplied to the bypass gate line GBLn, so as to connect the anode of the light-emitting diode LD to the second initialization line VINTL2.

[0124] A storage capacitor Cst may be formed or connected between a first power line VDD and the gate electrode (or first node N1) of a first thin-film transistor M1. In one embodiment, for example, a first electrode of the storage capacitor Cst may be connected to the first power line VDD, and a second electrode of the storage capacitor Cst may be connected to the gate electrode of the first thin-film transistor M1. The storage capacitor Cst may store a voltage corresponding to the data voltage and the threshold voltage of the first thin-film transistor M1 (e.g., a voltage obtained by reflecting the threshold voltage of the first thin-film transistor M1 onto the data voltage).

[0125] The anode of the light-emitting diode (LD) can be connected to the second electrode of the sixth thin-film transistor M6, and the cathode (or cathode electrode) of the LD can be connected to the second power supply line VSS. The LD can generate light with a predetermined brightness in accordance with the amount of current supplied from the first thin-film transistor M1.

[0126] Light-emitting diodes (LDs) can be configured as organic light-emitting diodes or inorganic light-emitting diodes such as micro light-emitting diodes or quantum dot light-emitting diodes. Furthermore, LDs can be light-emitting diodes made of organic and inorganic materials, or combinations thereof. In embodiments, such as... Figure 3 As shown, a pixel PXLnm may include a single light-emitting diode (LD), but is not limited thereto. In an alternative embodiment, a pixel PXLnm may include multiple light-emitting diodes, and the multiple light-emitting diodes may be connected in parallel or in series with each other.

[0127] The voltage applied to the first power line VDD can be set to be higher than the voltage applied to the first initialization line VINTL1, the second initialization line VINTL2, and the second power line VSS.

[0128] The first thin-film transistor M1, the second thin-film transistor M2, the fifth thin-film transistor M5, the sixth thin-film transistor M6, and the seventh thin-film transistor M7 can be implemented as P-type transistors. The channels of the first thin-film transistor M1, the second thin-film transistor M2, the fifth thin-film transistor M5, the sixth thin-film transistor M6, and the seventh thin-film transistor M7 can include or be configured with polysilicon. The polysilicon transistor can be a low-temperature polysilicon (“LTPS”) transistor. Polysilicon transistors have high electron mobility and, due to high electron mobility, exhibit fast drive characteristics.

[0129] The third thin-film transistor M3 and the fourth thin-film transistor M4 can be implemented using N-type transistors. The channels of the third thin-film transistor M3 and the fourth thin-film transistor M4 can include or be configured with oxide semiconductors. Oxide semiconductor transistors have a lower charge mobility than polysilicon transistors. Therefore, oxide semiconductor transistors can have a smaller leakage current in the off-state than polysilicon transistors.

[0130] Figure 4 It is a diagram. Figure 2A and Figure 2B A diagram of an embodiment of a compensation gate driver included in the display device shown.

[0131] refer to Figure 2A and Figure 4 An embodiment of the compensated gate driver GCDV may include multiple compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4 (or stages). For ease of illustration and description, in Figure 4 Only a portion of the compensated gate driver GCDV is schematically illustrated in the figure.

[0132] Each of the compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4 may include an input terminal IN0, a first power input terminal IN1, a second power input terminal IN2, a third power input terminal IN3, a first clock input terminal CIN1, a second clock input terminal CIN2, a reset terminal RST, and an output terminal OUT. (See later...) Figure 5 The internal circuit configurations of the compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4 are described as being substantially the same.

[0133] Each of the compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4 can be connected to the first gate power line VGHL1, the second gate power line VGHL2, the reference gate power line VGLL, clock signal lines CLKL1 and CLKL2, and the reset signal line RSTL. The reference gate power voltage can be obtained from the power supply PS (see...). Figure 1 A reference gate power line VGHL1 is applied. The reference gate power voltage may have a lower voltage level (e.g., logic high) than the gate power voltages applied to the first gate power line VGHL1 and the second gate power line VGHL2. A clock signal (or a compensation clock signal) may be generated from the timing controller TC (see...). Figure 1 This is applied to clock signal lines CLKL1 and CLKL2. (See later...) Figure 7B The second clock signal (or second compensation clock signal) applied to the second clock signal line CLKL2, as described, may have a phase opposite to or delayed by 180 degrees from the first clock signal (or first compensation clock signal) applied to the first clock signal line CLKL1. In the display device DD (see...) Figure 1 During the power-on and / or power-off of the sequence controller TC (see...), the reset signal can be obtained from the timing controller TC (see...). Figure 1 A start signal (e.g., a compensation start signal or a compensation start pulse) is applied to the reset signal line RSTL. In such an embodiment, a start signal (e.g., a compensation start signal or a compensation start pulse) can be generated from the timing controller TC (see [link to timing controller]). Figure 1 It is applied to the start signal line STPL.

[0134] In an embodiment, such as Figure 4As shown, in the odd-compensation stages GC_ST1 and GC_ST3, the first power input terminal IN1 can be connected to the first gate power line VGHL1, the second power input terminal IN2 can be connected to the second gate power line VGHL2, the third power input terminal IN3 can be connected to the reference gate power line VGLL, the first clock input terminal CIN1 can be connected to the first clock signal line CLKL1, the second clock input terminal CIN2 can be connected to the second clock signal line CLKL2, and the reset terminal RST can be connected to the reset signal line RSTL.

[0135] In such an embodiment, in the even-numbered compensation stages GC_ST2 and GC_ST4, the first power input terminal IN1 can be connected to the second gate power line VGHL2, the second power input terminal IN2 can be connected to the first gate power line VGHL1, the third power input terminal IN3 can be connected to the reference gate power line VGLL, the first clock input terminal CIN1 can be connected to the second clock signal line CLKL2, the second clock input terminal CIN2 can be connected to the first clock signal line CLKL1, and the reset terminal RST can be connected to the reset signal line RSTL.

[0136] In each of the compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4, the gate power voltage applied to the second power input terminal IN2 can be used to control the voltage of the internal nodes, and the gate power voltage applied to the first power input terminal IN1 can be used to output a compensation gate signal (or as a compensation gate signal output). In such an embodiment, the gate power voltage for controlling the voltage of the internal nodes and the gate power voltage for generating the compensation gate signal can be provided independently to each of the compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4. In such an embodiment, the first gate power line VGHL1 and the second gate power line VGHL2 for transmitting the gate power voltage to the compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4 are connected to each other in the pad region A_PD, such that the voltage drop path is lengthened, reducing the impact of the voltage drop on the other gate power line. Therefore, fluctuations in the gate power voltage for controlling the voltage of the internal nodes have no effect on the gate power voltage for generating the compensation gate signal, and the ripple of the compensation gate signal can be effectively reduced.

[0137] In this embodiment, the connection order of odd-numbered compensation stages GC_ST1 and GC_ST3 to the first gate power line VGHL1 and the second gate power line VGHL2 can be the reverse of the connection order of even-numbered compensation stages GC_ST2 and GC_ST4 to the first gate power line VGHL1 and the second gate power line VGHL2. In this embodiment, when the compensation gate signal is generated, the odd-numbered compensation stages GC_ST1 and GC_ST3 can use a different gate power voltage (i.e., the first gate power voltage applied to the first gate power line VGHL1) than the gate power voltage of the even-numbered compensation stages GC_ST2 and GC_ST4 (i.e., the second gate power voltage applied to the second gate power line VGHL2). Therefore, even if fluctuations occur in the compensation gate signal of a previous compensation stage, these fluctuations do not affect the gate power voltage of subsequent compensation stages or the subsequent compensation gate signal, and the ripple of the compensation gate signal can be reduced.

[0138] Each of the compensation stages GC_ST1, GC_ST2, GC_ST3 and GC_ST4 can be connected to the start signal line STPL or the output terminal of the previous compensation stage, and receives the start signal provided by the start signal line STPL or the previous compensation gate signal corresponding to the compensation gate signal of the previous compensation stage.

[0139] In one embodiment, for example, the input terminal IN0 of the first compensation stage GC_ST1 can be connected to the start signal line STPL. The first compensation stage GC_ST1 can generate a first compensation gate signal (e.g., delayed by half a cycle of the clock signal from the start signal) corresponding to the start signal applied to the start signal line STPL. In one embodiment, for example, the input terminal IN0 of the second compensation stage GC_ST2 can be connected to the output terminal OUT (or the first compensation gate line GCL1) of the first compensation stage GC_ST1. The second compensation stage GC_ST2 can generate a second compensation gate signal (e.g., delayed by half a cycle of the clock signal from the first compensation gate signal) corresponding to the first compensation gate signal. In such an embodiment, the input terminal IN0 of the third compensation stage GC_ST3 can be connected to the output terminal OUT (or the third compensation gate line GCL3) of the second compensation stage GC_ST2. The input terminal IN0 of the fourth compensation stage GC_ST4 can be connected to the output terminal OUT (or the fifth compensation gate line GCL5) of the third compensation stage GC_ST3.

[0140] In such an embodiment, compensation stages GC_ST1, GC_ST2, GC_ST3 and GC_ST4 can sequentially generate compensation gate signals corresponding to the start signal.

[0141] In an embodiment, each of the compensation stages GC_ST1, GC_ST2, GC_ST3 and GC_ST4 can be connected to two of the compensation gate lines GCL1, GCL2, GCL3, GCL4, GCL5, GCL6, GCL7 and GCL8, and these two compensation gate lines can output compensation gate signals simultaneously.

[0142] In one embodiment, for example, the output terminal OUT of the first compensation stage GC_ST1 can be connected to the first compensation gate line GCL1 and the second compensation gate line GCL2. The output terminal OUT of the second compensation stage GC_ST2 can be connected to the third compensation gate line GCL3 and the fourth compensation gate line GCL4. The output terminal OUT of the third compensation stage GC_ST3 can be connected to the fifth compensation gate line GCL5 and the sixth compensation gate line GCL6. The output terminal OUT of the fourth compensation stage GC_ST4 can be connected to the seventh compensation gate line GCL7 and the eighth compensation gate line GCL8. The compensation gate driver GCDV can output compensation gate signals for each pair of gate lines. In such an embodiment, compared to the case where each of the compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4 is connected to only a single gate line, the drive frequency of the compensation gate driver GCDV can be reduced, and the power consumption of the compensation gate driver GCDV can be reduced.

[0143] In an embodiment, such as Figure 4 As shown, each of the compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4 is connected to two compensation gate lines, but this disclosure is not limited thereto. In an alternative embodiment, for example, each of the compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4 may be connected to three or more compensation gate lines, and thus the power consumption of the compensation gate driver GCDV can be further reduced.

[0144] In the embodiments, as referenced above Figure 4The described compensated gate driver GCDV includes compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4. Gate power voltages for controlling the voltages of internal nodes and gate power voltages for generating the compensated gate signal are independently provided to the compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4 via a first gate power line VGHL1 and a second gate power line VGHL2. In such an embodiment, when the compensated gate signal is generated, the odd-numbered compensation stages GC_ST1 and GC_ST3 use gate power voltages different from those of the even-numbered compensation stages GC_ST2 and GC_ST4 (i.e., the second gate power voltage applied to the second gate power line VGHL2). Therefore, fluctuations in the gate power voltages used to control the voltages of internal nodes and ripples in the compensated gate signal caused by fluctuations in the previous compensated gate signal can be reduced.

[0145] Figure 5 It is a diagram. Figure 4 The circuit diagram shows an embodiment of the first and second compensation stages included in the compensated gate driver. (Refer to...) Figure 4 Each of the odd-compensation levels GC_ST1 and GC_ST3 described can be substantially the same as the first compensation level GC_ST1, and refer to Figure 4 Each of the even-numbered compensation levels GC_ST2 and GC_ST4 described can be substantially the same as the second compensation level GC_ST2. Therefore, the first compensation level GC_ST1 and the second compensation level GC_ST2 will be described in detail below, and any repeated detailed descriptions of other compensation levels will be omitted.

[0146] refer to Figure 4 and Figure 5In the first compensation stage GC_ST1, the first power input terminal IN1 can be connected to the first gate power line VGHL1, the second power input terminal IN2 can be connected to the second gate power line VGHL2, the third power input terminal IN3 can be connected to the reference gate power line VGLL, the first clock input terminal CIN1 can be connected to the first clock signal line CLKL1, the second clock input terminal CIN2 can be connected to the second clock signal line CLKL2, and the reset terminal RST can be connected to the reset signal line RSTL. The first gate power voltage VGH1 can be applied to the first gate power line VGHL1, the second gate power voltage VGH2 can be applied to the second gate power line VGHL2, the reference gate power voltage VGL can be applied to the reference gate power line VGLL (and the third power input terminal IN3), the first clock signal CLK1 can be applied to the first clock signal line CLKL1 (and the first clock input terminal CIN1), and the second clock signal CLK2 can be applied to the second clock signal line CLKL2 (and the second clock input terminal CIN2). The input terminal IN0 can be connected to the start signal line STPL. A gate voltage equal to the first gate voltage VGH1 can be applied to the second gate voltage line VGHL2. For ease of description, the gate voltage in the first gate voltage line VGHL1 will be referred to as the first gate voltage VGH1, and the gate voltage in the second gate voltage line VGHL2 will be referred to as the second gate voltage VGH2. In one embodiment, for example, the first gate voltage VGH1 and the second gate voltage VGH2 can be in the range of approximately 4 volts (V) to approximately 10 V, and the reference gate voltage VGL can be in the range of approximately -4 V to approximately -10 V.

[0147] In an embodiment, such as Figure 5 As shown, the first compensation level GC_ST1 (or odd compensation level GC_ST_ODD) may include a node controller SST1, an output unit SST2 (or a buffer unit) and a node holding unit SST3.

[0148] In such an embodiment, the output unit SST2 can be connected to the first power input terminal IN1 and the third power input terminal IN3. The output unit SST2 can output the first gate power voltage VGH1 as the first compensation gate signal to the output terminal OUT based on the voltage of the second control node Q and the voltage of the first control node QB.

[0149] The output unit SST2 may include a ninth transistor T9 (or a pull-up transistor) and a tenth transistor T10 (or a pull-down transistor).

[0150] The ninth transistor T9 may include a first electrode connected to the first power input terminal IN1, a second electrode connected to the output terminal OUT, and a gate electrode connected to the first control node QB.

[0151] The tenth transistor T10 may include a first electrode connected to the output terminal OUT, a second electrode connected to the third power input terminal IN3, and a gate electrode connected to the second control node Q.

[0152] The node controller SST1 can be connected to input terminal IN0, second power input terminal IN2, third power input terminal IN3, first clock input terminal CIN1, and second clock input terminal CIN2. The node controller SST1 can control the voltage of the first control node QB and the voltage of the second control node Q based on the start signal (or the previously compensated gate signal) provided through input terminal IN0 and the second gate power voltage VGH2 provided through the second power input terminal IN2.

[0153] The node controller SST1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eleventh transistor T11 and a twelfth transistor T12, a second capacitor C2 (or a coupling capacitor) and a third capacitor C3.

[0154] The first transistor T1 (or the zeroth transistor) may include a first electrode connected to the input terminal IN0, a second electrode connected to the first electrode of the twelfth transistor T12, and a gate electrode connected to the first clock input terminal CIN1.

[0155] The second transistor T2 may include a first electrode connected to the second power input terminal IN2, a second electrode connected to the first electrode of the third transistor T3, and a gate electrode connected to the first electrode of the eleventh transistor T11.

[0156] The third transistor T3 may include a first electrode connected to the second electrode of the second transistor T2, a second electrode connected to the second clock input terminal CIN2, and a gate electrode connected to the second control node Q.

[0157] The third capacitor C3 can be connected or formed between the second electrode of the second transistor T2 and the second control node Q, and includes a first electrode connected to the second electrode of the second transistor T2 and a second electrode connected to the second control node Q.

[0158] The fourth transistor T4 may include a first electrode connected to the gate electrode of the second transistor T2, a second electrode connected to the first clock input terminal CIN1, and a gate electrode connected to the second electrode of the first transistor T1.

[0159] The fifth transistor T5 may include a first electrode connected to the gate electrode of the second transistor T2, a second electrode connected to the third power input terminal IN3, and a gate electrode connected to the first clock input terminal CIN1.

[0160] The sixth transistor T6 may include a first electrode connected to the first control node QB, a second electrode connected to the first electrode of the seventh transistor T7, and a gate electrode connected to the second clock input terminal CIN2.

[0161] The seventh transistor T7 may include a first electrode connected to the second electrode of the sixth transistor T6, a second electrode connected to the second clock input terminal CIN2, and a gate electrode connected to the second electrode of the eleventh transistor T11.

[0162] The second capacitor C2 (or coupling capacitor) may be connected or formed between the second electrode of the eleventh transistor T11 and the second electrode of the sixth transistor T6, and includes a first electrode connected to the second electrode of the eleventh transistor T11 and a second electrode connected to the second electrode of the sixth transistor T6.

[0163] The eleventh transistor T11 (or the first coupled transistor) may include a first electrode connected to the gate electrode of the second transistor T2, a second electrode connected to the first electrode of the second capacitor C2, and a gate electrode connected to the third power input terminal IN3.

[0164] The twelfth transistor T12 (or the second coupled transistor) may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the second control node Q, and a gate electrode connected to the third power input terminal IN3.

[0165] The node holding unit SST3 can maintain the voltage of the first control node QB substantially constant in response to the voltage of the second control node Q. The node holding unit SST3 may include a first capacitor C1, an eighth transistor T8, and a thirteenth transistor T13.

[0166] A first capacitor C1 may be connected or formed between a first power input terminal IN1 and a first control node QB, and includes a first electrode connected to the first power input terminal IN1 and a second electrode connected to the first control node QB. The first capacitor C1 can maintain a substantially constant voltage difference between the first power input terminal IN1 and the first control node QB.

[0167] The eighth transistor T8 may include a first electrode connected to the first power input terminal IN1, a second electrode connected to the first control node QB, and a gate electrode connected to the second electrode of the first transistor T1. The eighth transistor T8 can constantly maintain the voltage of the first control node QB in response to the voltage at the second electrode of the first transistor T1 (i.e., the voltage of the second control node Q). In one embodiment, for example, when the voltage of the second control node Q is at a logic low level, the eighth transistor T8 can maintain the voltage of the first control node QB at a logic high level by using a first gate power voltage VGH1.

[0168] The thirteenth transistor T13 (or reset transistor) may include a first electrode connected to the first power input terminal IN1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the reset terminal RST. When the display device DD (see...) Figure 1 When the transistor is turned on or off, a reset signal with a logic low level can be applied to the reset terminal RST. The thirteenth transistor T13 can be turned on in response to the reset signal with a logic low level, and a reset operation can be performed such that the voltage at the second electrode of the first transistor T1 (i.e., the second control node Q) has a first gate power voltage VGH1.

[0169] In an embodiment, such as Figure 5 As shown, the first transistor T1 to the thirteenth transistor T13 can be implemented using P-type transistors. In an embodiment, the first transistor T1 to the thirteenth transistor T13 can be implemented using, for example... Figure 5 The single-gate transistor illustrated in the figure is used, but this disclosure is not limited thereto. In an alternative embodiment, for example, at least one of the first transistor T1 to the thirteenth transistor T13 may be implemented using a dual-gate transistor (i.e., a dual-gate transistor having two transistors configured to be connected in series with each other and including gate electrodes connected to each other) to improve reliability.

[0170] The second compensation level GC_ST2 (or even-numbered levels GC_ST_EVEN) can be substantially the same as or similar to the first compensation level GC_ST1. Therefore, any repeated detailed descriptions of their identical or similar elements will not be repeated.

[0171] In the second compensation stage GC_ST2, the first power input terminal IN1 can be connected to the second gate power line VGHL2, the second power input terminal IN2 can be connected to the first gate power line VGHL1, the third power input terminal IN3 can be connected to the reference gate power line VGLL, the first clock input terminal CIN1 can be connected to the second clock signal line CLKL2, the second clock input terminal CIN2 can be connected to the first clock signal line CLKL1, and the reset terminal RST can be connected to the reset signal line RSTL.

[0172] The following text will refer to Figure 5 and Figure 6 Describe the operations of the first compensation level GC_ST1 and the second compensation level GC_ST2.

[0173] Figure 6 It is a diagram. Figure 5 The waveform diagram shows an embodiment of the signal in the first compensation stage. The operations of the first compensation stage GC_ST1 and the second compensation stage GC_ST2 are substantially the same or similar to each other, and therefore, the operation of the first compensation stage GC_ST1 will be described, and for ease of description, any repeated detailed descriptions of the operation of the second compensation stage GC_ST2 will be omitted.

[0174] refer to Figure 5 and Figure 6 The first clock signal CLK1 applied to the first clock input terminal CIN1 can have a first logic low level and a logic high level during four horizontal periods 4H, which constitute one cycle. The first logic low level can correspond to the gate on-state voltage level when the P-type transistor is turned on, and is equal to the voltage level of the reference gate power voltage VGL. The logic high level can correspond to the gate off-state voltage level when the P-type transistor is turned off, and is equal to the voltage level of the gate power voltage VGH (e.g., the first gate power voltage VGH1 or the second gate power voltage VGH2).

[0175] The second clock signal CLK2 applied to the second clock input terminal CIN2 can have a waveform that is delayed by half a cycle (i.e., two horizontal time periods 2H) from the waveform of the first clock signal CLK1.

[0176] At the first time point t1, the input voltage V_IN (e.g., a start signal) at the input terminal IN0 can change from a first logic low level to a logic high level. In one embodiment, for example, the input voltage V_IN can remain at a logic high level for eight level periods 8H.

[0177] At the first time point t1, the second node voltage V_Q at the second control node Q can have a second logic low level, the first node voltage V_QB at the first control node QB can have a logic high level, and the output voltage V_OUT at the output terminal OUT (i.e., the first compensation gate signal) can have a logic low level. The second logic low level can have a voltage level similar to the voltage level of the first logic low level. In one embodiment, for example, the second logic low level can have a voltage level higher than the voltage level of the reference gate power voltage VGL than the voltage level of the transistor threshold voltage Vth (i.e., VGL + |Vth|).

[0178] At the second time point t2, the first clock signal CLK1 can be changed from logic high level to first logic low level.

[0179] Therefore, the first transistor T1 can be turned on in response to the first clock signal CLK1 having a first logic low level, and an input voltage V_IN having a logic high level can be applied to the first electrode of the twelfth transistor T12. Since the twelfth transistor T12 is in a state where it is turned on by the reference gate power voltage VGL, the input voltage V_IN having a logic high level can be applied to the second control node Q through the twelfth transistor T12. That is, the second node voltage V_Q can be changed to have a logic high level at the second time point t2.

[0180] Furthermore, the fifth transistor T5 can be turned on in response to a first clock signal CLK1 having a first logic low level, and a reference gate power voltage VGL can be applied to the first electrode of the eleventh transistor T11. Since the eleventh transistor T11 is in a state where it is turned on by the reference gate power voltage VGL, the reference gate power voltage VGL can be applied to the first electrode of the second capacitor C2. The seventh transistor T7 can be turned on in response to the reference gate power voltage VGL (i.e., the reference gate power voltage VGL applied to the first electrode of the second capacitor C2), and a second clock signal CLK2 having a logic high level can be applied to the second electrode of the second capacitor C2. Therefore, a voltage corresponding to the difference between the logic high level and the first logic low level can be charged into the second capacitor C2.

[0181] The second transistor T2 can be turned on in response to the reference gate power voltage VGL, and the second gate power voltage VGH2 can be applied to the first electrode of the third capacitor C3. Since the second electrode of the third capacitor C3 can be connected to the second control node Q, and the second node voltage V_Q has a logic high level, the third capacitor C3 can be discharged.

[0182] At the third time point t3, the second clock signal CLK2 can be changed from logic high level to first logic low level.

[0183] The sixth transistor T6 can be turned on in response to a second clock signal CLK2 having a first logic low level, and the second clock signal CLK2 having a first logic low level can be applied to the first control node QB via the seventh transistor T7, which is turned on through the second capacitor C2, and the turned-on sixth transistor T6. That is, the first node voltage V_QB can be changed to have a first logic low level at the third time point t3.

[0184] The ninth transistor T9 can be turned on in response to a first node voltage V_QB having a first logic low level, and a first gate power voltage VGH1 can be applied to the output terminal OUT through the first input terminal IN1 and the ninth transistor T9. That is, the output voltage V_OUT can be changed to have a logic high level at the third time point t3.

[0185] like Figure 5 As shown, the output voltage V_OUT (i.e., the first compensation gate signal) of the first compensation stage GC_ST1 can be applied to the first compensation gate line GCL1 and the second compensation gate line GCL2, and a temporary drop may occur in the first gate power voltage VGH1 due to the load of the first compensation gate line GCL1 and the second compensation gate line GCL2 (e.g., charging the capacitors of the first compensation gate line GCL1 and the second compensation gate line GCL2).

[0186] Subsequently, although the first control node QB is in a floating state due to the changes in the first clock signal CLK1 and the second clock signal CLK2, the first node voltage V_QB can be kept at a first logic low level by the first capacitor C1, and the output voltage V_OUT can be kept at a logic high level.

[0187] At the fourth time point t4, the input voltage V_IN can change from logic high level to the first logic low level.

[0188] At the fifth time point t5, the first clock signal CLK1 can be changed from logic high level to first logic low level.

[0189] The first transistor T1 can be turned on in response to a first clock signal CLK1 having a first logic low level, and an input voltage V_IN having a first logic low level can be applied to the first electrode of the twelfth transistor T12. Since the twelfth transistor T12 is in a state where it is turned on by a reference gate power voltage VGL, the input voltage V_IN having a first logic low level can be applied to the second control node Q through the twelfth transistor T12. The second node voltage V_Q can be changed to have a second logic low level (i.e., VGL + |Vth|) by the threshold voltage of the twelfth transistor T12.

[0190] The tenth transistor T10 can be turned on in response to a second node voltage V_Q having a second logic low level, and a reference gate power voltage VGL can be applied to the output terminal OUT. The output voltage V_OUT can be changed to have a fourth logic low level (i.e., VGL+2|Vth|) by the second node voltage V_Q having a second logic low level and the threshold voltage of the tenth transistor T10.

[0191] At the fifth time point t5, the fourth transistor t4 can be turned on by an input voltage V_IN with a first logic low level provided by the first transistor T1. Furthermore, at the fifth time point T5, the fifth transistor T5 can be turned on in response to a first clock signal CLK1 with a first logic low level, and a reference gate power voltage VGL (and the first clock signal CLK1) can be applied to the gate electrode of the second transistor T2.

[0192] The second transistor T2 can be turned on in response to a reference gate power voltage VGL, and a second gate power voltage VGH2 can be applied to the first electrode of the third transistor T3. Since the second electrode of the third capacitor C3 is connected to the second control node Q, a second node voltage V_Q with a second logic low level can be applied to the second electrode of the third capacitor C3. Due to the voltage difference across the third capacitor C3, the third capacitor C3 can be charged by the second gate power voltage VGH2 provided by the second transistor T2. In such an embodiment, a temporary drop in the second gate power voltage VGH2 may occur to charge the third capacitor C3. In such an embodiment, a drop in the second gate power voltage VGH2 may occur due to coupling errors in the third capacitor C3.

[0193] At the fifth time point t5, the eighth transistor T8 can be turned on by an input voltage V_IN with a first logic low level, and the first gate power voltage VGH1 can be applied to the first control node QB. That is, the first node voltage V_QB can be changed to have a logic high level.

[0194] At the sixth time point t6, the second clock signal CLK2 can be changed from logic high level to first logic low level.

[0195] Since the third transistor T3 is in a state where it is turned on by the second node voltage V_Q, the second clock signal CLK2 with a first logic low level can be applied to the first electrode of the third capacitor C3. The second node voltage V_Q can be boosted by the third capacitor C3 and changed to have a third logic low level. Additionally, corresponding to the second node voltage V_Q with a third logic low level, the output voltage V_OUT can be changed to have a first logic low level. The third logic low level can have a voltage level lower than the first logic low level. In one embodiment, for example, the third logic low level can have a voltage level lower than the reference gate power voltage VGL (i.e., 2VGL + |Vth|).

[0196] At the seventh time point t7, the second clock signal CLK2 can be changed from the first logic low level to the logic high level.

[0197] The second clock signal CLK2, which has a logic high level, can be applied to the first electrode of the third capacitor C3 through the third transistor T3. The second node voltage V_Q can be changed to have a fourth logic low level (i.e., VGL+2|Vth|) through the third capacitor C3.

[0198] In the embodiments, as referenced Figure 5 and Figure 6 As described, corresponding to the waveform of the second clock signal CLK2 delayed by half a cycle from the waveform of the input voltage V_IN (i.e., the start signal), the first compensation stage GC_ST1 can output the first gate power voltage VGH1 as the output voltage V_OUT (i.e., the first compensation gate signal).

[0199] In such an embodiment, the first gate power voltage VGH1 may temporarily drop at a third time point t3 (i.e., the moment when the output voltage V_OUT is changed to a logic high level), and the second gate power voltage VGH2 may temporarily drop at a fifth time point t5 (i.e., when the first clock signal CLK1 changes from a logic high level to a first logic low level while the output voltage V_OUT is at a logic low level). In such an embodiment, the first gate power line VGHL1 and the second gate power line VGHL2 are located in the compensated gate circuit region A_GCDV (see...). Figure 2A The state of separation between them in the first grid electric field line VGH1 and the second grid electric field line VGH2 can be reduced relatively by the number of times they fall (i.e., the ripples), and the brightness difference caused by the ripples can be reduced.

[0200] Reference Figure 7A , Figure 7B and Figure 8 The reduction in the number of drops (i.e., ripples) of the first gate power voltage VGH1 and the second gate power voltage VGH2 is described in more detail.

[0201] Figure 7A It is a diagram. Figure 2A A diagram showing an embodiment of a gate driver included in a display device. Figure 7B It is a diagram. Figure 7A The waveform diagram shows an embodiment of the signal in the gate driver.

[0202] refer to Figure 2A , Figure 5 , Figure 7A and Figure 7BAn embodiment of the gate driver GDV may include a write gate driver GWDV, a compensated gate driver GCDV, and an emitter driver EMDV. The write gate driver GWDV may include write stages GW_ST1, GW_ST2, GW_ST3, and GW_ST4, and each of the write stages GW_ST1, GW_ST2, GW_ST3, and GW_ST4 may be connected to one of the bypass gate lines GBL0, GBL1, GBL2, and GBL3, and one of the write gate lines GWL1, GWL2, GWL3, and GWL4. The compensated gate driver GCDV may include compensation stages GC_ST1, GC_ST2, ..., GC_ST6, and GC_ST7, and each of the compensation stages GC_ST1, GC_ST2, ..., GC_ST6, and GC_ST7 may be connected to two of the initialization gate lines GIL1, GIL2, GIL3, GIL4, ..., GIL11, GIL12, GIL13, and GIL14, or two of the compensation gate lines GCL1, GCL2, GCL3, and GCL4. Each of the compensation stages GC_ST1, GC_ST2, ..., GC_ST6, and GC_ST7 may be connected to the above references. Figure 5 The first compensation stage GC_ST1 or the second compensation stage GC_ST2 are substantially the same or similar. The transmit driver EMDV may include transmit stages EM_ST1 and EM_ST2, and each of the transmit stages EM_ST1 and EM_ST2 may be connected to two of the transmit gate lines EML1, EML2, EML3 and EML4.

[0203] The transmit start signal EM_STP can be applied to the transmit start line EM_STPL. The transmit driver EMDV can generate transmit gate signals EM[1], EM[2], EM[3] and EM[4] in response to the transmit start signal EM_STP transmitted to the transmit driver EMDV via the transmit start line EM_STPL.

[0204] In the embodiments, as referenced above Figure 4 As described, the first clock signal CLK1 and the second clock signal CLK2 can be provided to the compensation stages GC_ST1, GC_ST2, ..., GC_ST6 and GC_ST7 respectively via the first clock signal line CLKL1 and the second clock signal line CLKL2. (See reference...) Figure 4 As described, the first clock signal CLK1 and the second clock signal CLK2 can be applied to different clock input terminals of adjacent compensation stages GC_ST1, GC_ST2, ..., GC_ST6 and GC_ST7. In an embodiment, as... Figure 7BAs shown, the first clock signal CLK1 can have four horizontal periods consisting of logic low and logic high levels as one cycle. The second clock signal CLK2 can have a waveform that is delayed by two horizontal periods from the waveform of the first clock signal CLK1.

[0205] In an embodiment, such as Figure 7A and Figure 7B As shown, the first transmit gate signal EM[1] and the second transmit gate signal EM[2] can be provided from the first transmit stage EM_ST1 to the first transmit gate line EML1 and the second transmit gate line EML2. The third transmit gate signal EM[3] and the fourth transmit gate signal EM[4] can be provided from the second transmit stage EM_ST2 to the third transmit gate line EML3 and the fourth transmit gate line EML4.

[0206] The first write gate signal GW[1] can be provided from the first write stage GW_ST1 to the first write gate line GWL1. Since the zeroth bypass line GBL0 is connected to the first write gate line GWL1, the first write gate signal GW[1] can be provided to the zeroth bypass line GBL0 as the zeroth bypass gate signal GB[0].

[0207] In such an embodiment, the second write gate signal GW[2] can be provided from the second write stage GW_ST2 to the second write gate line GWL2, and is provided as the first bypass gate signal GB[1] to the first bypass line GBL1. The third write gate signal GW[3] can be provided from the third write stage GW_ST3 to the third write gate line GWL3, and is provided as the second bypass gate signal GB[2] to the second bypass line GBL2. The fourth write gate signal GW[4] can be provided from the fourth write stage GW_ST4 to the fourth write gate line GWL4, and is provided as the third bypass gate signal GB[3] to the third bypass line GBL3.

[0208] The initialization / compensation start signal GI / GC_STP can be provided to the start signal line STPL.

[0209] The first initialization gate signal GI[1] can be provided from the first compensation stage GC_ST1 to the first initialization gate line GIL1, and as the second initialization gate signal GI[2], it is provided to the second initialization gate line GIL2 (i.e., the second initialization gate line GIL2 connected to the first initialization gate line GIL1).

[0210] In such an embodiment, the third initialization gate signal GI[3] can be provided from the second compensation stage GC_ST2 to the third initialization gate line GIL3, and is provided as the fourth initialization gate signal GI[4] to the fourth initialization gate line GIL4 (i.e., the fourth initialization gate line GIL4 connected to the third initialization gate line GIL3).

[0211] The eleventh initialization gate signal GI

[11] can be provided from the sixth compensation stage GC_ST6 to the eleventh initialization gate line GIL11, and as the twelfth initialization gate signal GI

[12] to the twelfth initialization gate line GIL12. In such an embodiment, since the eleventh initialization gate line GIL11 is connected to the first compensation gate line GCL1 and the second compensation gate line GCL2, the eleventh initialization gate signal GI

[11] can be provided to the first compensation gate line GCL1 and the second compensation gate line GCL2 as the first compensation gate signal CG[1] and the second compensation gate signal GC[2], respectively.

[0212] In such an embodiment, the thirteenth initialization gate signal GI

[13] can be provided from the seventh compensation stage GC_ST7 to the thirteenth initialization gate line GIL13, and is provided as the fourteenth initialization gate signal GI

[14] to the fourteenth initialization gate line GIL14. In such an embodiment, since the thirteenth initialization gate line GIL13 is connected to the third compensation gate line GCL3 and the fourth compensation gate line GCL4, the thirteenth initialization gate signal GI

[13] can be provided as the third compensation gate signal CG[3] and the fourth compensation gate signal GC[4] to the third compensation gate line GCL3 and the fourth compensation gate line GCL4, respectively.

[0213] The first gate power voltage VGH1 can be supplied to the first gate power line VGHL1, and the second gate power voltage VGH2 can be supplied to the second gate power line VGHL2.

[0214] At the eleventh time point t11, the transmit start signal EM_STP can be changed from logic low level (or on level) to logic high level (or off level) and is maintained at logic high level until the twentieth time point t20. At the twentieth time point t20, the transmit start signal EM_STP changes from logic high level to logic low level. The first transmitter stage EM_ST1 can generate the first transmit gate signal EM[1] and the second transmit gate signal EM[2] by delaying the transmit start signal EM_STP by 2 horizontal time periods.

[0215] At the twelfth time point t12, the first transmit gate signal EM[1] and the second transmit gate signal EM[2] can be changed from logic low level to logic high level. The second transmitter stage EM_ST2 can generate the third transmit gate signal EM[3] and the fourth transmit gate signal EM[4] by delaying the first transmit gate signal EM[1] (or the second transmit gate signal EM[2]) by 2 horizontal time periods.

[0216] At the thirteenth time point t13, the third transmit gate signal EM[3] and the fourth transmit gate signal EM[4] can be changed from logic low level to logic high level.

[0217] Therefore, in such an embodiment, the transmitter stages EM_ST1 and EM_ST2 (or the transmitter driver EMDV) can sequentially output the transmitter gate signals EM[1], EM[2], EM[3] and EM[4] in pairs, corresponding to the transmitter start signal EM_STP.

[0218] In such an embodiment, at the thirteenth time point t13, the initialization / compensation start signal GI / GC_STP can be changed from logic low to logic high. The first compensation stage GC_ST1 (or the first initialization stage) can generate the first initialization gate signal GI[1] and the second initialization gate signal GI[2] by delaying the initialization / compensation start signal GI / GC_STP by half a cycle of the first clock signal CLK1 (i.e., 2 horizontal time periods).

[0219] At the fourteenth time point t14, the first initialization gate signal GI[1] and the second initialization gate signal GI[2] can be changed from logic low level to logic high level. (See above reference...) Figure 5 and Figure 6 As described, the first compensation stage GC_ST1 can output a first gate power voltage VGH1 as a first initial gate signal GI[1] and a second initial gate signal GI[2], and a temporary drop may occur in the first gate power voltage VGH1.

[0220] In such an embodiment, the second compensation stage GC_ST2 (or the second initialization stage) can generate the third initialization gate signal GI[3] and the fourth initialization gate signal GI[4] by delaying the first initialization gate signal GI[1] (or the second initialization gate signal GI[2]) by two horizontal time periods.

[0221] At the fifteenth time point t15, the third initialization gate signal GI[3] and the fourth initialization gate signal GI[4] can be changed from logic low to logic high. See reference 5 and Figure 6 As described, the second compensation stage GC_ST2 can output the second gate power voltage VGH2 as the third initial gate signal GI[3] and the fourth initial gate signal GI[4], and a temporary drop may occur in the second gate power voltage VGH2.

[0222] At time point t16 (the sixteenth time point), the initialization / compensation start signal GI / GC_STP can change from logic high to logic low. Time point t16 can be the time six horizontal time intervals after time point t14 (the fourteenth time point). Figure 6At the fifth time point t5 shown, a temporary drop in the second gate power voltage VGH2 may occur due to coupling error.

[0223] At time point t17, as at time point t15, the eleventh initialization gate signal GI

[11] and the twelfth initialization gate signal GI

[12] can be changed from logic low to logic high. That is, the sixth compensation stage GC_ST6 can output each of the eleventh initialization gate signal GI

[11] and the twelfth initialization gate signal GI

[12] with a logic high level. In such an embodiment, since the eleventh initialization gate signal GI

[11] is connected to the first compensation gate line GCL1 and the second compensation gate line GCL2, the first compensation gate signal GC[1] and the second compensation gate signal GC[2] can be changed from logic low to logic high.

[0224] The sixth compensation stage GC_ST6, which is an even-numbered compensation stage, can output the second gate power voltage VGH2 as the first compensation gate signal GC[1] and the second compensation gate signal GC[2], and there may be a temporary drop in the second gate power voltage VGH2.

[0225] At time point t18, similar to time point t14, the thirteenth initialization gate signal GI

[13] , the fourteenth initialization gate signal GI

[14] , the third compensation gate signal GC[3], and the fourth compensation gate signal GC[4] can be changed from logic low to logic high. Therefore, the seventh compensation stage GC_ST7 can output each of the thirteenth initialization gate signal GI

[13] , the fourteenth initialization gate signal GI

[14] , the third compensation gate signal GC[3], and the fourth compensation gate signal GC[4] with a logic high level.

[0226] The seventh compensation stage GC_ST7, which is an odd-numbered compensation stage, can output the first gate power voltage VGH1 as the third compensation gate signal GC[3] and the fourth compensation gate signal GC[4], and there may be a temporary drop in the first gate power voltage VGH1.

[0227] Depending on the operation of the gate driver GDV (or the compensating gate driver GCDV), a drop (or ripple) may occur in the first gate power voltage VGH1 and the second gate power voltage VGH2 every 4 horizontal time periods with a period of 4H.

[0228] In such an embodiment, at the eighteenth time point t18 (or during the first write period P_W1), the first write gate signal GW[1] and the zeroth bypass gate signal GB[0] can be changed from logic high to logic low. Subsequently, at intervals of one horizontal period 1H, other write gate signals GW[2], GW[3], and GW[4] (and other bypass gate signals GB[1], GB[2], and GB[3]) can be sequentially changed from logic high to logic low. In one embodiment, for example, at the nineteenth time point t19 (or during the second write period P_W2), the second write gate signal GW[2] and the first bypass gate signal GB[1] can be changed from logic high to logic low.

[0229] During the first write period P_W1 and the second write period P_W2, the second gate power voltage VGH2 generated by the first compensation gate signal GC[1] and the second compensation gate signal GC[2] corresponding to the first write gate signal GW[1] and the second write gate signal GW[2] can have no voltage drop. Therefore, the ripple of the second gate power voltage VGH2 can have no effect on the first write gate signal GW[1] and the second write gate signal GW[2]. Therefore, the pixel provided with the first write gate signal GW[1] and the second write gate signal GW[2] can accurately record the data voltage therein regardless of the ripple of the second gate power voltage VGH2 and emit light with a brightness corresponding to the data signal. Therefore, no substantial or identifiable brightness difference can occur between pixels.

[0230] Figure 8 It is a diagram. Figure 7A The waveform diagram shows a comparative example of the signal in the gate driver shown. Figure 8 The diagram shows when Figure 7A The first gate power line VGHL1 and the second gate power line VGHL2 shown are integrated into a single gate power line in the signal of the gate driver.

[0231] Figure 8 The waveform shown is the same as the reference. Figure 7B The waveforms described are substantially the same or similar, except for the gate power voltage VGH' applied to a single gate power line, and therefore any repeated detailed descriptions of the same or similar characteristics will be omitted.

[0232] In the comparative example, in reference Figure 7AWhen the compensation stages GC_ST1, GC_ST2, ..., GC_ST6 and GC_ST7 are connected to only a single gate power line instead of the first gate power line VGHL1 and the second gate power line VGHL2, the gate power voltage VGH' applied to the single gate power line may experience a drop (or ripple) with a period of 2 horizontal time intervals. Therefore, the initial gate signals GI[1]', GI[2]', GI[3]' and GI[4]' and the compensation gate signals GC[1]', GC[2]', GC[3]' and GC[4]' may have a voltage drop with a period of 2 horizontal time intervals.

[0233] During the first write period P_W1', the gate power voltage VGH' and the first compensation gate signal GC[1]' corresponding to the first write gate signal GW[1] may have a voltage drop. Therefore, the ripple of the gate power voltage VGH' may affect the first write gate signal GW[1]. In the comparative example, due to the third thin-film transistor M3 (see [reference]) of each first pixel in the first pixel provided with the first write gate signal GW[1], Figure 3 If the first compensation gate signal GC[1]' (i.e., the first compensation gate signal GC[1]' with voltage drop) is not properly turned on, the data voltage may not be accurately recorded in the storage capacitor Cst of each first pixel in the first pixel, and the first pixel may not emit light with the desired brightness.

[0234] In the comparative example, during the second write period P_W2', the gate power voltage VGH' and the second compensation gate signal GC[2]' corresponding to the second write gate signal GW[2] may not have any voltage drop. Therefore, the third thin-film transistor M3 (see [reference]) of each second pixel in the second pixel provided with the second write gate signal GW[2] Figure 3 The data voltage can be precisely recorded in the storage capacitor Cst of each second pixel in the second pixel, and the second pixel can emit light with the desired brightness. Therefore, a brightness difference may occur between the first pixel and the second pixel.

[0235] In embodiments of the present invention, as referenced above... Figure 7A , Figure 7B and Figure 8As described, since the compensation gate driver GCDV (or compensation stages GC_ST1, GC_ST2, ..., GC_ST6 and GC_ST7) receives the first gate power voltage VGH1 and the second gate power voltage VGH2 through the first gate power line VGHL1 and the second gate power line VGHL2, that is, since the output terminals of adjacent compensation stages among compensation stages GC_ST1, GC_ST2, ..., GC_ST6 and GC_ST7 are respectively connected to the independent first gate power line VGHL1 and the second gate power line VGHL2, as referenced Figure 5 As described, the number of drops (i.e., ripples) in the first gate power voltage VGH1 and the second gate power voltage VGH2 can be relatively reduced, and the brightness difference caused by the ripples can be reduced.

[0236] Figure 9 It is a diagram. Figure 4 The circuit diagram shows an alternative embodiment of the first and second compensation stages included in the compensated gate driver shown.

[0237] refer to Figure 5 and Figure 9 Apart from the connection configuration of the eighth transistor T8, the first compensation stage GC_ST1_1 and the second compensation stage GC_ST2_1 can be referenced above. Figure 5 The first compensation level GC_ST1 and the second compensation level GC_ST2 are basically the same or similar. Figure 9 The same or similar elements shown have been used in the above description Figure 5 The embodiments of the first compensation level GC_ST1 and the second compensation level GC_ST2 shown are labeled with the same reference numerals, and any repeated detailed descriptions thereof will be omitted or simplified below.

[0238] In one embodiment, in the first compensation stage GC_ST1_1, the first electrode of the eighth transistor T8 can be connected to the second gate power line VGHL2 (or the second power input terminal IN2). The eighth transistor T8 can maintain the voltage of the first control node QB constant in response to the voltage at the second electrode of the first transistor T1. In one embodiment, for example, when the voltage of the second control node Q is at a logic low level, the eighth transistor T8 can maintain the voltage of the first control node QB at a logic high level by using the second gate power voltage VGH2.

[0239] Although a voltage drop occurs in the second gate power voltage VGH2, due to the first capacitor C1, the voltage drop of the second gate power voltage VGH2 can have no substantial impact on the first control node QB.

[0240] Therefore, with reference Figure 7BCorresponding to the first write period P_W1 described, the first compensation stage GC_ST1_1 can output a first compensation gate signal without voltage drop.

[0241] In such an embodiment, in the second compensation stage GC_ST2_1, the first electrode of the eighth transistor T8 can be connected to the first gate power line VGHL1. Although a voltage drop occurs in the first gate power voltage VGH1, due to the first capacitor C1, the voltage drop of the first gate power voltage VGH1 can have almost no effect on the first control node QB.

[0242] Figure 10 It is a diagram. Figure 4 The circuit diagram shows another alternative embodiment of the first and second compensation stages included in the compensated gate driver shown. Figure 11 It is a diagram. Figure 4 The circuit diagram shows another alternative embodiment of the first and second compensation stages included in the compensated gate driver shown.

[0243] refer to Figure 5 and Figure 10 In addition to each of the first compensation stage GC_ST1_2 and the second compensation stage GC_ST2_2 further including a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16, Figure 10 The first compensation level GC_ST1_2 and the second compensation level GC_ST2_2 shown in the figure are... Figure 5 The first compensation level GC_ST1 and the second compensation level GC_ST2 shown are basically the same or similar. Figure 10 The same or similar elements shown have been used in the above description Figure 5 The embodiments of the first compensation level GC_ST1 and the second compensation level GC_ST2 shown are labeled with the same reference numerals, and any repeated detailed descriptions thereof will be omitted or simplified below.

[0244] In an embodiment, such as Figure 10 As shown, the sixteenth transistor T16 (or the third auxiliary transistor) may include a first electrode connected to the gate electrode of the third transistor T3, a second electrode connected to the second control node Q, and a gate electrode connected to the gate electrode of the third transistor T3. In such an embodiment, the sixteenth transistor T16 may be connected by a diode between the gate electrode of the third transistor T3 and the second control node Q.

[0245] In such an embodiment, as referenced above... Figure 5 and Figure 6 The description refers to the second node voltage V_Q of the second control node Q of the first compensation stage GC_ST1. Figure 6The output voltage V_OUT (or the first compensation gate signal) shown can alternately have a third logic low level (i.e., 2VGL+|Vth|) and a second logic low level (i.e., VGL+|Vth|) after the seventh time point t7. The output voltage V_OUT (or the first compensation gate signal) after the seventh time point t7 can have voltage fluctuations corresponding to the second node voltage V_Q.

[0246] In such an embodiment, at the seventh time point t7, the second clock signal CLK2 can change from a first logic low level to a logic high level, and the second clock signal CLK2 with a logic high level is applied to the first electrode of the third capacitor C3 through the third transistor T3. After the voltage at the gate electrode of the third transistor T3 is changed to a fourth logic low level (i.e., VGL + 2|Vth|), the sixteenth transistor T16 can maintain the second node voltage V_Q constant, regardless of voltage fluctuations at the gate electrode of the third transistor T3. Therefore, in reference... Figure 6 After the seventh time point t7 described, the output voltage V_OUT (or the first compensation gate signal) has no voltage fluctuation (or ripple) and can effectively prevent pixel failures caused by voltage fluctuations of the output voltage V_OUT.

[0247] The fourteenth transistor T14 (or the first auxiliary transistor) may include a first electrode connected to the input terminal IN0, a second electrode connected to the first electrode of the fifteenth transistor T15, and a gate electrode connected to the first clock input terminal CIN1. The fifteenth transistor T15 may include a first electrode connected to the second electrode of the fourteenth transistor T14, a second electrode connected to the gate electrode of the third transistor T3, and a gate electrode connected to the third power input terminal IN3.

[0248] The fourteenth transistor T14 can initialize the gate electrode of the third transistor T3 in response to a first clock signal CLK1 provided via the first clock input terminal CIN1 by using a start signal (or a previously compensated gate signal) provided to the input terminal IN0. In such an embodiment, if a sixteenth transistor T16 is further included, the gate electrode of the third transistor T3 is not initialized by the second control node Q.

[0249] The fifteenth transistor T15 (or the second auxiliary transistor) can reduce or share the bias voltage applied to the fourteenth transistor T14 between the input terminal IN0 and the gate electrode of the third transistor T3.

[0250] The second compensation level GC_ST2_2 (or even-numbered compensation level GC_ST_EVEN) is substantially the same as or similar to the first compensation level GC_ST1_2 (or odd-numbered compensation level GC_ST_ODD), and therefore, any repeated detailed descriptions will be omitted.

[0251] In an embodiment, such as Figure 10 As shown, the first compensation stage GC_ST1_2 (and the second compensation stage GC_ST2_2) further includes a fourteenth transistor T14, a fifteenth transistor T15 and a sixteenth transistor T16, and can prevent the compensation gate signal from fluctuating during the period when the compensation gate signal has a logic low level.

[0252] In this embodiment, the eighth transistor T8 of the first compensation stage GC_ST1_2 is connected to the first gate power line VGHL1, and the eighth transistor T8 of the second compensation stage GC_ST2_2 is connected to the second gate power line VGHL2, as follows. Figure 10 The illustrations are shown in the figure, but this disclosure is not limited thereto.

[0253] In alternative embodiments, such as Figure 11 As shown, the eighth transistor T8 of the first compensation stage GC_ST1_3 can be connected to the second gate power line VGHL2 (or the second power input terminal IN2), and the eighth transistor T8 of the second compensation stage GC_ST2_3 can be connected to the first gate power line VGHL1.

[0254] Figure 12A , Figure 12B , Figure 12C and Figure 12D It is a diagram. Figure 1 A plan view of an alternative embodiment of the display device shown.

[0255] refer to Figure 2A , Figure 12A , 12B And 12C, except that the display device DD_2 further includes a third gate power line VGHL3, Figure 12A , Figure 12B and Figure 12C The embodiment of the display device DD_2 shown is similar to Figure 2A The display device DD shown is basically the same.

[0256] In such an embodiment, a third gate power line VGHL3 may be provided or disposed in a non-display area of ​​the substrate SUB. The third gate power line VGHL3 may be connected to the first gate power line VGHL1 and the second gate power line VGHL2 in the pad area A_PD, and is disposed to be separated from the first gate power line VGHL1 and the second gate power line VGHL2 in a non-display area outside the pad area A_PD.

[0257] In an embodiment, such as Figure 12AAs shown, the third gate power line VGHL3 can be electrically isolated from the write gate power line VGHL_GW and the emit gate power line VGHL_EM. However, this disclosure is not limited thereto, and alternatively, the third gate power line VGHL3 can be electrically connected to at least one of the write gate power line VGHL_GW and the emit gate power line VGHL_EM. In alternative embodiments, such as Figure 12B As shown, the third gate power line VGHL3 can be connected to the write gate power line VGHL_GW on the upper side of the gate circuit region A_GDV (i.e., the side of the gate circuit region A_GDV opposite to the side adjacent to the pad region A_PD). ​​In another alternative embodiment, as... Figure 12C As shown, the third gate power line VGHL3 can be connected to the write gate power line VGHL_GW and the emitter gate power line VGHL_EM on the upper side of the gate circuit region A_GDV. In such an embodiment, the drop in gate power voltage applied to the third gate power line VGHL3, the write gate power line VGHL_GW, and the emitter gate power line VGHL_EM can be reduced.

[0258] In embodiments where the third gate power line VGHL3 is connected to at least one of the write gate power line VGHL_GW and the transmit gate power line VGHL_EM, the first gate power line VGHL1 and the second gate power line VGHL2 are not directly connected to the write gate power line VGHL_GW and the transmit gate power line VGHL_EM.

[0259] The compensated gate driver GCDV_1 (or initialized gate driver) may be in the form of a shift register and include multiple compensation stages (or initialization stages). The compensated gate driver GCDV_1 (or each of the compensation stages) may be connected to one of the first gate power line VGHL1, the second gate power line VGHL2, and the third gate power line VGHL3.

[0260] In this embodiment, the compensation gate driver GCDV_1 is arranged on one side (e.g., the left side) of the display unit DP, such as... Figure 12A , Figure 12B and Figure 12C The illustrations are shown in the figure, but this disclosure is not limited thereto.

[0261] In the following text, reference will be made to Figure 2B , Figure 12A and Figure 12D Description of an embodiment. The substrate SUB may further include a second compensation gate circuit region A_GCDV2 located on the other side (e.g., the right side) of the display region A_DP, and a second compensation gate driver GCDV2_1 may be formed or disposed in the second compensation gate circuit region A_GCDV2. The second compensation gate driver GCDV2_1 may be included in the gate driver GDV.

[0262] Each of the first gate power line VGHL1', the second gate power line VGHL2', and the third gate power line VGHL3' can extend upwards along the edge of the display area A_DP to the second compensation gate circuit area A_GCDV2. In such an embodiment, as referenced... Figure 12A As described, the first gate power line VGHL1', the second gate power line VGHL2', and the third gate power line VGHL3' can be connected to each other in the pad area A_PD. The first gate power line VGHL1', the second gate power line VGHL2', and the third gate power line VGHL3' can be unconnected to each other in a non-display area other than the pad area A_PD, and can be arranged to be spaced apart from each other. In an embodiment, as... Figure 12D As shown, one end of the first gate power line VGHL1', the second gate power line VGHL2', and the third gate power line VGHL3' can be connected to the first gate power pad PD_GC provided in the pad area A_PD, and one end of the first gate power line VGHL1', the second gate power line VGHL2', and the third gate power line VGHL3' can be connected to the third gate power pad PD_GC2 provided in the pad area A_PD.

[0263] The second compensation gate driver GCDV2_1 may be substantially the same as or similar to the compensation gate driver GCDV (or the first compensation gate driver), except for its arrangement.

[0264] The second compensated gate driver GCDV2_1 can be in the form of a shift register and includes multiple compensation stages (or initialization stages). The second compensated gate driver GCDV2_1 (or each of the compensation stages) can be connected to the first gate power line VGHL1', the second gate power line VGHL2', and the third gate power line VGHL3'. The compensation stages can correspond to those from the timing controller TC (see...). Figure 1 The received compensation start signal (or initialization start signal) sequentially generates compensation gate signals with an on-level (e.g., logic high level). The compensation gate signals generated by the second compensation gate driver GCDV2_1 can be provided to the corresponding compensation gate lines GCL1, ..., GCLn (see...). Figure 1 ).

[0265] In this embodiment, the compensation gate signal generated by the second compensation gate driver GCDV2_1 can be used as an initialization gate signal. The compensation gate signal generated by the second compensation gate driver GCDV2_1 can also be provided to the corresponding initialization gate lines GIL1, ..., and GILn (see...). Figure 1 ).

[0266] Figure 12B and Figure 12CThe embodiment of the display device DD_2 shown can be modified in various ways to achieve... Figure 12D The first gate power line VGHL1', the second gate power line VGHL2', the third gate power line VGHL3', and the second compensation gate driver GCDV2_1 are shown.

[0267] The following text will refer to Figure 13 Describe the connection configuration between the compensated gate driver GCDV_1 and the first gate power line VGHL1, the second gate power line VGHL2, and the third gate power line VGHL3.

[0268] Figure 13 It is a diagram. Figures 12A to 12D A diagram of an embodiment of a compensation gate driver included in the display device shown. Figure 14 It is a diagram. Figure 13 The circuit diagram shows an embodiment of the first compensation stage and the second compensation stage included in the compensated gate driver shown.

[0269] In the embodiment, reference Figure 12A and Figure 13 The compensated gate driver GCDV_1 may include multiple compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4 (or stages). For ease of description, Figure 13 Only a portion of the compensated gate driver GCDV_1 is illustrated. Except for the third gate power line VGHL3, the compensated gate driver GCDV_1 is essentially the same as the compensated gate driver GCDV, and therefore, overlapping descriptions will not be repeated.

[0270] The compensation stages GC_ST1, GC_ST2, GC_ST3 and GC_ST4 can be connected to one of the first gate power line VGHL1, the second gate power line VGHL2 and the third gate power line VGHL3.

[0271] In one embodiment, for example, in odd-numbered compensation stages GC_ST1 and GC_ST3, the first power input terminal IN1 can be connected to the first gate power line VGHL1. In even-numbered compensation stages GC_ST2 and GC_ST4, the first power input terminal IN1 can be connected to the second gate power line VGHL2. In compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4, the second power input terminal IN2 can be connected to the third gate power line VGHL3.

[0272] In the embodiments, as referenced Figure 4As described, each of the compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4 can be connected to two of the compensation gate lines GCL1, GCL2, GCL3, GCL4, GCL5, GCL6, GCL7, and GCL8, and outputs the compensation gate signal to both gate lines simultaneously. In an embodiment, each of the compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4 can provide the compensation gate signal as an initialization gate signal to the initialization gate lines GIL1, ..., GILn (see...). Figure 1 ).

[0273] refer to Figure 5 , Figure 13 and Figure 14 , Figure 14 The first compensation level GC_ST1 (or odd compensation level GC_ST_ODD) shown can be compared with... Figure 5 The first compensation level GC_ST1 shown is basically the same or similar, and Figure 14 The second compensation level GC_ST2 (or even-numbered compensation level GC_ST_EVEN) shown can be compared with... Figure 5 The second compensation level GC_ST2 shown is essentially the same or similar. Therefore, any repeated detailed descriptions will be omitted.

[0274] In such an embodiment, with Figure 5 Compared to the first compensation stage GC_ST1 and the second compensation stage GC_ST2 shown, the internal circuit configuration of each of the compensation stages GC_ST1, GC_ST2, GC_ST3 and GC_ST4 remains unchanged, and only the connection configuration between the first input terminal IN1, the second input terminal IN2 and the third input terminal IN3 of the compensation stages GC_ST1, GC_ST2, GC_ST3 and GC_ST4 and the first gate power line VGHL1, the second gate power line VGHL2 and the third gate power line VGHL3 can be changed.

[0275] In such an embodiment, such as Figure 13 and Figure 14As shown, the third gate power voltage (i.e., the gate power voltage applied to the second power input terminal IN2 via the third gate power line VGHL3) can typically be used in compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4 to control the voltages of internal nodes (i.e., the first control node Q and the second control node QB). In such an embodiment, the first gate power voltage VGH1 applied to the first gate power line VGHL1 can be used in odd-numbered compensation stages GC_ST1 and GC_ST3, and the second gate power voltage VGH2 applied to the second gate power line VGHL2 can be used in even-numbered compensation stages GC_ST2 and GC_ST4 to output compensated gate signals. In such an embodiment, as referenced... Figure 4 As described, a gate voltage equal to the first gate voltage VGH1 can be applied to the second gate voltage line VGHL2. For ease of description, the gate voltage in the first gate voltage line VGHL1 can be referred to as the first gate voltage VGH1, and the gate voltage in the second gate voltage line VGHL2 can be referred to as the second gate voltage VGH2.

[0276] In this embodiment, the gate power voltage used to control the voltage of the internal nodes and the gate power voltage used to generate the compensation gate signal can be provided independently to each of the compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4. In this embodiment, when the first gate power line VGHL1 and the second gate power line VGHL2 used to transmit the gate power voltage to the compensation stages GC_ST1, GC_ST2, GC_ST3, and GC_ST4 are connected to each other in the pad region A_PD, the impact of the voltage drop on the other gate power line is reduced because the path of the voltage drop is lengthened. Therefore, fluctuations in the gate power voltage used to control the voltage of the internal nodes have no substantial impact on the gate power voltage used to generate the compensation gate signal, and the ripple of the compensation gate signal can be reduced.

[0277] In such an embodiment, when generating the compensation gate signal, the odd-numbered compensation stages GC_ST1 and GC_ST3, and the even-numbered compensation stages GC_ST2 and GC_ST4, can alternately use the first gate power voltage VGH1 and the second gate power voltage VGH2. Therefore, even if fluctuations occur in the compensation gate signal of the previous compensation stage, these fluctuations do not affect the gate power voltage of the subsequent compensation stage or the subsequent compensation gate signal, and the ripple of the compensation gate signal can also be reduced.

[0278] Figure 14 Detailed circuit configurations of embodiments of the first compensation stage GC_ST1 (or odd compensation stage GC_ST_ODD) and the second compensation stage GC_ST2 (or even compensation stage GC_ST_EVEN) are shown, but this disclosure is not limited thereto.

[0279] Figure 15 , Figure 16 and Figure 17 It is a diagram. Figure 13 The circuit diagrams shown are of various embodiments of the first compensation stage and the second compensation stage included in the compensated gate driver.

[0280] In the embodiment, reference Figure 14 and Figure 15 In addition to the connection configuration of the eighth transistor T8, Figure 15 The first compensation level GC_ST1_1 and the second compensation level GC_ST2_1 shown can be... Figure 14 The first compensation level GC_ST1 and the second compensation level GC_ST2 shown are basically the same or similar. Figure 15 The same or similar elements shown have been used in the above description Figure 14 The embodiments of the first compensation level GC_ST1 and the second compensation level GC_ST2 shown are labeled with the same reference numerals, and any repeated detailed descriptions thereof will be omitted or simplified below.

[0281] In one embodiment, in the first compensation stage GC_ST1_1, the first electrode of the eighth transistor T8 may be connected to the third gate power line VGHL3 (or the second power input terminal IN2) instead of the first gate power line VGHL1. In such an embodiment, in the second compensation stage GC_ST2_1, the first electrode of the eighth transistor T8 may be connected to the third gate power line VGHL3 instead of the second gate power line VGHL2.

[0282] refer to Figure 14 and Figure 16 In addition to the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16, each of the first compensation stage GC_ST1_2 and the second compensation stage GC_ST2_2 may further include the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16. Figure 16 The first compensation level GC_ST1_2 and the second compensation level GC_ST2_2 shown in the figure are... Figure 14 The first compensation stage GC_ST1 and the second compensation stage GC_ST2 shown are substantially the same. In such an embodiment, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are the same as the reference. Figure 10 The descriptions are essentially the same, and any repetitive detailed descriptions will be omitted.

[0283] In another alternative embodiment, reference is made to... Figure 16 and Figure 17 In addition to the connection configuration of the eighth transistor T8, Figure 17The first compensation level GC_ST1_3 and the second compensation level GC_ST2_3 shown can be used with Figure 16 The first compensation level GC_ST1_2 and the second compensation level GC_ST2_2 shown are basically the same or similar. Figure 17 The same or similar elements shown have been used in the above description Figure 16 The embodiments of the first compensation level GC_ST1_2 and the second compensation level GC_ST2_2 shown are labeled with the same reference numerals, and any repeated detailed descriptions thereof will be omitted or simplified below.

[0284] In one embodiment, in the first compensation stage GC_ST1_3, the first electrode of the eighth transistor T8 may be connected to the third gate power line VGHL3 (or the second power input terminal IN2) instead of the first gate power line VGHL1. In such an embodiment, in the second compensation stage GC_ST2_3, the first electrode of the eighth transistor T8 may be connected to the third gate power line VGHL3 instead of the second gate power line VGHL2.

[0285] According to embodiments of this disclosure, a gate driver and a display device including the gate driver comprise stages, and each stage includes an output unit that outputs a gate power voltage as a gate signal and a node controller that controls the operation of the output unit. The node controller is connected to a first gate power line, and the output unit is connected to a second gate power line different from the first gate power line. Therefore, fluctuations in the gate power voltage in the first gate power line have no effect on the gate power voltage in the second gate power line. Consequently, fluctuations in the gate signal based on the gate power voltage and the brightness difference caused by such fluctuations can be reduced.

[0286] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the concept of the invention to those skilled in the art.

[0287] While the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to the invention without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A display device, comprising: A first gate electric line, a second gate electric line, and a third gate electric line, each of which is subjected to a first voltage, wherein the first gate electric line, the second gate electric line, and the third gate electric line extend to be spaced apart from each other; as well as The first gate driver includes multiple stages that output multiple gate signals. Each of the plurality of stages includes an input terminal connected to the first gate power line and the second gate power line. Each of the first and second stages of the plurality of stages includes a capacitor and a plurality of transistors connected to each other, and the first and second stages have the same structure. The first electrode of the first transistor in the first stage is connected to the first gate power line, and the second electrode of the first transistor in the first stage is connected to the output terminal of the first stage. The first electrode of the first transistor in the second stage is connected to the second gate power line, and the second electrode of the first transistor in the second stage is connected to the output terminal of the second stage.

2. The display device according to claim 1, wherein, Each of the first stage and the second stage further includes a second transistor, the second transistor including a first electrode connected to the third gate power line.

3. The display device according to claim 2, further comprising a reference gate electric field line, The first stage further includes a pull-down transistor, the pull-down transistor including a first electrode connected to the output terminal and a second electrode connected to the reference gate power line.

4. The display device according to claim 3, further comprising a first clock signal line, a second clock signal line, and a start signal line. The first level further includes: The zeroth transistor includes a first electrode, a second electrode, and a gate electrode connected to the start signal line or the output unit of the previous stage; The third transistor includes a first electrode connected to the second electrode of the second transistor, a second electrode connected to the second clock signal line, and a gate electrode connected to the gate electrode of the pull-down transistor; The fourth transistor includes a first electrode connected to the gate electrode of the second transistor, a second electrode connected to the first clock signal line, and a gate electrode connected to the second electrode of the zeroth transistor; The fifth transistor includes a first electrode connected to the first electrode of the fourth transistor, a second electrode connected to the reference gate power line, and a gate electrode connected to the first clock signal line; The first coupled transistor includes a first electrode, a second electrode connected to the first electrode of the fifth transistor, and a gate electrode connected to the reference gate power line; A coupling capacitor includes a first electrode and a second electrode connected to the second electrode of the first coupling transistor; The sixth transistor includes a first electrode connected to the gate electrode of the first transistor, a second electrode connected to the second electrode of the coupling capacitor, and a gate electrode connected to the second clock signal line; as well as The seventh transistor includes a first electrode connected to the second electrode of the coupling capacitor, a second electrode connected to the second clock signal line, and a gate electrode connected to the first electrode of the coupling capacitor.

5. The display device according to claim 4, wherein, The first level further includes: A capacitor, comprising a first electrode connected to the second electrode of the second transistor and a second electrode connected to the gate electrode of the third transistor; and The second coupled transistor includes a first electrode connected to the second electrode of the zeroth transistor, a second electrode connected to the gate electrode of the pull-down transistor, and a gate electrode connected to the reference gate power line.

6. The display device according to claim 5, wherein, The first level further includes: The eighth transistor includes a first electrode connected to the first gate power line, a second electrode connected to the gate electrode of the first transistor, and a gate electrode connected to the second electrode of the zeroth transistor; and The first capacitor includes a first electrode connected to the first gate power line and a second electrode connected to the gate electrode of the first transistor.

7. The display device according to claim 6, wherein, The first level further includes: The reset transistor includes a first electrode connected to the first gate power line, a second electrode connected to the second electrode of the zeroth transistor, and a gate electrode connected to the reset line.

8. The display device according to claim 5, wherein, The first level further includes: The eighth transistor includes a first electrode connected to the third gate power line, a second electrode connected to the gate electrode of the first transistor, and a gate electrode connected to the second electrode of the zeroth transistor; and The first capacitor includes a first electrode connected to the first gate power line and a second electrode connected to the gate electrode of the first transistor.

9. The display device according to claim 5, wherein, The first level further includes: The first auxiliary transistor includes a first electrode, a second electrode connected to the start signal line or the output unit of the previous stage, and a gate electrode connected to the first clock signal line; The second auxiliary transistor includes a first electrode connected to the second electrode of the first auxiliary transistor, a second electrode connected to the gate electrode of the third transistor, and a gate electrode connected to the reference gate power line; and The third auxiliary transistor includes a first electrode connected to the gate electrode of the third transistor, a second electrode connected to the gate electrode of the pull-down transistor, and a gate electrode connected to the gate electrode of the third transistor.

10. The display device according to claim 9, wherein, The first level further includes: The eighth transistor includes a first electrode connected to the third gate power line, a second electrode connected to the gate electrode of the first transistor, and a gate electrode connected to the second electrode of the zeroth transistor; and The first capacitor includes a first electrode connected to the first gate power line and a second electrode connected to the gate electrode of the first transistor.

11. The display device according to any one of claims 1-10, further comprising: The second gate driver includes multiple stages that output multiple gate signals. The first gate power line, the second gate power line, and the third gate power line extend from the first gate driver to the second gate driver along the edge of the display device.

12. The display device according to claim 11, wherein, One end of the first gate electric field line, the second gate electric field line, and the third gate electric field line are connected to each other.

13. A display device, comprising: The display unit includes multiple gate lines and multiple pixels connected to the multiple gate lines; as well as A first gate driver includes multiple stages for providing multiple gate signals to the multiple gate lines and multiple gate power lines for transmitting a first voltage to the multiple stages. The first level of the plurality of levels includes: A first node controller is connected to a second grid power line among the plurality of grid power lines, wherein the first node controller controls the voltage of a first control node; and A first output unit is connected to a first gate power line among the plurality of gate power lines, wherein the first output unit outputs the first voltage of the first gate power line as a gate signal in response to the voltage of the first control node, and The same voltage is applied to both the first gate electric field line and the second gate electric field line. The second level, which is adjacent to the first level among the plurality of levels, includes: A second node controller, connected to the first gate power line, wherein the second node controller controls the voltage of the first control node in the second stage; and A second output unit is connected to the second gate power line, wherein the second output unit outputs the first voltage of the second gate power line as a gate signal in response to the voltage of the first control node in the second stage.

14. The display device according to claim 13, wherein, The output terminal of the first stage is connected to two or more of the multiple gate lines.

15. The display device according to claim 13, further comprising a reference gate electric field line different from the gate electric field line. The first output unit includes: The pull-up transistor includes a first electrode connected to the first gate power line, a second electrode connected to the output terminal, and a gate electrode connected to the first control node; as well as The pull-down transistor includes a first electrode connected to the output terminal, a second electrode connected to the reference gate power line, and a gate electrode connected to the second control node.

16. The display device according to claim 15, further comprising a first clock signal line, a second clock signal line, and a start signal line. The first node controller includes: The first transistor includes a first electrode, a second electrode, and a gate electrode connected to the start signal line or the output unit of the previous stage; The second transistor includes a first electrode, a second electrode, and a gate electrode connected to the second gate power line; The third transistor includes a first electrode connected to the second electrode of the second transistor, a second electrode connected to the second clock signal line, and a gate electrode connected to the second control node; The fourth transistor includes a first electrode connected to the gate electrode of the second transistor, a second electrode connected to the first clock signal line, and a gate electrode connected to the second electrode of the first transistor. The fifth transistor includes a first electrode connected to the first electrode of the fourth transistor, a second electrode connected to the reference gate power line, and a gate electrode connected to the first clock signal line; The first coupled transistor includes a first electrode, a second electrode connected to the first electrode of the fifth transistor, and a gate electrode connected to the reference gate power line; A coupling capacitor includes a first electrode and a second electrode connected to the second electrode of the first coupling transistor; The sixth transistor includes a first electrode connected to the first control node, a second electrode connected to the second electrode of the coupling capacitor, and a gate electrode connected to the second clock signal line; as well as The seventh transistor includes a first electrode connected to the second electrode of the coupling capacitor, a second electrode connected to the second clock signal line, and a gate electrode connected to the first electrode of the coupling capacitor.

17. The display device according to claim 16, wherein, The first node controller further includes: A capacitor, comprising a first electrode connected to the second electrode of the second transistor and a second electrode connected to the gate electrode of the third transistor; and The second coupled transistor includes a first electrode connected to the second electrode of the first transistor, a second electrode connected to the second control node, and a gate electrode connected to the reference gate power line.

18. The display device according to claim 17, wherein, The first level further includes: The eighth transistor includes a first electrode connected to the first gate power line, a second electrode connected to the first control node, and a gate electrode connected to the second electrode of the first transistor; and The first capacitor includes a first electrode connected to the first gate power line and a second electrode connected to the first control node.

19. The display device according to claim 18, wherein, The first level further includes: The reset transistor includes a first electrode connected to the first gate power line, a second electrode connected to the second electrode of the first transistor, and a gate electrode connected to the reset line.

20. The display device according to claim 17, wherein, The first level further includes: The eighth transistor includes a first electrode connected to the second gate power line, a second electrode connected to the first control node, and a gate electrode connected to the second electrode of the first transistor; and The first capacitor includes a first electrode connected to the first gate power line and a second electrode connected to the first control node.

21. The display device according to claim 17, wherein, The first node controller further includes: The first auxiliary transistor includes a first electrode, a second electrode connected to the start signal line or the output unit of the previous stage, and a gate electrode connected to the first clock signal line; The second auxiliary transistor includes a first electrode connected to the second electrode of the first auxiliary transistor, a second electrode connected to the gate electrode of the third transistor, and a gate electrode connected to the reference gate power line; and The third auxiliary transistor includes a first electrode connected to the gate electrode of the third transistor, a second electrode connected to the second control node, and a gate electrode connected to the gate electrode of the third transistor.

22. The display device according to claim 21, wherein, The first level further includes: The eighth transistor includes a first electrode connected to the second gate power line, a second electrode connected to the first control node, and a gate electrode connected to the second electrode of the first transistor; and The first capacitor includes a first electrode connected to the first gate power line and a second electrode connected to the first control node.

23. The display device according to any one of claims 13 to 22, wherein, The plurality of gate power lines are separated from each other in the first gate driver and connected to each other outside the first gate driver.

24. The display device according to claim 23, further comprising: The second gate driver provides multiple gate signals to the multiple gate lines. The first gate driver is arranged on one side of the display unit, and The second gate driver is arranged on the other side of the display unit, and The gate power lines extend from the first gate driver to the second gate driver along the edge of the display unit.

25. The display device of claim 13, wherein each of the plurality of stages includes a first power input terminal and a second power input terminal, and The first power input terminal of the odd-numbered stages and the second power input terminal of the even-numbered stages are connected to the first gate power line, and The second power input terminal of the odd-numbered stage among the plurality of stages and the first power input terminal of the even-numbered stage among the plurality of stages are connected to the second gate power line.

26. The display device according to claim 25, further comprising: First clock signal line and second clock signal line Each of the plurality of stages further includes a first clock input terminal and a second clock input terminal, and The first clock input terminal of the odd-numbered stages and the second clock input terminal of the even-numbered stages are connected to the first clock signal line, and The second clock input terminal of the odd-numbered stage and the first clock input terminal of the even-numbered stage are connected to the second clock signal line.

27. A display device, comprising: The display unit includes multiple gate lines and multiple pixels connected to the multiple gate lines; as well as A first gate driver includes multiple stages for providing multiple gate signals to the multiple gate lines and multiple gate power lines for transmitting a first voltage to the multiple stages. The first level of the plurality of levels includes: A first node controller is connected to a second grid power line among the plurality of grid power lines, wherein the first node controller controls the voltage of a first control node; and A first output unit is connected to a first gate power line among the plurality of gate power lines, wherein the first output unit outputs the first voltage of the first gate power line as a gate signal in response to the voltage of the first control node, and The same voltage is applied to both the first gate electric field line and the second gate electric field line. The second level, which is adjacent to the first level among the plurality of levels, includes: A second node controller, connected to the second gate power line, wherein the second node controller controls the voltage of the first control node in the second stage; and A second output unit is connected to a third gate power line among the plurality of gate power lines, wherein the second output unit outputs the first voltage of the third gate power line as a gate signal in response to the voltage of the first control node in the second stage, and The same voltage is applied to the first gate power line, the second gate power line, and the third gate power line.

28. The display device of claim 27, wherein each of the plurality of stages includes a first power input terminal and a second power input terminal. The second power input terminal of each of the plurality of stages is connected to the second gate power line, and The first power input terminal of the odd-numbered stages among the plurality of stages is connected to the first gate power line, and The first power input terminal of the even-numbered stage among the plurality of stages is connected to the third gate power line.

29. The display device according to claim 28, wherein, The first level further includes: The eighth transistor includes a first electrode connected to the second gate power line and a second electrode connected to the first control node; and The first capacitor includes a first electrode connected to the first gate power line and a second electrode connected to the first control node.

30. The display device according to claim 28, wherein, The first level further includes: The eighth transistor includes a first electrode connected to the first gate power line and a second electrode connected to the first control node; and The first capacitor includes a first electrode connected to the first gate power line and a second electrode connected to the first control node.

31. The display device according to claim 28, further comprising: A first clock signal line, a second clock signal line, a start signal line, and a reference gate power line that is different from the gate power lines. The first node controller includes: The first transistor includes a first electrode, a second electrode, and a gate electrode connected to the start signal line or the output unit of the previous stage; The second transistor includes a first electrode, a second electrode, and a gate electrode connected to the second gate power line; The third transistor includes a first electrode connected to the second electrode of the second transistor, a second electrode connected to the second clock signal line, and a gate electrode connected to the second control node; The first auxiliary transistor includes a first electrode, a second electrode connected to the start signal line or the output unit of the previous stage, and a gate electrode connected to the first clock signal line; The second auxiliary transistor includes a first electrode connected to the second electrode of the first auxiliary transistor, a second electrode connected to the gate electrode of the third transistor, and a gate electrode connected to the reference gate power line; and The third auxiliary transistor includes a first electrode connected to the gate electrode of the third transistor, a second electrode connected to the second control node, and a gate electrode connected to the gate electrode of the third transistor.

32. The display device according to claim 31, wherein, The first level further includes: The eighth transistor includes a first electrode connected to the second gate power line, a second electrode connected to the first control node, and a gate electrode connected to the second electrode of the first transistor; and The first capacitor includes a first electrode connected to the first gate power line and a second electrode connected to the first control node.

33. The display device according to claim 27, wherein, The first gate power line, the second gate power line, and the third gate power line are separated from each other in the first gate driver and connected to each other outside the first gate driver.

34. A display device, comprising: The substrate includes a display area, a non-display area, and a pad area that are distinct from each other; Multiple gate lines and multiple pixels are arranged on the substrate in the display area, wherein the multiple pixels are connected to the multiple gate lines; A gate driver, disposed on the substrate in the non-display area, the gate driver comprising multiple stages connected to the plurality of gate lines; Gate power pads are disposed on the substrate in the pad area; as well as Multiple gate power lines are arranged on the substrate, wherein the multiple gate power lines connect the gate power pads to the multiple stages. The plurality of gate power lines are separated from each other in the non-display area and connected to each other in the pad area. Each of the plurality of stages includes a first power input terminal. The first power input terminal of the odd-numbered stages among the plurality of stages is connected to the first grid power line among the plurality of grid power lines. The first power input terminal of the even-numbered stage among the plurality of stages is connected to the second grid power line among the plurality of grid power lines.

35. The display device according to claim 34, wherein, Each of the plurality of levels is connected to two or more of the plurality of gate lines.

36. The display device of claim 35, wherein each of the plurality of stages further comprises a second power input terminal, and The second power input terminal of the even-numbered stage among the plurality of stages is connected to the first gate power line among the plurality of gate power lines, and The second power input terminal of the odd-numbered stage among the plurality of stages is connected to the second gate power line among the plurality of gate power lines.

37. A display device, comprising: The substrate includes a display area, a non-display area, and a pad area that are distinct from each other; Multiple gate lines and multiple pixels are arranged on the substrate in the display area, wherein the multiple pixels are connected to the multiple gate lines; A gate driver, disposed on the substrate in the non-display area, the gate driver comprising multiple stages connected to the plurality of gate lines; Gate power pads are disposed on the substrate in the pad area; as well as Multiple gate power lines are arranged on the substrate, wherein the multiple gate power lines connect the gate power pads to the multiple stages. The plurality of gate power lines are separated from each other in the non-display area and connected to each other in the pad area. Each of the plurality of stages includes a first power input terminal and a second power input terminal. The second power input terminal of each of the plurality of stages is connected to the second grid power line among the plurality of grid power lines, and The first power input terminal of the odd-numbered stages among the plurality of stages is connected to the first grid power line among the plurality of grid power lines, and The first power input terminal of the even-numbered stage among the plurality of stages is connected to the third gate power line among the plurality of gate power lines.

38. A display device, comprising: Multiple stages provide multiple gate signals to multiple gate lines; as well as Multiple grid power lines transmit a first voltage to the multiple stages, wherein the first voltage is a DC voltage. The first level of the plurality of levels includes: A first node controller is connected to a second grid power line among the plurality of grid power lines, wherein the first node controller controls the voltage of a first control node; and A first output unit is connected to a first gate power line among the plurality of gate power lines, wherein the first output unit outputs the first voltage of the first gate power line as a gate signal in response to the voltage of the first control node, and The same voltage is applied to both the first gate electric field line and the second gate electric field line. The second level, which is adjacent to the first level among the plurality of levels, includes: A second node controller, connected to the first gate power line, wherein the second node controller controls the voltage of the first control node in the second stage; and A second output unit is connected to the second gate power line, wherein the second output unit outputs the first voltage of the second gate power line as a gate signal in response to the voltage of the first control node in the second stage.

Images