Camera module, related operation method and electronic device

Abstract

A camera module, a related operation method, and an electronic device are disclosed. The camera module includes: an image sensor that captures an image of a target to generate first image data, outputs the first image data, and outputs an interval information signal; an image signal processor that receives the first image data, performs image processing on the first image data to generate second image data, and outputs the second image data; and an interface circuit that receives the second image data and the interval information signal and outputs the second image data as third image data. The interface circuit adjusts the timing of outputting the third image data based on the interval information signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0069036 filed on June 8, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a camera module. Background Art

[0004] The camera module may generate image data indicating an object and / or a scene corresponding to the object. As the performance of mobile devices such as smart phones and smart tablets / tablets increases, camera (i.e., image) modules may be increasingly used in mobile devices. Because image modules used in mobile devices generate image data, image modules may be used to create image-based content.

[0005] In order to generate image data with improved quality, various techniques for eliminating, suppressing or compensating various noises occurring in the process of generating image data may be applied to a camera module or a processor (e.g., an application processor) receiving image data from the camera module. However, conventional techniques fail to provide solutions for all noises. Summary of the invention

[0006] Embodiments of the inventive concept provide a camera module that removes noise occurring in image data due to operation of an interface circuit, an operating method of the camera module, and an electronic device including the camera module.

[0007] According to an example embodiment, a camera module includes: an image sensor that captures an image of a target to generate first image data, outputs the first image data and outputs an interval information signal; an image signal processor that receives the first image data, performs image processing on the first image data to generate second image data, and outputs the second image data; and an interface circuit that receives the second image data and the interval information signal and outputs the second image data as third image data. The interface circuit adjusts a timing of outputting the third image data based on the interval information signal.

[0008] According to an example embodiment, a method for operating a camera module includes: generating first image data by capturing an image of a target using an image sensor of the camera module; outputting an interval information signal identifying a prohibited interval from the image sensor; generating second image data by performing image processing on the first image data; starting to output the second image data as third image data when outside the prohibited interval; and ending the output of the third image data when outside the prohibited interval.

[0009] According to an example embodiment, an electronic device includes: a camera module group including two or more camera modules, each camera module being configured to capture an image of a target to generate image data; an application processor, the application processor independently controlling the two or more camera modules in the camera module group and receiving the image data from each of the two or more camera modules; and a power management integrated circuit, the power management integrated circuit supplying power to the two or more camera modules in the camera module group in response to a control signal from the application processor. The two or more camera modules each include: an image sensor that captures an image of the target to generate first image data, outputs the first image data, and outputs an interval information signal; an image signal processor that receives the first image data, performs image processing on the first image data to generate second image data, and outputs the second image data; and an interface circuit that receives the second image data and the interval information signal and outputs the second image data as the image data. The interface circuit adjusts the timing of outputting the third image data based on the interval information signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present inventive concept will become apparent by describing in detail example embodiments of the present inventive concept with reference to the attached drawings.

[0011] Figure 1 A camera module according to an embodiment of the inventive concept is shown.

[0012] Figure 2 An image sensor according to an embodiment of the inventive concept is illustrated.

[0013] Figure 3 Shows Figure 2 An example of a sensing interval of an image sensor.

[0014] Figure 4 An example of an interface circuit according to an embodiment of the inventive concept is shown.

[0015] Figure 5 An example is shown in which the interface circuit outputs the third image data.

[0016] Figure 6 The change of the ramp signal of the image sensor and the output of the third image data are shown together.

[0017] Figure 7 An example of an operating method of the interface circuit is shown.

[0018] Figure 8 Examples of ramp signals and interval information signals are shown.

[0019] Fig. 9 An example is shown where the interface circuit calculates an inhibit interval based on the start of a transmission.

[0020] Fig.10 An example is shown where the interface circuit calculates an inhibit interval based on the end of a transmission.

[0021] Fig.11 An example is shown in which the interface circuit calculates the inhibit interval based on the start of transmission and the end of transmission.

[0022] Fig.12 An example is shown in which the interface circuit outputs the third image data based on the inhibition interval.

[0023] Fig.13 An example of a camera module setting up and initializing an inhibit interval is shown.

[0024] Fig.14 is a block diagram of an electronic device including a multi-camera module.

[0025] Fig.15 yes Fig.14 Detailed block diagram of the camera module. DETAILED DESCRIPTION

[0026] Below, embodiments of the inventive concept may be described in detail and clearly to such an extent that a person having ordinary skill in the art can implement the inventive concept.

[0027] Figure 1 1 shows a camera module 100 according to an embodiment of the inventive concept. Figure 1 , the camera module 100 may include an image sensor 110 , an image signal processor 120 , an interface circuit 130 , and first to fourth connectors 101 to 104 .

[0028] The first to third connectors 101 to 103 may be used for the camera module 100 to output image data (e.g., third image data ID3) to an external device (e.g., an application processor). The fourth connector 104 may be used to provide power including voltage and current to the image sensor 110, the image signal processor 120, and the interface circuit 130. As used herein, the term "connector" may refer to a component for outputting voltage, current, signal, etc. to an external device or receiving voltage, current, signal, etc. from an external device. The term "connector" may be interchangeable with any other terms having similar meanings (e.g., pads and terminals).

[0029] The image sensor 110 may include a lens 111. The image sensor 110 may capture an image of a target using the lens 111. For example, the image sensor 110 may capture an image of a target by capturing the intensity of light incident through the lens 111 after being reflected by the target. The image sensor 110 may output the captured image as first image data ID1.

[0030] The image sensor 110 may also output an interval information signal II. The interval information signal II may include information about at least one interval (or period) during which the image sensor 110 performs sensing. For example, the interval information signal II may include information about at least one time interval during which noise can be added to the first image data ID1 of the image sensor 110 due to an instantaneous change in voltage or current (e.g., a peak current) of the power system.

[0031] The image signal processor 120 may receive the first image data ID1 from the image sensor 110. The image signal processor 120 may perform image processing on the first image data ID1. For example, the image processing may include various types of processing, such as noise removal, white balance, format conversion, compression, and target recognition. The format conversion may include converting image data based on a Bayer pattern or a non-Bayer pattern (e.g., a quaternary system (tetra) or a nona system (nona)) into image data based on RGB. The image signal processor 120 may output the result of the image processing as the second image data ID2.

[0032] The interface circuit 130 may receive the second image data ID2 from the image signal processor 120. The interface circuit 130 may store the second image data ID2. The interface circuit 130 may also receive the interval information signal II from the image sensor 110. The interface circuit 130 may output the second image data ID2 as the third image data ID3 based on the interval information signal II.

[0033] For example, the interface circuit 130 may perform an operation of causing a voltage or current of the power system to change instantaneously in a state outside of at least one interval indicated by the interval information signal II. For example, the interface circuit 130 may start and end the output of the third image data ID3 in a state outside of at least one interval known by the interval information signal II (e.g., based on time).

[0034] That is, the image sensor 110 and the interface circuit 130 can prevent, eliminate or suppress noise that may occur due to instantaneous changes in the voltage and current of the power system. When the interface circuit 130 operates in response to the interval information signal II from the image sensor 110, the quality of the third image data ID3 output by the camera module 100 can be improved.

[0035] In an embodiment, the interface circuit 130 may output the third image data ID3 through the first to third connectors 101 to 103 according to the C-PHY standard defined by MIPI (Mobile Industry Processor Interface). However, the scheme in which the interface circuit 130 outputs the third image data ID3 is not limited to C-PHY.

[0036] Figure 2 An image sensor 200 according to an embodiment of the inventive concept is shown. Figure 2 The image sensor 200 may correspond to Figure 1 The image sensor 110. Figure 1 and Figure 2 , the image sensor 200 may include a pixel array 210 , a row driver 220 , a ramp signal generator (RSG) 230 , a comparator group 240 , a counter group 250 , a memory group 260 , and a timing generator (TG) 270 .

[0037] The pixel array 210 may include a plurality of pixels PX arranged in a matrix form along rows and columns. Each of the plurality of pixels PX may include a photoelectric conversion element. For example, the photoelectric conversion element may include a photodiode, a phototransistor, a photogate, a pinned photodiode, etc. Each of the plurality of pixels PX may sense light using a photoelectric conversion element, and may convert the sensed amount of light into an electrical signal, such as a voltage or a current.

[0038] A plurality of pixels PX may be divided into a plurality of pixel groups. Each pixel group may include at least two or more pixels PX. In an embodiment, a pixel group may include pixels PX arranged in two rows and two columns or in three rows and three columns. The pixels PX constituting a pixel group may share at least one floating diffusion node (or floating diffusion region).

[0039] A color filter array may be inserted between the pixel array 210 and the lens 111. The color filter array may include a red (R) color filter, a green (G) color filter, and a blue (B) color filter. A pixel group may correspond to a color filter of the same color. For example, a pixel group may include a red (R) pixel PX for converting light of a red spectrum into an electrical signal, a green (Gr or Gb) pixel PX for converting light of a green spectrum into an electrical signal, or a blue (B) pixel PX for converting light of a blue spectrum into an electrical signal. For example, the color filters in the color filter array on the pixel array 210 may be arranged in the form of a Bayer pattern or in the form of a non-Bayer pattern.

[0040] The row driver 220 may be connected to the rows of pixels PX of the pixel array 210 through the first to m-th row lines RL1 to RLm (m is a positive integer). The row driver 220 may decode the address and / or control signal generated by the timing generator 270. According to the decoding result, the row driver 220 may sequentially drive the first to m-th row lines RL1 to RLm of the pixel array 210, and may drive the selected row line with a specific voltage. For example, the row driver 220 may drive the selected row line with a voltage suitable for sensing light.

[0041] Each of the first to mth row lines RL1 to RLm respectively connected to rows of pixels PX may include two or more lines. The two or more lines may transmit, for example, a signal for selecting a pixel PX, a signal for resetting a floating diffusion area, a signal for selecting a column line, etc.

[0042] The ramp signal generator 230 may generate a ramp signal RS. The ramp signal generator 230 may operate under the control of the timing generator 270. For example, the ramp signal generator 230 may operate in response to a control signal such as a ramp enable signal or a mode signal. When the ramp enable signal is activated, the ramp signal generator 230 may generate a ramp signal RS having a slope set based on the mode signal. For example, the ramp signal generator 230 may generate a ramp signal RS that continuously (i.e., monotonically / continuously) decreases or increases from an initial level over time.

[0043] The comparator group 240 may be connected to the columns of the pixels PX of the pixel array 210 through the first to n-th column lines CL1 to CLn (n is a positive integer). The comparator group 240 may include first to n-th comparators C1 to Cn connected to the first to n-th column lines CL1 to CLn, respectively. The first to n-th comparators C1 to Cn may receive the ramp signal RS from the ramp signal generator 230 in common (i.e., through a shared connection).

[0044] The first to nth comparators C1 to Cn may compare the voltage (or current) of the first to nth column lines CL1 to CLn with the ramp signal RS. When the continuously decreasing (or increasing) ramp signal RS becomes smaller than (or larger than) the voltage (or current) of the first to nth comparators C1 to Cn, the first to nth comparators C1 to Cn may invert the output signal. That is, the first to nth comparators C1 to Cn may output the result of comparing the magnitude (or amount) of the voltage (or current) output from the pixel PX to the first to nth column lines CL1 to CLn with the ramp signal RS.

[0045] The counter group 250 may include first to nth counters CNT1 to CNTn that receive output signals of the first to nth comparators C1 to Cn, respectively. The first to nth counters CNT1 to CNTn may start counting operations at the same time as the ramp signal RS starts to decrease (or increase) (for example, when the ramp signal RS starts to decrease (or increase)), before the ramp signal RS starts to decrease (or increase), or after the ramp signal RS starts to decrease (or increase). When the output signals of the first to nth comparators C1 to Cn are inverted, the first to nth counters CNT1 to CNTn may stop counting operations. For example, each of the first to nth counters CNT1 to CNTn may stop counting operations when the output signal of the corresponding comparator of the first to nth comparators C1 to Cn is inverted.

[0046] That is, the first to nth comparators C1 to Cn may measure the magnitudes of voltages (or currents) of the first to nth column lines CL1 to CLn using the ramp signal RS, and the first to nth counters CNT1 to CNTn may convert the measurement results into digital values.

[0047] The first to nth memories M1 to Mn of the memory group 260 may include first to nth memories M1 to Mn that receive output signals of the first to nth counters CNT1 to CNTn, respectively. The first to nth memories M1 to Mn may store the received output signals and may output the stored signals as the first image data ID1. For example, the first to nth memories M1 to Mn may include latches.

[0048] The timing generator 270 may control the timing of the operation of the image sensor 200. The timing generator 270 may control the timing of the row driver 220 sequentially selecting the first to mth row lines RL1 to RLm, and may control the timing of transmitting the signal through two or more lines included in the row lines selected from the first to mth row lines RL1 to RLm.

[0049] The timing generator 270 may control the timing of the ramp signal generator 230 generating the ramp signal RS and the timing of initializing / outputting the ramp signal RS. The timing generator 270 may control the timing of the first to nth comparators C1 to Cn starting the comparison operation and the timing of initializing the first to nth comparators C1 to Cn.

[0050] The timing generator 270 may control the timing at which the first to nth counters CNT1 to CNTn start counting operations and the timing at which the first to nth counters CNT1 to CNTn are initialized. The timing generator 270 may control the timing at which the first to nth memories M1 to Mn output the first image data ID1 and the timing at which the first to nth memories M1 to Mn are initialized.

[0051] Although not described above, the timing generator 270 may be configured to control various timings of various components required for the image sensor 200 to capture an image of a subject and output the captured image as the first image data ID1 .

[0052] Figure 3 Shows Figure 2 An example of a sensing interval SI of the image sensor 200. Figure 3 In the embodiment, the horizontal axis represents time "T" and the vertical axis represents voltage "V". Figure 3 The variation of the voltage of the ramp signal RS with time “T” is shown.

[0053] Reference Figure 2 and Figure 3 , the sensing interval SI may be an interval in which one row line is selected from the first to mth row lines RL1 to RLm of the pixels PX belonging to the pixel array 210 of the image sensor 200, and data sensed by the pixels PX of the selected row line is output as the first image data ID1. The selection of a row line and the reception of sensed data therefrom may be collectively referred to herein as “scanning” by the image sensor 200.

[0054] The sensing interval SI may include a reset phase RP and a signal phase SP. In the reset phase RP, the image sensor 200 may detect internal noise. The reset phase RP may include initialization INI and counting CNT.

[0055] In the initialization INI of the reset phase RP, the first to nth comparators C1 to Cn, the first to nth counters CNT1 to CNTn, and the first to nth memories M1 to Mn may be initialized. In the count CNT of the reset phase RP, the ramp signal generator 230 may continuously decrease the ramp signal RS.

[0056] In the count CNT of the reset phase RP, the first to nth column lines CL1 to CLn may have an initialized voltage (or current). The first to nth comparators C1 to Cn may compare the noise of the initialized voltage (or current) present on the first to nth column lines CL1 to CLn with the ramp signal RS.

[0057] In the count CNT of the reset phase RP, the first to nth counters CNT1 to CNTn may count the output signals of the first to nth comparators C1 to Cn, wherein the output signals include the noise (e.g., DC offset or gain thereof) of the first to nth comparators C1 to Cn in addition to the noise sensed by the first to nth comparators C1 to Cn. That is, in the reset phase RP, the noise of the first to nth column lines CL1 to CLn and the first to nth comparators C1 to Cn may be measured as count values ​​by the first to nth counters CNT1 to CNTn. The count values ​​may be stored in the first to nth memories M1 to Mn, respectively.

[0058] The signal phase SP may include an initialization INI and a count CNT. In the initialization INI of the signal phase SP, the first to nth comparators C1 to Cn, the first to nth counters CNT1 to CNTn, and the first to nth memories M1 to Mn may be initialized. In the initialization INI of the signal phase SP, the pixels PX of the row lines selected from the first to mth row lines RL1 to RLm may convert the amount of light received from outside the image sensor 200 into a voltage (or current). For example, the voltage (or current) may be stored at a floating diffusion node.

[0059] In the count CNT of the signal phase SP, the ramp signal generator 230 may continuously decrease the ramp signal RS. In the count CNT of the signal phase SP, the pixels PX of the selected row line may output a voltage (or current) corresponding to the sensed light amount to the first to nth column lines CL1 to CLn.

[0060] In the counting CNT of the signal phase SP, the first to nth comparators C1 to Cn may respectively compare the voltages (or currents) of the first to nth column lines CL1 to CLn with the ramp signal RS. The first to nth counters CNT1 to CNTn may respectively count the output signals of the first to nth comparators C1 to Cn.

[0061] After the counting CNT is completed, the count values ​​may be stored in the first to nth memories M1 to Mn, respectively. The count value of the reset phase RP may be subtracted from the count value of the signal phase SP stored in the first to nth memories M1 to Mn. That is, noise may be removed. The result of the subtraction may be output as the first image data ID1.

[0062] The image sensor 200 may repeatedly perform the sensing interval SI. For example, the image sensor 200 may perform the sensing interval SI while sequentially selecting the first to m-th row lines RL1 to RLm. Figure 3 The start and end of the sensing interval SI are shown in detail in FIG. However, the sensing interval SI may vary depending on the implementation of the image sensor 200 .

[0063] For example, Figure 3 As shown, the sensing interval SI may include one reset phase RP and one signal phase SP. For another example, the sensing interval SI may be modified to include two reset phases and two signal phases.

[0064] Figure 4 1 shows an example of an interface circuit 300 according to an embodiment of the inventive concept. In an embodiment, the interface circuit 300 may correspond to Figure 1 The interface circuit 130. Figure 1 and Figure 4 The interface circuit 300 may include first to third connectors 301 to 303 , a buffer 310 , a state machine 320 , a physical circuit 330 , and a transmitter group 340 .

[0065] The first to third connectors 301 to 303 may correspond to Figure 1 The first to third connectors 101 to 103 of the image signal processor 120. The buffer 310 may receive the second image data ID2 output from the image signal processor 120. The buffer 310 may store the second image data ID2. For example, the buffer 310 may be a line buffer that stores the second image data ID2 in units of lines (e.g., rows). The buffer 310 may be configured to store data of at least two lines.

[0066] The state machine 320 may receive the interval information signal II from the image sensor 110. The state machine 320 may activate the trigger signal TRG so that no instantaneous change in voltage or current occurs when data of at least one line is stored in the buffer 310 and within at least one interval indicated by the interval information signal II.

[0067] For example, the buffer 310 may output one line of data to the physical circuit 330 in response to the trigger signal TRG. Alternatively, the physical circuit 330 may read one line of data from the buffer 310 in response to the trigger signal TRG. Figure 4 3 shows an example in which the trigger signal TRG is transmitted to both the buffer 310 and the physical circuit 330 , but the trigger signal TRG may be transmitted to one of the buffer 310 and the physical circuit 330 .

[0068] The physical circuit 330 may receive data for one line from the buffer 310. The physical circuit 330 may encode the data for one line in a form suitable for transmission. For example, the physical circuit 330 may encode the data for one line according to C-PHY defined by MIPI. The physical circuit 330 may drive the transmitter group 340 based on the encoded data.

[0069] The transmitter group 340 may include first to third transmitters T1 to T3 and a high-speed transmitter HT. The first to third transmitters T1 to T3 may be connected to the first to third connectors 301 to 303, respectively. The high-speed transmitter HT may have three outputs connected to the first to third connectors 301 to 303, respectively.

[0070] The first to third transmitters T1 to T3 can be in a low power mode LP ( Figure 5 ) performs low power transmission in a low power interval of the low power mode LP. In some embodiments, the low power interval of the low power mode LP may also be a low speed transmission interval. The high speed transmitter HT may be in a high speed transmission mode HS ( Figure 5 ) performs high-speed transmission in a high-speed transmission interval of . The first to third transmitters T1 to T3 and the high-speed transmitter HT can perform low-power transmission and high-speed transmission according to C-PHY defined by MIPI.

[0071] Figure 5 FIG. 2 shows an example in which the interface circuit 300 outputs the third image data ID3. Figure 5 In FIG. 1 , the horizontal axis represents time “T” and the vertical axis represents an example of a signal output as the third image data ID3. Figure 1 , Figure 4 and Figure 5 , the interface circuit 300 can output the third image data ID3 in the high-speed transmission mode HS.

[0072] Initially, the interface circuit 300 may be in the low power mode LP. When at least one line of data is stored in the buffer 310, the interface circuit 300 may enter the high-speed transmission mode HS, and may output one line of data as the third image data ID3 through high-speed transmission. Thereafter, the interface circuit 300 may enter the low power mode LP again.

[0073] The interface circuit 300 may repeat the low power mode LP and the high speed transmission mode HS to output the third image data ID3 in units of lines. When the interface circuit 300 enters the high speed transmission mode HS from the low power mode LP, there may be a transmission start interval of transmission start SoT between the low power mode LP and the high speed transmission mode HS. When the interface circuit 300 enters the low power mode LP from the high speed transmission mode HS, there may be a transmission end interval of transmission end EoT between the high speed transmission mode HS and the low power mode LP.

[0074] In at least one of the start of transmission SoT or the end of transmission EoT, a transient change in voltage or current may occur. For example, in the start of transmission SoT in which switching from the low power mode LP to the high speed transmission mode HS is performed, the amount of current consumed by the interface circuit 300 may suddenly increase. This may result in a peak current in which the amount of current increases (or decreases) transiently.

[0075] For example, in the end of transmission EoT when switching from the high-speed transmission mode HS to the low-power mode LP is performed, the amount of current consumed by the interface circuit 300 may suddenly decrease, which may result in a peak current where the amount of current decreases (or increases) instantaneously.

[0076] like Figure 1 As shown, the image sensor 110 and the interface circuit 130 are configured to receive power in common through the fourth connector 104. Therefore, even at the image sensor 110, the peak current generated by the interface circuit 300 can be generated identically.

[0077] Figure 6 The change of the ramp signal RS of the image sensor 110 and the output third image data ID3 are shown together. Figure 6 In the figure, the horizontal axis represents time "T" and the vertical axis represents voltage "V". Figure 6 2 and 3. For better understanding, the ramp signal RS and the output third image data ID3 are shown together, but the voltage "V" of the ramp signal RS and the output third image data ID3 may be independent of each other.

[0078] Reference Figure 1 , Figure 2 and Figure 6 As shown in the dotted circle, the start of transmission SoT may exist in the count CNT of the reset phase RP belonging to the first sensing interval SI. In addition, the end of transmission EoT may exist in the count CNT of the signal phase SP belonging to the first sensing interval SI. In addition, the end of transmission EoT may exist in the initialization INI and the count CNT of the signal phase SP belonging to the second sensing interval SI.

[0079] The count CNT belonging to each of the reset phase RP and the signal phase SP can measure the size of the noise or signal using the ramp signal RS. When a peak current is generated in the count CNT, the level of the ramp signal RS also generates a peak. That is, in the process of measuring the size of the noise or signal, peak noise may appear at the ramp signal RS. The peak noise of the ramp signal RS may be displayed at the third image data ID3 (for example, in the third image data ID3) in the form of, for example, horizontal stripes.

[0080] In order to prevent / suppress noise caused by the peak current of the interface circuit 300, the image sensor 110 may output information about at least one interval (e.g., time interval) in which noise may occur due to the peak current during the sensing interval SI as the interval information signal II. For example, the at least one interval may include at least a portion of the interval in which the ramp signal RS continues to decrease (or increase).

[0081] During at least one interval indicated by the interval information signal II, the interface circuit 300 may prohibit operations that may cause a peak current (e.g., a start of transmission SoT or an end of transmission EoT), and may perform operations that may cause a peak current in a state outside of at least one (time-based) interval.

[0082] Figure 7 An example of the method of operation of the interface circuit 300 is shown. Figure 1 , Figure 4 and Figure 7 In operation S110, the interface circuit 300 may receive an interval information signal II from the image sensor 110. The interval information signal II may include information on at least one prohibition interval belonging to one sensing interval SI.

[0083] In operation S120, the interface circuit 300 may calculate a prohibition interval based on the interval information signal II. For example, the interface circuit 300 may calculate a prohibition interval in which the prohibition trigger signal TRG is activated based on the operating characteristics of the interface circuit 300 and information about at least one interval indicated by the interval information signal II. For example, the interface circuit 300 may calculate at least one prohibition interval within one sensing interval SI.

[0084] In operation S130, the interface circuit 300 may activate the trigger signal TRG in a state outside the prohibition interval. For example, after storing data of at least one line in the buffer 310 and when the current interval is not the prohibition interval, the state machine 320 of the interface circuit 300 may activate the trigger signal TRG. In response to the trigger signal TRG, the buffer 310 and the physical circuit 330 of the interface circuit 300 may output the third image data ID3.

[0085] Figure 8 An example of a ramp signal RS and an interval information signal II is shown. Figure 8 In the figure, the horizontal axis represents time "T" and the vertical axis represents voltage "V". Figure 82 shows the ramp signal RS and the interval information signal II. For better understanding, the ramp signal RS and the interval information signal II are shown together. However, the voltage "V" of the ramp signal RS and the voltage of the interval information signal II may be independent of each other.

[0086] Reference Figure 1 , Figure 2 and Figure 8 , the interval information signal II may include a first critical interval CI1 and a second critical interval CI2 within the sensing interval SI. The first critical interval CI1 may be associated with a first portion of the ramp signal RS that continues to decrease (or increase) during the reset phase RP. The second critical interval CI2 may be associated with a second portion of the ramp signal RS that continues to decrease (or increase) during the signal phase SP.

[0087] The image sensor 200 can notify the interface circuit 300 of the first critical interval CI1 and the second critical interval CI2 by setting the interval information signal II to a high level within the first critical interval CI1 and the second critical interval CI2. In an embodiment, the positions of the first critical interval CI1 and the second critical interval CI2 in time can be determined according to the structural and operational characteristics of the image sensor 200. Figure 8 The first critical interval CI1 and the second critical interval CI2 shown in FIG. 1 are examples, and the inventive concept is not limited thereto.

[0088] In an embodiment, the timing generator 270 may control the timing at which the interval information signal II turns to a high level and the timing at which the interval information signal II turns to a low level. During the manufacturing process of the image sensor 200, the timing at which the timing generator 270 controls the interval information signal II may be set to the image sensor 200 / set for the image sensor 200.

[0089] Fig. 9 FIG. 4 shows an example in which the interface circuit 300 calculates the inhibit interval based on the start of transmission SoT. Fig. 9 In the figure, the horizontal axis represents time "T" and the vertical axis represents voltage "V". Fig. 9 For better understanding, the first inhibit interval signal INH1 and the interval information signal II are shown together, but the voltage "V" of the first inhibit interval signal INH1 and the voltage of the interval information signal II may be independent of each other.

[0090] Reference Figure 1 , Figure 4 and Fig. 9 , the image sensor 110 may be as shown in FIG. Figure 8The interface circuit 300 can calculate the disable interval of the trigger signal TRG so that there is no transmission start SoT during the high level period of the interval information signal II.

[0091] The interface circuit 300 may apply the time from when the trigger signal TRG is activated to when the transmission of the transmitter group 340 starts SoT as the transmission delay TD to the prohibition interval. For example, the interface circuit 300 may apply the transmission delay TD to the prohibition interval by calculating an intermediate signal that is earlier than the interval information signal II by the transmission delay TD (i.e., appears earlier in time than the interval information signal II).

[0092] In addition, the interface circuit 300 can apply the duration of the interval of the transmission start SoT to the prohibition interval by calculating the first prohibition interval signal INH1 which is extended (EXT) to be earlier than the intermediate signal by the duration of the interval of the transmission start SoT. In the case where the prohibition interval is set according to the first prohibition interval signal INH1, the interface circuit 300 can avoid the occurrence of the transmission start SoT for outputting the third image data ID3 during the high level period of the interval information signal II.

[0093] Fig.10 FIG. 4 shows an example in which the interface circuit 300 calculates the inhibit interval based on the end of transmission EoT. Fig.10 In the figure, the horizontal axis represents time "T" and the vertical axis represents voltage "V". Fig.10 For better understanding, the second inhibit interval signal INH2 and the interval information signal II are shown together, but the voltage "V" of the second inhibit interval signal INH2 and the voltage of the interval information signal II may be independent of each other.

[0094] Reference Figure 1 , Figure 4 and Fig.10 , the image sensor 110 may be as shown in FIG. Figure 8 The interface circuit 300 may calculate the disable interval of the trigger signal TRG so that there is no end of transmission EoT during the high level period of the interval information signal II.

[0095] As described above, the interface circuit 300 may output the third image data ID3 in units of lines. Therefore, the amount of data output as the third image data ID3 between the start of transmission SoT and the end of transmission EoT may be consistent / fixed (e.g., line data). For example, in the high-speed transmission mode HS ( Figure 5) can output the same amount of data for multiple individual bursts / occurrences. Therefore, based on the frequency of outputting the third image data ID3, the interface circuit 300 can calculate the duration of the high-speed transmission mode HS associated with the third image data ID3, that is, the duration of the high-speed transmission interval as the transmission time TT. The interface circuit 300 can apply the time from the occurrence of the transmission start SoT to the occurrence of the transmission end EoT to the prohibition interval by calculating the intermediate signal that is delayed by the transmission time TT compared to the interval information signal II (that is, the transmission time TT is delayed after the interval information signal II).

[0096] In addition, the interface circuit 300 can apply the duration of the interval of the end of transmission EoT to the prohibition interval by calculating the second prohibition interval signal INH2 which is extended (EXT) to the duration of the interval of the end of transmission EoT delayed by the intermediate signal. In the case where the prohibition interval is set according to the second prohibition interval signal INH2, the interface circuit 300 can avoid the occurrence of the end of transmission EoT for outputting the third image data ID3 during the high level period of the interval information signal II.

[0097] Fig.11 FIG. 3 shows an example in which the interface circuit 300 calculates the inhibit interval based on the start of transmission SoT and the end of transmission EoT. Fig.11 In the figure, the horizontal axis represents time "T" and the vertical axis represents voltage "V". Fig.11 1, the interval information signal II, the first inhibit interval signal INH1, the second inhibit interval signal INH2 and the inhibit interval signal INH are shown in FIG. For better understanding, the interval information signal II, the first inhibit interval signal INH1, the second inhibit interval signal INH2 and the inhibit interval signal INH are shown together, but the voltages of the interval information signal II, the first inhibit interval signal INH1, the second inhibit interval signal INH2 and the inhibit interval signal INH may be independent of each other.

[0098] Reference Figure 1 , Figure 4 and Fig.11 , the interface circuit 300 may calculate the inhibit interval signal INH by performing an OR operation on the first inhibit interval signal INH1 and the second inhibit interval signal INH2.

[0099] exist Fig.11In the example, the remaining intervals except the prohibited interval indicated by the prohibited interval signal INH are marked in the form of a rectangle filled with dots. In the case where the activation trigger signal TRG is prohibited during the prohibited interval indicated by the prohibited interval signal INH, the interface circuit 300 can prevent / prohibit the occurrence of the transmission start SoT or the transmission end EoT in at least one interval indicated by the interval information signal II. Therefore, it is possible to prevent / suppress noise from being added to the first image data ID1 or the third image data ID3.

[0100] Fig.12 FIG. 2 shows an example in which the interface circuit 300 outputs the third image data ID3 based on the inhibition interval. Fig.12 In the figure, the horizontal axis represents time "T" and the vertical axis represents voltage "V".

[0101] Reference Figure 1 , Figure 4 and Fig.12 , the interface circuit 300 may activate the trigger signal TRG (eg, may allow the trigger signal TRG to transition to a high level or a low level) when it is outside the inhibit interval indicated by the inhibit interval signal INH (based on time). Fig.12 , the ramp signal RS, the interval information signal II, the inhibit interval signal INH, the trigger signal TRG, and the output third image data ID3 are shown in FIG. For better understanding, the ramp signal RS, the interval information signal II, the inhibit interval signal INH, the trigger signal TRG, and the output third image data ID3 are shown together, but the voltages of the ramp signal RS, the interval information signal II, the inhibit interval signal INH, the trigger signal TRG, and the output third image data ID3 may be independent of each other.

[0102] After the trigger signal TRG is activated and the transmission delay TD has passed, the transmission start SoT for outputting the third image data ID3 may occur. After the transmission start SoT occurs and the transmission time TT has passed, the transmission end EoT according to the output of the third image data ID3 may occur. Fig.12 As shown (refer to Figure 5 ), the transmission start SoT of the third image data ID3 and the transmission end EoT of the third image data ID3 may not overlap with the first critical interval CI1 and the second critical interval CI2 indicated by the interval information signal II, respectively. More specifically, the transmission start SoT may start after the trigger signal TRG and the transmission delay TD.

[0103] also, Fig.12It is shown that the interface circuit 300 can start and end the output / transmission of the third image data ID3 only when the interval information signal II is at a low level / voltage (and can avoid doing so when the interval information signal II is at a high level / voltage). Therefore, the transition to / from the high-speed transmission mode HS can only occur when the interval information signal II is at a low level / voltage ( Figure 5 ).

[0104] Fig.13 An example of the camera module 100 setting and initializing the inhibit interval is shown. Figure 1 , Figure 4 and Fig.13 In operation S210, the interface circuit 300 may detect the toggling of the interval information signal II. When the toggling of the interval information signal II is detected, in operation S220, the interface circuit 300 may perform operations S110 to S130 ( Figure 7 ) to set the prohibit interval.

[0105] For example, when the image sensor 110 generates the first image data ID1 of the first line, the image sensor 110 may switch the interval information signal II. Before transmitting the second image data ID2 to the buffer 310, the interface circuit 300 may set a prohibition interval in response to the switching of the interval information signal II.

[0106] While the camera module 100 continues to capture an image of a subject, the image sensor 110 may periodically output the first image data ID1 in units of lines. The interface circuit 300 may trigger output of the third image data ID3 by repeatedly using a set inhibit interval.

[0107] In an embodiment, based on the prohibition interval, the timing of the activation trigger signal TRG can be set from at least one of the switching timings of the interval information signal II. For example, the timing of the activation trigger signal TRG can be set to a delay value from at least one of the switching timings of the interval information signal II. Because the interface circuit 300 does not know the timing at which the image sensor 110 starts sensing, the interface circuit 300 can determine the timing of the activation trigger signal TRG based on the switching timing of the interval information signal II.

[0108] For example, the interface circuit 300 may include a counter. The interface circuit 300 may start a counting operation after a specific switching timing of the interval information signal II, and may activate the trigger signal TRG when the count value reaches the delay value. The interface circuit 300 according to an embodiment of the inventive concept is not limited to a counter. For example, the interface circuit 300 may be implemented using various devices that can activate the trigger signal TRG at a time delayed by as much as the delay value from a specific switching (or transition) timing of the interval information signal II.

[0109] In operation S230, the interface circuit 300 may detect the fixation of the interval information signal II. For example, when the camera module 100 does not capture an image of the target, the interval information signal II may be fixed without switching. In operation S240, when the interval information signal II is fixed (i.e., at a constant level without transition) for a predetermined threshold time or longer, the interface circuit 300 may reset the set prohibition interval. For example, the threshold time may be determined based on the duration of the sensing interval SI, such as a time corresponding to one sensing interval SI, a time corresponding to half of the sensing interval SI, or a time corresponding to k times of the sensing interval SI (k is a positive integer).

[0110] Thereafter, when the camera module 100 resumes capturing the target image at any time, the interface circuit 300 may set the inhibition interval again in operations S210 and S220 .

[0111] Fig.14 is a block diagram of an electronic device including a multi-camera module. Fig.15 yes Fig.14 Detailed block diagram of the camera module.

[0112] Reference Fig.14 , the electronic device 1000 may include a camera module group 1100 , an application processor 1200 , a power management integrated circuit (PMIC) 1300 , and an external memory 1400 .

[0113] The camera module group 1100 may include a plurality of camera modules 1100 a , 1100 b , and 1100 c . Fig.14 An embodiment in which three camera modules 1100a, 1100b, and 1100c are arranged is shown, but the embodiment is not limited thereto. In some embodiments, the camera module group 1100 may be modified to include only two camera modules. In addition, in some embodiments, the camera module group 1100 may be modified to include "n" camera modules (n is a natural number of 4 or greater). In an embodiment, the plurality of camera modules 1100a, 1100b, and 1100c of the camera module group 1100 may each include Figure 1 A camera module 100 is provided.

[0114] Next, we will refer to Fig.15 A detailed configuration of the camera module 1100 b is more fully described, but the following description may be equally applied to the remaining camera modules 1100 a and 1100 c .

[0115] Reference Fig.15 , the camera module 1100 b may include a prism 1105 , an optical path folding element (OPFE) 1110 , an actuator 1130 , an image sensing device 1140 , and a storage unit 1150 .

[0116] The prism 1105 may include a reflective plane 1107 having a light reflective material, and may change a path of light 'L' incident from the outside of the camera module 1100b.

[0117] In some embodiments, the prism 1105 may change the path of the light "L" incident along the first direction "X" to a second direction "Y" perpendicular to the first direction "X". In addition, the prism 1105 may change the path of the light "L" incident along the first direction "X" to a second direction "Y" perpendicular to the first direction "X" by rotating the reflective plane 1107 having the light reflective material around the central axis 1106 in the direction "A" or rotating the central axis 1106 in the direction "B". In this case, the OPFE 1110 may move in a third direction "Z" perpendicular to the first direction "X" and the second direction "Y".

[0118] In some embodiments, as shown in the figure, the maximum rotation angle of the prism 1105 in the direction "A" can be equal to or less than 15 degrees in the positive A direction and can be greater than 15 degrees in the negative A direction, but the embodiment is not limited thereto.

[0119] In some embodiments, prism 1105 can move within approximately 20 degrees in the positive B or negative B direction, between 10 and 20 degrees, or between 15 and 20 degrees; here, prism 1105 can move at the same angle in the positive B or negative B direction, or can move at similar angles within approximately 1 degree.

[0120] In some embodiments, the prism 1105 may move the reflective plane 1107 having the light reflective material in a third direction (eg, Z direction) parallel to the direction in which the central axis 1106 extends.

[0121] OPFE 1110 may include, for example, an optical lens composed of "m" groups (m is a natural number). Here, the "m" lenses may be moved along the second direction "Y" to change the optical zoom ratio of the camera module 1100b. For example, when the default optical zoom ratio of the camera module 1100b is "Z", the optical zoom ratio of the camera module 1100b may be changed to 3Z, 5Z, or 7Z or higher by moving the "m" lenses included in OPFE 1110.

[0122] The actuator 1130 may move the OPFE 1110 or the optical lens (hereinafter referred to as the “optical lens”) to a specific position. For example, the actuator 1130 may adjust the position of the optical lens so that the image sensor 1142 is placed at the focal length of the optical lens for accurate sensing.

[0123] The image sensing device 1140 may include an image sensor 1142, a control logic 1144, and a memory 1146. The image sensor 1142 may sense an image of a sensing target using light "L" provided through an optical lens. The image sensing device 1140 may correspond to Figure 1 In an embodiment, the image sensor 110 Fig.15 The image signal processor 120 and the interface circuit 300 are omitted to avoid unnecessary complication of drawing.

[0124] The control logic 1144 may control the overall operation of the camera module 1100b. For example, the control logic 1144 may control the operation of the camera module 1100b based on a control signal provided through the control signal line CSLb.

[0125] The memory 1146 may store information required for the operation of the camera module 1100b, such as calibration data 1147. The calibration data 1147 may include information required for the camera module 1100b to generate image data using light "L" provided from the outside of the camera module 1100b. The calibration data 1147 may include, for example, information about the above-mentioned rotation degree, information about the focal length, information about the optical axis, etc. In the case where the camera module 1100b is implemented in the form of a multi-state camera in which the focal length varies according to the position of the optical lens, the calibration data 1147 may include a focal length value for each position (or state) of the optical lens and information about autofocus.

[0126] The storage unit 1150 may store image data sensed by the image sensor 1142. The storage unit 1150 may be disposed outside the image sensing device 1140, and may be implemented in a shape in which the storage unit 1150 and a sensor chip constituting the image sensing device 1140 are stacked. In some embodiments, the storage unit 1150 may be implemented with an electrically erasable programmable read-only memory (EEPROM), but the embodiment is not limited thereto.

[0127] Refer to Fig.14 and Fig.15 In some embodiments, each of the plurality of camera modules 1100a, 1100b, and 1100c may include an actuator 1130. In this way, the same calibration data 1147 or different calibration data 1147 may be included in the plurality of camera modules 1100a, 1100b, and 1100c according to the operation of the actuator 1130 included in the plurality of camera modules 1100a, 1100b, and 1100c.

[0128] In some embodiments, one camera module (e.g., 1100b) among the multiple camera modules 1100a, 1100b, and 1100c may be a folded lens shaped camera module including the above-mentioned prism 1105 and OPFE 1110, and the remaining camera modules (e.g., 1100a and 1100c) may be vertical shaped camera modules not including the above-mentioned prism 1105 and OPFE 1110; however, the embodiments are not limited thereto.

[0129] In some embodiments, one camera module (e.g., 1100c) among the plurality of camera modules 1100a, 1100b, and 1100c may be, for example, a vertically shaped depth camera that extracts depth information using infrared (IR) rays. In this case, the application processor 1200 may combine image data provided from the depth camera with image data provided from any other camera module (e.g., 1100a or 1100b), and may generate a three-dimensional (3D) depth image.

[0130] In some embodiments, at least two camera modules (e.g., 1100a and 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may have different fields of view. In this case, at least two camera modules (e.g., 1100a and 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may include different optical lenses, but are not limited thereto.

[0131] In addition, in some embodiments, the fields of view of the plurality of camera modules 1100a, 1100b, and 1100c may be different. In this case, the plurality of camera modules 1100a, 1100b, and 1100c may include different optical lenses, but are not limited thereto.

[0132] In some embodiments, the plurality of camera modules 1100a, 1100b, and 1100c may be arranged to be physically separated from each other. That is, the plurality of camera modules 1100a, 1100b, and 1100c may not use the sensing area of ​​one image sensor 1142, but the plurality of camera modules 1100a, 1100b, and 1100c may include independent image sensors 1142, respectively.

[0133] Return to reference Fig.14 , the application processor 1200 may include an image processing device 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 may be implemented to be separate from the plurality of camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the plurality of camera modules 1100a, 1100b, and 1100c may be implemented using separate semiconductor chips.

[0134] The image processing device 1210 may include a plurality of sub-image processors (also referred to as sub-processors) 1212 a , 1212 b , and 1212 c , an image generator 1214 , and a camera module controller 1216 .

[0135] The image processing device 1210 may include a plurality of sub-image processors 1212a, 1212b, and 1212c, the number of which corresponds to the number of the plurality of camera modules 1100a, 1100b, and 1100c.

[0136] The image data generated from the camera modules 1100a, 1100b, and 1100c, respectively, may be provided to the corresponding sub-image processors 1212a, 1212b, and 1212c, respectively, through separate image signal lines ISLa, ISLb, and ISLc. For example, the image data generated from the camera module 1100a may be provided to the sub-image processor 1212a through the image signal line ISLa, the image data generated from the camera module 1100b may be provided to the sub-image processor 1212b through the image signal line ISLb, and the image data generated from the camera module 1100c may be provided to the sub-image processor 1212c through the image signal line ISLc. The image data transmission may be performed, for example, by using a camera serial interface (CSI) based on MIPI (Mobile Industry Processor Interface), but the embodiment is not limited thereto.

[0137] Meanwhile, in some embodiments, one sub-image processor may be configured to correspond to a plurality of camera modules. For example, sub-image processor 1212a and sub-image processor 1212c may be implemented as one unit, rather than as Fig.14 in this case, one of a plurality of pieces of image data respectively provided from camera module 1100a and camera module 1100c can be selected by a selection element (eg, a multiplexer), and the selected image data can be provided to an integrated sub-image processor.

[0138] The image data respectively provided to the sub-image processors 1212a, 1212b, and 1212c may be provided to the image generator 1214. The image generator 1214 may generate an output image by using the image data respectively provided from the sub-image processors 1212a, 1212b, and 1212c according to the generation information (or image generation information) or the mode signal.

[0139] In detail, the image generator 1214 may generate an output image by merging at least a portion of the image data generated from the camera modules 1100a, 1100b, and 1100c, respectively, having different fields of view, according to the generation information or the mode signal. In addition, the image generator 1214 may generate an output image by selecting one of the image data generated from the camera modules 1100a, 1100b, and 1100c, respectively, having different fields of view, according to the generation information or the mode signal.

[0140] In some embodiments, the generated information may include a zoom signal or a zoom factor. Furthermore, in some embodiments, the mode signal may be a signal based on a mode selected by a user, for example.

[0141] In the case where the generated information is a zoom signal (or zoom factor) and the camera modules 1100a, 1100b, and 1100c have different fields of view (or fields of view), the image generator 1214 may perform different operations according to the type of the zoom signal. For example, in the case where the zoom signal is a first signal, the image generator 1214 may merge the image data output from the camera module 1100a and the image data output from the camera module 1100c, and may generate an output image by using the merged image signal and the image signal output from the camera module 1100b that is not used in the merging operation. In the case where the zoom signal is a second signal different from the first signal, in the case where there is no image data merging operation, the image generator 1214 may select one of the image data output from the camera modules 1100a, 1100b, and 1100c, respectively, and may output the selected image data as an output image. However, the embodiment is not limited thereto, and if necessary, the manner of processing the image data may be modified without limitation.

[0142] In some embodiments, the image generator 1214 may generate merged image data with an increased dynamic range by receiving multiple image data with different exposure times from at least one of the multiple sub-image processors 1212a, 1212b, and 1212c and performing high dynamic range (HDR) processing on the multiple image data.

[0143] The camera module controller 1216 may provide control signals to the camera modules 1100a, 1100b, and 1100c, respectively. The control signals generated from the camera module controller 1216 may be provided to the corresponding camera modules 1100a, 1100b, and 1100c, respectively, through control signal lines CSLa, CSLb, and CSLc separated from each other.

[0144] According to the generation information including the zoom signal or the mode signal, one of the plurality of camera modules 1100a, 1100b and 1100c may be designated (using the designated information) as a master camera (e.g., 1100b), and the remaining camera modules (e.g., 1100a and 1100c) may be designated (using the designated information) as slave cameras. The designated information may be included in the control signal, and the control signal including the designated information may be provided to the corresponding camera modules 1100a, 1100b and 1100c respectively through control signal lines CSLa, CSLb and CSLc separated from each other.

[0145] The camera module used as the master and slave devices can be changed according to the zoom factor or the operating mode signal. For example, when the field of view of the camera module 1100a is wider than the field of view of the camera module 1100b and the zoom factor indicates a low zoom ratio, the camera module 1100b can be used as the master device and the camera module 1100a can be used as the slave device. On the contrary, when the zoom factor indicates a high zoom ratio, the camera module 1100a can be used as the master device and the camera module 1100b can be used as the slave device.

[0146] In some embodiments, the control signal provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c may include a synchronization enable signal. For example, in the case where the camera module 1100b is used as a master camera and the camera modules 1100a and 1100c are used as slave cameras, the camera module controller 1216 may send a synchronization enable signal to the camera module 1100b. The camera module 1100b provided with the synchronization enable signal may generate a synchronization signal based on the provided synchronization enable signal, and may provide the generated synchronization signal to the camera modules 1100a and 1100c through the synchronization signal line SSL. The camera module 1100b and the camera modules 1100a and 1100c may be synchronized using the synchronization signal to send image data to the application processor 1200.

[0147] In some embodiments, the control signal provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c may include mode information according to the mode signal. Based on the mode information, the plurality of camera modules 1100a, 1100b, and 1100c may operate in the first operating mode and / or the second operating mode with respect to the sensing speed.

[0148] In the first operation mode, the plurality of camera modules 1100a, 1100b, and 1100c may generate image signals at a first speed (e.g., may generate image signals at a first frame rate), may encode the image signals at a second speed (e.g., may encode the image signals at a second frame rate higher than the first frame rate), and transmit the encoded image signals to the application processor 1200. In this case, the second speed may be 30 times or less than the first speed.

[0149] The application processor 1200 may store the received image signal (i.e., the encoded image signal) in the internal memory 1230 provided in the application processor 1200 or in the external memory 1400 placed outside the application processor 1200. Thereafter, the application processor 1200 may read and decode the encoded image signal from the internal memory 1230 or the external memory 1400, and may display image data generated based on the decoded image signal. For example, a corresponding one of the sub-image processors 1212a, 1212b, and 1212c of the image processing device 1210 may perform decoding, and may also perform image processing on the decoded image signal.

[0150] In the second operation mode, the plurality of camera modules 1100a, 1100b, and 1100c may generate image signals at a third speed (e.g., may generate image signals at a third frame rate lower than the first frame rate), and transmit the image signals to the application processor 1200. The image signals provided to the application processor 1200 may be uncoded signals. The application processor 1200 may perform image processing on the received image signals, or may store the image signals in the internal memory 1230 or the external memory 1400.

[0151] The PMIC 1300 may provide power, such as a power supply voltage, to the plurality of camera modules 1100a, 1100b, and 1100c, respectively. For example, under the control of the application processor 1200, the PMIC 1300 may provide a first power to the camera module 1100a through a power signal line PSLa, may provide a second power to the camera module 1100b through a power signal line PSLb, and may provide a third power to the camera module 1100c through a power signal line PSLc.

[0152] In response to the power control signal PCON from the application processor 1200, the PMIC 1300 may generate power corresponding to each of the plurality of camera modules 1100a, 1100b, and 1100c, and may adjust the size of the power. The power control signal PCON may include a power adjustment signal for each operating mode of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the operating mode may include a low power mode. In this case, the power control signal PCON may include information about the camera module operating in the low power mode and the set power size. The power levels provided to the plurality of camera modules 1100a, 1100b, and 1100c, respectively, may be the same as or different from each other. In addition, the power size may be changed dynamically.

[0153] In the above embodiments, the components according to the present invention are described by using the terms "first", "second", "third", etc. However, the terms "first", "second", "third", etc. may be used to distinguish components from each other and do not limit the present invention. For example, the terms "first", "second", "third", etc. do not refer to any form of order or numerical meaning.

[0154] In the above embodiments, the components of the embodiments according to the present invention are described by using blocks. These blocks can be implemented using various hardware devices, such as integrated circuits (ICs), application specific ICs (ASICs), field programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs), as well as firmware, software (e.g., applications) driven in hardware devices, or a combination of hardware devices and software. In addition, blocks may include circuits implemented with semiconductor elements in integrated circuits or circuits registered as intellectual property (IP).

[0155] According to the inventive concept, the interface circuit of the camera module is configured to start and end the output of image data in a state outside the prohibited interval time determined by the image sensor. Therefore, a camera module that prevents / suppresses the peak current from the interface circuit from affecting the image data and generates image data with improved quality, an operating method of the camera module, and an electronic device including the camera module are provided.

[0156] While the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the scope of the inventive concept as set forth in the appended claims.

Claims

1. A camera module, the camera module include: an image sensor configured to capture an image of a target to generate first image data, output the first image data, and output an interval information signal; wherein the interval information signal includes information about at least one interval in which noise occurs due to a peak current of an interface circuit of the camera module; an image signal processor configured to receive the first image data, perform image processing on the first image data to generate second image data, and output the second image data; and the interface circuit being configured to receive the second image data and the interval information signal and output the second image data as third image data, Wherein, the interface circuit is also configured to adjust the timing of outputting the third image data based on the interval information signal, start the output of the third image data outside at least one time interval indicated by the interval information signal; and end the output of the third image data outside the at least one time interval.

2. The camera module according to claim 1, in, The image sensor comprises: a ramp signal generator configured to generate a ramp signal that decreases continuously during a specific interval, The interval information signal includes information about at least a portion of the specific interval.

3. The camera module according to claim 1, in, The interface circuit is further configured as: The third image data is output through a low-speed transmission interval, a transmission start interval, a high-speed transmission interval, and a transmission end interval.

4. The camera module according to claim 3, in, The interface circuit adjusts a timing of outputting the third image data in such a manner that the transmission start interval does not overlap with at least one interval indicated by the interval information signal.

5. The camera module according to claim 4, in, The interface circuit enters the high-speed transmission interval through the transmission start interval in response to a trigger signal, and outputs the third image data in the high-speed transmission interval; wherein the interface circuit is further configured to disable the trigger signal during a specific interval, and wherein the timing of the specific interval is advanced by a transmission delay relative to at least one interval, and the advanced specific interval is extended to be advanced by the length of the transmission start interval, and the transmission delay is required for the interface circuit to start outputting the third image data in response to the trigger signal.

6. The camera module according to claim 3, in, The interface circuit adjusts a timing of outputting the third image data in such a manner that the transmission end interval does not overlap with at least one interval indicated by the interval information signal.

7. The camera module according to claim 6, in, the interface circuit enters the high-speed transmission interval through the transmission start interval in response to a trigger signal, outputs the third image data in the high-speed transmission interval, and enters the transmission end interval after outputting the third image data, wherein the interface circuit is further configured to disable the trigger signal during a specific interval, and The timing of the specific interval is delayed by the duration of the high-speed transmission interval relative to the at least one interval, and the delayed specific interval is extended to be delayed by the duration of the transmission end interval.

8. The camera module according to claim 3, in, The interface circuit adjusts a timing of outputting the third image data in such a manner that the transmission start interval and the transmission end interval do not overlap with at least one interval indicated by the interval information signal.

9. The camera module according to claim 1, in, The interface circuit is further configured to adjust the timing in response to detecting that the interval information signal switches between a high level and a low level.

10. The camera module according to claim 1, in, The interface circuit is further configured to reset the timing in response to detecting that the interval information signal is at a constant level during a threshold time or longer.

11. The camera module according to claim 10, in, The threshold time depends on the time it takes the image sensor to scan a row of pixels of the image sensor.

12. The camera module according to claim 1, in, The interface circuit comprises: a buffer configured to store the second image data; a state machine configured to activate a trigger signal when the second image data is stored in the buffer and outside a prohibited interval defined based on the interval information signal; a physical circuit configured to convert the second image data into the third image data in response to the trigger signal; and A transmitter is configured to output the third image data.

13. The camera module according to claim 1, in, The interval information signal includes a high level and a low level, and The interface circuit starts and ends outputting the third image data only when the interval information signal is at the low level.

14. A method for operating a camera module, the method include: capturing an image of a target using an image sensor of the camera module to generate first image data; outputting an interval information signal identifying a prohibited interval from the image sensor; wherein the interval information signal includes information about at least one interval in which noise occurs due to a peak current of an interface circuit of the camera module; performing image processing on the first image data by an image signal processor of the camera module to generate second image data; When the prohibition interval is outside, the interface circuit of the camera module starts outputting the second image data as third image data; and when the prohibition interval is outside, the output of the third image data ends.

15. The method according to claim 14, in, The generation of the first image data further comprises: Converting incident light into voltage using pixels of the image sensor; generating a ramp signal including a monotonically decreasing or monotonically increasing ramp portion; converting the voltage quantity into digital data using the ramp signal; and outputting the digital data as the first image data, Wherein, the inhibit interval overlaps with at least a portion of the ramp portion of the ramp signal.

16. The method according to claim 14, in, The starting of outputting the second image data as third image data includes switching from a low power mode to a high speed transmission mode, and Wherein, ending the output of the third image data includes switching from the high-speed transmission mode to the low-power mode.

17. The method according to claim 16, in, In each of the plurality of bursts in the high-speed transmission mode, an equal amount of data is output.

18. An electronic device, the electronic device include: a camera module group, the camera module group comprising two or more camera modules, each camera module configured to capture an image of a target to generate image data; an application processor configured to independently control the two or more camera modules in the camera module group and receive the image data from each of the two or more camera modules; as well as a power management integrated circuit configured to supply power to the two or more camera modules in the camera module group in response to a control signal from the application processor, Wherein, the two or more camera modules each include: an image sensor configured to capture an image of the target to generate first image data, output the first image data, and output an interval information signal; wherein the interval information signal includes information about at least one interval in which noise occurs due to a peak current of an interface circuit of the camera module; an image signal processor configured to receive the first image data, perform image processing on the first image data to generate second image data, and output the second image data; and the interface circuit being configured to receive the second image data and the interval information signal and output the second image data as the image data, The interface circuit is further configured to adjust the timing of outputting the image data based on the interval information signal, start outputting the image data outside at least one time interval indicated by the interval information signal, and end outputting the image data outside the at least one time interval.

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