A data backup method, device and equipment

Abstract

The application provides a data backup method, device and equipment. A programmable chip is integrated on a mainboard. When storing data, the programmable chip parses the data packet to be backed up received from a network card to obtain a TCP data packet containing only a data stream in the data to be backed up. After the TCP data packet is stored in a target cache data space, the physical address of the TCP data packet written into the disk array is obtained from a CPU. Finally, the TCP data packet is stored in a specified position of the disk array corresponding to the physical address. It can be seen that the technical solution provided by the embodiment of the application can greatly reduce the CPU overhead, so that the CPU will not cause insufficient processing performance due to storage of the TCP data packet, thereby affecting the backup performance.

Description

TECHNICAL FIELD

[0001] The present application relates to data storage technology, in particular to a data backup method, device and equipment. BACKGROUND

[0002] Network backup refers to centralized management of full network data backup through data backup management software in combination with corresponding hardware and storage devices, so as to realize automatic backup, file archiving, data hierarchical storage, disaster recovery and the like. Backup client software is installed on a server in a network requiring data backup management, and data is centrally backed up to a storage device through the network.

[0003] At present, in the backup task execution process, the existing technology usually transmits two types of data packets, i.e., control flow type and data flow type, to the backup server. All data is transmitted by the CPU (central processing unit) to the backup software in the user space for processing, and then stored in the disk array. However, the CPU resources are consumed during data copying. However, in actual application, the data of control flow type is generally small and does not have a significant impact on the CPU, while the data of data flow type contains all the data to be backed up, usually several hundred MB to several hundred GB, which will cause a great CPU overhead, and further affect the backup performance due to insufficient CPU processing performance. SUMMARY

[0004] The present application provides a data backup method, device and equipment to reduce the impact of insufficient CPU processing performance on backup performance.

[0005] The technical scheme provided by the present application includes:

[0006] In a first aspect, the present application provides a data backup method applied to a programmable chip, the programmable chip being integrated on a mainboard and connected with a CPU, a network card and a disk array on the mainboard, and the method comprises the following steps:

[0007] analyzing the to-be-backed-up data received from the network card to obtain a transmission control protocol (TCP) data packet containing only data flow in the to-be-backed-up data;

[0008] finding an idle target cache data space for storing data blocks from the programmable chip, and storing the TCP data packet in the target cache data space;

[0009] sending a disk array addressing instruction for storing the TCP data packet to the CPU, so that the CPU determines a physical address for writing the TCP data packet to the disk array;

[0010] According to the physical address returned by the CPU, the TCP data packet is stored in a specified position of the disk array corresponding to the physical address.

[0011] In a second aspect, the embodiments of the present application provide another data backup method, applied to a CPU, the CPU being connected with a programmable chip integrated on a mainboard, and the programmable chip being further connected with a network card and a disk array, the method comprising:

[0012] obtaining a disk array addressing instruction for storing a TCP data packet sent by the programmable chip, wherein the TCP data packet is a data packet containing only a data stream obtained by the programmable chip by analyzing to-be-backup data received from the network card, and the disk array addressing instruction is an instruction sent by the programmable chip after storing the TCP data packet in a target cache data space found by the programmable chip to be idle for storing a data block;

[0013] determining a physical address for writing the TCP data packet into the disk array according to the disk array addressing instruction;

[0014] sending the determined physical address to the CPU according to a physical address returned by the CPU, so that the programmable chip stores the TCP data packet in a specified position of the disk array corresponding to the physical address.

[0015] In a third aspect, the embodiments of the present application provide a data backup device, applied to a programmable chip, the programmable chip being integrated on a mainboard and connected with a CPU, a network card and a disk array on the mainboard, the device comprising:

[0016] an analyzing unit, configured to analyze to-be-backup data received from the network card, and obtain a TCP data packet containing only a data stream in the to-be-backup data;

[0017] a data cache unit, configured to find a target cache data space for storing a data block from the programmable chip, and store the TCP data packet in the target cache data space;

[0018] an address instruction sending unit, configured to send a disk array addressing instruction for storing the TCP data packet to the CPU, so that the CPU determines a physical address for writing the TCP data packet into the disk array;

[0019] a disk storage unit, configured to store the TCP data packet in a specified position of the disk array corresponding to a physical address returned by the CPU according to the physical address.

[0020] In a fourth aspect, the embodiments of the present application provide another data backup device, which is applied to a CPU, the CPU is connected with a programmable chip integrated on a mainboard, the programmable chip is also connected with a network card and a disk array, and the device comprises:

[0021] an instruction obtaining unit, configured to obtain a disk array addressing instruction for storing a TCP data packet sent by the programmable chip; wherein the TCP data packet is a data packet containing only a data stream obtained by the programmable chip from analyzing to-be-backup data received from the network card; and the disk array addressing instruction is an instruction sent by the programmable chip after the TCP data packet is stored in a target cache data space in which an idle data block for storing data is found;

[0022] an address determining unit, configured to determine a physical address for writing the TCP data packet into the disk array according to the disk array addressing instruction;

[0023] an address sending unit, configured to send the determined physical address to the programmable chip according to a physical address returned by the CPU, so that the programmable chip stores the TCP data packet into a specified position of the disk array corresponding to the physical address.

[0024] As can be seen from the above technical solution, in the present application, the programmable chip is integrated on the mainboard, when storing data, the programmable chip analyzes the to-be-backup data packet received from the network card to obtain the TCP data packet containing only a data stream in the to-be-backup data, obtains the physical address for writing the TCP data packet into the disk array from the CPU after the TCP data packet is stored in the target cache data space, and finally stores the TCP data packet into the specified position of the disk array corresponding to the physical address. It can be seen that when storing the TCP data packet of the type of data stream by using the method provided by the embodiments of the present application, the CPU is no longer relied on for processing, but the programmable chip is specially configured on the mainboard to specially replace the CPU for sharing the storage, which greatly reduces the CPU overhead, so that the CPU will not cause insufficient processing performance due to storing the TCP data packet, and further affect the backup performance. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the present disclosure.

[0026] Figure 1 a schematic diagram of data backup provided by the prior art;

[0027] Figure 2 a flowchart of a data backup method provided by the present application;

[0028] Figure 3 A flowchart of another data backup method provided in this application;

[0029] Figure 4 A structural diagram of a data backup device provided in this application;

[0030] Figure 5 A structural diagram of another data backup device provided in this application;

[0031] Figure 6 This is a schematic diagram of the structure of an electronic device provided in this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] Network backup refers to the centralized management of data backup across the entire network in a network environment, achieved through data backup management software combined with appropriate hardware and storage devices. This enables automated backup, file archiving, tiered data storage, and disaster recovery. Its working principle involves selecting an application server on the network, installing network data storage management server-side software, and using it as the backup server for the entire network. A large-capacity storage device is then connected to this backup server. Backup client software is installed on the servers within the network that require data backup management, centrally backing up data to the storage devices over the network.

[0034] Currently, existing technologies in the backup task execution process, such as Figure 1 As shown, specifically: the backup client sends a control packet of backup type control flow via TCP socket. Figure 1 The dashed arrow indicates the control flow and the data packets of type data stream. Figure 1 The data stream (indicated by the solid arrow) is sent to the backup server, which then processes it according to the different data types received. The backup server receives control packets (control flow type) and data packets (data flow type) from the network card. The CPU copies the data containing the control packets and data packets from the network card to the socket buffer, and then copies the data in the socket buffer to the user buffer, switching from kernel mode to user mode. The backup software parses the data and performs corresponding processing, while simultaneously initiating write operations on the control flow data and data flow data that need to be stored. After switching from user mode to kernel mode, the CPU copies the user-specified storage data from the user buffer to the kernel buffer, and then copies the specified data from the kernel buffer to the disk array.

[0035] As can be seen, in existing technologies, all data is transmitted by the CPU to backup software in user space for processing before being stored in the disk array. However, data copying continuously consumes CPU resources. Frequent CPU usage for switching between kernel and user modes and for data copying can easily exceed the CPU's processing capacity, becoming a bottleneck for backup performance. In practical applications, control flow data is generally small and does not have a significant impact on the CPU. However, data flow data is different; it contains all the data that needs to be backed up, typically ranging from hundreds of MB to hundreds of GB. This causes significant CPU overhead, leading to insufficient CPU processing performance and impacting backup performance.

[0036] To address the aforementioned technical problems, this application provides a data backup method. This method is applied to a programmable chip integrated on a motherboard and connected to a CPU, network interface card (NIC), and disk array on the motherboard. Specifically, the method involves: parsing the data to be backed up received from the NIC to obtain TCP (Transmission Control Protocol) data packets containing only data streams; locating a free target cache data space for storing data blocks within the programmable chip and storing the TCP data packets in the target cache data space; sending a disk array addressing instruction to the CPU for storing the TCP data packets, so that the CPU determines the physical address to write the TCP data packets to the disk array; and storing the TCP data packets in a specified location on the disk array corresponding to the physical address returned by the CPU. As can be seen, when storing TCP packets of type data stream using the method provided in this application embodiment, the CPU is no longer fully relied upon for processing. Instead, a programmable chip is specially configured on the host to replace the CPU for storing TCP packets of type data stream. This greatly reduces CPU overhead and prevents the CPU from becoming insufficient in processing performance due to storing TCP packets, thereby affecting backup performance.

[0037] See Figure 2 , Figure 2 The flowchart of a data backup method provided in this application is shown. The method can be applied to a programmable chip, which is integrated on a motherboard and connected to a CPU, network card and disk array on the motherboard.

[0038] This programmable chip can primarily operate in parallel and is implemented using a hardware description language, serving as an independent intelligent computing unit.

[0039] like Figure 1 As shown, the process of implementing this method may include the following steps:

[0040] Step 101, parsing the to-be-backed-up data received from the network card to obtain TCP data packets containing only data streams in the to-be-backed-up data.

[0041] The to-be-backed-up data includes TCP control packets of the control stream type and TCP data packets of the data stream type. Since the TCP data packets of the data stream type contain data of several hundred MB to several hundred GB, the programmable chip can be specially used to parse and obtain the TCP data packets of the data stream type from the to-be-backed-up data packets for subsequent processing.

[0042] Step 102, finding an idle target cache data space for storing data blocks from the programmable chip, and storing the TCP data packets in the target cache data space.

[0043] The target cache data space is a cache space capable of storing TCP data packets, and the size of the target cache data space is greater than or equal to the TCP data packets. In this way, the TCP data packets can be stored. If the idle target cache data space is too small, as an embodiment, a prompt information indicating that the target cache data space is insufficient is sent to the user for processing to obtain sufficient target cache data space to store the TCP data packets.

[0044] Step 103, sending a disk array addressing instruction for storing the TCP data packets to the CPU to enable the CPU to determine a physical address of the disk array for writing the TCP data packets.

[0045] After the TCP data packets are cached in the idle target cache data space in the programmable chip, the disk array addressing instruction for obtaining the physical address of the disk array for storing the TCP data packets is sent to the CPU. In this way, the CPU sends the physical address to the programmable chip, and the TCP data packets can be stored in the disk array according to the physical address.

[0046] As an embodiment, the implementation of step 102 can include step A:

[0047] Step A, finding an idle target cache data space from the numbers corresponding to the cache data spaces.

[0048] The cache data spaces are spaces obtained by equally dividing the cache space of the programmable chip according to the maximum value of each backup data, and each cache data space corresponds to a different number.

[0049] In this step, the cache spaces include cache data spaces storing data blocks and idle cache data spaces not storing data blocks, and the target cache data space is a cache data space not storing data blocks.

[0050] It should be noted that the cache spaces can be equally divided according to the implementation manner as described above, can not be equally divided, and actually need to be divided, and the embodiment does not limit this.

[0051] As an embodiment, each cache data space is numbered, and the numbers of the cache data spaces are different from each other, the numbers of the cache data spaces in which the data blocks have been stored are stored in a set, and the numbers of the cache data spaces in which the data blocks have not been stored are stored in another set, so that when the idle cache data spaces are searched, the numbers of the cache data spaces in which the data blocks can be stored can be found from the other set, and then the cache data spaces are obtained according to the found numbers and used as target cache data spaces.

[0052] Based on step A, the implementation manner of step 103 can include step B:

[0053] In step B, a disk array addressing instruction carrying the numbers corresponding to the target cache data spaces and used for storing the TCP data packets is sent to the CPU, so that the CPU determines the physical address of the disk array to which the TCP data packets are written according to the numbers corresponding to the target cache data spaces.

[0054] The CPU obtains the disk array addressing instruction, parses the numbers from the disk array addressing instruction, determines the storage space required by the disk array according to the numbers, and then determines the physical address of the disk array to which the TCP data packets can be stored according to the specific storage condition of the disk array.

[0055] It can be seen that by applying the technical solution provided in the embodiment of the application, the target cache space for storing the TCP data packets can be quickly determined according to the numbers corresponding to the cache data spaces, and the CPU can also quickly determine the physical address for storing the TCP data packets.

[0056] The programmable chip of the embodiment stores the backup data to the hardware RAID (Redundant Arrays of independent Disks), avoids the data PCIE (Peripheral component interconnect express) DMA (Direct Memory Access) transfer between the network card and the operating system backup software and between the operating system software and the hardware RAID, obviously reduces the load of the whole machine in the PCIE MEMERY I / O, and effectively improves the performance of the data backup to the RAID.

[0057] Step 104, according to the physical address returned by the CPU, the TCP packet is stored in the specified location of the disk array corresponding to the physical address.

[0058] After the CPU determines the physical address of storing the TCP packet in the disk array, it directly returns to the programmable chip, so that the programmable chip stores the TCP packet in the specified location of the disk array corresponding to the physical address.

[0059] So far, the Figure 2 description shown.

[0060] From the above technical solution, in the present application, the programmable chip is integrated on the mainboard, when storing data, the programmable chip parses the TCP data packet containing only data stream in the to-be-backed-up data received from the network card, after the TCP data packet is stored in the target cache data space, the physical address of writing the TCP data packet into the disk array is obtained from the CPU, and finally, the TCP data packet is stored in the specified location of the disk array corresponding to the physical address. It can be seen that when the method provided by the present application is applied to store the TCP data packet of the data stream type, the CPU is no longer relied on for processing, but a programmable chip is specially configured on the host to specially replace the CPU for sharing storage, which greatly reduces the CPU overhead, so that the CPU will not cause insufficient processing performance due to storing the TCP data packet, thereby affecting the backup performance.

[0061] Referring to Figure 3 , Figure 3 the flowchart of another data backup method provided by the present application, the method can be applied to the CPU, the CPU is connected with the programmable chip integrated on the mainboard, and the programmable chip is also connected with the network card and the disk array.

[0062] As Figure 3 shown, the method can include the following steps:

[0063] Step 201, obtaining the disk array addressing instruction for storing the TCP data packet sent by the programmable chip.

[0064] Among them, the TCP packet is a data packet containing only data stream obtained by the programmable chip by parsing the to-be-backed-up data received from the network card; the disk array addressing instruction is an instruction sent by the programmable chip after storing the TCP data packet in the target cache data space in which the idle data block for storing data has been found.

[0065] The programmable chip sends a disk array addressing instruction for obtaining a physical address of the disk array for storing the TCP data packet to the CPU after buffering the TCP data packet in the idle target cache data space of the programmable chip, so that the CPU obtains the disk array addressing instruction and determines the physical address of the disk array for storing the TCP data packet according to the disk array addressing instruction.

[0066] Step 202: determining the physical address of the disk array for writing the stored TCP data packet according to the number corresponding to the target cache data space.

[0067] As an embodiment, the implementation of step 201 can include step C:

[0068] Step C: obtaining the disk array addressing instruction for storing the TCP data packet sent by the programmable chip and carrying the number corresponding to the target cache data space.

[0069] The target cache data space is the idle cache data space found by the programmable chip from the numbers corresponding to the cache data spaces, the cache data spaces are spaces obtained by equally dividing the cache space of the programmable chip according to the maximum value of each backup data, and each cache data space corresponds to a different number.

[0070] In this step, the cache space includes the cache data space storing the data block and the idle cache data space not storing the data block, and the target cache data space is the cache data space not storing the data block.

[0071] It should be noted that the cache space can be equally divided according to the above implementation, can not be equally divided, and can be actually divided, and the embodiment does not limit this.

[0072] As an embodiment, each cache data space is numbered, and the numbers of each cache data space are different, the numbers of the cache data spaces storing the data block are stored in a set, and the numbers of the cache data spaces not storing the data block are stored in another set, so that when the idle cache data space is searched, the numbers of the cache data spaces capable of storing the data block can be found from the other set, and then the cache data spaces are obtained according to the found numbers and used as the target cache data space.

[0073] Based on step C, the implementation of step 202 can include step D:

[0074] Step D: determining the physical address of the disk array for writing the TCP data packet according to the number corresponding to the target cache data space.

[0075] The CPU acquires a disk array addressing instruction, parses the numbers from the disk array addressing instruction, determines the storage space required by the disk array according to the numbers, and further determines the physical location capable of storing the TCP data packet according to the specific storage condition of the disk array.

[0076] It can be seen that, by applying the technical solution provided in the embodiment of the present application, the CPU can quickly determine the physical address for storing the TCP data packet according to the numbers corresponding to the cache data space.

[0077] In step 203, the determined physical address is sent to the programmable chip according to the physical address returned by the CPU, so that the programmable chip stores the TCP data packet into the specified location of the disk array corresponding to the physical address.

[0078] After the CPU determines the physical address of the disk array for storing the TCP data packet, the physical address is directly returned to the programmable chip, so that the programmable chip stores the TCP data packet into the specified location of the disk array corresponding to the physical address.

[0079] At this point, the process of Figure 3 is completed.

[0080] As can be seen from the above technical solution, in the present application, the programmable chip is integrated on the mainboard and connected with the CPU. When storing data, the CPU determines the physical address of the TCP data packet according to the disk array addressing instruction for determining the physical address of the TCP data packet sent by the programmable chip, and sends the determined physical address to the programmable chip, so that the programmable chip stores the TCP data packet into the specified location of the disk array corresponding to the physical address. It can be seen that, when storing the TCP data packet of the data stream type by applying the method provided in the embodiment of the present application, the CPU no longer depends on the CPU for processing, but a programmable chip is specially configured on the mainboard to specially replace the CPU for sharing the storage of the TCP data packet of the data stream type. This greatly reduces the CPU overhead, so that the CPU will not cause insufficient processing performance due to storing the TCP data packet, thereby affecting the backup performance.

[0081] After completing the steps of the flowchart shown in Figure 3 As an embodiment, the method further includes the following steps E to G after completing the steps of the flowchart shown in

[0082] In step E, the data to be backed up received from the network card is parsed to obtain the TCP control packet containing only the control flow in the data to be backed up.

[0083] In step F, the TCP control packet is copied to the Socket buffer, and the TCP control packet in the Socket buffer is copied to the user buffer on the user side.

[0084] Step G, after determining that the user gives a storage instruction to the TCP control package of the user buffer, copying the TCP control package from the user buffer to the disk array.

[0085] It can be seen that in the technical scheme provided by the embodiment of the application, the CPU only processes the TCP control package of the control flow type, so as to quickly complete the storage of the TCP control package in the disk array while reducing the CPU overhead.

[0086] The device provided by the application is described as follows:

[0087] Referring to Figure 4 , Figure 4 The structure diagram of the first disk backup device 400 for the switching device provided by the application is shown in the figure, the programmable chip is integrated on the mainboard and connected with the CPU, the network card and the disk array on the mainboard, and the device can include:

[0088] The analysis unit 401 is configured to analyze the to-be-backup data received from the network card to obtain the TCP data package containing only the data flow in the to-be-backup data;

[0089] The data caching unit 402 is configured to find the idle target cache data space for storing the data block from the programmable chip and store the TCP data package into the target cache data space;

[0090] The address instruction sending unit 403 is configured to send the disk array addressing instruction for storing the TCP data package to the CPU, so that the CPU determines the physical address for writing the TCP data package into the disk array;

[0091] The disk storage unit 404 is configured to store the TCP data package into the specified position of the disk array corresponding to the physical address according to the physical address returned by the CPU.

[0092] In one embodiment, the data caching unit 402 is specifically configured to find the idle target cache data space from the numbers corresponding to each cache data space, the cache data space is the space obtained by equally dividing the cache space of the programmable chip according to the maximum value of each backup data, and each cache data space corresponds to a different number;

[0093] The address instruction sending unit 403 is specifically configured to send the disk array addressing instruction for storing the TCP data package and carrying the number corresponding to the target cache data space to the CPU, so that the CPU determines the physical address for writing the TCP data package into the disk array according to the number corresponding to the target cache data space.

[0094] So far, the completion Figure 4 The description is shown.

[0095] From the above technical solutions, in the present application, the main board is integrated with a programmable chip. When storing data, the programmable chip parses the data packet to be backed up received from the network card to obtain a TCP data packet containing only data flow in the data to be backed up. After the TCP data packet is stored in the target cache data space, the physical address of the TCP data packet written into the disk array is obtained from the CPU. Finally, the TCP data packet is stored in the specified position of the disk array corresponding to the physical address. It can be seen that when the method provided by the embodiment of the present application is applied to store the TCP data packet of the data flow type, the CPU is no longer relied on for processing. Instead, a programmable chip is specially configured on the host to specially replace the CPU for sharing storage of the TCP data packet of the data flow type. This greatly reduces the CPU overhead, so that the CPU will not cause insufficient processing performance due to storage of the TCP data packet, thereby affecting the backup performance.

[0096] Referring to Figure 5 , Figure 5 The structure diagram of the second data backup device 500 for the switching device provided by the present application is shown. The device is applied to a CPU connected with a programmable chip integrated on a main board. The programmable chip is also connected with a network card and a disk array. The device can include:

[0097] An instruction obtaining unit 501 is configured to obtain a disk array addressing instruction for storing a TCP data packet sent by the programmable chip. The TCP data packet is a data packet containing only data flow obtained by the programmable chip by parsing data to be backed up received from the network card. The disk array addressing instruction is an instruction sent by the programmable chip after the TCP data packet is stored in the target cache data space in which the idle data block for storing data is found.

[0098] An address determining unit 502 is configured to determine a physical address of the storage TCP data packet written into the disk array according to the disk array addressing instruction.

[0099] An address sending unit 503 is configured to send the determined physical address to the programmable chip according to the physical address returned by the CPU, so that the programmable chip stores the TCP data packet in the specified position of the disk array corresponding to the physical address.

[0100] In one embodiment, the address determining unit 502 is specifically configured to:

[0101] acquire the disk array addressing instruction sent by the programmable chip and carrying the number corresponding to the target cache data space, wherein the target cache data space is an idle cache data space found by the programmable chip from the numbers corresponding to the cache data spaces, the cache data space is a space equally divided from the cache space of the programmable chip according to the maximum value of data backup each time, and each cache data space corresponds to a different number;

[0102] The address determination unit 502 is specifically configured to determine the physical address of the disk array to which the TCP data packet is written according to the number corresponding to the target cache data space.

[0103] Thus, the process of storing the TCP data packet is completed. Figure 5 The above description is shown.

[0104] As can be seen from the above technical solutions, in the present application, the programmable chip is integrated on the mainboard and connected with the CPU. When storing data, the CPU determines the physical address of the disk array according to the disk array addressing instruction sent by the programmable chip for determining the physical address of the TCP data packet, and sends the determined physical address to the programmable chip, so that the programmable chip stores the TCP data packet in the specified position of the disk array corresponding to the physical address. It can be seen that when storing the TCP data packet of the data stream type, the method provided by the present application no longer depends on the CPU for processing, but a programmable chip is specially configured on the host to specially replace the CPU for sharing the storage of the TCP data packet of the data stream type. This greatly reduces the CPU overhead, so that the CPU will not cause insufficient processing performance due to storing the TCP data packet, thereby affecting the backup performance.

[0105] The implementation process of the functions and roles of each unit in the above device is specifically described in the implementation process of the corresponding steps in the above method, which will not be described here.

[0106] The electronic device provided by the present application, from the hardware layer, the hardware architecture schematic diagram can be seen from the Figure 6 The machine readable storage medium stores machine executable instructions that can be executed by the processor. The processor is used to execute the machine executable instructions to realize the data backup operation disclosed in the above examples.

[0107] The machine readable storage medium provided by the present application stores machine executable instructions. When the machine executable instructions are called and executed by the processor, the machine executable instructions prompt the processor to realize the data backup operation disclosed in the above examples.

[0108] Here, the machine-readable storage medium can be any electronic, magnetic, optical, or other physical storage device that contains or stores information, such as executable instructions, data, etc. For example, the machine-readable storage medium can be a Random Access Memory (RAM), a volatile memory, a non-volatile memory, a flash memory, a storage drive, such as a hard drive, a solid-state drive, any type of storage disk (e.g., a floppy disk, a DVD, a CD, etc.), or any suitable storage medium, or a combination thereof.

[0109] The systems, apparatuses, modules or units disclosed in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer, and the specific form of the computer can be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0110] For the convenience of description, the above apparatuses are described in various units by functions respectively. Of course, the functions of the units can be implemented in one or more software and / or hardware in the implementation of the present application.

[0111] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, a disk storage, a CD-ROM, an optical storage, etc.) containing computer-usable program code.

[0112] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus produce a device implemented in accordance with the flowcharts and / or block diagrams. Figure 1 The device that implements the function specified in one flow or multiple flows and / or blocks. Figure 1 The device that implements the function specified in one flow or multiple flows and / or blocks.

[0113] Moreover, these computer program instructions can also be stored in a computer readable memory capable of directing a computer or other programmable data processing apparatus with the Figure 1 flow or flows and / or blocks Figure 1 flow or flows and / or blocks.

[0114] These computer program instructions can also be loaded into a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flow or flows and / or blocks Figure 1 flow or flows and / or blocks Figure 1 flow or flows and / or blocks.

[0115] For device embodiments, since they basically correspond to the method embodiments, the relevant parts can be seen from the parts of the method embodiments. The device embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed to multiple network units. Part or all of the modules can be selected to achieve the purposes of the present application according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0116] So far, the description of the devices shown in the Figure 6 is completed.

[0117] The above only describes the preferred embodiments of the present application, and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of protection of the present application.

Claims

1. A data backup method characterized by, The method is applied to a programmable chip integrated on a mainboard and connected with a central processing unit (CPU), a network card and a disk array on the mainboard, and comprises the following steps: analyzing the to-be-backed-up data received from the network card to obtain a transmission control protocol (TCP) data packet containing only a data stream in the to-be-backed-up data, wherein the to-be-backed-up data comprises a TCP control packet of a control stream type and a TCP data packet of a data stream type; finding an idle target cache data space for storing a data block in the programmable chip and storing the TCP data packet in the target cache data space; sending, to the CPU, a disk array addressing instruction carrying a number corresponding to the target cache data space and used for storing the TCP data packet, so that the CPU determines a required storage space size of the disk array according to the number corresponding to the target cache data space and determines a physical address for writing the TCP data packet into the disk array; storing the TCP data packet into a specified position of the disk array corresponding to the physical address according to the physical address returned by the CPU.

2. The method of claim 1, wherein, The step of finding an idle target cache data space for storing a data block in the programmable chip and storing the TCP data packet in the target cache data space comprises the following steps: finding an idle target cache data space from numbers corresponding to the cache data spaces, wherein the cache data spaces are spaces obtained by equally dividing a cache space of the programmable chip according to a maximum value of data each time, and each cache data space corresponds to a different number.

3. A data backup method characterized by, The method is applied to a CPU connected with a programmable chip integrated on a mainboard, and the programmable chip is further connected with a network card and a disk array, and comprises the following steps: obtaining a disk array addressing instruction carrying a number corresponding to a target cache data space and used for storing a TCP data packet sent by the programmable chip, wherein the TCP data packet is a data packet containing only a data stream obtained by the programmable chip by analyzing to-be-backed-up data received from the network card, the to-be-backed-up data comprises a TCP control packet of a control stream type and a TCP data packet of a data stream type, and the disk array addressing instruction is an instruction sent by the programmable chip after storing the TCP data packet in an idle target cache data space for storing a data block found by the programmable chip; determining a required storage space size of the disk array according to the number corresponding to the target cache data space carried by the disk array addressing instruction and determining a physical address for writing the TCP data packet into the disk array; sending, to the programmable chip, the physical address determined according to the physical address returned by the CPU, so that the programmable chip stores the TCP data packet into a specified position of the disk array corresponding to the physical address.

4. The method of claim 3, wherein, The step of obtaining the disk array addressing instruction carrying the number corresponding to the target cache data space and used for storing the TCP data packet sent by the programmable chip comprises the following steps: Obtaining the disk array addressing instruction sent by the programmable chip, the disk array addressing instruction carrying the number corresponding to the target cache data space and being used for storing the TCP data packet; wherein, the target cache data space is an idle cache data space found by the programmable chip from the numbers corresponding to the cache data spaces, the cache data space being a space equally divided from the cache space of the programmable chip according to the maximum value of data backup each time, and each cache data space corresponding to a different number.

5. The method according to claim 3 or 4, characterized in that, The method further comprises: analyzing the to-be-backup data received from the network card to obtain a TCP control packet containing only a control flow in the to-be-backup data; copying the TCP control packet to a Socket buffer and copying the TCP control packet in the Socket buffer to a user buffer on the user side; after determining that the user makes a storage instruction on the TCP control packet in the user buffer, copying the TCP control packet from the user buffer to a disk array.

6. A data backup apparatus characterized by comprising: The application is applied to a programmable chip integrated on a mainboard and connected with a central processing unit (CPU), a network card and a disk array on the mainboard, and the device comprises: an analyzing unit configured to analyze to-be-backup data received from the network card to obtain a transmission control protocol (TCP) data packet containing only a data flow in the to-be-backup data; the to-be-backup data comprising a TCP control packet of a control flow type and a TCP data packet of a data flow type; a data caching unit configured to find an idle target cache data space for storing a data block from the programmable chip and store the TCP data packet in the target cache data space; an address instruction sending unit configured to send a disk array addressing instruction carrying a number corresponding to the target cache data space and being used for storing the TCP data packet to the CPU, so that the CPU determines the storage space size required by the disk array according to the number corresponding to the target cache data space and determines a physical address for writing the TCP data packet to the disk array; a disk storage unit configured to store the TCP data packet in a specified position of the disk array corresponding to the physical address according to the physical address returned by the CPU.

7. The apparatus of claim 6, wherein, The data caching unit is specifically configured to: find an idle target cache data space from numbers corresponding to the cache data spaces, the cache data space being a space equally divided from the cache space of the programmable chip according to the maximum value of data backup each time, and each cache data space corresponding to a different number.

8. A data backup apparatus characterized by comprising: The application is applied to a CPU connected with a programmable chip integrated on a mainboard, and the programmable chip is further connected with a network card and a disk array, and the device comprises: The instruction obtaining unit is configured to obtain a disk array addressing instruction sent by the programmable chip, the disk array addressing instruction carrying a number corresponding to a target cache data space and being used for storing a TCP data packet; the TCP data packet is a data packet containing only a data stream and obtained by the programmable chip from analyzing to-be-backed-up data received from a network card, the to-be-backed-up data including a TCP control packet of a control stream type and a TCP data packet of a data stream type; the disk array addressing instruction is an instruction sent by the programmable chip after the TCP data packet is stored in a target cache data space, which is an idle data block storage space, that is found by the programmable chip. The address determining unit is configured to determine a storage space size required by a disk array according to the number corresponding to the target cache data space carried by the disk array addressing instruction, and determine a physical address of the disk array to which the TCP data packet is written. The address sending unit is configured to send the determined physical address to the programmable chip according to a physical address returned by the CPU, so that the programmable chip stores the TCP data packet in a specified position of the disk array corresponding to the physical address.

9. The apparatus of claim 8, wherein, The address determining unit is specifically configured to: Obtain a disk array addressing instruction sent by the programmable chip, the disk array addressing instruction carrying a number corresponding to the target cache data space and being used for storing a TCP data packet; the target cache data space is an idle cache data space found by the programmable chip from numbers corresponding to various cache data spaces; the cache data space is a space obtained by equally dividing a cache space of the programmable chip according to a maximum value of data to be backed up each time, and each cache data space corresponds to a different number.

10. An electronic device, comprising: The processor is configured to execute the machine-executable instructions to implement the method steps of any one of claims 1-5.

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