Semiconductor package with enhanced layers

Abstract

Semiconductor package with reinforcing layer. A semiconductor package is provided. The semiconductor package can include a substrate, a chip stack disposed on the substrate, the chip stack including a plurality of semiconductor chips, a plurality of bonding wires electrically connecting the substrate to the plurality of semiconductor chips, a reinforcing layer disposed on the chip stack, and a molding layer surrounding side surfaces of the chip stack and the bonding wires and contacting side surfaces of the reinforcing layer. The reinforcing layer can include a lower layer including an adhesive, an intermediate layer disposed on the lower layer, and an upper layer disposed on the intermediate layer. The intermediate layer can have an elongation in a range of 5% to 70%. The upper layer can have an elongation less than 5%.

Description

Technical Field

[0001] This disclosure generally relates to a semiconductor package having an enhancement layer and a method for manufacturing the semiconductor package. Background Technology

[0002] As mobile devices become smaller, the thickness of semiconductor packages is gradually decreasing. As a result, semiconductor packages have weaker mechanical strength and are more prone to breakage. Summary of the Invention

[0003] A semiconductor package according to embodiments of the present disclosure may include: a substrate; a chip stack disposed on the substrate, the chip stack including a plurality of semiconductor chips; a plurality of bonding wires electrically connecting the substrate to the plurality of semiconductor chips; a reinforcement layer disposed on the chip stack; and a molding layer surrounding a side surface of the chip stack and the bonding wires and contacting a side surface of the reinforcement layer. The reinforcement layer may include: a lower layer including an adhesive; an intermediate layer disposed on the lower layer; and a upper layer disposed on the intermediate layer. The intermediate layer may have an elongation in the range of 5% to 70%. The upper layer may have an elongation of less than 5%.

[0004] A semiconductor package according to embodiments of the present disclosure may include: a substrate; a chip stack disposed on the substrate, the chip stack including a plurality of semiconductor chips; bonding wiring electrically connecting the substrate to the plurality of semiconductor chips; a reinforcement layer disposed on the chip stack; and a molding layer contacting a side surface of the reinforcement layer, the molding layer surrounding the side surface of the chip stack and the bonding wiring. The reinforcement layer may include a lower layer, an intermediate layer on the lower layer, and an upper layer on the intermediate layer. The lower layer may include an adhesive film. The intermediate layer may include a first polymeric resin. The upper layer may include a second polymeric resin, silica filler, and carbon. The first polymeric resin may be different from the second polymeric resin. The intermediate layer may be relatively softer than the upper layer. The upper layer may be relatively harder than the intermediate layer.

[0005] A semiconductor package according to embodiments of the present disclosure may include: a substrate; a chip stack disposed on the substrate, the chip stack including a plurality of semiconductor chips; a plurality of bonding wires electrically connecting the substrate to the plurality of semiconductor chips; a reinforcement layer disposed on the chip stack; and a molding layer surrounding a side surface of the chip stack and the bonding wires and contacting a side surface of the reinforcement layer. The reinforcement layer may include: a lower layer including an adhesive; an intermediate layer disposed on the lower layer; and an upper layer disposed on the intermediate layer. The intermediate layer may be more flexible than the upper layer. Attached Figure Description

[0006] Figure 1 This is a side view illustrating a semiconductor package according to an embodiment of the present disclosure.

[0007] Figure 2 This is an example Figure 1 A magnified view of region A.

[0008] Figure 3A , Figure 3B , Figure 3C and Figure 3D A method for manufacturing a semiconductor package according to an embodiment of the present disclosure is illustrated schematically.

[0009] Figure 4 This is a side cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure.

[0010] Figure 5 A block diagram illustrating an electronic system employing a memory card including a semiconductor package according to an embodiment of the present disclosure is shown.

[0011] Figure 6 A block diagram illustrating another electronic system including a semiconductor package according to an embodiment of the present disclosure is shown. Detailed Implementation

[0012] Various examples and embodiments of the disclosed technology are described in detail below with reference to the accompanying drawings. The drawings may not necessarily be drawn to scale, and in some cases, the scale of at least some structures in the drawings may have been exaggerated to clearly illustrate certain features of the described examples or embodiments. When a particular example in the drawings or description is presented as a multilayer structure having two or more layers, the relative positioning of these layers or the order in which these layers are arranged reflects a particular embodiment of the described or illustrated example, and different relative positioning or order in which these layers are arranged may also exist. Furthermore, the described or illustrated example of a multilayer structure may not reflect all layers present in that particular multilayer structure (e.g., one or more additional layers may exist between two illustrated layers). As a specific example, when the first layer in the described or illustrated multilayer structure is referred to as "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or the substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

[0013] This disclosure provides a semiconductor package with good toughness. For example, the semiconductor package according to embodiments of this disclosure can have better toughness than conventional semiconductor packages without a reinforcement layer. Therefore, the semiconductor package according to embodiments can have excellent fracture resistance to physical impact.

[0014] Figure 1 This is a side view illustrating a semiconductor package 100 according to an embodiment of the present disclosure. Figure 2 This is an example Figure 1 A magnified view of region A.

[0015] Reference Figure 1 and Figure 2 The semiconductor package 100 may include a substrate 10, a chip stack 20, a reinforcement layer 30, and a molding layer 70. The semiconductor package 100 may further include bonding wiring 60. The semiconductor package 100 may further include a support member 40 and a controller 50.

[0016] Substrate 10 may include a printed circuit board (PCB). Substrate 10 may include a plurality of substrate interconnects 11, a plurality of top pads 12, and a plurality of bottom pads 13. Substrate interconnects 11 may transmit electrical signals within substrate 10. For example, substrate interconnects 11 may electrically connect top pads 12 to bottom pads 13. Top pads 12 may directly electrically connect some of the substrate interconnects 11 to some of the bonding traces 60. In one embodiment, top pads 12 may include bonding fingers. Bottom pads 13 may electrically connect some of the substrate interconnects 11 to a motherboard or external system. For example, bottom pads 13 may be electrically connected to a motherboard or external system via metal bumps or solder balls. Substrate interconnects 11, top pads 12, and bottom pads 13 may include metals such as copper (Cu). In one embodiment, substrate 10 may include a redistribution layer (RDL). For example, substrate 10 may include an insulating material such as silicon oxide or silicon nitride surrounding the substrate interconnects 11. In one embodiment, substrate 10 may include an interposer. For example, substrate 10 may include an insulating material such as plastic, ceramic or polymeric organic material surrounding substrate interconnect 11.

[0017] The chip stack 20 may include a plurality of semiconductor chips 21 stacked in a stepped manner. An adhesive layer, such as a die-attach film (DAF), may be used to bond and stack the semiconductor chips 21. In one embodiment, at least one of the plurality of semiconductor chips 21 may include NAND flash memory. Each semiconductor chip 21 may include chip pads 22 exposed on a portion of its exposed top surface. The chip pads 22 may be respectively positioned closer to one side edge of the respective semiconductor chip 21. In one embodiment, the chip pads 22 may be positioned closer to two opposite side edges of the respective semiconductor chip 21.

[0018] The bonding wiring 60 can electrically connect the chip pads 22 of the semiconductor chip 21 to the top pads 12 of the substrate 10. The semiconductor chips 21 can be electrically connected to each other through the bonding wiring 60.

[0019] A reinforcement layer 30 may be disposed on the uppermost semiconductor chip 21t among a plurality of semiconductor chips 21 in a chip stack 20. The side surfaces of the reinforcement layer 30 and the side surfaces of the uppermost semiconductor chip 21t may be vertically aligned. In one embodiment, at least one side surface of the reinforcement layer 30 and at least one side surface of the uppermost semiconductor chip 21t may be vertically aligned. In the figures, both side surfaces of the reinforcement layer 30 and both side surfaces of the uppermost semiconductor chip 21t are vertically aligned. In one embodiment, the sidewalls of the reinforcement layer 30 may not be aligned with the sidewalls of the uppermost semiconductor chip 21t. For example, the bottom surface of the reinforcement layer 30 may be exposed, such as an eave or overhang. In other words, the edge portion of the top surface of the uppermost semiconductor chip 21t may be partially exposed and not covered by the reinforcement layer 30.

[0020] The reinforcement layer 30 may include a lower layer 31, an intermediate layer 32 stacked on the lower layer 31, and an upper layer 33 stacked on the intermediate layer 32.

[0021] The lower layer 31 may be an adhesive film with adhesive properties. In one embodiment, the lower layer 31 may include an adhesive. The lower layer 31 may be bonded to the top surface of the uppermost semiconductor chip 21t in the stacked semiconductor chips 21 of the chip stack 20. The lower layer 31 may include an epoxy resin. The lower layer 31 may also include an acrylic resin. The lower layer 31 may include at least one of epoxy resin or acrylic resin. The top surfaces of the reinforcing layer 30 and the uppermost semiconductor chip 21t of the chip stack 20 may be directly bonded to each other. The lower layer 31 may be a thermosetting resin. The lower layer 31 may be flexible to allow a portion of the bonding wiring 60 connected to the uppermost semiconductor chip 21t to penetrate the lower layer 31 before curing. Thus, a portion of the uppermost bonding wiring 60t of the bonding wiring 60 connected to the uppermost semiconductor chip 21t may be immersed in the lower layer 31. For example, the uppermost bonding wiring 60t of the bonding wiring 60 may be partially immersed, inserted, embedded, hidden, or buried in the lower layer 31. The lower layer 31 may have sufficient thickness to allow portions of the bonding wiring 60 to be immersed, inserted, embedded, hidden, or buried. For example, the lower layer 31 may have a thickness of about 30 μm or more. In one embodiment, the lower layer 31 may have a thickness in the range of about 30 μm to 120 μm.

[0022] The intermediate layer 32 may comprise at least one of a material that is more flexible than the upper layer 33 and a softer material. In some embodiments, the intermediate layer 32 may be more flexible than the upper layer 33. In some embodiments, the intermediate layer 32 may be softer than the upper layer 33. For example, the intermediate layer 32 may have an elongation in the range of about 5% to 70%. In some embodiments, the amount of elongation of the intermediate layer 32 under stress before it breaks may be in the range of about 5% to 70% of the original length of the intermediate layer 32. In some embodiments, the intermediate layer 32 may have an elongation at break between about 5% and about 70%. In some embodiments, the intermediate layer 32 may have an elongation at break between about 5% and about 70% of the initial size of the intermediate layer 32 before it breaks. Additionally, the intermediate layer 32 may have high heat resistance so that the laser used in the marking process does not deform some of the bonding wiring 60 in the lower layer 31. For example, the intermediate layer 32 may be able to block or mitigate the transfer of heat generated from the laser from the upper layer 33 to the lower layer 31. In other words, the intermediate layer 32 can prevent or mitigate damage to the bonding wiring 60 from the heat generated by the laser.

[0023] Intermediate layer 32 may have adhesiveness for proper bonding with upper layer 33. Intermediate layer 32 may include a first polymeric resin different from epoxy resin. For example, the first polymeric resin may include at least one of polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), or polyetheretherketone (PEEK). Intermediate layer 32 may have a suitable thickness to absorb and relieve external stress. For example, intermediate layer 32 may have a thickness of 10 μm or greater. In one embodiment, intermediate layer 32 may have a thickness in the range of 10 μm to 40 μm.

[0024] The upper layer 33 may include a material that is relatively harder and more rigid than the intermediate layer 32. The upper layer 33 may have an elongation of less than 5%. In one embodiment, the amount of elongation of the upper layer 33 under stress before it breaks may be less than about 5% of its original length. In another embodiment, the upper layer 33 may have an elongation at break greater than 5%. In yet another embodiment, the elongation at break of the upper layer 33 before it breaks may be greater than 5% of its initial size. In one embodiment, the upper layer 33 may have a hardness and strength substantially similar to the molding layer 70. The upper layer 33 may include a second polymeric resin and a silica filler. The first and second polymeric resins may include materials different from each other. For example, the second polymeric resin may include an epoxy resin. The upper layer 33 may also include carbon. For example, the upper layer 33 may include an epoxy resin, a silica filler, and carbon. The upper layer 33 may include a marking 75. The marking 75 may include a package ID, a barcode, or a quick response (QR) code. Mark 75 may have a longitudinal cross-section with a recessed shape created by a laser marking process, such as a groove shape. In one embodiment, mark 75 may include a mark having at least one groove. In another embodiment, mark 75 may include a mark having at least one groove, such as... Figure 1 , Figure 2 and Figure 4 As shown. The upper layer 33 may have a color substantially the same as or similar to that of the molding layer 70, such as black. Therefore, it is difficult to visually distinguish the boundary between the upper layer 33 of the reinforcing layer 30 and the molding layer 70. Typically, the marking 75 may be marked or engraved in the molding layer 70. The molding layer 70 may have a dark color (i.e., black) to absorb the laser used in the marking process. In this embodiment, the upper layer 33 may have a dark color (i.e., black) to adequately absorb the laser in the marking process.

[0025] In one embodiment, the intermediate layer 32 may be exposed at the bottom of the mark 75. For example, in one embodiment, the intermediate layer 32 may be exposed through a trench without a bottom surface. The upper layer 33 may have an appropriate thickness to protect the chip stack 20 of the semiconductor package 100 from external impacts. For example, the upper layer 33 may have a thickness of 10 μm or greater. In one embodiment, the upper layer 33 may have a thickness in the range of 10 μm to 40 μm.

[0026] Materials with high hardness and strength are typically brittle and therefore prone to breakage or fracture. Since the reinforcing layer 30 according to embodiments of this disclosure includes an intermediate layer 32 with flexibility and high elongation, the toughness of the upper layer 33 can be increased. That is, the intermediate layer 32 is capable of absorbing or mitigating external impacts and physical stresses.

[0027] A molding layer 70 may be disposed on the substrate 10 to surround the side surfaces of the chip laminate 20 and to contact or abut the side surfaces of the reinforcement layer 30. The upper surface of the reinforcement layer 30 may be exposed and not covered by the molding layer 70. The top surfaces of the reinforcement layer 30 and the molding layer 70 may be coplanar. The molding layer 70 may include epoxy molding compound (EMC). For example, the molding layer 70 may include epoxy resin, silica filler, and carbon. As described above, the molding layer 70 may be black. The molding layer 70 may be adhesive. The molding layer 70 may supplement the adhesion between the intermediate layer 32 and the upper layer 33 of the reinforcement layer 30.

[0028] The support member 40 provides a shielding space (S) by spaced the chip stack 20 from the upper surface of the substrate 10. In one embodiment, the support member 40 can provide a space (S) formed by the overlapping of the chip stack 20 and by spaced the chip stack 20 from the upper surface of the substrate 10. The support member 40 may include at least one of a dummy semiconductor chip, an insulating pillar, or an insulating dam. In one embodiment, a thermosetting polymer material such as a film on die (FOD), an underfill material, or an insulating material such as epoxy molding compound (EMC) may be disposed in the shielding space S. In one embodiment, the shielding space S may be an empty space. The controller 50 may be disposed in the shielding space S. Although reference numerals are omitted, some pads of the controller 50 and the top pad 12 of the substrate 10 may be electrically connected to each other using wiring.

[0029] In one embodiment, an insulating material may be provided to cover the controller 50 mounted on the substrate 10, and the chip stack 20 may be stacked on the insulating material. The insulating material may include thermosetting polymeric materials such as FOD or FOW (wire over film).

[0030] The top bonding wiring 60t, partially immersed in the lower layer 31, is protected from thermal deformation or thermal / physical damage (bending or breakage). In this embodiment, the top bonding wiring 60t, partially embedded in the lower layer 31, is protected from thermal deformation or thermal / physical damage (bending or breakage). Because the intermediate layer 32 can block heat transfer from the upper layer 33 to the lower layer 31, the lower layer 31 and the upper bonding wiring 60t are protected from thermal stress. For example, the top bonding wiring 60t may have a bending shape substantially the same as the other bonding wiring 60. The lowest bonding wiring 60 may have various shapes depending on the package type.

[0031] Figures 3A to 3D A method for manufacturing a semiconductor package according to an embodiment of the present disclosure is illustrated schematically. (Refer to...) Figure 3AThe method may include performing a mounting process to mount the controller 50 onto a substrate 10, arranging a support 40 on the substrate 10, and forming a chip stack 20 on the support 40. The substrate 10 may include substrate interconnects 11, a top pad 12, and a bottom pad 13. The chip stack 20 may include a plurality of semiconductor chips 21. The semiconductor chips 21 may be stacked in a stepped or zigzag shape. The method may also include performing a wiring bonding process to connect the chip pads 22 of the semiconductor chips 21 of the chip stack 20 in parallel with each other using bonding wiring 60. The chip pads 22 may be electrically connected to the top pad 12 of the substrate 10 via bonding wiring 60. In one embodiment, the support 40 may be omitted. In one embodiment, the method may include covering the controller 50 with an adhesive film such as FOD or FOW and mounting the chip stack 20 onto the FOD or FOW.

[0032] Reference Figure 3B The method may include performing an enhancement process to form an enhancement layer 30 on a chip stack 20. The enhancement process may include performing an bonding process and a curing process. The bonding process may include providing the enhancement layer 30 in the form of a film on the top surface of the uppermost semiconductor chip 21t and applying pressure to the enhancement layer 30 to bond it to the top surface of the uppermost semiconductor chip 21t. For example, the bonding process may include applying a pressure to the enhancement layer 30 in the range of about 0.5 kgf / cm² to 3.0 kgf / cm² and heating the lower layer 31 of the enhancement layer 30 to a temperature in the range of about 80°C to 150°C. The curing process may include heating the lower layer 31 of the enhancement layer 30 to a temperature in the range of about 100°C to 180°C. In one embodiment, the enhancement layer 30 may be initially cured by the enhancement process or on the top surface of the chip stack 20. In one embodiment, the curing process may be omitted. That is, since the lower layer 31 is not cured, the enhancement layer 30 may be in a weakly bonded state, such as a weakly cured state.

[0033] Reference Figure 3C The method may include performing a molding process to form a molding layer 70. The molding process may include providing molding material around the chip stack 20, the reinforcement layer 30, and the bonding wiring 60, and heating and curing the molding material to form the molding layer 70. In one embodiment, during the molding process, the underlying layer 31 of the reinforcement layer 30 may be fully cured.

[0034] Reference Figure 3DThe method may further include performing a marking process using a laser source Ls to engrave a mark 75 on the upper layer 33 of the reinforcement layer 30. Grooves or trenches can be formed in the upper layer 33 by the marking process. The intermediate layer 32 may be exposed to the bottom of the grooves or trenches. For example, portions of the upper layer 33 irradiated by the laser L can be removed during the marking process. The intermediate layer 32 can block or mitigate the diffusion of heat energy from the laser L to the lower layer 31 and the bonding wiring 60. Therefore, the intermediate layer 32 can prevent the lower layer 31 and the bonding wiring 60 from being damaged by the heat energy of the laser L.

[0035] Figure 4 This is a side cross-sectional view illustrating a semiconductor package 101 according to an embodiment of the present disclosure. (Refer to...) Figure 4 The semiconductor package 101 according to embodiments of the present disclosure may include a substrate 10, a controller 50, a die bonding layer 25, a semiconductor chip 23, a reinforcement layer 30, and a molding layer 70. The controller 50 may be directly mounted on the substrate 10. The die bonding layer 25 may cover the controller 50. For example, the die bonding layer 25 may include a film on the die (FOD) or a film on the wiring (FOW). The semiconductor chip 23 may be disposed on the die bonding layer 25. In one embodiment, the semiconductor chip 23 may include multiple stacked semiconductor chips. The controller 50 and the semiconductor chip 23 may be electrically connected to the top pad 12 of the substrate 10 via bonding wiring 60. The semiconductor chip 23 may include one or more NAND flash memory chips. In one embodiment, the semiconductor chip 23 may include multiple stacked semiconductor memory chips. Elements not described may be understood with reference to other accompanying drawings.

[0036] Figure 5 A block diagram illustrating an electronic system including a memory card 7800 employing at least one of the semiconductor packages according to an embodiment is shown. The memory card 7800 includes a memory 7810, such as a non-volatile memory device, and a memory controller 7820. The memory 7810 and memory controller 7820 can store data or read stored data. At least one of the memory 7810 and memory controller 7820 may include at least one of the semiconductor packages 100 and 101 according to the described embodiment.

[0037] The memory 7810 may include a non-volatile memory device to which the techniques of embodiments of the present disclosure are applied. The memory controller 7820 may control the memory 7810 such that stored data or stored data can be read in response to a read / write request from the host 7830.

[0038] Figure 6A block diagram illustrating an electronic system 8710 including at least one of semiconductor packages 100 and 101 according to the described embodiments is shown. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be interconnected via a bus 8715 providing the path traversed by data movement.

[0039] In an embodiment, controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. Controller 8711 or memory 8713 may include one or more semiconductor packages 100 and 101 according to embodiments of this disclosure. Input / output device 8712 may include at least one selected from a keypad, keyboard, display device, touchscreen, etc. Memory 8713 is a means for storing data. Memory 8713 may store commands and / or data to be executed by controller 8711.

[0040] The memory 8713 may include volatile memory devices such as DRAM and / or non-volatile memory devices such as flash memory. For example, flash memory can be installed in information processing systems such as mobile terminals or desktop computers. Flash memory can form a solid-state drive (SSD). In this case, the electronic system 8710 can stably store large amounts of data in the flash memory system.

[0041] The electronic system 8710 may further include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 may be of wired or wireless type. For example, the interface 8714 may include an antenna, or a wired or wireless transceiver.

[0042] The electronic system 8710 can be implemented as a mobile system, a personal computer, an industrial computer, or a logical system performing various functions. For example, a mobile system can be any of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smartphone, a cordless phone, a laptop computer, a memory card, a digital music system, and an information sending / receiving system.

[0043] If electronic system 8710 represents equipment capable of performing wireless communication, then electronic system 8710 can be used in communication systems using technologies such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0044] While this disclosure contains numerous details, these details should not be construed as limiting any invention or the scope that may be claimed, but rather as descriptions of features that may be specific to particular embodiments of a particular invention. Some features described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented separately or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, and even initially claimed to be so, one or more features in a claimed combination may be removed from the combination in certain circumstances, and a claimed combination may refer to a sub-combination or a variation of a sub-combination.

[0045] Similarly, although operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring the operations to be performed in the specific order shown or in a sequential order, or to perform all illustrated operations to obtain the desired result. Furthermore, the separation of various system components in the embodiments described in this patent document should not be construed as requiring such separation in all embodiments. Only some embodiments and examples have been described. Other embodiments, enhancements, and modifications can be made based on what is described and illustrated in this patent document.

[0046] Cross-reference to related applications

[0047] This application claims priority to Korean Patent Application No. 10-2020-0077653, filed on June 25, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor package comprising: a substrate; a chip stack provided on the substrate, the chip stack including a plurality of semiconductor chips; a plurality of bonding wires electrically connecting the substrate to the plurality of semiconductor chips; a reinforcement layer provided on the chip stack; and a molding layer surrounding side surfaces of the chip stack and the plurality of bonding wires and contacting side surfaces of the reinforcement layer, wherein the reinforcement layer includes: a lower layer including an adhesive; an intermediate layer provided on the lower layer, the intermediate layer having an elongation in a range of 5% to 70%; and an upper layer provided on the intermediate layer, the upper layer having an elongation less than 5%. The upper layer includes at least one of an epoxy resin, a silica filler, and carbon.

2. The semiconductor package of claim 1, wherein, The upper layer includes a mark having a groove shape.

3. The semiconductor package of claim 1, wherein, The intermediate layer is exposed at a bottom of the mark.

4. The semiconductor package of claim 3, wherein, An uppermost bonding wire of the plurality of bonding wires is embedded in the lower layer.

5. The semiconductor package of claim 1, wherein, The intermediate layer includes one or more of polyimide, polybenzoxazole, benzocyclobutene, polyethylene naphthalate, polyethylene terephthalate, and polyether ether ketone.

6. The semiconductor package of claim 1, wherein, The lower layer is directly adhered to a top surface of an uppermost semiconductor chip stacked at a highest level of stacked semiconductor chips of the chip stack.

7. The semiconductor package of claim 1, wherein, The lower layer includes at least one of an epoxy resin and an acrylic resin.

8. The semiconductor package of claim 1, wherein, The reinforcement layer has a thickness in a range of 50 μm to 200 μm.

9. The semiconductor package of claim 1, wherein, 10.The semiconductor package of claim 9, wherein, the lower layer of the reinforcement layer has a thickness in a range of 30 μm to 120 μm, the intermediate layer of the reinforcement layer has a thickness in a range of 10 μm to 40 μm, and the upper layer of the reinforcement layer has a thickness in a range of 10 μm to 40 μm. A top surface of the molding layer and a top surface of the reinforcement layer are coplanar.

11. The semiconductor package of claim 1, wherein, The upper layer of the reinforcement layer and the molding layer have a same color.

12. The semiconductor package of claim 1, wherein, 13.The semiconductor package of claim 1, further comprising: a support member spacing the chip stack apart from the substrate to provide a space between a top surface of the substrate and a bottom surface of the chip stack; and a controller provided in the space. The support member includes one or more of a dummy chip, an insulating pillar, and an insulating dam. 15.The semiconductor package of claim 1, further comprising:

14. The semiconductor package of claim 13, wherein, a controller provided on the substrate; and an insulating material covering the controller, wherein the chip stack is stacked on the insulating material. 16.A semiconductor package comprising: a substrate; a chip stack provided on the substrate, the chip stack including a plurality of semiconductor chips; a plurality of bonding wires electrically connecting the substrate to the plurality of semiconductor chips; ​ ​ ​ a reinforcing layer provided on the chip stack, and a molding layer in contact with a side surface of the reinforcing layer, the molding layer surrounding a side surface of the chip stack and the plurality of bonding wires, wherein the reinforcing layer includes a lower layer, an intermediate layer on the lower layer, and an upper layer on the intermediate layer, wherein the lower layer includes an adhesive film, the intermediate layer includes a first polymeric resin, the upper layer includes a second polymeric resin, silica filler, and carbon, the first polymeric resin is different from the second polymeric resin, the intermediate layer is relatively softer than the upper layer, and the upper layer is relatively harder than the intermediate layer.

17. The semiconductor package of claim 16, wherein the first polymeric resin includes one or more of polyimide, polybenzoxazole, benzocyclobutene, polyethylene naphthalate, polyethylene terephthalate, and polyether ether ketone, and the second polymeric resin includes an epoxy resin.

18. The semiconductor package of claim 16, wherein the intermediate layer has an elongation at break greater than 5%, and the upper layer has an elongation at break less than 5%.

19. The semiconductor package of claim 16, wherein, a portion of an uppermost bonding wire of the plurality of bonding wires is embedded in the lower layer.

20. A semiconductor package, comprising: a substrate; a chip stack provided on the substrate, the chip stack including a plurality of semiconductor chips; a plurality of bonding wires electrically connecting the substrate to the plurality of semiconductor chips; a reinforcing layer provided on the chip stack; and a molding layer surrounding a side surface of the chip stack and the plurality of bonding wires and in contact with a side surface of the reinforcing layer, wherein the reinforcing layer includes: a lower layer including an adhesive; an intermediate layer provided on the lower layer; and an upper layer provided on the intermediate layer, wherein the intermediate layer is more flexible than the upper layer, wherein an upper surface of the reinforcing layer is exposed without being covered by the molding layer, and wherein the upper layer of the reinforcing layer includes a trench-shaped mark.

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