Semiconductor package structure and method of forming the same

Abstract

This invention relates to a semiconductor package structure and a method for forming the same. The semiconductor package structure includes: a substrate; an interposer electrically connected to the upper surface of the substrate, the interposer including a first I / O surface and a second I / O surface respectively provided with I / Os, the first I / O surface and the second I / O surface being non-parallel, the interposer including traces and vias respectively connected to the I / Os at the first I / O surface and the I / Os at the second I / O surface, wherein one of the I / Os at the first I / O surface or the I / Os at the second I / O surface is a via cross-section, and in a top view, the I / O at the via cross-section is part of a stack of multiple non-concentric circular vias.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure and a method for forming the same. Background Technology

[0002] Current wearable devices mainly employ a design with two non-coplanar modules to meet the needs of wearers. Therefore, the primary objective is to electrically connect these two non-coplanar modules.

[0003] refer to Figure 1A and Figure 1B As shown, one current design primarily utilizes a flexible printed circuit board 12 as a connector between two non-coplanar modules 14 and 16 to meet the requirements of wearing on curved surfaces of the human body. However, this design suffers from the disadvantage of large size and the inability to modularly replace either module in case of failure.

[0004] refer to Figure 1C , Figure 1D and Figure 1E As shown, another design currently in use involves soldering 21 (on non-horizontal surfaces within the module). Figure 1C ), Conductor frame 22 ( Figure 1D ) or connecting lead 23 ( Figure 1E This design allows for direct external I / O connection as a connector. While this design can reduce the size of the connector, the pitch between the external lines is too large, which does not meet the future requirements for finer pitch. Summary of the Invention

[0005] In view of the problems of large size, inability to be modularly replaced, and excessively large line pitch in related technologies, this invention proposes a semiconductor packaging structure and its formation method.

[0006] According to one aspect of the present invention, a semiconductor package structure is provided, comprising: a substrate; an interposer electrically connected to the upper surface of the substrate, the interposer including a first I / O surface and a second I / O surface respectively provided with I / O, the first I / O surface and the second I / O surface being non-parallel, the interposer including traces and vias respectively connected to the I / O at the first I / O surface and the I / O at the second I / O surface, wherein one of the I / O at the first I / O surface or the I / O at the second I / O surface is a via cross-section, and in a top view, the I / O at the via cross-section is part of a stack of multiple non-concentric circular vias.

[0007] In some embodiments, the I / O at the through-hole cross-section has different widths along the direction of multiple non-concentric stacked circles.

[0008] In some embodiments, the first I / O surface is connected to the substrate, and the first I / O surface is a through-hole cut surface.

[0009] In some embodiments, in a direction perpendicular to the second I / O plane, the interposer layer comprises a plurality of alternating via layers and trace layers stacked together.

[0010] In some embodiments, the outermost layer of the I / O at the second I / O surface is a solder layer.

[0011] In some embodiments, the first I / O surface is connected to the substrate, and the second I / O surface is a through-hole cut surface.

[0012] In some embodiments, in a direction perpendicular to the first I / O plane, the interposer layer comprises a plurality of alternating via layers and trace layers stacked together.

[0013] In some embodiments, the semiconductor package structure further includes a molding compound located above a substrate, with a first I / O surface connected to the substrate, the molding compound surrounding an interposer and exposing I / O at a second I / O surface.

[0014] In some embodiments, the first I / O surface is perpendicular to the second I / O surface.

[0015] According to one aspect of the present invention, a method for forming a semiconductor package structure is provided, comprising: forming an interposer layer having a via cross-section, wherein forming the via cross-section comprises: forming a plurality of vias arranged in the interposer layer in a manner in which a plurality of non-concentric circles are interconnected; cutting the plurality of vias in the interposer layer in a direction perpendicular to the plane containing the plurality of non-concentric circles to form the via cross-section, wherein the via cross-section is a first I / O surface of the interposer layer or a second I / O surface not parallel to the first I / O surface, wherein the I / O at the first I / O surface is interconnected with the I / O at the second I / O surface through a circuit in the interposer layer; and electrically connecting the interposer layer to a substrate through the first I / O surface.

[0016] In some embodiments, the via cut is a second I / O surface, and the cutting of the interposer is performed after the interposer is electrically connected to the substrate.

[0017] In some embodiments, after the interposer is electrically connected to the substrate, a plurality of circuit layers in the interposer are parallel to the substrate.

[0018] In some embodiments, the via cut is the first I / O face, and the cutting of the interposer is performed before the interposer is electrically connected to the substrate.

[0019] In some embodiments, after the interposer is electrically connected to the substrate, the plurality of circuit layers of the interposer are perpendicular to the substrate.

[0020] In some embodiments, forming an interposer layer further includes: forming a circuit layer; and covering the circuit layer with a dielectric layer.

[0021] In some embodiments, the interposer layer has a side surface opposite to the cut surface, and the cut surface and the side surface are not parallel.

[0022] In some embodiments, the I / O at the second I / O surface has a different width.

[0023] In some embodiments, the via section is a first I / O surface, and the second I / O includes a solder ball. The method further includes cutting the solder ball to remove a portion of the solder ball, the remaining portion of the solder ball forming the outermost layer of the second I / O.

[0024] In some embodiments, the method further includes: forming a molding over a substrate; cutting the molding to expose a second I / O surface.

[0025] In some embodiments, the first I / O surface is perpendicular to the second I / O surface. Attached Figure Description

[0026] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion.

[0027] Figures 1A to 1E This is a schematic diagram of an existing semiconductor packaging structure.

[0028] Figure 2 This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention.

[0029] Figure 3A A top view of the intermediate layer 220 in the stacking direction of the plurality of through holes is shown before the through-hole cross-section is formed.

[0030] Figure 3B yes Figure 3A An enlarged schematic diagram of region A in the image.

[0031] Figure 3C and Figure 3D These are schematic diagrams illustrating exposed I / O according to some embodiments.

[0032] Figure 4 This is a top view of the intermediary layer according to some embodiments.

[0033] Figure 5 This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention.

[0034] Figures 6A to 6CA schematic diagram of several stages of a method for forming a semiconductor package structure according to an embodiment of the present invention is shown.

[0035] Figures 7A to 7C A schematic diagram of several stages of a method for forming a semiconductor package structure according to an embodiment of the present invention is shown. Specific Implementation

[0036] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various instances. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0037] An embodiment of the present invention provides a semiconductor packaging structure. Figure 2 This is a side view schematic diagram of a semiconductor package structure according to an embodiment of the present invention. Figure 2 In the semiconductor package structure 200 shown, an interposer 220 is electrically connected to the upper surface of the substrate 210. The interposer 220 includes a first I / O (input / output) surface 221 and a second I / O surface 222, with a plurality of I / Os 231 and 232 respectively disposed on the first I / O surface 221 and the second I / O surface 222. In one embodiment, the plurality of I / Os at the first I / O surface 221 and the second I / O surface 222 can be arranged in an array. The I / Os at the second I / O surface 222 can be used to connect external components.

[0038] The first I / O surface 221 and the second I / O surface 222 are not parallel to each other. In the illustrated embodiment, the first I / O surface 221 and the second I / O surface 222 are perpendicular to each other. In other embodiments, the first I / O surface 221 and the second I / O surface 222 may also be formed at other angles. The interposer layer 220 may also include traces and vias that are respectively connected to the I / O at the first I / O surface 221 and the I / O at the second I / O surface 222.

[0039] In a direction perpendicular to the upper surface of the substrate 210, the interposer 220 may include a plurality of stacked dielectric layers. Traces and vias may be located on the plurality of dielectric layers, and traces in adjacent dielectric layers may be electrically connected to each other through vias. Therefore, the interposer 220 includes a plurality of alternating stacks of via layers and trace layers. In some embodiments, the linewidth / spacing L / S of the traces in the interposer 220 may be less than 15 / 15 μm. The interposer 220 has a thickness in the direction of the stacking of the plurality of dielectric layers. In some embodiments, the thickness of the interposer 220 may be less than 100 μm. In addition to the interposer 220, other electronic components 250 may also be bonded to the upper surface of the carrier 110.

[0040] exist Figure 2 In the embodiment shown, the second I / O surface 222 is a through-hole cross-section passing through the through-hole 241 in the interposer layer 220. Figure 3A A top view of the intermediate layer 220 in the stacking direction of the plurality of through holes is shown before the through-hole cross-section is formed. Figure 3B yes Figure 3A An enlarged view of region A in the diagram. (Reference) Figure 3A Before forming the via cross-section and the I / O at the via cross-section, the intermediate layer 220 has a via 241 formed by a plurality of non-concentric circular vias 243 partially overlapping each other. The via is cut along, for example, a cutting line L1, to form the via cross-section and the I / O of the intermediate layer 220. Therefore, the I / O formed at the first I / O surface 221 is part of a stack of a plurality of non-concentric circular vias 243.

[0041] A through-hole 241 consisting of multiple non-concentric circular through-holes 243 stacked can be formed by performing multiple drilling processes. The through-hole 241 is formed using a multiple drilling method, with each drilling extending horizontally outward to form a long, strip-shaped multi-through-hole stack structure. This increases the size of the through-hole 241 in the direction of the stacking of multiple non-concentric circular through-holes 243. Thus, when along... Figure 3B When the cutting line L1 is used to perform the cutting process to form I / O, even if the cutting line deviates from the preset cutting line and the actual cutting is performed along line L2, the increased dimension in the length direction of the through hole 241 ensures that the area of ​​the I / O 232 exposed when cutting along line L2 is sufficient. Figure 3C As shown. However, compared to forming a single circular through-hole, if the cutting line is offset to L2 ( Figure 3B When performing the cut, the area of ​​the exposed I / O 232 (e.g.) Figure 3D (As shown) The area will be smaller than the I / O 232 obtained along the cutting line L1.

[0042] Figure 4 A top view of the intermediary layer 220 in another embodiment is shown. Figure 4As shown, the interposer layer 220 has a side surface 229 opposite to the cut surface, and the cut surface is not parallel to the side surface 229. That is, the second I / O surface 232 (i.e., the via cut surface) may not be parallel to the opposite side surface 229 of the interposer layer 220. In this embodiment, the I / O 232 at the via cut surface has different widths or dimensions along the direction of the stack of multiple non-concentric circles.

[0043] Continue to refer to Figure 2 As shown, in the semiconductor package structure 200, the interposer 220 is connected to the substrate 210 via a first I / O surface 221. In some embodiments, the first I / O surface 221 is connected to traces on the substrate 210 via solder balls 252. The interposer 220 and other electronic components 250 on the substrate 210 are surrounded by a molding compound 260. Furthermore, the molding compound 260 exposes I / O 232 at the second I / O surface 222.

[0044] Figure 5 This is a side view schematic diagram of a semiconductor package structure according to an embodiment of the present invention. Wherein, for... Figure 2 Similar components use the same reference numerals, and their detailed descriptions are omitted. Figure 5 In the semiconductor package structure 500 shown, an interposer 220 is electrically connected to the upper surface of a substrate 210. The interposer 220 includes a first I / O surface 221 and a second I / O surface 222, with multiple I / O pins 231 and 232 respectively disposed on the first I / O surface 221 and the second I / O surface 222. The I / O pins 232 at the second I / O surface 222 can be used to connect external components. A molding 260 on the substrate 210 surrounds the interposer 220. The upper surface of the molding 260 may be flush with the upper surface of the interposer 220. In other embodiments, the upper surface of the molding 260 may be higher than the upper surface of the interposer 220. In a direction perpendicular to the second I / O surface 222, the interposer 220 includes a stack of multiple alternating via layers and trace layers.

[0045] exist Figure 5 In the semiconductor package structure 500, the first I / O surface 221 is connected to the substrate 210. The first I / O surface 221 is a through-hole section. The molded part 260 exposes the I / O at the second I / O surface 222. (Refer to the above reference...) Figures 3A to 3D Similarly, the I / O 232 formed at the second I / O surface 222 is part of a stack of multiple non-concentric circular vias, as described above. Figures 3A to 3D As described. Detailed description of this is omitted here.

[0046] The outermost layer of the I / O 232 at the second I / O surface 222 exposed by the molding material 260 is a solder layer 238. The solder layer 238 can be connected to the traces in the interposer layer 220.

[0047] exist Figure 2 Semiconductor packaging structure 200 and Figure 5 In the semiconductor package structure 500, vias in the interposer are used as external I / O, resulting in a smaller overall package size, easier modular replacement, and a reduced pitch for the external I / O. Furthermore, to avoid misalignment during dicing that could affect the I / O area and degrade electrical performance, this invention further discloses a via design for the external I / O. This design uses a multi-via stack structure formed by multiple drilling operations, overcoming the problem of reduced I / O surface area due to dicing misalignment.

[0048] According to embodiments of the present invention, a method for forming a semiconductor package structure is also provided. Figures 6A to 6C A schematic diagram of several stages of a method for forming a semiconductor package structure according to an embodiment of the present invention is shown. Figures 6A to 6C The method shown can be used to form, for example, Figure 2 The semiconductor package structure 200 shown is shown.

[0049] First refer to Figure 6A As shown, an interposer 220 is provided on substrate 210. Other electronic components 250 may also be placed on substrate 210. The steps of forming interposer 220 may include: forming a first circuit layer and covering the first circuit layer with a first dielectric layer, then forming a second circuit layer on the first dielectric layer and covering the second circuit layer with a second dielectric layer, and so on to form a desired number of circuit layers and dielectric layers. The circuits in interposer 220 include traces and vias.

[0050] Interchange layer 220 has a first I / O surface 221. Interchange layer 220 is electrically connected to substrate 210 via first I / O surface 221. In some embodiments, first I / O surface 221 is connected to traces on substrate 210 via solder balls 252. After interchange layer 220 is electrically connected to substrate 210, a plurality of circuit layers of interchange layer 220 are parallel to substrate 210.

[0051] refer to Figure 6B As shown, a molding 260 is formed above substrate 210. The molding 260 surrounds interposer 220 and electronic component 250. The upper surface of the molding 260 may be flush with the upper surface of interposer 220. In other embodiments, the upper surface of the molding 260 may also be higher than the upper surface of interposer 220.

[0052] refer to Figure 6C As shown, this represents the cross-section of the via forming the intermediate layer 220. Specifically, the intermediate layer 220 may contain a plurality of vias 241 arranged in a manner that interconnects with each other in a plurality of non-concentric circles, as described above. Figures 3A to 3DThe description will not be repeated here. In a direction perpendicular to the plane containing the multiple non-concentric circles, i.e., perpendicular to the first I / O surface 221, the multiple vias 241 of the interposer layer 220 are cut to form via cross-sections. These via cross-sections form the second I / O surface 222 of the interposer layer 220. The I / O 231 at the first I / O surface 221 is interconnected with the I / O 232 at the second I / O surface 222 via wiring within the interposer layer 220.

[0053] Intermediate layer 220 has a side surface opposite to the cut surface, and the cut surface and the side surface are not parallel. The I / O at the second I / O surface 222 has a different width. (As mentioned above...) Figure 4 and Figure 3B What has been described will not be repeated here.

[0054] Figures 7A to 7C A schematic diagram of several stages of a method for forming a semiconductor package structure according to another embodiment of the present invention is shown. Figures 7A to 7C The method shown can be used to form, for example, Figure 5 The semiconductor package structure 500 is shown.

[0055] refer to Figure 7A As shown, an interposer 220 is provided on substrate 210. Other electronic components may also be placed on substrate 210. The steps of forming interposer 220 may include: forming a first circuit layer and covering the first circuit layer with a first dielectric layer, then forming a second circuit layer on the first dielectric layer and covering the second circuit layer with a second dielectric layer, and so on to form a desired number of circuit layers and dielectric layers. The circuits in interposer 220 include traces and vias.

[0056] Interposer 220 has a first I / O surface 221. Interposer 220 is electrically connected to substrate 210 via the first I / O surface 221. In some embodiments, the first I / O surface 221 is connected to traces on substrate 210 via solder balls 252. After the interposer 220 is electrically connected to substrate 210, a plurality of circuit layers of interposer 220 are perpendicular to substrate 210. Here, interposer 220 has been formed with the via cross-section described above. The via cross-section is the first I / O surface 221. Solder balls 228 are provided on the side perpendicular to the first I / O surface 221.

[0057] As described above, the interposer 220 can be cut to form a through-hole cut surface before it is electrically connected to the substrate 210. The interposer 220 has a side surface opposite to the cut surface, and the cut surface is not parallel to the side surface. The I / O at the second I / O surface 222 has a different width. As mentioned above regarding Figure 4 and Figure 3B What has been described will not be repeated here.

[0058] refer to Figure 7B As shown, a molding 260 is formed above substrate 210. The molding 260 surrounds interposer 220 and electronic components. The upper surface of the molding 260 may also be higher than the upper surface of interposer 220. In other embodiments, the upper surface of the molding 260 may be flush with the upper surface of interposer 220.

[0059] refer to Figure 7C As shown, the molded object 260, substrate 210, and solder balls 228 are cut to form the second I / O surface 222 of the interposer layer. A portion of the solder balls 228 is removed, and the remaining portion of the solder balls is used to form a solder layer 238, which is the outermost layer of the second I / O.

[0060] Figures 6A to 6C and Figures 7A to 7C The semiconductor packaging structure obtained by the method can have the above-mentioned characteristics. Figure 2 and Figure 5 The benefits discussed in the semiconductor packaging structure.

[0061] The foregoing summary outlines features of several embodiments that enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on this invention to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A semiconductor package structure, comprising: Comprising: a substrate; an interposer electrically connected to an upper surface of the substrate, the interposer comprising a first I / O surface and a second I / O surface each provided with I / Os, the first I / O surface being non-parallel to the second I / O surface, the interposer comprising within it traces and vias connecting I / Os at the first I / O surface and I / Os at the second I / O surface, wherein one of the I / Os at the first I / O surface or the I / Os at the second I / O surface is a via cut surface, in a top view, the I / Os at the via cut surface are part of a plurality of non-concentric circular via stacks, wherein the via cut surface extends in a direction perpendicular to the plurality of non-concentric circular via stacks, and wherein the I / Os at the via cut surface have different widths in a direction along the plurality of non-concentric circular stacks.

2. The semiconductor package structure of claim 1, wherein, The first I / O surface is connected to the substrate and the first I / O surface is the via cut surface.

3. The semiconductor package structure of claim 2, wherein, In a direction perpendicular to the second I / O surface, the interposer comprises a plurality of stacks of alternating via layers and trace layers.

4. The semiconductor package structure of claim 2, wherein, An outermost layer of the I / Os at the second I / O surface is a solder layer.

5. The semiconductor package structure of claim 1, wherein, The first I / O surface is connected to the substrate and the second I / O surface is the via cut surface.

6. The semiconductor package structure of claim 5, wherein, In a direction perpendicular to the first I / O surface, the interposer comprises a plurality of stacks of alternating via layers and trace layers.

7. The semiconductor package structure of claim 1, wherein, Further comprising a mold material over the substrate, the first I / O surface being connected to the substrate, the mold material surrounding the interposer and exposing the I / Os at the second I / O surface.

8. The semiconductor package structure of claim 1, wherein, The first I / O surface is perpendicular to the second I / O surface.

9. A method of forming a semiconductor package structure, comprising: Comprising: forming an interposer with a via cut surface, wherein forming the via cut surface comprises: forming a plurality of vias in the interposer configured in a plurality of non-concentric circles connected to each other; cutting the plurality of vias of the interposer in a direction perpendicular to a plane in which the plurality of non-concentric circles lie to form the via cut surface, the via cut surface being a first I / O surface of the interposer or a second I / O surface non-parallel to the first I / O surface, wherein I / Os at the first I / O surface are connected to I / Os at the second I / O surface through lines within the interposer; electrically connecting the interposer to a substrate through the first I / O surface, wherein the interposer has a side opposite to a cut surface of the cutting, the cut surface being non-parallel to the side, and wherein I / Os at the second I / O surface have different widths.

10. The method of forming a semiconductor package structure of claim 9, wherein, The via cut surface is the second I / O surface and the cutting of the interposer is performed after electrically connecting the interposer to the substrate.

11. The method of forming a semiconductor package structure of claim 10, wherein, After electrically connecting the interposer to the substrate, a plurality of line layers in the interposer are parallel to the substrate.

12. The method of forming a semiconductor package structure of claim 9, wherein, The via cut surface is the first I / O surface and the cutting of the interposer is performed before electrically connecting the interposer to the substrate.

13. The method of forming a semiconductor package structure of claim 12, wherein, After electrically connecting the interposer to the substrate, a plurality of line layers of the interposer are perpendicular to the substrate.

14. The method of forming a semiconductor package structure of claim 9, wherein, Forming the interposer further comprises: forming a line layer; A dielectric layer is overlaid on the circuit layer.

15. The method of forming a semiconductor package structure of claim 9, wherein, The via cut is the first I / O face, the second I / O includes a solder ball, wherein the method further comprises: Performing a cut on the solder ball to remove a portion of the solder ball, a remaining portion of the solder ball forming an outermost layer of the second I / O.

16. The method of forming a semiconductor package structure of claim 9, wherein, Also comprising: Forming a mold over the substrate; Cutting the mold such that the mold exposes the second I / O face.

17. The method of forming a semiconductor package structure of claim 9, wherein, The first I / O face is perpendicular to the second I / O face.

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