Managing programming mode transitions to accommodate constant size of data transfer between host system and memory subsystem

Abstract

A memory sub-system is configured to manage programming mode transitions to accommodate constant sizes of data transfers between a host system and the memory sub-system. The memory sub-system counts single page transitions of an atomic programming mode performed within the memory sub-system, and determines whether to allow any two page transitions of the atomic programming mode based on whether an odd or even number of the single page transitions have been counted. When an odd number of the transitions have been counted, a two page transition is not allowed; otherwise, one or more two page transitions can be allowed. A next transition of the atomic programming mode is selected based on the determination of whether to allow any two page transitions.

Description

[0001] Related applications

[0002] This application claims priority to non-provisional U.S. Patent Application No. 16 / 883,826, filed May 26, 2020, entitled “Management of Programming Mode Transitions to Accommodate a Constant Size of Data Transfer between a Host System and a Memory Sub-System,” which claims priority to provisional U.S. Patent Application No. 62 / 868,060, filed June 28, 2019, also entitled “Management of Programming Mode Transitions to Accommodate a Constant Size of Data Transfer between a Host System and a Memory Sub-System,” the entire disclosure of which is hereby incorporated by reference. Technical Field

[0003] At least some of the embodiments disclosed herein generally relate to memory systems, and more specifically (but not limited to) to managing programming mode shifts to accommodate a constant size of data transfers between a host system and a memory subsystem. Background Technology

[0004] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, the host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Attached Figure Description

[0005] Embodiments are shown in the figures by way of example rather than limitation, and similar reference numerals indicate similar elements in the figures.

[0006] Figure 1 Examples of computing systems including a memory subsystem are shown according to some embodiments of the present disclosure.

[0007] Figure 2This demonstrates a timed data transfer manager configured to control data transfer between the host system and the storage subsystem.

[0008] Figure 3 This section demonstrates an example of a memory subsystem with timed data transfer.

[0009] Figure 4 This illustrates an example of a data structure configured to support data transfer between the host system and the memory subsystem.

[0010] Figure 5 This demonstrates a method for timed data transmission.

[0011] Figure 6 This indicates the size of the data to be programmed in atomic programming operations in response to a change in programming mode.

[0012] Figure 7 This demonstrates a method for managing programming mode transitions to accommodate a constant size of data transfers between the host system and the memory subsystem.

[0013] Figure 8 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0014] At least some aspects of this disclosure relate to data transfer between a host system and a memory subsystem. For example, data transfer is timed / scheduled to reduce buffer memory requirements in the memory subsystem, and thus reduce the requirements for power-failure-safe circuitry in the memory subsystem. For example, transitions between atomic programming modes are managed to accommodate a constant size of data transfer between the host system and the memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0015] Traditionally, cache-based architectures are used in memory subsystems to isolate the host system from the memory subsystem. When a write command is received from the host system in the memory subsystem, data is passed from the host system to the cache in the memory subsystem. When the write workload exceeds the bandwidth of the memory subsystem's media and data cannot be committed, stored, or programmed into the media, I / O activity in the host system is suppressed due to a lack of available space in the cache buffer. While such architectures can provide low-latency writes using cached data, they have disadvantages when the write workload exceeds the bandwidth of the memory subsystem's media. For example, the number of unprocessed commands that can be issued to the memory subsystem is limited by the size of the cache buffer memory in the memory subsystem. Increasing the size of the cache buffer memory increases the energy storage capacity requirements of the power failure backup circuitry. Furthermore, command conflicts occur when two or more commands are mapped to the same medium cell that can only execute one command at a time. Conflicts lead to higher cache memory consumption and longer lifespans of data stored in the cache memory. This can increase system costs in terms of both the increased cache buffer memory size requirements and the increased energy storage capacity of the power failure backup circuitry. Furthermore, the first write stream can block the second write stream by buffering data in the cache buffer memory and not reserving buffer space for the second write stream, so that even when there is a medium cell available to execute a write command on the second write stream, the second write stream is blocked due to the lack of buffer space in the cache buffer memory.

[0016] At least some aspects of this disclosure address the above and other deficiencies through timed data transfer between the host system and the memory subsystem. A queuing mechanism is configured to allow commands to be accepted in the memory subsystem without requiring data to be logged there. Queued commands can be mapped to media cells and maintained in a pending queue for each media cell. When a media cell becomes available to execute a write command, buffer space is allocated for the write command data; and depending on the availability of data acceptance at the media cell, the transfer of data for the write command from the host system to the cache buffer of the memory subsystem for logging into the media cell is deferred. Commands in the queue of media cells may not be executed in the order they were received from the host system. Data is transferred in a timely manner via the cache buffer for submission, writing, or programming into the media cells. Therefore, non-blocking command processing can be performed. This arrangement reduces the cache buffer size requirement and the lifetime of data in the cache buffer. For example, the cache buffer size can be reduced to a size proportional to the number of media cells available to support the parallel execution of write commands. The buffer lifetime can be reduced to a time period proportional to the number of data transfers between the host system and memory subsystem executed concurrently for write commands. The significant reduction in cache buffer memory requirements and buffer lifetime reduces power-failure retention requirements. For example, the static random access memory (SRAM) of the memory subsystem controller can be used as a cache buffer. Dynamic random access memory (DRAM) caching can be eliminated. This technique eliminates the double cost of power-failure protection for volatile memory in a computer system by storing more data in host-controlled memory that uses circuitry within the host system for power-failure protection. When using this technique, the increased number of host write streams and / or collisions does not increase the requirements for cache buffer memory and power-failure retention circuitry in the memory subsystem. Furthermore, this technique can offer the benefits of non-blocking and out-of-order command processing. Additionally, transitions between atomic programming modes can be managed based on counting mode transitions that produce single-page data programming and allowing mode transitions that produce two-page data programming after an even number of single-page transitions, as described in further detail below.

[0017] Figure 1 Example computing system 100 including memory subsystem 110 according to some embodiments of the present disclosure is shown. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 102), one or more non-volatile memory devices (e.g., memory device 104), or combinations of such devices.

[0018] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0019] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0020] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0021] Host system 120 may include a processor chipset (e.g., processing device 118) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., controller 116) (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to and read data from memory subsystem 110.

[0022] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect High Speed ​​(PCIe) interface, Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via PCIe interface, host system 120 can further utilize NVM Express (NVMe) interface to access components (e.g., memory device 104). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0023] The processing unit 118 of the host system 120 may be, for example, a microprocessor, a central processing unit (CPU), a processor core, an execution unit, etc. In some cases, the controller 116 may be referred to as a memory controller, a memory management unit, and / or an initiator. In one example, the controller 116 controls communication on a bus coupled between the host system 120 and the memory subsystem 110. Typically, the controller 116 may send commands or requests to the memory subsystem 110 to request access to memory devices 102, 104. The controller 116 may further include an interface circuitry for communicating with the memory subsystem 110. The interface circuitry may translate responses received from the memory subsystem 110 into information for the host system 120.

[0024] The controller 116 of the host system 120 can communicate with the controller 115 of the memory subsystem 110 to perform operations, such as reading, writing, or erasing data at memory devices 102, 104, and other such operations. In some cases, the controller 116 is integrated within the same package as the processing device 118. In other cases, the controller 116 is packaged separately from the processing device 118. The controller 116 and / or the processing device 118 may include hardware such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, cache memory, or combinations thereof. The controller 116 and / or the processing device 118 may be a microcontroller, a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0025] Memory devices 102 and 104 may include different types of non-volatile memory components and / or any combination of volatile memory components. Volatile memory devices (e.g., memory device 102) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0026] Examples of non-volatile memory components include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. Crosspoint arrays of non-volatile memory can be combined with stackable cross-grid data access arrays to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0027] Each of the memory devices 104 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 104 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 104 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0028] Although non-volatile memory devices, such as 3D crosspoint type and NAND type memory (e.g., 2D NAND, 3D NAND), are described, memory device 104 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0029] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 104 to perform operations, such as reading, writing, or erasing data at the memory device 104, and other such operations (e.g., in response to commands scheduled on the command bus by controller 116). Controller 115 may include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic for performing the operations described herein. Controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0030] The controller 115 may include a processing means 117 (processor) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0031] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is shown to include a controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0032] Typically, controller 115 may receive commands or operations from host system 120 and may translate these commands or operations into instructions or appropriate commands to perform the desired access to memory device 104. Controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with memory device 104. Controller 115 may further include host interface circuitry for communicating with host system 120 via a physical host interface. The host interface circuitry may translate commands received from the host system into command instructions to access memory device 104, and translate responses associated with memory device 104 into information for host system 120.

[0033] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive and decode addresses from the controller 115 to access the memory device 104.

[0034] In some embodiments, memory device 104 includes a local media controller 105, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 104. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 104 (e.g., perform media management operations on memory device 104). In some embodiments, memory device 104 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 105) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0035] The computing system 100 includes a data transfer manager 113 in a memory subsystem 110 that postpones data transfer for write commands until it is determined that one or more media units / memory devices are available to submit, store, write, or program data into the media units / memory devices. Alternatively or in combination, the data transfer manager 113 may manage transitions between atomic programming modes to accommodate a constant size of data transfers between the host system and the memory subsystem. In some embodiments, a controller 115 in the memory subsystem 110 includes at least a portion of the data transfer manager 113. In other embodiments, or in combination, a controller 116 and / or a processing device 118 in the host system 120 includes at least a portion of the data transfer manager 113. For example, controllers 115, 116, and / or processing device 118 may include a logic circuitry system implementing the data transfer manager 113. For example, controller 115 or the processing device 118 (processor) of the host system 120 may be configured to execute instructions stored in memory to perform the operations of the data transfer manager 113 described herein. In some embodiments, the data transfer manager 113 is implemented in an integrated circuit chip housed in the memory subsystem 110. In other embodiments, the data transfer manager 113 is part of the operating system of the host system 120, a device driver, or an application.

[0036] Data transfer manager 113 can schedule data transfer from host system 120 to memory subsystem 110 to reduce the amount and time of data buffered in memory subsystem 110 before data is submitted, stored, written, or programmed into media units / memory devices 102 through 104. For example, when a media unit (e.g., 102 or 104) is determined to be available for executing a write command (e.g., not busy with other operations), data transfer manager 113 initiates the transfer of data for the write command from host system 120 to memory subsystem 110. When a media unit (e.g., 102 or 104) is determined to be busy with another command operation, data transfer manager 113 postpones the transfer of data for queued write commands from host system 120 to memory subsystem 110 for media units (e.g., 102 or 104). Generally, the data transfer manager 113 is configured to initiate the transfer of data from the host system 120 to the memory subsystem 110 for a subset of media units 102 to 104 (determined to be available for write operations), and to defer the transfer of more data for the remaining subset of media units 102 to 104 that are busy with other operations. Because data for write commands is retrieved from the host system 120 in a timely manner for execution, the data transfer manager 113 can reduce and / or minimize the amount and time of data being buffered in the memory subsystem 110, depending on the bandwidth of the media units / memory devices 102 to 104 used to write, store, commit, or program data for storage. Further details regarding the operation of the data transfer manager 113 are described below.

[0037] Figure 2 This demonstrates a timed data transfer manager 113 configured to control data transfer between the host system 120 and the memory subsystem 110. For example, Figure 2 Data transfer manager 113 can be used Figure 1 Implemented in computer system 100.

[0038] exist Figure 2 In this system, host system 120 has volatile memory 133 for storing data to be written to memory subsystem 110 in medium 203.

[0039] The host system 120 has a power failure retention circuit 131, which may be a volatile memory 133 and / or other components of the host system 120 (e.g., Figure 1The processing device 118 shown provides sufficient power to ensure the safety of data 135 in the volatile memory 133 in the event of a power failure. For example, during a power failure event, the power failure holding circuit 131 can power the volatile memory 133 for a period of time long enough to allow data in the volatile memory 133 to be stored in the non-volatile medium 203 of the memory subsystem 110 and / or another memory device.

[0040] Optionally, the host system 120 may cache the data 135 in non-volatile memory instead of volatile memory 133. Therefore, the data 135 stored in non-volatile memory is protected against power failures; and the power failure protection circuitry 131 for volatile memory 133 can be eliminated. However, using non-volatile memory instead of volatile memory 133 may reduce data access performance and / or increase the cost of the host system 120. In some examples, a combination of volatile memory 133 and non-volatile memory may be used in the host system 120 (e.g., to protect data and / or improve data access performance in the event of a power failure).

[0041] Figure 2 In this context, the data transfer manager 113 of the memory subsystem 110 may maintain at least one command queue 143 for commands received from the controller 116 of the host system 120. The commands in the queue 143 may be stored in the controller of the memory subsystem 110 (e.g., ...). Figure 1 In the local memory 119 (shown as 115), write commands from the host system 120 can be accepted into queue 143 without writing data to the medium 203. Queuing of commands allows commands to be executed out of order in the memory subsystem 110 to achieve performance optimization in some cases.

[0042] Figure 2 In this embodiment, local memory 119 has a power failure retention circuit 141, which can be used to protect the contents of local memory 119 during a power failure event (e.g., 146 and 143). During a power failure event, power failure retention circuit 141 can power local memory 119 for a period of time long enough to allow the contents to be stored in non-volatile memory (e.g., medium 203).

[0043] Optionally, the local memory 119 may be implemented using non-volatile memory to eliminate the need for the power failure retention circuit 141, or a combination of non-volatile memory may be implemented to reduce the requirements for the power failure retention circuit 141.

[0044] exist Figure 2In this configuration, the data transfer manager 113 is configured to time / schedule data transfers between the host system 120 and the memory subsystem 110, thereby reducing the size requirements of the local memory 119 and / or the capacity requirements of the power failure retention circuit 141.

[0045] For example, data transfer manager 113 does not automatically accept and / or transfer data for all write commands queued in command queue 143. To reduce the amount of data 145 buffered in local memory 119, data transfer manager 113 postpones the transfer of data for write commands, and when the media unit (e.g., 109A or 109N, such as...) Figure 1 The transfer is initiated when one of the memory devices 102 and / or 104 shown is determined to be ready to execute a write command.

[0046] Therefore, for each of media units 109A to 109N, local memory 119 may buffer some write command data, but not other write command data. In some embodiments, local memory 119 is configured to buffer no more than a predetermined number of commands (e.g., one command per media unit, or two commands, or another number of commands). However, command queue 143 may buffer more write commands for each of media units 109A to 109N than local memory 119 may buffer for the corresponding media unit (e.g., 109A or 109N) (e.g., to enable out-of-order command execution).

[0047] When the size ratio between a command and its data is large, the technique of buffering commands by reducing the buffering of the command's data can be particularly advantageous.

[0048] Optionally, the data transfer manager 113 may configure a queue (e.g., 143) for each of the media units 109A to 109N. Alternatively, the data transfer manager 113 may configure a combined command queue (e.g., 143) for the media units 109A to 109N, and dynamically assign write commands to the media units 109A to 109N when they become available for execution. For example, when a write command is ready to be executed in an available media unit (e.g., 109A or 109N), a portion of a media layout may be dynamically generated to map the logical address identified in the write command to a memory location in the currently available media unit (e.g., 109A or 109N). Thus, the write command can be executed in the available media unit (e.g., 109A or 109N).

[0049] Figure 3 This section demonstrates an example of a memory subsystem with timed data transfer. For instance, Figure 3The memory subsystem can use Figure 2 Data transfer manager 113 in Figure 1 It is implemented in the memory subsystem 110. However, Figure 1 and Figure 2 The technology is not limited to Figure 3 The implementation scheme of the memory subsystem is shown in the figure. For example, the technology can be implemented as a planar block device, a device supporting namespaces, or a device supporting partitioned namespaces (e.g., Figure 3 (The memory subsystem shown in the diagram). Therefore, the disclosure presented herein is not limited to... Figure 3 Examples.

[0050] exist Figure 3 In this context, namespace 201 is configured over the media storage capacity of memory subsystem 110. Namespace 201 provides a logical block addressing space that can be used by host system 120 to specify memory locations for read or write operations. Namespace 201 can be allocated over a portion or the entire media storage capacity of memory subsystem 110. In some cases, multiple namespaces can be allocated over separate, non-overlapping portions of the media storage capacity of memory subsystem 110.

[0051] exist Figure 3 In this context, namespace 201 is configured to have multiple zones 211, 213, ..., 219. Each zone (e.g., 211) in the namespace allows random read access to local block addressing (LBA) addresses within the zone (e.g., 211) and sequential write access to LBA addresses within the zone (e.g., 211), but not random write access to random LBA addresses within the zone (211). Therefore, data is written to the zone (e.g., 211) in a predetermined sequential order within the LBA address space of namespace 201.

[0052] When configuring a region (e.g., 211) in namespace 201, it is possible to predetermine the media layout for said region (e.g., 211), for example, for simplicity. The LBA addresses in the region (e.g., 211) may be pre-mapped to the media 203 of the memory subsystem 110. However, as discussed above, this predetermined media layout can cause media access conflicts when multiple concurrent write streams are present. Randomizing the mapping from the LBA addresses in the region (e.g., 211) to memory locations in the media 203 can reduce conflicts, but not eliminate them.

[0053] Preferably, a dynamic data placer 153 is configured in the memory subsystem 110 to create a portion of the media layout 130 when scheduling write commands for execution, thereby completely eliminating media access conflicts. In some embodiments, the dynamic data placer 153 may be a portion of the data transfer manager 113.

[0054] For example, the medium 203 of the memory subsystem 110 may have multiple integrated circuit dies 205, ..., 207. Each of the integrated circuit dies (e.g., 205) may have multiple planes 221, ..., 223 of memory cells (e.g., NAND memory cells). Each plane (e.g., 221) may have multiple blocks 231, ..., 233 of memory cells (e.g., NAND memory cells). Each block (e.g., 231) may have multiple pages 241, ..., 243 of memory cells (e.g., NAND memory cells). The memory cells in each page (e.g., 241) are configured to be programmed to store / write / commit data together in an atomic operation; and the memory cells in each block (e.g., 231) are configured to erase data together in an atomic operation.

[0055] When write commands (e.g., 123A and 123N) are scheduled for parallel execution due to the parallel operation of two integrated circuit dies (e.g., 205 and 207) available for write commands (e.g., 123A and 123N), and another write command (e.g., 123N) for storing data in one area (e.g., 211) is scheduled for parallel execution, the dynamic data placer 153 maps the LBA addresses of the write commands to pages located on different dies (e.g., 205 and 207). This avoids media access conflicts.

[0056] Furthermore, when two integrated circuit dies (e.g., 205 and 207) are determined to be available for execution of write commands (e.g., 123A and 123N), the data transfer manager 113 initiates the transfer of data 145 of the write commands (e.g., 123A and 123N) from the host system 120's memory 133 to the local memory 119 of the memory subsystem 110. Thus, most of the data 135 of the write commands in queue 143 can be stored in the host memory 133, while the respective write commands themselves are accepted in the command queue 143 of the memory subsystem 110. The data 145 is used for write commands (e.g., 123A and 123N) ready to be executed for storing data into memory cells in the integrated circuit dies (e.g., 205 and 207) available for servicing the write commands (e.g., 123A and 123N). Because data 145 is only delivered promptly to available integrated circuit dies (e.g., 205 and 207), the lifetime of data 145 buffered in local memory 119 is shortened and / or minimized. Furthermore, the amount of data 145 buffered in local memory 119 can be reduced and / or minimized. The reduced lifetime and amount of data 145 for write commands lowers the requirements for protecting the contents of local memory 119 in the event of a power failure.

[0057] Figure 4 This illustrates an example of a data structure configured to support data transfer between the host system and the storage subsystem. For instance, it can be used... Figure 4 To implement data structures Figure 3 The media layout is 130.

[0058] exist Figure 4 In this configuration, zone mapping 301 is configured to provide media layout information for zones (e.g., 211) within a namespace (e.g., 201). Zone mapping 301 may have multiple entries. Each entry in zone mapping 301 identifies information about a zone (e.g., 211), such as the starting LBA address 311 of the zone (e.g., 211), the block set identifier 313 of the zone (e.g., 211), the cursor value 315 of the zone (e.g., 211), the status 317 of the zone (e.g., 211), etc.

[0059] Host system 120 begins writing data into a region (e.g., 211) at the region's starting LBA address 311. Host system 120 sequentially writes data into the region (e.g., 211) within the LBA space. After a certain amount of data has been written into the region (e.g., 211), a cursor value 315 identifies the current starting LBA address for writing subsequent data. For each write command to the region, the cursor value 315 is moved to a new starting LBA address for the next write command to said region. State 317 may have values ​​indicating that the region (e.g., 211) is empty, full, implicitly open, explicitly open, closed, etc.

[0060] exist Figure 4 In this context, the logical-to-physical block mapping 303 is configured to facilitate the translation of LBA addresses (e.g., 331) into physical addresses in the medium (e.g., 203).

[0061] The logical-to-physical block mapping 303 may have multiple entries. An LBA address (e.g., 331) can be used as an index to, or translated into, an entry in the logical-to-physical block mapping 303. The index can be used to look up an entry for the LBA address (e.g., 331). Each entry in the logical-to-physical block mapping 303 identifies the physical address of a memory block in the medium (e.g., 203) for the LBA address (e.g., 331). For example, the physical address of a memory block in the medium (e.g., 203) may include a die identifier 333, a block identifier 335, a page mapping entry identifier 337, etc.

[0062] The die identifier 333 identifies a specific integrated circuit die (e.g., 205 or 207) in the medium 203 of the memory subsystem 110.

[0063] Block identifier 335 identifies a specific memory block (e.g., NAND flash memory) within an integrated circuit die (e.g., 205 or 207) identified using die identifier 333.

[0064] Page mapping entry identifier 337 identifies entries in page mapping 305.

[0065] Page mapping 305 may have multiple entries. Each entry in page mapping 305 may contain a page identifier 351 that identifies a memory cell page within a memory cell block (e.g., a NAND memory cell). For example, page identifier 351 may contain the page's word line number and the page's sub-block number within the NAND memory cell block. Furthermore, the page entry may contain a page programming mode 353. For example, the page may be programmed in SLC mode, MLC mode, TLC mode, or QLC mode. When configured in SLC mode, each memory cell in the page stores one data bit. When configured in MLC mode, each memory cell in the page stores two data bits. When configured in TLC mode, each memory cell in the page stores three data bits. When configured in QLC mode, each memory cell in the page stores four data bits. Different pages in an integrated circuit die (e.g., 205 or 207) may have different modes for data programming.

[0066] exist Figure 4 In the block set table 307, data on the dynamic media layout of the storage control area (e.g., 211) is stored.

[0067] Block set table 307 may have multiple entries. Each entry in block set table 307 identifies the number / count 371 of integrated circuit dies (e.g., 205 and 207) containing data in the storage area (e.g., 211). For each of the integrated circuit dies (e.g., 205 and 207) used for the area (e.g., 211), the entry in block set table 307 has a die identifier 373, a block identifier 375, a page mapping entry identifier 377, etc.

[0068] Die identifier 373 identifies a specific integrated circuit die (e.g., 205 or 207) in the medium 203 of the memory subsystem 110, on which subsequent data of a storage area (e.g., 211) can be stored.

[0069] Block identifier 375 identifies a specific block (e.g., 231 or 233) of memory (e.g., NAND flash memory) within an integrated circuit die (e.g., 205 or 207) identified using die identifier 373, where subsequent data of a storage area (e.g., 211) may be stored.

[0070] Page mapping entry identifier 337 identifies entries in page mapping 305 that identify pages (e.g., 241 or 241) that can be used to store subsequent data in the storage area (e.g., 211).

[0071] Figure 5 This demonstrates a method for timed data transmission. Figure 5The method can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, special-purpose logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, at least in part, through... Figure 1 , 2 Or 3's data transfer manager 113 executes Figure 5 The method is described. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0072] At block 401, memory subsystem 110 receives multiple streams of write commands from host system 120. For example, each corresponding stream of the multiple streams is configured to sequentially write data in the logical address space in one embodiment; and in another embodiment, the streams of the multiple streams are configured to pseudo-sequentially or randomly write data in the logical address space in one embodiment. Each write stream contains a set of commands annotated to group the dataset together for writing, fine-tuning, or rewriting. Within the group, data may be written sequentially, randomly, or pseudo-sequentially in the logical space. Preferably, data in the group is written to an erase block set, wherein memory cells in the erase block set store data from the stream but not data from other streams. The erase block set can be erased to remove data from the stream without erasing data from other streams.

[0073] For example, each write in the write stream is permitted to be written sequentially at an LBA address in a region (e.g., 211) of the namespace (e.g., 201) allocated on the medium 203 of the memory subsystem 110, but unordered writing of data in the LBA address space is prohibited.

[0074] At box 403, the data transfer manager 113 of the memory subsystem 110 identifies multiple media cells (e.g., 109A to 109N) in the memory subsystem 110 that can be used for parallel writing of data.

[0075] At box 405, the data transfer manager 113 selects a first command from multiple streams for parallel execution in multiple media units available for writing data.

[0076] At block 407, the data transfer manager 113 initiates the transfer of first data from the host system 120 to the local buffer memory 119 of the memory subsystem 110 in response to a first command being selected for parallel execution across multiple media units. For example, the transfer of the first data is deferred until multiple media units become available for write operations to store the first data. This deferred transfer shortens the time the first data is buffered. In response to multiple media units becoming available for write operations, buffer space in the local buffer memory 119 is allocated for buffering the first data transferred from the host system 120 to the memory subsystem 110.

[0077] At block 409, memory subsystem 110 executes the first command in parallel by storing data into multiple memory cells. For example, once the first data has been transferred from local buffer memory 119 to multiple media cells, the buffer space allocated for the first data can be released from buffering the first data. In some examples, the buffer space can be released before the programming / writing of the first data is completed on multiple media cells.

[0078] For example, while the first command is scheduled for execution, a second command may be being executed in a subset of the memory cells of the medium 203 of the memory subsystem 110. Therefore, the subset of memory cells used to execute the second command is unavailable for the first command. After scheduling the first command for a subset of the memory cells of the medium 203 of the memory subsystem 110, the data transfer manager 113 initiates the transfer of data to be written via the first command from the host system 120 to the memory subsystem 110. The timely transfer of data for the first command reduces the amount of time data is buffered in the local memory 119 of the memory subsystem 110, and thus reduces the capacity requirements of the local memory 119 and the capacity requirements of the power failure retention circuitry 141 configured for the local memory 119. The first command can be executed in parallel across multiple medium cells, and / or in parallel with the execution of the second command in the remaining medium cells of the memory subsystem 110.

[0079] For example, memory subsystem 110 is configured to buffer no more than a predetermined number of data units in local buffer memory 119. This predetermined number corresponds to the number of media units 109A to 109N in memory subsystem 110 that can operate independently of each other to write data. Each data unit does not exceed the maximum amount of data to be written to a media unit (e.g., 109A or 109N) in response to a single write command. Therefore, the buffer capacity of local memory 119 does not limit the number of write streams that host system 120 can send to memory subsystem 110. The reduced time data is buffered in local memory 133 reduces the requirements for the corresponding power-failure retention circuitry 141 in memory subsystem 110.

[0080] The memory subsystem 110 can accept write commands and queue them in one or more queues 143 in local memory 119. The number of queued write commands can significantly exceed a predetermined number of data units that can be buffered in local memory 119. Because the performance of the memory subsystem 110 is limited by the bandwidth of the media units 109A to 109N used to submit, write, store, or program data in parallel during the execution of parallel write commands, the limited buffering capacity of the local memory 119 for write commands does not affect the performance of the memory subsystem 110.

[0081] When more commands than can be executed in parallel are queued, memory subsystem 110 may selectively execute certain commands out of the order in which they arrive at memory subsystem 110.

[0082] The reduced buffer memory requirement allows local memory 119 to be configured as static random access memory (SRAM) of controller 115, and therefore DRAM is not required in the process of buffering data to be written to medium 203 of memory subsystem 110. For example, the capacity of the static random access memory (SRAM) used to buffer the data for write commands may be less than the capacity required for all write commands queued in the buffer memory subsystem.

[0083] Optionally, each corresponding media unit (e.g., 109A or 109N) has a command queue configured to write data to the corresponding media unit (e.g., 109A or 109N). The command queue can store multiple write commands; and the local memory 119 can be configured to limit its buffer memory for the data used for write commands. For example, the buffer memory can be limited to a small portion of the capacity of the commands in the queue. For example, the buffer memory can be limited to the size of the data programmable / written / stored / submitted to the corresponding media unit (e.g., 109A or 109N) in response to a single write command (or a predetermined number of write commands less than the total number of write commands that can be queued for the corresponding media unit).

[0084] Optionally, in response to determining that the first command can be executed in parallel in available media units, a portion of the media layout 130 for the logical address used in the first command is dynamically determined.

[0085] For example, after identifying multiple memory cells (e.g., integrated circuit dies) that can be used to execute subsequent commands, the data transfer manager 113 can identify physical addresses from the block set table 307 that can be used to store data for the subsequent commands. These physical addresses can be used to update the corresponding entries in the logical-to-physical block mapping 303 for the LBA addresses used in the subsequent commands.

[0086] For example, when an integrated circuit die (e.g., 205) is freely writable, the data transfer manager 113 can determine commands for regions that can be written to / programmed into memory cells within the integrated circuit die (e.g., 205). Based on the block set table 307, the data transfer manager 113 and / or the dynamic data placer 153 can locate entries for regions (e.g., 205), locate block identifiers 375 and page map entry identifiers 377 associated with the identifier 373 of the integrated circuit die (e.g., 205), and use the die identifier 373, block identifier 375, and page map entry identifier 377 to update the corresponding fields of the entries in the logical-to-physical block map 303 for the LBA address 331 used in the commands for regions (e.g., 211). Therefore, for LBA address 331, commands for regions (e.g., 211) can be executed without media access conflicts.

[0087] Within a media cell (e.g., 109A to 109N or 205 to 207), memory cells (e.g., NAND type) can be organized into blocks (e.g., 231 to 233), where memory cells within each block are erased together in an atomic operation. Memory cell blocks can be divided into sub-blocks and pages. A memory cell page is the smallest unit of memory cells programmed together in an atomic operation. Pages within a sub-block and across a given word line are typically not programmed sequentially. The page programming order within a block can skip across word lines, sub-blocks, and pages to optimize the signal-to-noise ratio (SNR) across word lines and sub-blocks. Therefore, the page programming order within a block can be irregular and have complex patterns.

[0088] Due to multiple programming passes and irregular page mapping, the granularity of atomic programming is not fixed and is variable. When the host system issues write commands with fixed / constant input / output (I / O) sizes, the host I / O size does not always match the programming granularity of the media. This mismatch can increase the requirements for controller memory and power backup, potentially leading to increased costs.

[0089] In at least some of the embodiments disclosed herein, page mapping may still be irregular to accommodate different SNR ratios for word lines within a sub-block and for sub-blocks across a block. However, page mapping is subject to constrained scheduling such that a fixed host I / O size can be matched with a fixed atomic programming size. This constraint is based on a count of transitions to a specific type of programming mode, as discussed further below.

[0090] Figure 6 This indicates the size of the data to be programmed in atomic programming operations in response to a change in programming mode.

[0091] Multi-pass programming techniques can be implemented using multiple atomic programming operations. Each of these atomic programming operations can transition from one memory cell programming mode to another.

[0092] For example, when multi-pass programming techniques are applied to a set of pages of memory cells for TLC programming, multi-pass TLC programming can be implemented via several transitions in atomic programming modes. For example, multi-pass TLC programming can begin on a set of fresh pages that have not yet been programmed to store data (e.g., after an erase operation). A new multi-pass TLC programming can transition from no programming on the fresh page set to atomic SLC programming of memory cell pages to store one page of data of a predetermined size. Alternatively, a new multi-pass TLC programming can transition from no programming to atomic MLC programming of two pages of data, each page having a predetermined size. Subsequently, as a result of said transition, multi-pass TLC programming can optionally transition from atomic SLC programming to atomic MLC programming of one page of data of the predetermined size. Optionally, as a result of said transition, multi-pass TLC programming can continue to transition from atomic SLC programming to atomic TLC programming of two pages of data, each page having a predetermined size. Alternatively, as a result of said transition, multi-pass TLC programming can transition from atomic MLC programming to atomic TLC programming of one page of data of the predetermined size.

[0093] Similarly, when multi-pass programming techniques are applied to a set of pages of memory cells for QLC programming, multi-pass QLC programming can be implemented via several transformations of the atomic programming mode. Multi-pass QLC programming can have the same transformations as in multi-pass TLC programming. Furthermore, multi-pass QLC programming can optionally be transformed from atomic MLC programming to atomic QLC programming of two pages of data, each page having a predetermined size. Alternatively, as a result of said transformation, multi-pass QLC programming can optionally be transformed from atomic TLC programming to atomic QLC programming of one page of data of a predetermined size.

[0094] against Figure 6 The page count of the transition options shown can be used to manage programming mode transitions in memory subsystem 110, as described below. Figure 7 Further discussion. For example, a transition type with an atomic programming size of one page can be interleaved with a transition type with an atomic programming size of two pages; and an even number of transition types with an atomic programming size of one page must occur sequentially before one or more subsequent transitions that allow for an atomic programming size of two pages. When irregular page mappings do not follow this transition pattern, a fixed host input / output size cannot always be mapped to the next atomic programming granularity.

[0095] For example, atomic programming granularity sequences of "one page, two pages, etc." do not follow the pattern of having a two-page transition after an even number of single-page transitions. Therefore, mapping fixed host input / output sizes (e.g., one page or two pages) to a sequence can be challenging. For instance, the host size is fixed at one page. After the first programming at one page, the next host input / output of that page cannot be processed until another host input / output is received and mapped to the same die and block for two-page atomic programming. In another instance, the host size is fixed at two pages. One-page atomic programming can be used to program the first half of the two-page host input / output. However, the second half of the two-page host input / output cannot be programmed until another host input / output is received and mapped to the same die and block for two-page atomic programming. Waiting for the next input / output to map to the same die and block can increase buffer memory usage and the lifetime of data buffered in memory, especially when there are multiple unprocessed commands that do not match the atomic granularity. Increased use of buffer memory and the increased lifetime of buffered data may increase the requirements for controller memory and power failure protection backup capacity.

[0096] However, when using a sequence of atomic programming granularities such as "one page, one page, two pages, etc." with an even number of single-page transitions following a two-page transition, a fixed host input / output size can be matched with the atomic programming granularity in the sequence. For example, when the host size is fixed at two pages. Therefore, the first atomic programming of one page can be used to program the first half of the two-page host input / output; and the second atomic programming of one page can be used to program the second half. Subsequent programming of two pages can be used to program the next two-page host input / output.

[0097] If the zone / flow size is 4 (multi-plane) blocks, due to irregular page mapping, a mix of 2-plane and 4-plane programming must be used instead of always using 4-plane programming to match the fixed host I / O size (4 pages in an instance). This mix of 2-plane and 4-plane programming, instead of always using 4-plane programming, results in performance penalties and increased power consumption.

[0098] Therefore, it is advantageous to implement a page mapping sequence in which 1) transition types with an atomic programming size of 1 page are interleaved with transition types with an atomic programming size of 2 pages; and 2) an even number of transition types with an atomic programming size of 1 page must occur sequentially before the transition sequence with an atomic programming size of 2 pages occurs. This pattern can be repeated any number of times in the page mapping sequence.

[0099] Figure 7 This demonstrates a method for managing programming mode transitions to accommodate a constant size of data transfers between the host system and the memory subsystem. Figure 7The method can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, special-purpose logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, Figure 5 The method is at least in part by Figure 1 , 2 The data transfer manager 113 and / or dynamic data placer 153 may execute the process. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0100] At box 421, the data transfer manager 113 and / or the dynamic data placer 153 begin counting single-page transitions of atomic programming modes performed within the memory subsystem (e.g., 110). Each single-page transition implements atomic programming of a single page of data of a predetermined size.

[0101] At box 423, the data transfer manager 113 and / or the dynamic data placer 153 determine whether the number of transformations is odd or even.

[0102] For example, a one-bit counter can be used to count single-page transitions in atomic programming mode. A one-bit counter can be initially set to have a value of zero. When a single-page transition occurs, a one can be added to the one-bit counter (e.g., via a logical AND operation) to update its content.

[0103] If it is determined at box 425 that an odd number of single-page transitions for the atomic programming mode have been counted, then the data transfer manager 113 and / or the dynamic data placer 153 prevent two-page transitions for the atomic programming mode at box 427. Each two-page transition implements atomic programming of two pages of data, each page having a predetermined size.

[0104] If an even number of single-page transitions in the atomic programming mode are determined to have occurred at box 425, then the data transfer manager 113 and / or the dynamic data placer 153 allow one or more two-page transitions in the atomic programming mode at box 429. Each two-page transition implements atomic programming of two pages of data, each page having a predetermined size.

[0105] For example, a one-bit counter has a value of one and can block any two-page transition in time until the one-bit counter has a value of zero.

[0106] At box 431, the data transfer manager 113 and / or dynamic data placer 153 switch programming modes according to the restrictions / permissions defined in boxes 427 and 429.

[0107] At box 433, the data transfer manager 113 and / or dynamic data placer 153 update the count of programming mode transitions.

[0108] The operations in boxes 423 to 433 can be repeated for the pages in the block.

[0109] For example, multiple programming operations can be performed to store data. Each multiple programming operation can be performed on the page set via multiple atomic programming operations in the memory subsystem 110. Each multiple programming operation can store at least one memory cell page in either a three-level cell (TLC) mode or a four-level cell (QLC) mode. The atomic programming operation can transition from a first mode to a second mode, wherein the first and second modes are different modes of: no programming; programming to store one bit in each memory cell; programming to store two bits in each memory cell; programming to store three bits in each memory cell; and programming to store four bits in each memory cell.

[0110] A single-page transition can be from no programming to single-level cell (SLC) mode, from SLC mode to multi-level cell (MLC) mode, from MLC mode to three-level cell (TLC) mode, or from three-level cell (TLC) mode to four-level cell (QLC) mode.

[0111] Two-page transitions can be from single-level cell (SLC) mode to three-level cell (TLC) mode, from multi-level cell (MLC) mode to four-level cell (QLC) mode, or from no programming to multi-level cell (MLC) mode.

[0112] The memory subsystem 110 may receive multiple streams of write commands from the host system 120 and perform multiple passes of programming data to store data in multiple planes within one or more media cells (e.g., dies 205 to 207). The memory subsystem 110 may select the next transition of the atomic programming mode based on determining whether any two-page transition of the atomic programming mode is permitted, and make the size of the atomic programming mode resulting from the next transition match the size of the write commands from the host system.

[0113] In some implementations, the communication channel between the processing device 118 and the memory subsystem 110 includes a computer network, such as a local area network, wireless local area network, wireless personal area network, cellular communication network, or broadband high-speed always-connected wireless communication connection (e.g., current or future generation mobile network link); and the processing device 118 and the memory subsystem may be configured to communicate with each other using data storage management and usage commands similar to those in the NVMe protocol.

[0114] The memory subsystem 110 may typically have a non-volatile storage medium. Examples of non-volatile storage media include memory cells formed in integrated circuits and magnetic materials coated on a hard disk. Non-volatile storage media can maintain the data / information stored therein without consuming power. Memory cells can be implemented using various memory / storage device technologies, such as NAND logic gates, NOR logic gates, phase-change memory (PCM), magnetic random access memory (MRAM), resistive random access memory, cross-point memory devices, and memory devices (e.g., 3D XPoint memory). Cross-point memory devices use transistorless memory elements, each of which has memory cells and selectors stacked together in a column. The column of memory elements is connected via two vertical wire layers, one layer above the column and the other layer below. Each memory element can be individually selected at the intersection of a wire on each of the two layers. Cross-point memory devices are fast and non-volatile and can be used as a unified memory pool for processing and storage.

[0115] The controller (e.g., 115) of the memory subsystem (e.g., 110) may run firmware to perform operations in response to communications from the processing device 118. Generally, firmware is a type of computer program that provides control, monitoring, and data manipulation for an engineered computing device.

[0116] Some embodiments involving the operation of controller 115 may be implemented using computer instructions (e.g., firmware of controller 115) executed by controller 115. In some cases, hardware circuitry may be used to implement at least some of the functions. The firmware may be initially stored in a non-volatile storage medium or another non-volatile device and loaded into volatile DRAM and / or in-processor cache memory for execution by controller 115.

[0117] Non-transitory computer storage media may be used to store instructions for the firmware of a memory subsystem (e.g., 110). When executed by controller 115 and / or processing device 117, the instructions cause controller 115 and / or processing device 117 to perform the methods described above.

[0118] Figure 8 An example machine of computer system 500 is shown, within which an instruction set executable for causing the machine to perform any one or more of the methods discussed herein is provided. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform the operations of the data transfer manager 113 (e.g., execute instructions to perform operations corresponding to the reference). Figure 1-7 The operation of the data transfer manager 113 is described. In alternative embodiments, the machine may connect (e.g., network) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment within the capacity of a server or client machine in a client-server network environment.

[0119] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or jointly execute a set (or sets of sets) of instructions to perform any or more of the methods discussed herein.

[0120] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530 (which may include multiple buses).

[0121] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communication via network 520.

[0122] Data storage system 518 may include machine-readable storage medium 524 (also called computer-readable medium) on which one or more instruction sets 526 or software embodying any one or more methods or functions described herein are stored. Instructions 526 may also reside wholly or at least partially within main memory 504 and / or processing device 502 during execution by computer system 500, which also constitute machine-readable storage media. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0123] In one embodiment, instruction 526 includes implementations corresponding to data transfer manager 113 (e.g., reference 113). Figure 1-8 The data transfer manager 113 described contains functional instructions. While the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing the one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" should be accordingly understood to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0124] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and are generally considered, a self-consistent sequence of operations that produce the desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for reasons of common use, it has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0125] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0126] The present invention also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for a particular purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0127] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the teachings and procedures herein, or it may prove convenient to construct more specialized devices to implement the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0128] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable for programming a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0129] In this specification, various functions and operations are described as being executed or caused by computer instructions for the sake of simplicity. However, those skilled in the art will recognize that such expressions are intended to mean that the functions originate from one or more controllers or processors (e.g., microprocessors) executing computer instructions. Alternatively or in combination, the functions and operations may be implemented using a dedicated circuit system with or without software instructions, such as using an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). Embodiments may be implemented using hardwired circuit systems without software instructions or in combination with software instructions. Therefore, the techniques described are neither limited to any particular combination of hardware circuit systems and software, nor to any particular source of instructions executed by a data processing system.

[0130] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method comprising: The single-page transitions of the atomic programming mode executed within the memory subsystem are counted, wherein each of the single-page transitions implements atomic programming of a single page of data of a predetermined size in the memory subsystem; Determine whether the number of page transitions is odd or even; Determine whether any two-page transition is allowed in atomic programming patterns that implement atomic programming of two pages of data, each having the predetermined size, wherein: When an odd number of the aforementioned transitions have been counted, two-page transitions in the atomic programming mode for implementing the predetermined two-page atomic programming are not permitted; and When an even number of the aforementioned transitions have been counted, at least one two-page transition of an atomic programming pattern that enables atomic programming of the predetermined two-page size is permitted; and The transition of the atomic programming mode is selected based on whether any two-page transition of the atomic programming mode is allowed.

2. The method according to claim 1, further comprising: Multiple rounds of programming of the page set are performed via multiple atomic programming operations in the memory subsystem.

3. The method of claim 2, wherein each atomic programming operation performed for the multiple iterations of programming of the page set transitions from a first mode to a second mode.

4. The method of claim 3, wherein the first mode and the second mode are different modes among the following: No programming required; Programming used to store a bit in each memory cell; Programming used to store two bits in each memory cell; Programming used to store three bits in each memory cell; and Programming used to store four bits in each memory cell.

5. The method according to claim 4, wherein the multi-pass programming is a three-level cell (TLC) pattern for the page set or a four-level cell (QLC) pattern for the page set.

6. The method of claim 1, wherein the single-page transition in the atomic programming mode comprises multiple programming operations transitioning from no programming to atomic programming in the single-level cell (SLC) mode.

7. The method of claim 6, wherein the single-page transition of the atomic programming mode comprises the multi-pass programming operation transitioning from the single-level cell (SLC) mode to the multi-level cell (MLC) mode.

8. The method of claim 7, wherein the single-page transition of the atomic programming mode comprises the multi-pass programming operation transitioning from a multi-level cell (MLC) mode to a three-level cell (TLC) mode.

9. The method of claim 8, wherein the single-page transition of the atomic programming mode comprises the multi-pass programming operation transitioning from the three-level cell (TLC) mode to the four-level cell (QLC) mode.

10. The method of claim 8, wherein the two-page transition of the atomic programming mode for implementing the atomic programming of the predetermined two pages is from the single-level cell (SLC) mode to the three-level cell (TLC) mode.

11. The method of claim 8, wherein the two-page transition of the atomic programming mode that implements the atomic programming of the predetermined two pages is from the multi-level cell (MLC) mode to the four-level cell (QLC) mode.

12. The method of claim 8, wherein the two-page transition of the atomic programming mode that implements the atomic programming of the predetermined two pages is from no programming to the multi-level cell (MLC) mode.

13. A memory subsystem comprising: Multiple media units that can write data in parallel; At least one processing device is configured to: Receive multiple write command streams from the host system; In the medium unit, multiple passes of programming of the page set are performed via multiple atomic programming operations; The single-page transitions in the atomic programming mode are counted, wherein each single-page transition implements atomic programming of a single page of data of a predetermined size in the media unit; Determine whether the number of page transitions is odd or even; Determine whether to allow any two-page transitions in the atomic programming mode, wherein each two-page transition implements atomic programming of two pages of data of the predetermined size, wherein: Two-page transitions in atomic programming mode are not allowed when an odd number of the transitions have already been counted; and When an even number of the aforementioned transitions have been counted, one or more two-page transitions in an atomic programming mode are permitted; and The next transition of the atomic programming mode is selected based on whether any two-page transition of the atomic programming mode is allowed.

14. The memory subsystem of claim 13, wherein the at least one processing means is further configured to select the next transition such that the size of the atomic programming pattern generated by the next transition matches the size of the write command from the host system.

15. The memory subsystem of claim 14, wherein the multiple-pass programming of the page set is performed on the pages in at least a three-level cell (TLC) mode or a four-level cell (QLC) mode.

16. The memory subsystem of claim 15, wherein each atomic programming operation performed for the multiple passes of programming of the page set transitions from a first mode to a second mode.

17. The memory subsystem of claim 16, wherein the first mode and the second mode are different modes among the following: No programming required; Programming used to store a bit in each memory cell; Programming used to store two bits in each memory cell; Programming used to store three bits in each memory cell; and Programming used to store four bits in each memory cell.

18. A non-transitory computer storage medium storing instructions, said instructions, when executed in a memory subsystem, causing the memory subsystem to perform a method, said method comprising: Receive multiple write command streams from the host system; Perform multiple programming operations, wherein each multiple programming operation programs a set of pages in the memory subsystem via multiple atomic programming operations; The page transitions in the atomic programming mode are counted, wherein each page transition implements atomic programming of a predetermined size of page data in the memory subsystem; Determine whether to allow any two-page transitions in the atomic programming mode, wherein each two-page transition implements atomic programming of two pages of data of the predetermined size, wherein: Two-page transitions in atomic programming mode are not allowed when an odd number of the transitions have already been counted; and When an even number of the aforementioned transitions have been counted, one or more two-page transitions in an atomic programming mode are permitted; and The next transition of the atomic programming mode is selected based on whether any two-page transition of the atomic programming mode is allowed.

19. The non-transitory computer storage medium of claim 18, wherein the next transition is selected such that the size of the atomic programming pattern resulting from the next transition matches the size of the write command from the host system.

20. The non-transitory computer storage medium of claim 18, wherein each page transition is one of the following: The transition is from no programming to programming memory cells to each store a single bit; The process has shifted from programming memory cells to store individual bits to programming memory cells to store two bits each. The program was changed from programming memory cells to store two bits each to programming memory cells to store three bits each; and The program was changed from programming memory cells to store three bits each to programming memory cells to store four bits each; and The two-page transitions mentioned therein are one of the following: The transition is from no programming to programming memory cells to each store two bits; The shift is from programming memory cells to store individual bits to programming memory cells to store three bits each; and The program has shifted from programming memory cells to store two bits each to programming memory cells to store four bits each.

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