A debugging and upgrading system, method and device for an expansion chip

Abstract

The embodiments of the present application disclose a system, method, and device for debugging and upgrading an expansion chip, wherein a BMC is connected to a first UART SW chip; each expansion chip is connected to at least one second UART SW chip; and the first UART SW chip is connected to each second UART SW chip. The BMC is connected to a CPLD, and the register information of the CPLD is adjusted according to the target expansion chip that currently needs to be debugged and upgraded. The CPLD is connected to the first UART SW chip, and is used to control the connection between the first UART SW chip and the second UART SW chip corresponding to the target expansion chip according to the register information, and to control the disconnection between the first UART SW chip and the second UART SW chips corresponding to the remaining expansion chips, so as to achieve debugging and upgrading of the target expansion chip. The cooperation between the BMC and the CPLD reduces the difficulty of debugging and upgrading.

Description

Technical Field

[0001] The present application relates to the technical field of server hardware management and control, and in particular to a debugging and upgrading system, method, and device for an expansion chip. Background Art

[0002] With the development of big data, the storage capacity demand for servers is increasing, which in turn requires an increasing number of hard drives connected to servers. Server hard drives include hard disk drives (HDDs) and non-volatile memory express (NVME) hard drives.

[0003] Server hardware requires multiple SAS Expander chips or PCIe Switch chips to connect a large number of hard drives. A SAS Expander chip is a device that expands a single SAS port into multiple SAS ports.

[0004] SAS Expander chips or PCIE Switch chips are typically located deep inside the chassis, making debugging and firmware upgrades difficult. SAS Expander chips and PCIE Switch chips are typically connected to a personal computer (PC) via a Universal Asynchronous Receiver / Transmitter (UART) debug cable, allowing debugging and firmware upgrades to be performed on the PC.

[0005] Figure 1 This diagram shows a framework for implementing expansion chip (SAS EXP / PCIE SW) debugging and firmware programming in the prior art. A SAS Expander or PCIE Switch chip typically has two serial debug ports: an SDB (Serial Debug UART) port and a UART port. The SDB port is primarily used to access and read / write the expansion chip's internal registers, allowing for testing and debugging. The UART port is primarily used for firmware upgrades and configuration, with firmware files being burned into the Flash memory connected to the expansion chip. A PC establishes a connection to the expansion chip by running serial port software, enabling debugging of the expansion chip or firmware programming.

[0006] Existing technical solutions use a dedicated UART cable to debug the expansion chip and burn the firmware during the single-board hardware debugging phase. After the server can run the system program (Windows or Linux system) normally, online debugging and remote firmware upgrade can be performed through commands. However, during the single-board hardware debugging phase, if the server cannot run the system software normally, system debugging and remote firmware upgrade are impossible and can only be performed using the dedicated UART cable.

[0007] Connecting a UART debug cable from a PC outside the chassis to a board inside the deep server chassis is inconvenient. Furthermore, the compact space inside the server chassis, with its large number of boards and cables, makes plugging and unplugging the dedicated UART cable difficult. Furthermore, debugging multiple expansion chips and programming firmware requires multiple cable plugging and unplugging, which requires opening the server chassis cover multiple times, significantly complicating debugging work.

[0008] It can be seen that how to reduce the difficulty of debugging work is a problem that those skilled in the art need to solve. Summary of the Invention

[0009] The purpose of the embodiments of the present application is to provide a debugging and upgrading system, method and device for an expansion chip, which can reduce the difficulty of debugging work.

[0010] To solve the above technical problems, an embodiment of the present application provides a debugging and upgrading system for an extension chip, comprising a BMC, a CPLD, a UART SW chip, and an extension chip; wherein the BMC is connected to a first UART SW chip; each extension chip is connected to at least one second UART SW chip; the first UART SW chip is connected to each of the second UART SW chips;

[0011] The BMC is connected to the CPLD and is used to adjust the register information of the CPLD according to the target expansion chip that needs to be debugged and upgraded currently;

[0012] The CPLD is connected to the first UART SW chip and is used to control the first UART SW chip to connect with the second UART SW chip corresponding to the target expansion chip and control the first UART SW chip to disconnect from the second UART SW chips corresponding to the remaining expansion chips based on the register information, so as to realize the debugging and upgrading of the target expansion chip.

[0013] Optionally, the CPLD and the first UART SW chip are arranged on the same IO board.

[0014] Optionally, the number of second UART SW chips connected to each extension chip is set based on the number of serial debugging ports included in a single extension chip and the model of the second UART SW chip.

[0015] Optionally, the number of the first UART SW chips is set based on the number of the second UART SW chips and the model of the first UART SW chip.

[0016] Optionally, a PC is also included;

[0017] The PC is connected to the serial debugging port of each expansion chip respectively to realize local debugging and upgrading of the expansion chip.

[0018] Optionally, the CPLD is connected to the enable terminal of the first UART SW chip, and is used to control the first UART SW chip to be turned off when performing local debugging and upgrading; and to control the first UART SW chip to be connected when performing BMC debugging and upgrading.

[0019] The present application also provides a debugging and upgrading method for an expansion chip, which is applicable to a debugging and upgrading system including a BMC, a CPLD, a UART SW chip, and an expansion chip; wherein the BMC is connected to the CPLD and the first UART SW chip respectively; each expansion chip is connected to at least one second UART SW chip; the first UART SW chip is connected to each of the second UART SW chips; the method includes:

[0020] According to the target expansion chip currently requiring debugging and upgrading, register information of the CPLD is adjusted so that the CPLD controls the first UART SW chip to connect with the second UART SW chip corresponding to the target expansion chip and controls the first UART SW chip to disconnect from the second UART SW chips corresponding to other expansion chips, thereby achieving debugging and upgrading of the target expansion chip.

[0021] Optionally, it also includes:

[0022] In the case of local debugging and upgrading, adjusting register information corresponding to the first UART SW chip in the CPLD to a non-enable value so that the CPLD controls the first UART SW chip to shut down; wherein the CPLD is connected to the enable terminal of the first UART SW chip;

[0023] When performing BMC debugging and upgrading, the register information corresponding to the first UART SW chip in the CPLD is adjusted to an enable value, so that the CPLD controls the first UART SW chip to be connected.

[0024] The embodiment of the present application further provides a debugging and upgrading device for an extension chip, which is applicable to a debugging and upgrading system including a BMC, a CPLD, a UART SW chip, and an extension chip; wherein the BMC is connected to a first UART SW chip; each extension chip is connected to at least one second UART SW chip; the first UART SW chip is connected to each of the second UART SW chips; the device includes an adjustment unit;

[0025] The adjustment unit is configured to adjust register information of the CPLD based on a target expansion chip that currently needs to be debugged and upgraded, so that the CPLD controls the first UART SW chip to connect to the second UART SW chip corresponding to the target expansion chip, and controls the first UART SW chip to disconnect from the second UART SW chips corresponding to other expansion chips, thereby enabling debugging and upgrading of the target expansion chip.

[0026] Optionally, the adjustment unit is further used to adjust the register information corresponding to the first UART SW chip in the CPLD to a non-enabled value in the case of local debugging and upgrading, so that the CPLD controls the first UART SW chip to shut down; wherein, the CPLD is connected to the enable end of the first UART SW chip; when performing BMC debugging and upgrading, the register information corresponding to the first UART SW chip in the CPLD is adjusted to an enabled value, so that the CPLD controls the first UART SW chip to be connected.

[0027] It can be seen from the above technical solution that the debugging and upgrading system of the expansion chip includes BMC, CPLD, UART SW chip and expansion chip; in order to solve the problems caused by the compact internal space of the server chassis, and the problem that the system software cannot run normally in the initial stage of single-board startup debugging, the BMC is used to control the CPLD to realize the debugging and upgrading of the internal expansion chip of the server. In the specific implementation, the BMC can be connected to the first UARTSW chip; each expansion chip is connected to at least one second UART SW chip; the first UART SW chip is connected to each second UART SW chip. The BMC is connected to the CPLD, and when it is necessary to perform debugging or upgrading operations on a target expansion chip, the BMC can adjust the register information of the CPLD according to the target expansion chip that needs to be debugged and upgraded. The register information of the CPLD can be used to indicate the connection and disconnection between the first UART SW chip and each second UART SW chip. CPLD is connected to the first UART SW chip. CPLD can control the first UART SW chip to be connected to the second UART SW chip corresponding to the target expansion chip according to register information, and control the first UART SW chip to be disconnected from the second UART SW chips corresponding to the remaining expansion chips, so as to realize the debugging and upgrading of the target expansion chip. In this technical scheme, a UART signal is expanded into multiple channels by the first UART SW chip, so as to realize the control of multiple expansion chips. Through the cooperation of BMC and CPLD, the on-off between the first UART SW chip and the second UART SW chip can be controlled. Since each expansion chip is connected with at least one second UART SW chip, the on-off between the first UART SW chip and the expansion chip can be controlled. By controlling the gating of the UART channel by CPLD, remote online debugging and FW burning and upgrading of multiple expansion chips are realized, which solves the problem of frequently plugging and unplugging debugging cables and frequently switching server chassis, and effectively reduces the difficulty of debugging and upgrading work. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0029] Figure 1 This is a framework diagram for implementing extended chip debugging and FW burning in the existing technology;

[0030] Figure 2 A schematic diagram of the structure of a debugging and upgrading system for an expansion chip provided in an embodiment of the present application;

[0031] Figure 3 A schematic diagram of the hardware device connection relationship of a debugging and upgrading system for an expansion chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0033] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the accompanying drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or elements is not limited to the listed steps or elements and may include steps or elements that are not listed.

[0034] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0035] Next, a debugging and upgrading system for an expansion chip provided by an embodiment of the present application is described in detail. Figure 2 A structural diagram of a debugging and upgrading system for an extension chip provided in an embodiment of the present application, the system includes a BMC (Baseboard Management Controller) 11, a CPLD (Complex Programmable Logic Device) 12, a UART SW (UART SWitch) chip and an extension chip 15; wherein the BMC 11 is connected to a first UART SW chip 13; each extension chip 15 is connected to at least one second UART SW chip 14; and the first UART SW chip 13 is connected to each second UART SW chip 14.

[0036] In a specific implementation, the first UART SW chip 13 and the second UART SW chip 14 can be chips of the same model. The chip model may include the number of chip output ports. In the embodiment of the present application, to facilitate distinguishing different UART SW chips, the UART SW chip directly connected to the BMC and CPLD is referred to as the first UART SW chip 13, and the UART SW chip directly connected to the expansion chip 15 is referred to as the second UART SW chip 14.

[0037] The expansion chip may include a SAS Expander (Serial Attached SCSI Expander, hard disk switch) or a PCIE Switch.

[0038] Taking into account the compact space caused by the large number of single boards and cables inside the server chassis in the prior art, it is difficult to plug and unplug the UART dedicated cable. Moreover, multiple expansion chip debugging and FW burning require multiple plugging and unplugging cables, which requires opening the server chassis cover multiple times to plug and unplug the cables, causing great trouble to the debugging work. The method of implementing the debugging of the expansion chip and remote FW burning through instructions requires that online debugging and remote FW burning be performed through instructions after the server can run the system program (Windows or Linux system) normally. However, during the single-board hardware debugging stage, when the server cannot run the system software normally, system debugging and remote FW burning cannot be performed, and debugging and FW burning can only be performed through the UART dedicated cable.

[0039] Therefore, the embodiment of the present application provides a feasible implementation method. For the expansion chip, a second UARTSW chip 14 is provided. The BMC 11 can connect to different second UARTSW chips 14 through the first UARTSW chip 13. The BMC 11 can control the on / off of each output port of the first UARTSW chip 13 by controlling the CPLD 12.

[0040] In a specific implementation, the BMC 11 is connected to the CPLD 12 , and the BMC 11 can adjust the register information of the CPLD 12 according to the target expansion chip 15 that needs to be debugged and upgraded.

[0041] In practical applications, the CPLD 12 may include registers for recording the status of each output port of the first UART SW chip 13. Different numbers may be used in the registers to represent different states of the output ports. For example, the number "1" may be used to indicate that the output port is connected, and the number "0" may be used to indicate that the output port is disconnected.

[0042] The first UART SW chip 13 may include multiple output ports, each of which is connected to a second UART SW chip 14 , thereby achieving connection to multiple extension chips 15 .

[0043] In actual applications, generally, debugging or upgrading operations are performed sequentially on each expansion chip 15. For the sake of distinction, the expansion chip 15 that needs to be debugged or upgraded is referred to as the target expansion chip 15.

[0044] When debugging or upgrading the target expansion chip 15, it is necessary to ensure that the remaining expansion chips 15 are not affected. Therefore, the CPLD 12 is connected to the first UART SW chip 13. Based on the register information, the CPLD 12 can control the first UART SW chip 13 to connect with the second UART SW chip 14 corresponding to the target expansion chip 15, and control the first UART SW chip 13 to disconnect from the second UART SW chips 14 corresponding to the remaining expansion chips 15, so as to achieve the debugging and upgrading of the target expansion chip 15.

[0045] It can be seen from the above technical solution that the debugging and upgrading system of the expansion chip includes BMC, CPLD, UART SW chip and expansion chip; in order to solve the problems caused by the compact internal space of the server chassis, and the problem that the system software cannot run normally in the initial stage of single-board startup debugging, the BMC is used to control the CPLD to realize the debugging and upgrading of the internal expansion chip of the server. In the specific implementation, the BMC can be connected to the first UARTSW chip; each expansion chip is connected to at least one second UART SW chip; the first UART SW chip is connected to each second UART SW chip. The BMC is connected to the CPLD, and when it is necessary to perform debugging or upgrading operations on a target expansion chip, the BMC can adjust the register information of the CPLD according to the target expansion chip that needs to be debugged and upgraded. The register information of the CPLD can be used to indicate the connection and disconnection between the first UART SW chip and each second UART SW chip. CPLD is connected to the first UART SW chip. CPLD can control the first UART SW chip to be connected to the second UART SW chip corresponding to the target expansion chip according to register information, and control the first UART SW chip to be disconnected from the second UART SW chips corresponding to the remaining expansion chips, so as to realize the debugging and upgrading of the target expansion chip. In this technical scheme, a UART signal is expanded into multiple channels by the first UART SW chip, so as to realize the control of multiple expansion chips. Through the cooperation of BMC and CPLD, the on-off between the first UART SW chip and the second UART SW chip can be controlled. Since each expansion chip is connected with at least one second UART SW chip, the on-off between the first UART SW chip and the expansion chip can be controlled. By controlling the gating of the UART channel by CPLD, remote online debugging and FW burning and upgrading of multiple expansion chips are realized, which solves the problem of frequently plugging and unplugging debugging cables and frequently switching server chassis, and effectively reduces the difficulty of debugging and upgrading work.

[0046] In the embodiment of the present application, in order to save the space occupied by the debugging and upgrading system, the CPLD 12 and the first UART SW chip 13 can be set on the same IO board.

[0047] Each expansion chip 15 can contain multiple SAS Expanders or PCIE Switches, and each SAS Expander or PCIE Switch has two serial debug ports. Therefore, the second UART SW chip 14 requires two output ports to connect to a single SAS Expander or PCIE Switch. However, due to model limitations, the number of output ports corresponding to the second UART SW chip 14 is limited. Therefore, a single second UART SW chip 14 can only connect to a limited number of SAS Expanders or PCIE Switches. If the number of SAS Expanders or PCIE Switches contained in a single expansion chip 15 exceeds the maximum number of connections supported by a single second UART SW chip 14, multiple second UART SW chips 14 can be configured for each expansion chip 15.

[0048] In actual applications, the number of second UART SW chips 14 connected to each expansion chip 15 can be set based on the number of serial debugging ports included in a single expansion chip 15 and the model of the second UART SW chip 14 .

[0049] For example, assuming that the second UART SW chip 14 includes four output ports and a single extension chip 15 includes eight serial debugging ports, then 8 / 4=2 second UART SW chips 14 need to be provided for the single extension chip 15 .

[0050] The first UART SW chip 13 needs to connect to multiple second UART SW chips 14 . Therefore, in practical applications, the number of first UART SW chips 13 can be set based on the number of second UART SW chips 14 and the model of the first UART SW chip 13 .

[0051] For example, assuming that the model of the first UART SW chip 13 includes 4 output ports and the number of the second UART SW chips 14 is 4, then 4 / 4=1 first UART SW chip 13 needs to be provided to achieve connection with all the second UART SW chips 14.

[0052] By calculating the required number of chips based on actual needs, it is possible to ensure smooth connection between the chips in the debugging and upgrading system, and effectively avoid the waste of hardware resources caused by setting too many chips.

[0053] In the embodiment of the present application, a third-party terminal device can remotely debug and upgrade each expansion chip on the server by interacting with the BMC. In addition to supporting remote debugging and upgrading, in a specific implementation, the debugging and upgrading system can also include a PC; the PC is connected to the serial debugging port of each expansion chip 15 to enable local debugging and upgrading of the expansion chip 15.

[0054] In order to avoid conflicts between local debugging and upgrading and remote debugging and upgrading, in an embodiment of the present application, the CPLD 12 can be connected to the enable terminal of the first UART SW chip 13. The CPLD 12 can control the first UART SW chip 13 to be turned off when performing local debugging and upgrading; and control the first UART SW chip 13 to be connected when performing BMC11 debugging and upgrading.

[0055] In a specific implementation, the CPLD 12 may include a register for recording the enable terminal status of the first UART SW chip 13. Different numbers may be used in the register to represent different states of the enable terminal. For example, the number "1" may be used to indicate that the enable terminal is enabled, and the number "0" may be used to indicate that the enable terminal is disabled. The BMC 11 may adjust the value of this register on the CPLD 12.

[0056] When the BMC 11 needs to perform remote debugging and upgrading, the value of the register on the CPLD 12 can be adjusted to “1”. At this time, the first UART SW chip 13 is in an enabled state, and the first UART SW chip 13 can communicate with the second UART SW chip 14 .

[0057] When the BMC 11 receives the notification of local debugging and upgrading, it can adjust the value of the register on the CPLD 12 to “0”. At this time, the first UART SW chip 13 is in a disabled state, and the first UART SW chip 13 is disconnected from all second UARTSW chips 14 .

[0058] In the embodiment of the present application, the enable end of the first UART SW chip 13 is controlled by CPLD12, which solves the problem of coexistence of remote debugging and upgrading of the UART interface and local debugging and upgrading, so that the debugging and upgrading system of the expansion chip provided in the embodiment of the present application can support both remote debugging and upgrading and local debugging and upgrading.

[0059] like Figure 3 The figure shows a schematic diagram of the hardware device connection relationship of a debugging and upgrading system of an expansion chip provided by an embodiment of the present application. Since there are generally multiple SAS Expander or PCIE Switch chips inside the server. Figure 3In the figure, n expansion chips are taken as an example. Each expansion chip includes a SAS Expander or PCIE Switch chip. Therefore, the expansion chip can be called a SAS EXP / PCIE SW Board. Figure 3 Different numerical suffixes are used to distinguish different expansion chips, such as SASEXP / PCIE SW Board0, SAS EXP / PCIE SW Board1, SAS EXP / PCIE SW Board2, and SAS EXP / PCIE SW Boardn.

[0060] The BMC has a limited number of UARTs. Therefore, in the embodiments of this application, a UART is derived from the motherboard's BMC. This UART is expanded into multiple UARTs via a switch chip, namely a UART SW. These multiple UARTs can be connected to multiple SAS Expanders or PCIE Switch chips, thereby enabling the BMC's UART to communicate with multiple expansion chips. A SAS Expander or PCIE Switch chip generally requires connection to two serial debug ports, namely two UART interfaces: a UART port and an SDB port. Figure 3 The example above takes the connection of one expansion chip to one UART SW. In actual applications, if multiple SAS Expander or PCIE Switch chips are located on a single board, each board may require multiple UART Switch chips.

[0061] The UART switch chip must have a strobe pin (S1, S2, and Sn). When one UART channel on the switch is enabled, the BMC establishes a connection with an expansion chip in the server, while simultaneously shutting down other UART communication channels. The switch's enable signal is connected to the CPLD. The BMC can control the switch chip's enable by rewriting the CPLD register value through instructions.

[0062] To address local and remote compatibility issues, during debugging and firmware upgrades on a SAS Expander or PCIE Switch, the SAS Expander or PCIE Switch acts as a UART slave device. When operating remotely, the server's BMC acts as the UART master device; when operating locally, a PC connected to a dedicated UART debug cable acts as the master device. The UART interface cannot automatically communicate with only one master device when multiple masters are communicating with slaves. Consequently, when the serial debug port (Debug port) is connected to a PC via a cable, two masters (BMC and PC) simultaneously communicate with the SAS Expander or PCIE Switch, preventing normal communication. When the PC's UART is connected to the Debug port, the BMC's UART channel must be disabled. Furthermore, when the BMC's UART is communicating with the expansion chip, the dedicated UART debug cable connecting the PC and the Debug port must be unplugged. Therefore, in an embodiment of the present application, the enable (OE) control pin of the UART Switch chip is connected to the CPLD. When the local PC communicates with the expansion chip through a UART dedicated cable, the administrator can input instructions to the BMC to make the BMC adjust the register value of the enable end in the CPLD, control the UART Switch chip to shut down, and close the UART communication channel between the BMC and the expansion chip. In this way, the PC can communicate with the expansion chip normally, thereby realizing local debugging or FW burning and upgrading of the expansion chip.

[0063] The hardware in the server chassis can be set on one mainboard, or multiple mainboards, an IO board in the middle, and n single boards containing one or more SAS Expander or PCIE Switch chips.

[0064] Each SAS Expander or PCIE Switch chip on a SAS EXP / PCIE SW board connects to two debug ports (one UART port and one SDB port). If a SAS EXP / PCIE SW board has n SAS Expanders or PCIE Switch chips, 2n debug ports are required. The debug port on the SAS EXP / PCIE SW board is connected to a PC via a dedicated UART debug cable to implement local UART communication. This allows local debugging of the SAS Expander or PCIE Switch chip and firmware upgrades.

[0065] The UART path from the motherboard's BMC to the SAS Expander or PCIE Switch chip enables remote UART communication, allowing for debugging and firmware upgrades of the SAS Expander or PCIE Switch chip. The remote UART channel extends from the motherboard's BMC through the UART Switch chip on the I / O board to form multiple UART interfaces.

[0066] The UART interfaces extended by the IO board are connected to n SAS EXP / PCIE SW boards respectively. The UART Switch chip on the SAS EXP / PCIE SW board expands one UART channel entering the board into multiple channels.

[0067] The IO board also contains a CPLD. This CPLD is responsible for selecting the UART channels (S0, S1, S2, Sn) of the UARTSwitch chips on the IO board and the SAS EXP / PCIE SW board, as well as enabling and disabling the UART Switch chip (OE). The S0, S1, S2, Sn, and OE signals are connected to the CPLD, which is then connected to the motherboard BMC via I2C. The motherboard BMC rewrites the CPLD register values ​​through instructions, thereby rewriting the S0, S1, S2, Sn, and OE signal register values ​​to select the UART channels and switch between local and remote UART channels. Figure 3 For ease of illustration, all selection signals are represented as S0..Sn. The selection signals S0, S1, S2,...Sn of the UART switch chip on the I / O board are responsible for selecting which SAS EXP / PCIE SW board the BMC's UART is connected to. The selection signals S0, S1, S2,...Sn of the UART switch chip on the SAS EXP / PCIE SW board are responsible for selecting which SAS Expander or PCIE Switch chip the BMC's UART communicates with, and for selecting whether to communicate with the SAS Expander or PCIE Switch chip's UART interface or the SDB interface.

[0068] The OE signal of the UART switch chip solves the problem of simultaneous communication between remote and local UART channels. When the local UART is communicating with the SAS Expander or PCIE Switch chip, the OE signal shuts down the UART switch chip, thereby disconnecting the UART connection between the BMC and the SAS Expander or PCIE Switch chip. When the BMC is communicating remotely with the SAS Expander or PCIE Switch chip, the OE signal enables the UART switch chip, manually unplugging the local UART dedicated debug cable, and disconnecting the local UART channel.

[0069] The present application also provides a debugging and upgrading method for an expansion chip, which is applicable to a debugging and upgrading system including a BMC, a CPLD, a UART SW chip, and an expansion chip. The BMC is connected to the CPLD and a first UART SW chip respectively; each expansion chip is connected to at least one second UART SW chip; and the first UART SW chip is connected to each second UART SW chip. The method includes:

[0070] According to the target expansion chip that needs to be debugged and upgraded, the register information of the CPLD is adjusted so that the CPLD controls the first UART SW chip to connect with the second UART SW chip corresponding to the target expansion chip and controls the first UART SW chip to disconnect with the second UART SW chips corresponding to other expansion chips, thereby achieving the debugging and upgrading of the target expansion chip.

[0071] Optionally, it also includes:

[0072] In the case of local debugging and upgrading, adjusting register information corresponding to the first UART SW chip in the CPLD to a non-enable value so that the CPLD controls the first UART SW chip to shut down; wherein the CPLD is connected to the enable terminal of the first UART SW chip;

[0073] When performing BMC debugging and upgrading, the register information corresponding to the first UART SW chip in the CPLD is adjusted to an enable value, so that the CPLD controls the connection of the first UART SW chip.

[0074] It can be seen from the above technical solution that the debugging and upgrading system of the expansion chip includes BMC, CPLD, UART SW chip and expansion chip; in order to solve the problems caused by the compact internal space of the server chassis, and the problem that the system software cannot run normally in the initial stage of single-board startup debugging, the BMC is used to control the CPLD to realize the debugging and upgrading of the internal expansion chip of the server. In the specific implementation, the BMC can be connected to the first UARTSW chip; each expansion chip is connected to at least one second UART SW chip; the first UART SW chip is connected to each second UART SW chip. The BMC is connected to the CPLD, and when it is necessary to perform debugging or upgrading operations on a target expansion chip, the BMC can adjust the register information of the CPLD according to the target expansion chip that needs to be debugged and upgraded. The register information of the CPLD can be used to indicate the connection and disconnection between the first UART SW chip and each second UART SW chip. CPLD is connected to the first UART SW chip. CPLD can control the first UART SW chip to be connected to the second UART SW chip corresponding to the target expansion chip according to register information, and control the first UART SW chip to be disconnected from the second UART SW chips corresponding to the remaining expansion chips, so as to realize the debugging and upgrading of the target expansion chip. In this technical scheme, a UART signal is expanded into multiple channels by the first UART SW chip, so as to realize the control of multiple expansion chips. Through the cooperation of BMC and CPLD, the on-off between the first UART SW chip and the second UART SW chip can be controlled. Since each expansion chip is connected with at least one second UART SW chip, the on-off between the first UART SW chip and the expansion chip can be controlled. By controlling the gating of the UART channel by CPLD, remote online debugging and FW burning and upgrading of multiple expansion chips are realized, which solves the problem of frequently plugging and unplugging debugging cables and frequently switching server chassis, and effectively reduces the difficulty of debugging and upgrading work.

[0075] The present invention provides a schematic structural diagram of an extension chip debugging and upgrading device, which is applicable to a debugging and upgrading system including a BMC, a CPLD, a UART SW chip, and an extension chip. The BMC is connected to a first UART SW chip; each extension chip is connected to at least one second UART SW chip; the first UART SW chip is connected to each second UART SW chip; and the device includes an adjustment unit.

[0076] The adjustment unit is used to adjust register information of the CPLD according to the target expansion chip that currently needs to be debugged and upgraded, so that the CPLD controls the first UART SW chip to connect with the second UART SW chip corresponding to the target expansion chip and controls the first UART SW chip to disconnect from the second UART SW chips corresponding to other expansion chips based on the register information, so as to achieve debugging and upgrading of the target expansion chip.

[0077] Optionally, the adjustment unit is further used to adjust the register information corresponding to the first UART SW chip in the CPLD to a non-enabled value in the case of local debugging and upgrading, so that the CPLD controls the first UART SW chip to shut down; wherein the CPLD is connected to the enable end of the first UART SW chip; when performing BMC debugging and upgrading, the register information corresponding to the first UART SW chip in the CPLD is adjusted to an enabled value, so that the CPLD controls the first UART SW chip to be connected.

[0078] It can be seen from the above technical solution that the debugging and upgrading system of the expansion chip includes BMC, CPLD, UART SW chip and expansion chip; in order to solve the problems caused by the compact internal space of the server chassis, and the problem that the system software cannot run normally in the initial stage of single-board startup debugging, the BMC is used to control the CPLD to realize the debugging and upgrading of the internal expansion chip of the server. In the specific implementation, the BMC can be connected to the first UARTSW chip; each expansion chip is connected to at least one second UART SW chip; the first UART SW chip is connected to each second UART SW chip. The BMC is connected to the CPLD, and when it is necessary to perform debugging or upgrading operations on a target expansion chip, the BMC can adjust the register information of the CPLD according to the target expansion chip that needs to be debugged and upgraded. The register information of the CPLD can be used to indicate the connection and disconnection between the first UART SW chip and each second UART SW chip. CPLD is connected to the first UART SW chip. CPLD can control the first UART SW chip to be connected to the second UART SW chip corresponding to the target expansion chip according to register information, and control the first UART SW chip to be disconnected from the second UART SW chips corresponding to the remaining expansion chips, so as to realize the debugging and upgrading of the target expansion chip. In this technical scheme, a UART signal is expanded into multiple channels by the first UART SW chip, so as to realize the control of multiple expansion chips. Through the cooperation of BMC and CPLD, the on-off between the first UART SW chip and the second UART SW chip can be controlled. Since each expansion chip is connected with at least one second UART SW chip, the on-off between the first UART SW chip and the expansion chip can be controlled. By controlling the gating of the UART channel by CPLD, remote online debugging and FW burning and upgrading of multiple expansion chips are realized, which solves the problem of frequently plugging and unplugging debugging cables and frequently switching server chassis, and effectively reduces the difficulty of debugging and upgrading work.

[0079] The above describes in detail the debugging and upgrading system, method, and device for an expansion chip provided by the embodiments of the present application. The various embodiments are described in a progressive manner in this specification, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between the various embodiments can be referenced to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For relevant parts, refer to the method description.

[0080] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0081] The above is a detailed introduction to the debugging and upgrading system, method and device for an expansion chip provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A debugging and upgrading system for an expansion chip, characterized in that: The system comprises a BMC, a CPLD, a UART SW chip and an expansion chip; wherein the BMC is connected to a first UART SW chip; each expansion chip is connected to at least one second UART SW chip; the first UART SW chip is connected to each of the second UART SW chips; The BMC is connected to the CPLD and is used to adjust the register information of the CPLD according to the target expansion chip that needs to be debugged and upgraded currently; The CPLD is connected to the first UART SW chip and is used to control the first UART SW chip to be connected to the second UART SW chip corresponding to the target extension chip and to control the first UART SW chip to be disconnected from the second UART SW chips corresponding to the remaining extension chips according to the register information, so as to realize debugging and upgrading of the target extension chip; The number of second UART SW chips connected to each expansion chip is set based on the number of serial debug ports included in the single expansion chip and the model of the second UART SW chip; The number of the first UART SW chips is set based on the number of the second UART SW chips and the model of the first UART SW chip; The CPLD includes registers for recording the status of each output port of the first UART SW chip; the first UART SW chip includes multiple output ports, and each output port is connected to a second UART SW chip.

2. The debugging and upgrading system of the expansion chip according to claim 1, characterized in that: The CPLD and the first UART SW chip are arranged on the same IO board.

3. The debugging and upgrading system of the expansion chip according to claim 1, characterized in that: Also includes PC; The PC is connected to the serial debugging port of each expansion chip respectively to realize local debugging and upgrading of the expansion chip.

4. The debugging and upgrading system of the expansion chip according to claim 3, characterized in that: The CPLD is connected to the enable terminal of the first UART SW chip, and is used to control the first UART SW chip to be turned off when performing local debugging and upgrading; and to control the first UART SW chip to be connected when performing BMC debugging and upgrading.

5. A debugging and upgrading method for an expansion chip, characterized in that: The invention is applicable to a debugging and upgrading system including a BMC, a CPLD, a UART SW chip, and an expansion chip; wherein the BMC is connected to the CPLD and the first UART SW chip respectively; each expansion chip is connected to at least one second UART SW chip; the first UART SW chip is connected to each of the second UART SW chips; and the method comprises: Adjusting register information of the CPLD according to the target expansion chip currently requiring debugging and upgrading, so that the CPLD controls the first UART SW chip to connect with the second UART SW chip corresponding to the target expansion chip and controls the first UART SW chip to disconnect from the second UART SW chips corresponding to the remaining expansion chips, thereby achieving debugging and upgrading of the target expansion chip; The number of second UART SW chips connected to each expansion chip is based on the number of serial debug ports included in a single expansion chip and the model of the second UART SW chip; the number of first UART SW chips is based on the number of second UART SW chips and the model of the first UART SW chip; the CPLD includes registers for recording the status of each output port of the first UART SW chip; the first UART SW chip includes multiple output ports, each of which is connected to a second UART SW chip.

6. The debugging and upgrading method of the expansion chip according to claim 5, characterized in that: Also includes: In the case of local debugging and upgrading, adjusting register information corresponding to the first UART SW chip in the CPLD to a non-enable value so that the CPLD controls the first UART SW chip to shut down; wherein the CPLD is connected to the enable terminal of the first UART SW chip; When performing BMC debugging and upgrading, the register information corresponding to the first UART SW chip in the CPLD is adjusted to an enable value, so that the CPLD controls the first UART SW chip to be connected.

7. A debugging and upgrading device for an expansion chip, characterized in that: Applicable to a debugging and upgrading system including a BMC, a CPLD, a UART SW chip, and an expansion chip; wherein the BMC is connected to a first UART SW chip; each expansion chip is connected to at least one second UART SW chip; the first UART SW chip is connected to each of the second UART SW chips; the device includes an adjustment unit; The adjusting unit is configured to adjust register information of the CPLD according to a target expansion chip currently required for debugging and upgrading, so that the CPLD controls the first UART SW chip to be connected to the second UART SW chip corresponding to the target expansion chip, and controls the first UART SW chip to be disconnected from the second UART SW chips corresponding to the remaining expansion chips, so as to implement debugging and upgrading of the target expansion chip; The number of second UART SW chips connected to each expansion chip is based on the number of serial debug ports included in a single expansion chip and the model of the second UART SW chip; the number of first UART SW chips is based on the number of second UART SW chips and the model of the first UART SW chip; the CPLD includes registers for recording the status of each output port of the first UART SW chip; the first UART SW chip includes multiple output ports, each of which is connected to a second UART SW chip.

8. The debugging and upgrading device for the expansion chip according to claim 7, characterized in that: The adjustment unit is further configured to adjust, in the case of local debugging and upgrading, register information corresponding to the first UART SW chip in the CPLD to a non-enabled value, so that the CPLD controls the first UART SW chip to shut down; wherein the CPLD is connected to the enable terminal of the first UART SW chip; and when performing BMC debugging and upgrading, the register information corresponding to the first UART SW chip in the CPLD is adjusted to an enabled value, so that the CPLD controls the first UART SW chip to connect.

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