A method for realizing airtightness leak detection compatible with single channel and multi-channel

Abstract

The present invention discloses a method for realizing airtightness leak detection compatible with single channel and multi-channel, belonging to the field of airtightness leak detection technology, and comprising the following steps: S1: channel thread creation; S2: multi-thread time base sharing; S3: issuing access and control permissions. The present invention adopts a flexible and configurable technical solution of multi-thread calling the same task function, time base sharing, access and control permissions, which is compatible with the use requirements of single channel and multi-channel, greatly enhances the scalability and maintainability, improves the equipment utilization rate, meets the needs of rapid detection, and is worthy of being promoted and used.

Description

Technical Field

[0001] The present invention relates to the technical field of airtightness leak detection, and in particular to an airtightness leak detection implementation method that is compatible with single-channel and multi-channel. Background Art

[0002] In many fields, leak detection is needed to ensure quality, such as various products in industrial production, such as pipes, air conditioners, etc. Different application objects use different methods. Airtightness leak detection is one of the leak detection methods, and the commonly used airtightness leak detectors are mostly single-channel airtightness leak detectors. Existing single-channel airtightness leak detectors have the problems of single function and low detection efficiency. Therefore, a method for implementing airtightness leak detection that is compatible with single-channel and multi-channel is proposed. Summary of the invention

[0003] The technical problem to be solved by the present invention is: how to solve the problems of single function and low detection efficiency of existing single-channel airtightness leak detectors, and provide an airtightness leak detection implementation method that is compatible with single-channel and multi-channel. The method realizes the function of one detection device being able to detect multiple products at the same time, greatly improves the equipment utilization rate, and meets the needs of rapid detection.

[0004] The present invention solves the above technical problems through the following technical solutions, and the present invention comprises the following steps:

[0005] S1: Channel thread creation

[0006] Create multiple threads, each thread calls the same task function and has independent memory resources, and completes the creation of all threads with the same number of channels;

[0007] S2: Multi-threaded time base sharing

[0008] Multiple threads share a time base. When the time base reaches the overflow moment of the thread's execution beat, an overflow event message is sent to the corresponding thread.

[0009] S3: Delegating access and control permissions

[0010] Combined with the communication protocol, the host computer issues threads access and control permissions to each hardware resource.

[0011] Furthermore, in step S1, the channel is a test loop, and multi-channel means that there are multiple test loops at the same time. Different channels are independent of each other, and the task logic is the same. The test process of executing the channel is based on a process. A process is a combination of a group of beats. Each beat of the process controls the corresponding hardware resource state according to the operation code, and the operation code uses binary bits to represent the attributes of each hardware resource state.

[0012] Furthermore, in step S1, the channel and the thread satisfy a one-to-one or many-to-one relationship, and each thread calls the same task function and passes different element handles of the same structure array, so that each thread has the same algorithm logic and independent memory resources.

[0013] Furthermore, the core task of the thread is to update the running time of the process and control the hardware resource status of each beat in the execution process in turn.

[0014] Furthermore, the specific process of step S1 is as follows:

[0015] S11: Get the memory address of the process running time and assign it to the pointer member corresponding to the structure array element;

[0016] S12: Create a thread and pass the handle of the structure array element to the task function parameter;

[0017] S13: The array index points to the next element in the structure array until all threads with the same number of channels are created.

[0018] Furthermore, in the step S12, the structure array elements are independent memory resources and are static arrays inside the module. The members of the static array include the beat sequence number currently being executed, the number of beats in the beat queue, the timing instance handle, the process running time pointer, the beat control table, the thread ID and the permission mask. The beat control table is the beat control parameter of this process and is a structure array whose members include the beat duration and the hardware resource control operation code.

[0019] Furthermore, in step S2, the time reference is implemented by combining a hardware timer and a timing counter, the interruption period of the hardware timer is set to 1MS, and each time an interruption occurs, the timing counter is incremented by 1, indicating that the timing is 1MS.

[0020] Furthermore, the specific execution process of the hardware timer interrupt processing function is as follows:

[0021] S21: the timing counter is incremented by 1 to determine whether all timing instances have been traversed, if yes, the process ends, otherwise, the process proceeds to step S22;

[0022] S22: Determine whether the current timed instance is active, if yes, proceed to step S23, otherwise proceed to step S21;

[0023] S23: Determine whether the overflow time of the timing counter is equal to the overflow time of the timing instance. If yes, set the current timing instance to an inactive state, execute the callback function of the current timing instance, and then enter step S21; otherwise, directly enter step S21.

[0024] Furthermore, the timing instance represents a software timer applied for by a thread, which is used to complete timing tasks during the execution process. The structure array instantiates multiple software timers, whose element members include overflow time, active status flag, thread ID and callback function pointer.

[0025] Furthermore, in the step S3, the host computer sends the beat control parameters one by one, and the corresponding command packet payload includes an operation code, a beat duration, a channel number, and a permission mask, wherein the channel number specifies the target channel to which the command parameters are sent. When the last beat is received, the process running flag is set, and the process starts to execute the beats in sequence; before each process running parameter is sent, the current beat sequence number needs to be cleared in order to recount the number of beats executed by the current process.

[0026] Compared with the prior art, the present invention has the following advantages: the airtightness leak detection implementation method that is compatible with single-channel and multi-channel uses a flexible and configurable technical solution of multi-threaded calling of the same task function, time base sharing, access and control permissions, and is compatible with the use requirements of single-channel and multi-channel, greatly enhances scalability and maintainability, improves equipment utilization, meets the needs of rapid detection, and is worthy of popularization and use. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of the process of channel thread creation in an embodiment of the present invention;

[0028] Figure 2 is a flow chart of a timing interrupt processing function in an embodiment of the present invention;

[0029] Figure 3 It is a schematic diagram of the thread task function control flow in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following is a detailed description of an embodiment of the present invention. This embodiment is implemented on the premise of the technical solution of the present invention, and a detailed implementation method and a specific operation process are given, but the protection scope of the present invention is not limited to the following embodiment.

[0031] This embodiment provides a technical solution: a method for implementing airtightness leak detection that is compatible with single-channel and multi-channel. This solution is designed to implement the function that a leak detection device can detect multiple products at the same time. A channel is a test loop, and a multi-channel means that multiple test loops are provided at the same time. Different channels (test loops) are independent of each other, but the task logic is the same. The test process of executing the channel is based on a process, and a process is a combination of a group of beats. That is, each test process includes multiple processes, and each process includes multiple beats arranged in the order of execution.

[0032] The core task of a thread is to update the elapsed time of the process and set the hardware resource status control for each beat in the process in turn, but the premise is that the thread has control rights over its hardware resources. Setting access and control rights is to avoid control conflicts between different threads over the same hardware resources.

[0033] Channels and threads satisfy a one-to-one or many-to-one relationship. Each thread calls the same task function and passes different element handles of the same structure array, so that each thread has the same algorithm logic and independent memory resources.

[0034] The thread creation process is as follows Figure 1 As shown, it specifically includes: taking the memory address of the process running time and assigning it to the pointer member corresponding to the structure array element; creating a thread and passing the handle of the structure array element to the task function parameter; the array index points to the next element in the structure array until all threads with the same number of channels are created. The structure array element is the independent memory resource mentioned above, and it is a static array inside the module. The members of the static array include the beat number currently being executed, the number of beats in the beat queue, the timed instance handle, the process running time pointer, the beat control table, the thread ID and the permission mask and related flags. The beat control table is the beat control parameter of this process. It is a structure array, and its members include the beat duration, hardware resource control operation code, etc. Figure 1 The process running time is an external variable of the module, and pointers are used to read and write it inside the task function.

[0035] Multithreaded shared time base technology means that all threads share the same time base, which is implemented by combining hardware timer and timing counter. The interrupt period of hardware timer is set to 1MS. Each time the interrupt is entered, the timing counter is increased by 1, indicating 1MS timing. The flowchart of hardware timer interrupt processing function is as follows: Figure 2 shown. Figure 2 The timing instance in represents the software timer applied by the thread, which mainly completes the timing task in the execution process of the test process. The present invention is designed to use a structure array to instantiate multiple software timers, and its element members include overflow time, active state flag, thread ID and callback function pointer. The thread to which the timing instance belongs sets the overflow time to it, and sets the current state to the active state. When the time base reaches the overflow time, the state is set to the inactive state, indicating that the timing task has been completed. When applying for a timing instance, the thread saves its ID to the thread ID member to which it belongs, and sets the processing function pointed to by the callback function pointer. When the overflow time is reached, the processing function sends an overflow event to the thread corresponding to the thread ID member of the instance.

[0036] The thread task function control flow in this embodiment is as follows Figure 3As shown, the design applies for two timing instances, namely A and B. Instance B is used to record the process running time, and instance A is used for the running control of the beat. The return handle when applying for the timing instance is saved in the corresponding member of the structure array element pointed to by the function parameter. Similarly, Figure 3 The beat sequence number, beat control parameters, permission mask, etc. in the process, where the beat sequence number is the sequence number of the currently executed beat. Combined with the number of beats to be executed issued by the host computer, it can be judged whether the execution is completed; the beat control table is the beat control parameter of this process, which is a structure array, and its members include beat duration, hardware resource control operation code, etc.; permission mask: binary bits are used to represent the thread's control or access rights to each hardware resource. Threads can monitor one or multiple channels at the same time, realizing single-channel and multi-channel compatibility design. For a single channel, its thread has access or control rights to all hardware resources. For multiple channels, its thread can only access or control hardware resources that it has permission to. Each beat of the process controls the corresponding hardware resource status according to the operation code, and the operation code uses binary bits to represent the attributes of each hardware resource status.

[0037] The host computer sends the beat control parameters one by one. The corresponding command packet payload includes the operation code, beat duration, channel number, and permission mask. The channel number specifies the target channel for sending the command parameters. When the last beat is received, the process running flag is set, and the process starts to execute the beats in sequence. It should be noted that before sending the process running parameters each time, the current beat sequence number needs to be cleared to recount the number of beats executed by the current process.

[0038] To sum up, the above-mentioned embodiment is a method for implementing airtight leak detection that is compatible with single-channel and multi-channel, and adopts a flexible and configurable technical solution of multi-threaded calls to the same task function, time base sharing, access and control permissions. It is compatible with the use requirements of single-channel and multi-channel, greatly enhances scalability and maintainability, improves equipment utilization, meets the needs of rapid detection, and is worthy of promotion and use.

[0039] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A method for realizing airtightness leak detection compatible with single channel and multi-channel, characterized in that: The following steps are involved: S1: Channel thread creation Create multiple threads, each thread calls the same task function and has independent memory resources, and completes the creation of all threads with the same number of channels; In S1, a channel is a test loop, and a multi-channel means that multiple test loops are provided at the same time. Different channels are independent of each other, and have the same task logic. The test process of executing a channel is based on a flow. A flow is a combination of a group of beats. Each beat of the flow controls the corresponding hardware resource state according to an operation code. The operation code uses binary bits to represent the attributes of each hardware resource state. In S1, channels and threads satisfy a one-to-one or many-to-one relationship. Each thread calls the same task function and passes different element handles of the same structure array, so that each thread has the same algorithm logic and independent memory resources. The core task of the thread is to update the running time of this process and control the hardware resource status of each beat in the execution process in sequence. The specific process of S1 is as follows: S11: Get the memory address of the process running time and assign it to the pointer member corresponding to the structure array element; S12: Create a thread and pass the handle of the structure array element to the task function parameter; S13: The array index points to the next element in the structure array until all threads with the same number of channels are created; In the S12, the structure array element is an independent memory resource and is a static array inside the module. The members of the static array include the beat sequence number currently being executed, the number of beats in the beat queue, the timed instance handle, the process running time pointer, the beat control table, the thread ID and the permission mask. The beat control table is the beat control parameter of this process, which is a structure array, and its members include the beat duration and the hardware resource control operation code; S2: Multi-threaded time base sharing Multiple threads share a time base. When the time base reaches the overflow moment of the thread's execution beat, an overflow event message is sent to the corresponding thread. S3: Delegating access and control permissions Combined with the communication protocol, the host computer issues threads access and control permissions to each hardware resource.

2. The method for realizing airtightness leak detection compatible with single channel and multi-channel according to claim 1, characterized in that: In S2, the time reference is implemented by combining a hardware timer and a timing counter. The interruption period set by the hardware timer is 1MS. Each time an interruption occurs, the timing counter is incremented by 1, indicating that the timing is 1MS.

3. The method for realizing airtightness leak detection compatible with single channel and multi-channel according to claim 2, characterized in that: The specific execution process of the hardware timer interrupt processing function is as follows: S21: The timing counter is incremented by 1 to determine whether all timing instances have been traversed. If yes, the process ends; otherwise, the process proceeds to S22; S22: Determine whether the current timed instance is active, if yes, go to S23, otherwise go to S21; S23: Determine whether the overflow time of the timing counter is equal to the overflow time of the timing instance. If yes, set the current timing instance to an inactive state, execute the callback function of the current timing instance, and then enter S21. Otherwise, directly enter S21.

4. The method for realizing airtightness leak detection compatible with single channel and multi-channel according to claim 3, characterized in that: The timing instance represents a software timer applied for by a thread, which is used to complete the timing task during the execution process. The structure array instantiates multiple software timers, and its element members include overflow time, active status flag, thread ID and callback function pointer.

5. The method for realizing airtightness leak detection compatible with single channel and multi-channel according to claim 4, characterized in that: In S3, the host computer sends the beat control parameters one by one, and the corresponding command packet payload includes an operation code, a beat duration, a channel number, and a permission mask, wherein the channel number specifies the target channel to which the command parameters are sent. When the last beat is received, the process running flag is set, and the process starts to execute the beats in sequence; Before sending the process running parameters each time, the current beat sequence number needs to be cleared to recount the number of beats executed by the current process.

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