Heterogeneous multi-core processor data communication method, device, equipment and medium

Abstract

The present invention relates to the field of data processing, and discloses a heterogeneous multi-core processor data communication method, device, equipment and medium, wherein the method comprises: a first processor sets a message indication state and a request message in a shared storage area according to a request content, and the message indication state and the request message are associated with each other; a second processor obtains the request message according to the message indication state, and generates a processing result of the request message; the second processor updates the message indication state and the request message according to the processing result; the first processor obtains the updated request message according to the updated message indication state to obtain the processing result. The present invention can improve the ease of use and adjustability of multi-core processor data communication, solve the problem of poor scalability, and greatly improve the efficiency of data communication.

Description

Technical Field

[0001] The present invention relates to the field of data processing, and in particular to a data communication method, device, equipment and medium for heterogeneous multi-core processors. Background Art

[0002] In order to better process highly complex visual data, multiple processors are often equipped to complete different types of tasks. General-purpose processors, such as ARM (Advanced RISC Machine, an advanced computing chip based on a reduced instruction set) and CK810 (a high-performance embedded processor model), can be used to complete general control and scheduling tasks; dedicated processors, such as DSP (Digital Signal Processor) and NNP (Neural Network Processor), can be used to complete dedicated computing acceleration tasks.

[0003] Heterogeneous multi-core processor systems pose many challenges to software design. Among them, general-purpose processors have more peripheral resources and are easy to use. Special-purpose processors are often specially designed, with limited resources and troublesome debugging. Different processors have their own running contexts and generally cannot directly perform synchronous function calls. Processors generally exchange data through shared memory and interrupts. For example, a general-purpose processor copies data to a planned shared memory and notifies a special-purpose processor through an interrupt. After receiving the interrupt, the special-purpose processor copies the data from the shared memory to its own running memory for processing. In addition, software is often designed in layers, and each layer may need to define multiple interfaces. There is a lack of unified interfaces, and the efficiency of data transmission between layers is relatively low, and the scalability is relatively poor. Summary of the invention

[0004] Based on this, it is necessary to provide a heterogeneous multi-core processor data communication method, device, computer equipment and storage medium to address the above technical problems, so as to solve the low communication efficiency and poor scalability of heterogeneous multi-core processors.

[0005] A heterogeneous multi-core processor data communication method, comprising:

[0006] The first processor sets a message indication state and a request message in a shared storage area according to the request content, wherein the message indication state is associated with the request message;

[0007] The second processor obtains the request message according to the message indication status and generates a processing result of the request message;

[0008] The second processor updates the message indication status and the request message according to the processing result;

[0009] The first processor obtains the updated request message according to the updated message indication status to obtain the processing result.

[0010] Optionally, the shared storage area includes an event register and an event memory, the event register is used to store the message indication state, and the event memory is used to store the request message;

[0011] The first processor sets a message indication state and a request message in a shared storage area according to the request content, wherein the message indication state is associated with the request message, including:

[0012] The first processor sets the state of the specified bit address in the event register to 1 according to the request content, and writes request information to the memory block corresponding to the specified bit address in the event memory according to the request content; the message indication state includes the state of the specified bit address.

[0013] Optionally, the request message includes a message header and a message body, and the memory block used to store the message body includes a first field address and a second field address;

[0014] The step of writing the request content into a memory block corresponding to the designated bit address in the event memory includes:

[0015] The request content is written into a memory unit corresponding to the first field address.

[0016] Optionally, the second processor obtains the request message according to the message indication status, and generates a processing result of the request message, including:

[0017] When the second processor detects that the state of the designated bit address in the event register is set to 1, acquiring the request message from the event memory;

[0018] The second processor processes the request message and generates a processing result.

[0019] Optionally, the second processor updates the message indication status and the request message according to the processing result, including:

[0020] The second processor sets the state of the designated bit address in the event register to 0, and writes the processing result into a memory unit corresponding to the second field address.

[0021] Optionally, the first processor obtains the updated request message according to the updated message indication state to obtain the processing result, including:

[0022] When the first processor detects that the state of the designated bit address in the event register is set to 0, an updated request message is obtained according to the updated message indication state; and the processing result is obtained from the updated request message.

[0023] Optionally, the shared storage area includes a read pointer register, a write pointer register and a queue memory, the message indication state is a read pointer or a write pointer, the read pointer is stored in the read pointer register, the write pointer is stored in the write pointer register, and the request message is stored in the queue memory;

[0024] The first processor sets a message indication state and a request message in a shared storage area according to the request content, wherein the message indication state is associated with the request message, including:

[0025] The first processor writes the request message in a memory block corresponding to the address pointed to by the write pointer according to the request content, and updates the write pointer. The queue memory includes the memory unit.

[0026] Optionally, the request message includes a message header and a message body, and the message body includes a first field address and a second field address;

[0027] The first processor writes the request message in a memory block corresponding to the address pointed to by the write pointer according to the request content, including:

[0028] The request message is written into a memory unit corresponding to the first field address according to the request content.

[0029] Optionally, the address pointed to by the read pointer is the same as the address pointed to by the write pointer before updating;

[0030] The second processor obtains the request message according to the message indication status, and generates a processing result of the request message, including:

[0031] The second processor obtains the request message according to the read pointer, processes the request message, generates a processing result, and updates the address pointed to by the read pointer to the updated address pointed to by the write pointer.

[0032] Optionally, the address pointed to by the updated write pointer includes the second field address;

[0033] The second processor updates the message indication status and the request message according to the processing result, including:

[0034] The second processor writes the processing result into the memory block corresponding to the second field address and updates the write pointer.

[0035] Optionally, the first processor obtains the updated request message according to the updated message indication state to obtain the processing result, including:

[0036] The first processor obtains the processing result from the address pointed to by the updated read pointer, and updates the read pointer.

[0037] Optionally, the first processor is provided with a first upper-layer service module, a first registration service module and a first inter-core communication module; and the heterogeneous multi-core processor data communication method includes:

[0038] The first upper-layer service module obtains the request content and the memory space of the request content;

[0039] The first registration service module obtains the request content and the memory space of the request content from the first upper-layer business module, and configures a setting instruction for setting the message indication state and the request message according to the request content and the memory space of the request content;

[0040] The first inter-core communication module obtains the setting instruction from the first registration service module, and sends the setting instruction to the shared storage area, so as to set a message indication state and a request message in the shared storage area according to the setting instruction.

[0041] Optionally, the second processor is provided with a second upper layer service module, a second registration service module and a second inter-core communication module; and the heterogeneous multi-core processor data communication method includes:

[0042] The second inter-core communication module obtains the request message from the shared storage area;

[0043] The second registration service module obtains the request message from the second inter-core communication module, parses the request message, and obtains the request content;

[0044] The second upper-layer business module obtains the request content from the second registration service module, processes the request content according to a preset processing rule, and generates the processing result.

[0045] A heterogeneous multi-core processor data communication device comprises a first processor, a second processor and a shared storage area;

[0046] The first processor is used to set a message indication state and a request message in the shared storage area according to the request content, and the message indication state is associated with the request message;

[0047] The second processor is used to obtain the request message according to the message indication status, and generate a processing result of the request message;

[0048] The second processor is further used to update the message indication status and the request message according to the processing result;

[0049] The first processor is further configured to obtain an updated request message according to an updated message indication status to obtain the processing result.

[0050] A computer device comprises a memory, a processor and computer-readable instructions stored in the memory and executable on the processor, wherein the processor implements the above-mentioned heterogeneous multi-core processor data communication method when executing the computer-readable instructions.

[0051] One or more readable storage media storing computer-readable instructions, wherein when the computer-readable instructions are executed by at least two processors, the at least two processors execute the heterogeneous multi-core processor data communication method as described above.

[0052] The heterogeneous multi-core processor data communication method, device, computer equipment and storage medium provided by the present invention, the first processor sets the message indication state and the request message in the shared storage area according to the request content, and the message indication state is associated with the request message to write the request content into the shared storage area. The second processor obtains the request message according to the message indication state and generates the processing result of the request message. Here, the second processor obtains the request content from the shared storage area and generates the processing result, which can improve the processing efficiency of the request content. The second processor updates the message indication state and the request message according to the processing result to write the processing result into the shared storage area. The first processor obtains the updated request message according to the updated message indication state to obtain the processing result. Here, the first processor obtains the processing result (or the storage address of the processing result) from the shared storage area, which can reduce the consumption of computing resources of the first processor and improve the overall processing efficiency of the heterogeneous multi-core processor. By setting the message indication status and request message in the shared storage area, the first processor and the second processor can share computing resources and file resources, thereby improving the usability and adjustability of data communication between multi-core processors; the data communication method between heterogeneous processors is defined and unified (i.e., 1. the first processor sets the message indication status and request message in the shared storage area according to the request content, 2. the second processor obtains the request message according to the message indication status; 3. the second processor updates the message indication status and the request message according to the processing result; 4. the first processor obtains the updated request message according to the updated message indication status to obtain the processing result), and the underlying module does not need to be modified when expanding the function, thereby solving the problem of poor scalability; the request message transmitted in the shared storage area only transmits the address, thereby reducing the copying of data and greatly improving the efficiency of data communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0054] Figure 1 It is a flow chart of a heterogeneous multi-core processor data communication method according to an embodiment of the present invention;

[0055] Figure 2 is a schematic diagram of data communication between a first processor and a second processor in a synchronization event in an embodiment of the present invention;

[0056] Figure 3is a schematic diagram of data communication between a first processor and a second processor in a circular queue in one embodiment of the present invention;

[0057] Figure 4 is a schematic diagram of the architecture of a first processor and a second processor in one embodiment of the present invention;

[0058] Figure 5 It is a structural schematic diagram of a heterogeneous multi-core processor data communication device in one embodiment of the present invention;

[0059] Figure 6 is a schematic diagram of a computer device in one embodiment of the present invention. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0061] In one embodiment, if Figure 1 As shown, a heterogeneous multi-core processor data communication method is provided, comprising the following steps:

[0062] S10. The first processor sets a message indication state and a request message in a shared storage area according to the request content, wherein the message indication state is associated with the request message.

[0063] Understandably, a heterogeneous multi-core processor includes multiple processors. These processors use more than one architecture. The architecture of the processor can be set according to actual needs. In some examples, the first processor can be a general-purpose processor, such as CK810 (a general-purpose processor designed based on ARM architecture); the second processor can be a dedicated processor, such as a DSP chip (a chip that can implement digital signal processing technology). In other examples, the first processor can be a dedicated processor and the second processor can be a general-purpose processor.

[0064] It should be noted that the first processor refers to the data requester (or initiator), while the second processor refers to the data processor (or receiver). The request content depends on the actual situation, such as the storage address of the data to be processed. The data to be processed can be image data or other types of data. The shared storage area can be a cache in the processor or a memory connected to a heterogeneous multi-core processor.

[0065] In a heterogeneous multi-core processor, there are several communication modes between the processors, such as synchronous events (event), circular queues (queue), etc. Different communication modes generally have different corresponding message indication states. The request message (Msg) includes a message header (MsgHeader) and a message body (MsgCore). The message body includes a first address field (req) for recording the request content and a second address field (cnf) for recording the processing result. The storage address of the first address field is the first field address, and the storage address of the second address field is the second field address. The first field address refers to the physical address used to store the request content. The second field address refers to the physical address used to store the processing result.

[0066] There is an association between the request message and the message indication status. The association between the request message and the message indication status varies in different communication modes. In some examples, for synchronization events, the message indication status refers to the bit address (bit) of the event register. For example, if the state of the bit address is 1, it means that an event has occurred and the second processor is required to process the request message corresponding to the event; if the state of the bit address is 0, it means that the event processing is completed and the first processor can obtain the processing result from the request message. The message indication status in the circular queue refers to the write pointer (QueueWR) or the read pointer (QueueRD). The write pointer is used to indicate the write address of the request message. The read pointer is used to indicate the read address of the request message.

[0067] S20. The second processor obtains the request message according to the message indication status and generates a processing result of the request message.

[0068] Understandably, after the first processor sets the message indication state and the request message in the shared storage area according to the request content, the second processor can obtain the request message according to the message indication state and generate a processing result of the request message. Specifically, the second processor can obtain the request message from the shared storage area according to the message indication state, then read out the request content in the request message, and then process the request content to generate a processing result.

[0069] S30. The second processor updates the message indication status and the request message according to the processing result.

[0070] Understandably, after the second processor obtains the request message according to the message indication state and generates the processing result of the request message, the second processor can update the message indication state and the request message according to the processing result. Specifically, different communication modes have different ways of updating the message indication state. For example, for synchronous events, after obtaining the processing result, it is necessary to set the bit address of the event register to 0, and write the processing result (or the storage address of the processing result) to the request message. For a circular queue, the request message is read according to the read pointer, and the read pointer is updated at the same time; the request content or the processing result is written according to the write pointer, and the write pointer is updated at the same time.

[0071] S40. The first processor obtains the updated request message according to the updated message indication status to obtain the processing result.

[0072] Understandably, after the second processor updates the message indication status and the request message according to the processing result, the first processor can obtain the updated request message according to the updated message indication status to obtain the processing result according to the request information. Specifically, for synchronous events, the first processor obtains the processing result (or the storage address of the processing result) from the request message after learning that the bit address of the event register is 0. For a circular queue, the processing result (or the storage address of the processing result) is obtained from the request message according to the address indicated by the updated read pointer.

[0073] In steps S10-S40, the first processor sets a message indication state and a request message in a shared storage area according to the request content, and the message indication state is associated with the request message to write the request content into the shared storage area. The second processor obtains the request message according to the message indication state and generates a processing result of the request message. Here, the second processor obtains the request content from the shared storage area and generates a processing result, which can improve the processing efficiency of the request content. The second processor updates the message indication state and the request message according to the processing result to write the processing result into the shared storage area. The first processor obtains the updated request message according to the updated message indication state to obtain the processing result. Here, the first processor obtains the processing result (or the storage address of the processing result) from the shared storage area, which can reduce the consumption of computing resources of the first processor and improve the overall processing efficiency of the heterogeneous multi-core processor. The heterogeneous multi-core processor data communication method provided in the embodiment of the present invention can realize the sharing of computing resources and file resources between different processors, thereby improving the usability and adjustability of multi-core processor data communication; it defines and unifies the data communication mode between heterogeneous processors, and there is no need to change the underlying module when expanding functions, thereby solving the problem of poor scalability; the request message only transmits the address, reducing the copying of data, and greatly improving the efficiency of data communication.

[0074] Optionally, the shared storage area includes an event register and an event memory, the event register is used to store the message indication state, and the event memory is used to store the request message;

[0075] Step S10, i.e., the first processor sets a message indication state and a request message in a shared storage area according to the request content, wherein the message indication state is associated with the request message, includes:

[0076] S101. The first processor sets the state of the designated bit address in the event register to 1 according to the request content, and writes the request information into the memory block corresponding to the designated bit address in the event memory according to the request content; the message indication state includes the state of the designated bit address.

[0077] Understandably, the shared storage area includes an event register (EventFLAG) and an event memory (EventRAM), and the event register is used to store the message indication status. The event register is provided with a number of specified bit addresses, and each specified bit address can store the request indication status of a request message. The event memory can be divided into the same number of memory blocks according to the number of bit addresses of the event register. The specified bit address corresponds to the memory block one by one. In some examples, the shared storage area may be provided with N groups of event registers and event memories. The value of N may be 2. The size of the event register may be 32 bits (bit), which can be used to indicate an event. The size of the event memory may be 128 bytes (Bytes), which is used to store the event message pointer (i.e., the request message).

[0078] This embodiment belongs to a synchronous event, runs in a serial manner, takes a long time, and has low efficiency. It is suitable for occasions with low efficiency requirements, such as reset message sending, debugging information reading, etc.

[0079] Specifically, in one example, Figure 2 As shown, the first processor can set the bit address (Eventi) in the event register to 1 according to the request content, and write the request content (which can be a physical address) into the event memory (SRAM) corresponding to Eventi. The event memory corresponding to Eventi is used to store the request message ( Figure 2 , represented as request message [0] and request message [i]).

[0080] In this embodiment, the physical address of the request content is stored in the request message. The request message only transmits the address, which reduces data copying and greatly improves the efficiency of data communication.

[0081] Optionally, the request message includes a message header and a message body, and the memory block used to store the message body includes a first field address and a second field address;

[0082] Step S101, i.e., writing the request information into the memory block corresponding to the designated bit address in the event memory according to the request content, comprises:

[0083] S1011. Write the request content into a memory unit corresponding to the first field address.

[0084] Understandably, the request message includes a message header and a message body. The message header is used to record the information of the first processor (initiator) calling the second processor (receiver), such as the callback function address, user data address, occupied semaphore address and other auxiliary information used to complete the communication. The message body includes a first address field (represented by Req) and a second address field (represented by Cnf). The message body is stored in a memory block. The first address field is stored in the first field address in the memory block, and the second address field is stored in the second field address in the memory block.

[0085] Here, writing the request content into the memory block corresponding to the specified bit address in the event memory is essentially writing the request message (which can be a physical address) into the memory unit corresponding to the first field address. The memory block is divided into several memory units. In some cases, in order to ensure the integrity of the data in the specified bit address and event memory when they are modified, a mutex lock can be set to protect the specified bit address and event memory. The mutex lock can ensure that only one thread can access the data in the specified bit address and event memory at any time.

[0086] After writing the request content into the first field address, the first processor needs to wait for the bit address in the event register to change.

[0087] In this embodiment, by writing the request content (or the address of the request content) into the memory unit corresponding to the first field address, the request content can be transmitted and the copying of data can be reduced.

[0088] Optionally, step S20, that is, the second processor obtains the request message according to the message indication status and generates a processing result of the request message, includes:

[0089] S201, when the second processor detects that the state of the designated bit address in the event register is set to 1, obtaining the request message from the event memory;

[0090] S202: The second processor processes the request message and generates a processing result.

[0091] Understandably, the second processor can query the state of the specified bit address in the event register through its inter-core communication interface. If the state of the specified bit address is 1, the request message is obtained from the event memory corresponding to the specified bit address. Here, the acquisition method can be reading. After obtaining the request message, the processing function can be called, and the message body containing the request message can be set as the input parameter of the processing function. Then, the processing function with the input parameter set is executed to obtain the processing result.

[0092] In this embodiment, the second processor processes the request message and generates a processing result, which is then transmitted to the first processor. Thus, the first processor can share the computing resources or data resources of the second processor.

[0093] Optionally, step S30, that is, the second processor updates the message indication status and the request message according to the processing result, includes:

[0094] S301. The second processor sets the state of the designated bit address in the event register to 0, and writes the processing result into a memory unit corresponding to the second field address.

[0095] Understandably, after obtaining the processing result, the second processor sets the state of the specified bit address in the event register to 0, and writes the processing result into the memory unit corresponding to the second field address. Thus, the request message includes the processing result, and the first processor can obtain the processing result from the request message.

[0096] This embodiment completes writing the processing result into the request message, so that the shared storage area can store the processing result.

[0097] Optionally, step S40, that is, the first processor obtains the updated request message according to the updated message indication state to obtain the processing result, includes:

[0098] S401. When the first processor detects that the state of the designated bit address in the event register is set to 0, obtain an updated request message according to the updated message indication state; and obtain the processing result from the updated request message.

[0099] Understandably, when the second processing device sets the state of the specified bit address in the event register to 0 and writes the processing result to the memory unit corresponding to the second field address, the first processor can detect the change in the state of the specified bit address. When the first processor detects that the state of the specified bit address is 0, the processing result is obtained from the memory unit corresponding to the second field address of the event memory. After the first processor obtains the processing result, the previously set mutex lock can be released, and the processing result is returned to the requester of the request content.

[0100] In this embodiment, the first processor acquires the processing result from the event memory when the state of the designated bit address in the monitoring event register becomes 0, thereby realizing the transmission of the processing result and reducing the copying of data.

[0101] Optionally, the shared storage area includes a read pointer register, a write pointer register and a queue memory, the message indication state is a read pointer or a write pointer, the read pointer is stored in the read pointer register, the write pointer is stored in the write pointer register, and the request message is stored in the queue memory;

[0102] Step S10, i.e., the first processor sets a message indication state and a request message in a shared storage area according to the request content, wherein the message indication state is associated with the request message, includes:

[0103] S102. The first processor writes the request message in a memory unit corresponding to the address pointed to by the write pointer according to the request content, and updates the write pointer. The queue memory includes the memory unit.

[0104] Understandably, the shared memory area includes a read pointer register, a write pointer register, and a queue memory. Here, the message indicates that the state is a read pointer or a write pointer, which is used to point to the address of the request message, which is within the queue memory. The read pointer is stored in the read pointer register, the write pointer is stored in the write pointer register, and the request message is stored in the queue memory.

[0105] This embodiment belongs to a circular queue, runs in an asynchronous manner, passes pointers, avoids data copying, and has high efficiency. It is suitable for occasions with high efficiency requirements, such as computing acceleration tasks.

[0106] Specifically, in one example, Figure 3 As shown, the first processor writes the requested content to the address pointed to by the write pointer and updates the write pointer.

[0107] In this embodiment, the physical address of the request content is stored in the request message. The request message only transmits the address, which reduces data copying and greatly improves the efficiency of data communication.

[0108] Optionally, the request message includes a message header and a message body, and a memory block (the queue memory includes several memory blocks) for storing the message body includes a first field address and a second field address;

[0109] Step S102, that is, the first processor writes a request message in a memory block corresponding to the address pointed to by the write pointer according to the request content, includes:

[0110] S1021. Write the request content into a memory block corresponding to the first field address.

[0111] Understandably, the request message includes a message header and a message body. The message header is used to record the information of the first processor (initiator) calling the second processor (receiver), such as the callback function address, user data address, occupied semaphore address and other auxiliary information used to complete the communication. The message body includes a first address field (represented by Req) and a second address field (represented by Cnf). The message body is stored in a memory block. The first address field is stored in the first field address in the memory block, and the second address field is stored in the second field address in the memory block.

[0112] Here, writing the request content to the address pointed to by the write pointer is essentially writing the request content (which may be a physical address) to the memory unit corresponding to the first field address.

[0113] Optionally, the address pointed to by the read pointer is the same as the address pointed to by the write pointer before updating;

[0114] Step S20, i.e. the second processor obtains the request message according to the message indication status and generates a processing result of the request message, includes:

[0115] S203. The second processor obtains the request message according to the read pointer, processes the request content, generates a processing result, and updates the address pointed to by the read pointer to the updated address pointed to by the write pointer.

[0116] Understandably, the second processor obtains the request message from the address pointed to by the read pointer, and then processes the request message to generate a processing result. At the same time, the second processor updates the address pointed to by the read pointer to the address pointed to by the updated write pointer. Here, the processing method of the request message can refer to the processing method of the request message during the synchronization event, which will not be repeated here.

[0117] In this embodiment, the second processor processes the request message and generates a processing result, which is then transmitted to the first processor. Thus, the first processor can share the computing resources or data resources of the second processor.

[0118] Optionally, the address pointed to by the updated write pointer includes the second field address;

[0119] Step S30, i.e. the second processor updates the message indication status and the request message according to the processing result, includes:

[0120] S302: The second processor writes the processing result into the memory unit corresponding to the second field address and updates the write pointer.

[0121] Understandably, after obtaining the processing result, the second processor writes the processing result into the second field address. Thus, the request message includes the processing result, and the first processor can obtain the processing result from the request message according to the updated read pointer. The updated write pointer can be used to process the next request content.

[0122] This embodiment completes writing the processing result into the request message, so that the shared storage area obtains the processing result.

[0123] Optionally, step S40, that is, the first processor obtains the updated request message according to the updated message indication state to obtain the processing result, includes:

[0124] S402: The first processor obtains the processing result from the address pointed to by the updated read pointer, and updates the read pointer.

[0125] Understandably, after the second processing device writes the processing result into the second field address, the first processor obtains the processing result from the address pointed to by the updated read pointer and updates the read pointer at the same time. After the first processor obtains the processing result, the processing result can be returned to the requester of the request content. The updated read pointer can be used to process the next request content.

[0126] In this embodiment, the first processor obtains the processing result from the address pointed to by the updated read pointer and updates the read pointer, which can realize the transmission of the processing result and reduce data copying. At the same time, the state of the read pointer is updated so that the read pointer can be used to execute the next communication task.

[0127] Optionally, the first processor is provided with a first upper-layer service module, a first registration service module and a first inter-core communication module; and the heterogeneous multi-core processor data communication method includes:

[0128] S11, the first upper-layer service module obtains the request content and the memory space of the request content;

[0129] S12, the first registration service module obtains the request content and the memory space of the request content from the first upper-layer business module, and configures a setting instruction for setting the message indication state and the request message according to the request content and the memory space of the request content;

[0130] S13. The first inter-core communication module obtains the setting instruction from the first registration service module, and sends the setting instruction to the shared storage area, so as to set a message indication status and a request message in the shared storage area according to the setting instruction.

[0131] Understandably, if Figure 4 As shown, Figure 4 The schematic diagram of the architecture of the first processor and the second processor. The first processor is provided with a first upper-layer business module, a first registration service module and a first inter-core communication module. Among them, the first upper-layer business module is used to obtain the request content and the memory space of the request content. The first registration service module is used to obtain the request content and the memory space of the request content from the first upper-layer business module, and configure the setting instructions for setting the message indication state and the request message according to the request content and the memory space of the request content. The first inter-core communication module is used to obtain the setting instructions from the first registration service module, and send the setting instructions to the shared storage area, so as to set the message indication state and the request message in the shared storage area according to the setting instructions.

[0132] The implementation of the two inter-core communication methods, synchronous events and circular queues, depends on the first inter-core communication module on the first processor side. The first registration service module is responsible for registering callable functions and providing an encapsulation interface of the communication service for the first upper-layer business module to call. When the function of the first processor needs to be expanded, it is only necessary to register the corresponding service in the first registration service module, or to set a new interface between the first upper-layer business module and the first registration service module, without changing the overall architecture of the first processor, which greatly improves the scalability of the first processor.

[0133] Optionally, the second processor is provided with a second upper layer service module, a second registration service module and a second inter-core communication module; and the heterogeneous multi-core processor data communication method includes:

[0134] S14, the second inter-core communication module obtains the request message from the shared storage area;

[0135] S15. The second registration service module obtains the request message from the second inter-core communication module, parses the request message, and obtains the request content;

[0136] S16. The second upper-layer business module obtains the request content from the second registration service module, processes the request content according to a preset processing rule, and generates the processing result.

[0137] Understandably, if Figure 4 As shown, Figure 4 Schematic diagram of the first processor architecture and the second processor architecture. The second processor is provided with a second upper-layer business module, a second registration service module and a second inter-core communication module. Among them, the second inter-core communication module is used to obtain a request message from a shared storage area. The second registration service module obtains the request message from the second inter-core communication module, parses the request message, and obtains the request content. The second upper-layer business module is used to obtain the request content from the second registration service module, process the request content through a preset processing rule, and generate a processing result.

[0138] The implementation of the two inter-core communication methods, synchronous events and circular queues, depends on the second inter-core communication module on the second processor side. The second registration service module is responsible for registering callable functions and providing an encapsulation interface of the communication service for the second upper-layer business module to call. When the function of the second processor needs to be expanded, it is only necessary to register the corresponding service in the second registration service module, or to set a new interface between the second upper-layer business module and the second registration service module, without changing the overall architecture of the second processor, which greatly improves the scalability of the second processor.

[0139] In one example, the synchronization event can adopt the following calling process. This example is used to query the image processing operators supported by the DSP. Among them, the model of the first processor is CK810, and the second processor is DSP. After the DSP is started, the query processing function (such as CvLookUpFunc) is registered in the second registration service module of the DSP. The first upper-level business module of CK810 applies for memory space for the query request message (including req and cnf). Req fills in the physical address, the function name to be queried, etc. (ie, the request content), and cnf requires the DSP to fill in the query result (ie, the processing result). The first upper-level business module of CK810 calls the synchronization event interface (such as CvFuncQuery) of the first registration service module to send a message. The first input parameter is the address of req and cnf. The synchronous event interface (CvFuncQuery) of the first registered service module of CK810 processes the first input parameter as follows: 1. Address conversion, the virtual addresses of req and cnf are converted into physical addresses; 2. Request memory for the inter-core communication message body, and store the physical addresses of req and cnf; 3. Call the event sending interface of the first inter-core communication module, and the second input parameter is the physical address of the message body (i.e., the request content) and the event bit address (bit) to be set.

[0140] The event sending interface (EventSend) of the first inter-core communication module of CK810 processes the second input parameter, specifically: 1. Apply for a mutex lock, and use the mutex lock to protect the event register (EventFLAG) and event memory (EventRAM); 2. Write the physical address of the message body into the event memory, and set the event bit address (also called event flag bit) in the event register. The value of the event bit address is set to 1, and wait for the event bit address to be cleared (that is, set to 0).

[0141] DSP queries the event bit address through the event receiving interface of the second inter-core communication module and sets it to 1, reads the message body in the event memory, and calls the query processing function with the message body as input parameter. The query processing function fills the queried information into the cnf address and sets the value of the event bit address to 0 (i.e., clears the event flag bit).

[0142] The event sending interface of the first inter-core communication module of CK810 queries the value of the event bit address and sets it to 0, releases the mutex lock, and returns to the synchronous event interface of the first registration service module, which releases the memory containing the message body and returns to the first upper-level business module for further processing.

[0143] In some examples, the circular queue includes a synchronous queue and an asynchronous queue. Taking the image processing operator that calls the DSP as an example, the model of the first processor is CK810, and the second processor is DSP, then the synchronous queue can adopt the following calling process.

[0144] The first upper-layer business module of CK810 obtains the relevant information of the image operator and applies for the memory space of the request message (req and cnf). req is filled with the operator function to be called, and the required physical memory address is calculated, etc. cnf requires DSP to fill in the query result (i.e., the processing result).

[0145] The first upper-layer business module calls the synchronization queue interface (CvSyncQueue) of the first registration service module to send a message. The first synchronization queue input parameters are the addresses of req and cnf. The first registration service module processes the first synchronization queue input parameters as follows: 1. Address conversion, converting the virtual addresses of req and cnf into physical addresses; 2. Applying for the memory of the request message (including the message header and the message body), applying for a semaphore (sem) in the internal semaphore pool, filling in the virtual address and physical address of the request message and the address of the semaphore in the message header of the request message; filling in the physical addresses of req and cnf in the message body; 3. Pushing the request message into the internal message queue of the first registration service module, waiting for the semaphore to block the current user thread;

[0146] The message processing thread (MsgTx thread) inside the first registration service module of CK810 reads the request message from the internal message queue and processes it as follows: 1. Call the message sending interface (MsgSend interface) of the first inter-core communication module, and the second synchronization queue input parameter is the physical address of the message body in the request message; 2. The physical address and the virtual address of the request message are paired and saved in the internal database. The message sending interface of the first inter-core communication module processes the second synchronization queue input parameter as follows: 1. Write the physical address of MsgCore to the address indicated by the write pointer of the CK810toDSP queue; 2. Update the write pointer.

[0147] The visual processing interface (CvProcess interface) of the second registration service module of the DSP receives the request message through the message receiving interface (MsgRcvd interface) of the second inter-core communication module. The visual processing interface can perform the following steps: 1. Read the address indicated by the read pointer of the CK810toDSP queue; 2. Update the read pointer. After receiving the physical address of the message body, take out the physical addresses of req and cnf from the address, and call the operator for processing. After processing, obtain the processing result. Call the message sending interface (MsgSend interface) of the second inter-core communication module to write the processing result (physical address) into the DSPtoCK810 queue. The writing process is the same as above.

[0148] The message reading thread (MsgRx thread) inside the first registration service module of CK810 calls the message receiving interface of the first inter-core communication module to receive the request message. The message receiving interface of the first inter-core communication module performs the following steps: 1. Read the address indicated by the read pointer of the DSPtoCK810 queue; 2. Update the read pointer. After reading the physical address of the message body, query the internal database to obtain the virtual address of the request message, and then obtain the semaphore address and release the semaphore.

[0149] The first registered service module visual synchronization queue interface (CvSyncQueue interface) of CK810 obtains the semaphore, exits waiting, releases the address of the request message, and returns to the upper application for processing.

[0150] In some examples, taking calling an image processing operator of a DSP as an example, the model of the first processor is CK810, and the model of the second processor is a DSP, the asynchronous queue may adopt the following calling process.

[0151] The first upper layer service of CK810 obtains the relevant information of the image operator, applies for the memory space of the request message (req and cnf), fills in the operator function to be called in req, calculates the required physical memory address, etc., and cnf requires DSP to fill in the query result (i.e., the processing result).

[0152] The first upper-layer business module calls the synchronous queue interface (CvAsyncQueue interface) of the first registered service module to send a request message, with the input parameters being the addresses of req and cnf, as well as the callback function and the user data address. The visual asynchronous queue interface (CvAsyncQueue interface) of the first registered service module performs the following steps: 1. Address conversion, converting the virtual addresses of req and cnf into physical addresses; 2. Applying for memory for the request message (including the message header and the message body), applying for a semaphore (sem) in the internal semaphore pool, filling in the virtual and physical addresses of the request message, the callback function, and the address of the user data in the message header; filling in the physical addresses of req and cnf in the message body; 3. Pushing the request message into the internal message queue of the first registered service module, and returning to the upper layer for further processing.

[0153] The internal message processing thread (MsgTx thread) of the first registration service module of CK810 reads the request message from the internal message queue and executes the following steps: 1. Calls the message sending interface (MsgSend interface) of the first inter-core communication module, and the input parameter is the physical address of the message body in the request message; 2. Pairs the physical address and the virtual address of Msg and saves them in the internal database.

[0154] The message sending interface of the first inter-core communication module can execute the following steps: 1. Write the physical address of the message body into the address indicated by the write pointer of the CK810toDSP queue; 2. Update the write pointer.

[0155] The visual processing interface (CvProcess interface) of the second registration service module of the DSP receives the request message through the message receiving interface (MsgRcvd interface) of the second inter-core communication module. The visual processing interface can perform the following steps: 1. Read the address indicated by the read pointer of the CK810toDSP queue; 2. Update the read pointer. After receiving the physical address of the message body, take out the physical addresses of req and cnf from the address, and call the operator for processing. After processing, obtain the processing result. Call the message sending interface (MsgSend interface) of the second inter-core communication module to write the processing result (physical address) into the DSPtoCK810 queue. The writing process is the same as above.

[0156] The message reading thread (MsgRx thread) of the first registration service module of CK810 calls the message receiving interface of the first inter-core communication module to receive the request message. The message receiving interface of the first inter-core communication module performs the following steps: 1. Read the address indicated by the read pointer of the DSPtoCK810 queue; 2. Update the read pointer. After reading the physical address of the message body, query the internal database to obtain the virtual address of the request message, and then obtain the callback function and user data address, call the callback function to notify the upper-layer application so that it can obtain the processing result.

[0157] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0158] In one embodiment, a heterogeneous multi-core processor data communication device is provided, and the heterogeneous multi-core processor data communication device corresponds one-to-one to the heterogeneous multi-core processor data communication method in the above embodiment. Figure 5 As shown, the heterogeneous multi-core processor data communication device includes a first processor 10, a second processor 20 and a shared storage area 30;

[0159] The first processor 10 is used to set a message indication state and a request message in the shared storage area 30 according to the request content, and the message indication state is associated with the request message;

[0160] The second processor 20 is used to obtain the request message according to the message indication status and generate a processing result of the request message;

[0161] The second processor 20 is further configured to update the message indication status and the request message according to the processing result;

[0162] The first processor 10 is further configured to obtain an updated request message according to the updated message indication state to obtain the processing result.

[0163] Optionally, the shared storage area 30 includes an event register and an event memory, the event register is used to store the message indication state, and the event memory is used to store the request message;

[0164] The first processor 10 sets a message indication state and a request message in the shared storage area 30 according to the request content, wherein the message indication state is associated with the request message, including:

[0165] The first processor 10 sets the state of the specified bit address in the event register to 1 according to the request content, and writes the request information to the memory block corresponding to the specified bit address in the event memory according to the request content; the message indication state includes the state of the specified bit address.

[0166] Optionally, the request message includes a message header and a message body, and the memory block used to store the message body includes a first field address and a second field address;

[0167] Writing the request information into a memory block corresponding to the designated bit address in the event memory according to the request content includes:

[0168] The request information is written into a memory unit corresponding to the first field address.

[0169] Optionally, the second processor 20 obtains the request message according to the message indication status, and generates a processing result of the request message, including:

[0170] When the second processor 20 detects that the state of the designated bit address in the event register is set to 1, the request message is obtained from the event memory;

[0171] The second processor 20 processes the request message and generates a processing result.

[0172] Optionally, the second processor 20 updates the message indication status and the request message according to the processing result, including:

[0173] The second processor 20 sets the state of the designated bit address in the event register to 0, and writes the processing result into the memory unit corresponding to the second field address.

[0174] Optionally, the first processor 10 acquires the updated request message according to the updated message indication state to obtain the processing result, including:

[0175] When the first processor 10 detects that the state of the designated bit address in the event register is set to 0, it obtains an updated request message according to the updated message indication state; and obtains the processing result from the updated request message.

[0176] Optionally, the shared storage area 30 includes a read pointer register, a write pointer register and a queue memory, the message indication state is a read pointer or a write pointer, the read pointer is stored in the read pointer register, the write pointer is stored in the write pointer register, and the request message is stored in the queue memory;

[0177] The first processor 10 sets a message indication state and a request message in the shared storage area 30 according to the request content, wherein the message indication state is associated with the request message, including:

[0178] The first processor 10 writes the request content into the address pointed to by the write pointer and updates the write pointer, where the address pointed to by the write pointer is within the queue memory.

[0179] Optionally, the request message includes a message header and a message body, and the message body includes a first field address and a second field address;

[0180] The first processor 10 writes the request content into a memory block corresponding to the address pointed to by the write pointer, including:

[0181] The request message is written into a memory unit corresponding to the first field address according to the request content.

[0182] Optionally, the address pointed to by the read pointer is the same as the address pointed to by the write pointer before updating;

[0183] The second processor 20 obtains the request message according to the message indication status, and generates a processing result of the request message, including:

[0184] The second processor 20 obtains the request content according to the read pointer, processes the request content, generates a processing result, and updates the address pointed to by the read pointer to the updated address pointed to by the write pointer.

[0185] Optionally, the address pointed to by the updated write pointer includes the second field address;

[0186] The second processor 20 updates the message indication status and the request message according to the processing result, including:

[0187] The second processor 20 writes the processing result into the second field address and updates the write pointer.

[0188] Optionally, the first processor 10 acquires the updated request message according to the updated message indication state to obtain the processing result, including:

[0189] The first processor 10 obtains the processing result from the address pointed to by the updated read pointer, and updates the read pointer.

[0190] Optionally, the first processor 10 is provided with a first upper layer service module, a first registration service module and a first inter-core communication module; the heterogeneous multi-core processor data communication method includes:

[0191] The first upper-layer service module obtains the request content and the memory space of the request content;

[0192] The first registration service module obtains the request content and the memory space of the request content from the first upper-layer business module, and configures a setting instruction for setting the message indication state and the request message according to the request content and the memory space of the request content;

[0193] The first inter-core communication module obtains the setting instruction from the first registration service module, and sends the setting instruction to the shared storage area 30, so as to set the message indication status and the request message in the shared storage area 30 according to the setting instruction.

[0194] Optionally, the second processor 20 is provided with a second upper layer service module, a second registration service module and a second inter-core communication module; the heterogeneous multi-core processor data communication method includes:

[0195] The second inter-core communication module obtains the request message from the shared storage area 30;

[0196] The second registration service module obtains the request message from the second inter-core communication module, parses the request message, and obtains the request content;

[0197] The second upper-layer business module obtains the request content from the second registration service module, processes the request content according to a preset processing rule, and generates the processing result.

[0198] For the specific definition of the heterogeneous multi-core processor data communication device, please refer to the definition of the heterogeneous multi-core processor data communication method above, which will not be repeated here. Each module in the above-mentioned heterogeneous multi-core processor data communication device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0199] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 6 As shown. The computer device includes a processor, a memory, a network interface, a display screen and an input device connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a readable storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer-readable instructions. The internal memory provides an environment for the operation of the operating system and computer-readable instructions in the readable storage medium. The network interface of the computer device is used to communicate with an external server via a network connection. When the computer-readable instructions are executed by the processor, a heterogeneous multi-core processor data communication method is implemented. The readable storage medium provided in this embodiment includes a non-volatile readable storage medium and a volatile readable storage medium.

[0200] In one embodiment, a computer device is provided, including a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor, wherein the processor executes the computer-readable instructions to implement the following steps:

[0201] The first processor sets a message indication state and a request message in a shared storage area according to the request content, wherein the message indication state is associated with the request message;

[0202] The second processor obtains the request message according to the message indication status and generates a processing result of the request message;

[0203] The second processor updates the message indication status and the request message according to the processing result;

[0204] The first processor obtains the updated request message according to the updated message indication status to obtain the processing result.

[0205] In one embodiment, one or more computer-readable storage media storing computer-readable instructions are provided. The readable storage media provided in this embodiment include non-volatile readable storage media and volatile readable storage media. The readable storage media store computer-readable instructions. When the computer-readable instructions are executed by at least two processors, the following steps are implemented:

[0206] The first processor sets a message indication state and a request message in a shared storage area according to the request content, wherein the message indication state is associated with the request message;

[0207] The second processor obtains the request message according to the message indication status and generates a processing result of the request message;

[0208] The second processor updates the message indication status and the request message according to the processing result;

[0209] The first processor obtains the updated request message according to the updated message indication status to obtain the processing result.

[0210] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing related hardware through computer-readable instructions, and the computer-readable instructions can be stored in a non-volatile readable storage medium or a volatile readable storage medium. When the computer-readable instructions are executed, they may include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0211] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0212] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A heterogeneous multi-core processor data communication method, characterized in that: include: The first processor sets a message indication state and a request message in a shared storage area according to the request content, wherein the message indication state is associated with the request message; the shared storage area includes an event register and an event memory, wherein the event register is used to store the message indication state, and the event memory is used to store the request message; The first processor sets a message indication state and a request message in a shared storage area according to the request content, wherein the message indication state is associated with the request message, including: The first processor sets the state of the designated bit address in the event register to 1 according to the request content, and writes request information into the memory block corresponding to the designated bit address in the event memory according to the request content; the message indication state includes the state of the designated bit address; The second processor obtains the request message according to the message indication status and generates a processing result of the request message; The second processor updates the message indication status and the request message according to the processing result; The first processor obtains the updated request message according to the updated message indication status to obtain the processing result.

2. The heterogeneous multi-core processor data communication method according to claim 1, characterized in that: The request message includes a message header and a message body, and the memory block used to store the message body includes a first field address and a second field address; Writing the request information into a memory block corresponding to the designated bit address in the event memory according to the request content includes: The request information is written into a memory unit corresponding to the first field address.

3. The heterogeneous multi-core processor data communication method according to claim 2, characterized in that: The second processor obtains the request message according to the message indication status, and generates a processing result of the request message, including: When the second processor detects that the state of the designated bit address in the event register is set to 1, acquiring the request message from the event memory; The second processor processes the request message and generates a processing result.

4. The heterogeneous multi-core processor data communication method according to claim 3, characterized in that: The second processor updates the message indication status and the request message according to the processing result, including: The second processor sets the state of the designated bit address in the event register to 0, and writes the processing result into a memory unit corresponding to the second field address.

5. The heterogeneous multi-core processor data communication method according to claim 1, characterized in that: The first processor is provided with a first upper layer service module, a first registration service module and a first inter-core communication module; The heterogeneous multi-core processor data communication method comprises: The first upper-layer service module obtains the request content and the memory space of the request content; The first registration service module obtains the request content and the memory space of the request content from the first upper-layer business module, and configures a setting instruction for setting the message indication state and the request message according to the request content and the memory space of the request content; The first inter-core communication module obtains the setting instruction from the first registration service module, and sends the setting instruction to the shared storage area, so as to set a message indication state and a request message in the shared storage area according to the setting instruction.

6. The heterogeneous multi-core processor data communication method according to claim 1, characterized in that: The second processor is provided with a second upper layer service module, a second registration service module and a second inter-core communication module; The heterogeneous multi-core processor data communication method comprises: The second inter-core communication module obtains the request message from the shared storage area; The second registration service module obtains the request message from the second inter-core communication module, parses the request message, and obtains the request content; The second upper-layer business module obtains the request content from the second registration service module, processes the request content according to a preset processing rule, and generates the processing result.

7. A heterogeneous multi-core processor data communication device, characterized in that: comprising a first processor, a second processor and a shared memory area; The first processor is used to set a message indication state and a request message in the shared storage area according to the request content, and the message indication state is associated with the request message; the shared storage area includes an event register and an event memory, the event register is used to store the message indication state, and the event memory is used to store the request message; The first processor sets a message indication state and a request message in a shared storage area according to the request content, wherein the message indication state is associated with the request message, including: The first processor sets the state of the designated bit address in the event register to 1 according to the request content, and writes request information into the memory block corresponding to the designated bit address in the event memory according to the request content; the message indication state includes the state of the designated bit address; The second processor is used to obtain the request message according to the message indication status, and generate a processing result of the request message; The second processor is further used to update the message indication status and the request message according to the processing result; The first processor is further configured to obtain an updated request message according to an updated message indication status to obtain the processing result.

8. A computer device comprising a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor, characterized in that: The processor includes a first processor and a second processor, and when the processor executes the computer-readable instructions, the heterogeneous multi-core processor data communication method according to any one of claims 1 to 6 is implemented.

9. One or more readable storage media storing computer-readable instructions, wherein when the computer-readable instructions are executed by at least two processors, the at least two processors execute the heterogeneous multi-core processor data communication method as claimed in any one of claims 1 to 6.

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