A debugging circuit for expanding I2C pins

Abstract

The present invention discloses a debugging circuit for expanding I2C pins. Among them, a debugging enable circuit is used to generate a debugging enable signal; the debugging enable circuit is connected to pins IO_SCL, IO_SDA, IO_RESETb, IO_IOA, and IO_IOB, and the pin IO_RESETb is used to externally reset the chip; a clock control circuit is used to select the clock output of the internal oscillator or the external input clock of the chip pins according to the debugging enable signal; an I2C control circuit is used to parse the I2C protocol and read and write the I2C register group; the I2C register group is used to store the current sampling value of the signal to be observed and the selection signal of the pure combinational logic pin control circuit; the pure combinational logic pin control circuit is used to decode the debugging enable signal and the selection signal of the I2C register group, and control whether to multiplex the chip output pin to output the signal to be observed, and switch different signals to be observed to the limited chip pins. The present invention utilizes the existing mature I2C protocol to implement the debugging logic with the least amount of logic and without additional timing constraints.

Description

Technical Field

[0001] The present invention relates to the technical field of chip debugging, and particularly to a debugging circuit for expanding I2C pins. Background Art

[0002] In chip testing, the purpose of chip testing is to quickly determine whether the chip is working properly with high stability. Now, chip design teams generally recognize that this requires adding DFT (Design for Testability) circuits to the chip.

[0003] In chip debugging, the purpose of chip debugging is not simply to determine that the chip has a fault, but to find out the cause of the fault. This inspection is not limited to a few seconds on the test bench and may last for several weeks. It is not automatic, but requires the chip design team to consider possible problems that may occur during later chip debugging during the chip design process, and then use the limited chip pins to control and observe the internal signals of the chip as much as possible.

[0004] The digital chip design field basically adopts synchronous clock design, and most digital circuits are clock-driven. If there are problems with the clock, such as the chip internal oscillator fails to start, the clock jitter is too large, or the clock frequency seriously exceeds or is lower than the design index, the digital circuit will not be able to work and be debugged normally. To ensure that the chip can still be debugged even if there are problems with the clock, usually chip design engineers need to prepare a debugging circuit inside the chip in advance, connect to an external clock by multiplexing chip pins, and output the internal signals to an oscilloscope for observation by multiplexing chip pins.

[0005] The prior art usually requires an extra pin to select whether the chip digital circuit uses the clock of the internal oscillator or the external debugging clock of the chip. Since using a pin requires considering issues such as ESD (Electrostatic Discharge), a single pin needs to occupy a not-small chip area, which makes some projects that are very sensitive to chip area indicators unable to meet the requirements. At the same time, due to the ESD problem, there are more uncertain factors in chip mass production.

[0006] There is also other prior art that selects whether the chip digital circuit uses the clock of the internal oscillator or the external debugging clock of the chip by inputting a complex timing sequence into the chip pins. In this way, the external mcu (Micro Control Unit) is required to generate specific timing information during the debugging process, making the debugging process complicated. At the same time, the chip internal debugging circuit also needs to meet requirements such as timing constraints. Otherwise, the debugging circuit cannot complete the predetermined debugging logic and the chip still cannot be debugged. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a debugging circuit for expanding I2C pins that uses the least amount of logic, requires no additional timing constraints, and can implement debugging logic.

[0008] To solve the above problems, the present invention provides a debugging circuit for expanding I2C pins, which includes:

[0009] A debugging enable circuit, a clock control circuit, an oscillator, an I2C control circuit, an I2C register group, and a pure combinational logic pin control circuit;

[0010] The debugging enable circuit is used to generate a debugging enable signal; the debugging enable circuit is connected to pins IO_SCL, IO_SDA, IO_RESETb, IO_IOA, and IO_IOB, and the pin IO_RESETb is used to externally reset the chip;

[0011] The clock control circuit is used to select the clock output of the internal oscillator or the external input clock of the chip pins according to the debugging enable signal;

[0012] The I2C control circuit is used to parse the I2C protocol and read and write the I2C register group;

[0013] The I2C register group is used to store the current sampling value of the signal to be observed and the selection signal of the pure combinational logic pin control circuit;

[0014] The pure combinational logic pin control circuit is used to decode the debugging enable signal and the selection signal of the I2C register group, and control whether to multiplex the chip output pin to output the signal to be observed, and switch different signals to be observed to the limited chip pins.

[0015] As a further improvement of the present invention, the debugging enable circuit includes DFF1 and MUX1. The resetb terminal of DFF1 is connected to MUX1, and the pin IO_RESETb is the clock of DFF1, which is used to determine whether it is in debugging enable at the rising edge of the pin IO_RESETb. The MUX1 is used to release IO_SDA for I2C protocol parsing after determining that the debugging enable is true.

[0016] As a further improvement of the present invention, the debugging enable circuit further includes DFF2. The resetb terminal of DFF2 takes over the pin IO_RESETb to make DFF2 have a correct initial value when powered on. DFF2 latches the Q value of DFF1 at the rising edge of IO_SCL.

[0017] As a further improvement of the present invention, the logic for determining that the debug enable is true is (IO_SCL is 0) and (IO_A is 1) and (IO_B is 0) and (IO_SDA is 0); where, (IO_SCL is 0) and (IO_A is 1) and (IO_B is 0) are reflected at the D terminal of DFF1, and (IO_SDA is 0) is reflected at the resetb terminal of DFF1.

[0018] As a further improvement of the present invention, after the debug enable signal is true, MUX1 selects the constant value 1'b1 as the resetb terminal of DFF1.

[0019] As a further improvement of the present invention, the pin IO_IOB is configured in a multiplexed manner to provide an external input clock for the chip pins in the debug mode.

[0020] As a further improvement of the present invention, when the chip is operating normally, at time 0, the pin IO_RESETb is always 0 during the power-on process.

[0021] As a further improvement of the present invention, when the chip is operating normally, after ensuring that the signal level at time 0 has stabilized, at time 1, the pin IO_RESETb is pulled high, and the chip operates normally. At this time, the debug enable signal is determined to be low.

[0022] As a further improvement of the present invention, when the chip enters the debug mode, at time 0, the pins IO_SCL and IO_SDA are forced to be 0 externally through a jumper cap, and the pins IO_A and IO_B are forced to be 1 and 0 respectively externally through a jumper cap.

[0023] As a further improvement of the present invention, when the chip enters the debug mode, after ensuring that the signal level at time 0 has stabilized, at time 1, the pin IO_RESETb is first pulled high. After the pin IO_RESETb is pulled high, the jumper caps of the pins IO_A and IO_B are released;

[0024] After ensuring that the signal level at time 1 has stabilized, at time 2, the jumper cap of the pin IO_SCL is released, and the level of the pin IO_SCL will be pulled high by an external pull-up resistor. At this time, the debug enable signal is determined to be high;

[0025] After ensuring that the signal level at time 2 has stabilized, at time 3, the jumper cap of the pin IO_SDA is released, and the level of the pin IO_SDA will be pulled high by an external pull-up resistor. After time 3, the pins IO_SCL and IO_SDA continue to be used for reading and writing the I2C register group through the I2C protocol.

[0026] Advantages of the present invention:

[0027] 1. The present invention proposes a brand-new debugging circuit by expanding the I2C pins. Based on the existing mature I2C protocol, it can implement the debugging logic with the least amount of logic and without additional timing constraints.

[0028] 2. The present invention does not require the use of additional chip pins to select whether the internal oscillator clock or the external debugging clock of the chip digital circuit is used.

[0029] 3. Although the present invention also requires specific external input timing, this specific timing is very simple and can be completed only by the chip test engineer manually unplugging and plugging the jumper cap.

[0030] 4. The debugging circuit proposed by the present invention can ensure that after entering the debugging mode, it is still possible to continue to read and write internal registers through the I2C protocol.

[0031] 5. The debugging circuit proposed by the present invention, through the reasonable design of the priority in the pure combinational logic pin control circuit, can enable different signals to be observed to be switched and output to limited chip pins by writing registers through the I2C protocol when the debugging enable mode is true.

[0032] The above description is only an overview of the technical solution of the present invention. In order to be able to more clearly understand the technical means of the present invention, it can be implemented in accordance with the content of the specification. And in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable, the following specific preferred embodiments are given and described in detail in conjunction with the drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic diagram of the debugging circuit for expanding I2C pins in the preferred embodiment of the present invention;

[0034] Figure 2 is a schematic diagram of the debugging enable circuit in the preferred embodiment of the present invention;

[0035] Figure 3 is the power-on timing diagram when the chip is working normally in the preferred embodiment of the present invention;

[0036] Figure 4 is the power-on timing diagram when the chip enters the debugging mode in the preferred embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] The following further describes the present invention in conjunction with the drawings and specific embodiments, so that those skilled in the art can better understand the present invention and implement it, but the embodiments given are not intended to limit the present invention.

[0038] As Figure 1 shown, it is the debugging circuit for expanding I2C pins in the preferred embodiment of the present invention, including:

[0039] Debug enable circuit, clock control circuit, oscillator, I2C control circuit, I2C register bank, pure combinational logic pin control circuit;

[0040] The debug enable circuit is used to generate a debug enable signal; the debug enable circuit is connected to pins IO_SCL, IO_SDA, IO_RESETb, IO_IOA, and IO_IOB, and the pin IO_RESETb is used to externally reset the chip; further, the pin IO_IOB is configured in a multiplexed manner to provide an external input clock for the chip pins in the debug mode.

[0041] According to the I2C protocol, the pins IO_SCL and IO_SDA are two necessary pins for the I2C protocol, and the protocol stipulates that pull-up resistors must be added to IO_SCL and IO_SDA. When IO_SCL and IO_SDA are in the idle state, the levels of IO_SCL and IO_SDA should be high.

[0042] The clock control circuit is used to select the clock output of the internal oscillator or the external input clock of the chip pins according to the debug enable signal;

[0043] The I2C control circuit is used to parse the I2C protocol and read and write the I2C register bank;

[0044] The I2C register bank is used to store the current sampling value of the signal to be observed and the selection signal of the pure combinational logic pin control circuit;

[0045] The pure combinational logic pin control circuit is used to decode the debug enable signal and the selection signal of the I2C register bank, and control whether to multiplex the chip output pins to output the signal to be observed, and switch different signals to be observed to the limited chip pins.

[0046] The present invention can ensure that when the debug enable mode is true, the I2C protocol can still read and write the I2C register bank. Therefore, only by reasonably configuring the priority of the pure combinational logic pin control circuit, it can be ensured that when the debug enable mode is true, different signals to be observed can still be switched to the limited chip pins by writing the register through the I2C protocol.

[0047] As Figure 2 shown, the debug enable circuit includes DFF1 and MUX1. The resetb terminal of DFF1 is connected to MUX1, and the pin IO_RESETb is the clock of DFF1, which is used to determine whether the current is in the debug enable state at the rising edge of the pin IO_RESETb. The MUX1 is used to release IO_SDA for I2C protocol parsing after determining that the debug enable is true.

[0048] It should be noted that the DFF is an edge-triggered D flip-flop with asynchronous reset. The logic of this D flip-flop is to latch the signal at the D terminal on the rising edge of CK and output it at the Q terminal. If the input at the resetb terminal is 0, the Q terminal is immediately set to 0.

[0049] Specifically, since the pin IO_RESETb is only pulled up once during the power-on process and then remains unchanged when the chip is working properly, the pin IO_RESETb is used as the clock of DFF1 to determine whether debugging is enabled currently. The logic for determining that debugging is enabled is (IO_SCL is 0) and (IO_A is 1) and (IO_B is 0) and (IO_SDA is 0). Among them, (IO_SCL is 0) and (IO_A is 1) and (IO_B is 0) are directly reflected at the D terminal of DFF1, while (IO_SDA is 0) is reflected at the resetb terminal of DFF1.

[0050] The MUX1 circuit is used to release IO_SDA for I2C protocol parsing after determining that debugging is enabled. When the debugging enable signal is true, MUX1 will select the constant value 1'b1 as the resetb terminal of DFF1.

[0051] Since the MUX1 circuit may make the resetb terminal of DFF1 constantly 1'b1, resulting in a logical loop between the resetb terminal and the Q terminal of DFF1 if there are only DFF1 and the MUX1 circuit. After power-on, if the initial value of the Q terminal of DFF1 is 1, DFF1 will never be able to be reset, which does not conform to the designed function. Therefore, further, the debugging enable circuit of the present invention also includes DFF2 to ensure the correct initial value during power-on.

[0052] The resetb terminal of DFF2 is connected to IO_RESETb, which can ensure that DFF2 has a correct initial value during power-on. DFF2 latches the Q value of DFF1 on the rising edge of the pin IO_SCL. In this way, if it is determined that debugging is enabled through DFF1, then after being latched by DFF2, the pin IO_SDA can be released.

[0053] Such as Figure 3As shown, when the chip is operating normally, at time 0, it is ensured that the pin IO_RESETb is always 0 during the power-on process. Regarding the pins IO_SCL and IO_SDA, depending on the design of the external circuit of the chip, they may have been pulled high by the pull-up resistor before time 0 when the chip is powered on, or may be pulled high by the pull-up resistor at the same time as time 0 when the chip is powered on. Meanwhile, the power-on levels of the pins IO_A and IO_B depend on the design of the external circuit of the chip and may be high or low at time 0. After ensuring that the signal levels at time 0 have stabilized, at time 1, the pin IO_RESETb is pulled high and the chip operates normally. At this time, the debug enable signal is determined to be low.

[0054] As Figure 4 As shown, compared with the power-on timing when the chip is operating normally, at time 0, it is ensured that the pin IO_RESETb is always 0 during the power-on process. The pins IO_SCL and IO_SDA are externally forced to 0 through jumpers, and the pins IO_A and IO_B are externally forced to 1 and 0 respectively through jumpers. After ensuring that the signal levels at time 0 have stabilized, at time 1, the pin IO_RESETb is first pulled high. After the pin IO_RESETb is pulled high, the jumpers of the pins IO_A and IO_B can be released for other uses. After ensuring that the signal levels at time 1 have stabilized, at time 2, the jumper of the pin IO_SCL is released, and the level of the pin IO_SCL will be pulled high by the external pull-up resistor. At this time, the debug enable signal is determined to be high. After ensuring that the signal levels at time 2 have stabilized, at time 3, the jumper of the pin IO_SDA is released, and the level of the IO_SDA will be pulled high by the external pull-up resistor. After time 3, the pins IO_SCL and IO_SDA can continue to be used to read and write the I2C register group through the I2C protocol.

[0055] The present invention proposes a brand-new debugging circuit by expanding the I2C pins. Based on the existing mature I2C protocol, it can implement the debugging logic with the least amount of logic and without additional timing constraints. There is no need to use additional chip pins to select whether to use the clock of the internal oscillator of the chip digital circuit or the external debug clock of the chip. Although a specific external timing is also required, this specific timing is very simple and only requires the chip test engineer to manually plug and unplug the jumpers to complete. The debugging circuit proposed by the present invention can ensure that after entering the debug mode, it is still possible to continue to read and write the internal registers through the I2C protocol. The debugging circuit proposed by the present invention, through the reasonable design of the priority in the pure combinational logic pin control circuit, can enable different signals to be observed to be switched to the limited chip pins by writing registers through the I2C protocol when the debug enable mode is true.

[0056] The above embodiments are only preferred embodiments given to fully illustrate the present invention, and the protection scope of the present invention is not limited thereto. Equivalent substitutions or transformations made by those skilled in the art on the basis of the present invention are within the protection scope of the present invention. The protection scope of the present invention shall be subject to the claims.

Claims

1. An I2C pin expansion debugging circuit, characterized in that, Comprising: A debug enable circuit, a clock control circuit, an oscillator, an I2C control circuit, an I2C register bank, and a pure combinational logic pin control circuit; The debug enable circuit is used to generate a debug enable signal; the debug enable circuit is connected to pins IO_SCL, IO_SDA, IO_RESETb, IO_IOA, and IO_IOB, and the pin IO_RESETb is used to externally reset the chip; The clock control circuit is used to select the clock output of the internal oscillator or the external input clock of the chip pins according to the debug enable signal; The I2C control circuit is used to parse the I2C protocol and read and write the I2C register bank; The I2C register bank is used to store the current sampled value of the signal to be observed and the selection signal of the pure combinational logic pin control circuit; The pure combinational logic pin control circuit is used to decode the debug enable signal and the selection signal of the I2C register bank, and control whether to multiplex the chip output pins to output the signal to be observed, and switch different signals to be observed to the limited chip pins; The debug enable circuit includes DFF1 and MUX1. The resetb terminal of DFF1 is connected to MUX1. The pin IO_RESETb is the clock of DFF1, and is used to determine whether the current is debug enabled at the rising edge of the pin IO_RESETb. The MUX1 is used to release IO_SDA for I2C protocol parsing after determining that the debug enable is true.

2. The I2C pin expansion debugging circuit according to claim 1, characterized in that, The debug enable circuit further includes DFF2. The resetb terminal of DFF2 takes over the pin IO_RESETb to make DFF2 have a correct initial value when powered on. DFF2 latches the Q value of DFF1 at the rising edge of IO_SCL.

3. The I2C pin expansion debugging circuit according to claim 1, characterized in that, The logic for determining that the debug enable is true is (IO_SCL is 0) and (IO_A is 1) and (IO_B is 0) and (IO_SDA is 0); Among them, (IO_SCL is 0) and (IO_A is 1) and (IO_B is 0) are reflected at the D terminal of DFF1, and (IO_SDA is 0) is reflected at the resetb terminal of DFF1.

4. The I2C pin expansion debugging circuit according to claim 1, characterized in that, After the debug enable signal is true, MUX1 selects the constant value 1'b1 as the resetb terminal of DFF1.

5. The I2C pin expansion debugging circuit according to claim 1, characterized in that, The pin IO_IOB is configured in a multiplexed manner and is used to provide an external input clock for the chip pins in the debug mode.

6. The I2C pin expansion debugging circuit according to claim 1, characterized in that, When the chip is working normally, the pin IO_RESETb is always 0 during the power-on process at time 0.

7. The I2C pin expansion debugging circuit according to claim 6, characterized in that, When the chip is working normally, after ensuring that the signal level at time 0 is stable, the pin IO_RESETb is pulled high at time 1, and the chip works normally. At this time, the debug enable signal is determined to be low.

8. The I2C pin expansion debugging circuit according to claim 1, characterized in that, When entering the chip debug mode, at time 0, the pins IO_SCL and IO_SDA are externally forced to 0 through a jumper cap, and the pins IO_A and IO_B are externally forced to 1 and 0 respectively through a jumper cap.

9. The I2C pin expansion debugging circuit according to claim 8, characterized in that, When entering the chip debug mode, after ensuring that the signal level at time 0 is stable, at time 1, first pull up the pin IO_RESETb. After the pin IO_RESETb is pulled up, the jumpers on pins IO_A and IO_B are released; After ensuring that the signal level at time 1 is stable, at time 2, release the jumper on the pin IO_SCL. The level of the pin IO_SCL will be pulled up by an external pull-up resistor, and at this time, the debug enable signal is determined to be high; After ensuring that the signal level at time 2 is stable, at time 3, release the jumper on the pin IO_SDA. The level of the pin IO_SDA will be pulled up by an external pull-up resistor. After time 3, the pins IO_SCL and IO_SDA continue to be used for reading and writing the I2C register group using the I2C protocol.

Images