Display device

Abstract

A display device is provided. The display device may include a display panel, a data driving circuit, a scan driving circuit, and a driving controller, wherein the display panel includes a plurality of pixels respectively connected to a plurality of data lines and a plurality of scan lines, the data driving circuit drives the plurality of data lines, and the scan driving circuit drives the plurality of scan lines. The driving controller receives an image signal and a control signal, controls the data driving circuit and the scan driving circuit according to an operation mode, divides the display panel into a first display area and a second display area according to the operation mode, outputs a start signal indicating the start of a frame and a mask signal for indicating the start of the second display area, sets a basic driving frequency to a normal frequency when the operation mode is a normal frequency mode, and outputs a start signal and a mask signal when the operation mode is a multi-frequency mode so that the first display area operates at a first driving frequency and the second display area operates at a second driving frequency lower than the first driving frequency.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2020-0080260, filed on June 30, 2020, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0002] Embodiments of the present invention herein relate to a display device, and more particularly, to a multi-frequency drivable display device. Background Art

[0003] Among the display devices, an organic light emitting display device uses an organic light emitting diode for emitting light through recombination of electrons and holes to display an image. The organic light emitting display device has advantages such as fast response speed and low power consumption.

[0004] An organic light-emitting display device includes pixels connected to data lines and scan lines. Typically, each pixel includes an organic light-emitting diode (OLED) and a circuit unit for controlling the amount of current flowing through the OLED. In response to a data signal, the circuit unit controls the amount of current flowing from a first drive voltage through the OLED to a second drive voltage. Here, light of a predetermined brightness is generated in response to the amount of current flowing through the OLED. Summary of the Invention

[0005] In the case of displaying a moving image on a display device, as the driving frequency becomes higher, the display quality can be improved. However, for a display device operating at a high driving frequency, power consumption increases.

[0006] Embodiments of the present invention provide a display device capable of reducing power consumption.

[0007] Embodiments of the present invention provide a display device, which includes a display panel including a plurality of pixels connected to a plurality of data lines and a plurality of scan lines, a data driving circuit for driving the plurality of data lines, a scan driving circuit for driving the plurality of scan lines, and a driving controller. The driving controller receives an image signal and a control signal, controls the data driving circuit and the scan driving circuit according to an operation mode, divides the display panel into a first display area and a second display area according to the operation mode, outputs a start signal indicating the start of a frame and a mask signal for indicating the start of the second display area, sets a base driving frequency to a normal frequency when the operation mode is a normal frequency mode, and sets the base driving frequency to a frequency lower than the normal frequency when the operation mode is a multi-frequency mode, and outputs a start signal and a mask signal so that the first display area operates at a first driving frequency and the second display area operates at a second driving frequency lower than the first driving frequency. The scan driving circuit sequentially drives the plurality of scan lines in synchronization with the start signal, and stops driving a scan line corresponding to the second display area among the plurality of scan lines in response to the mask signal.

[0008] In an embodiment, the first driving frequency may be higher than a basic driving frequency of the multi-frequency mode, and the second driving frequency may be lower than the basic driving frequency of the multi-frequency mode.

[0009] In an embodiment, during the multi-frequency mode, a first frame may have a first duration, a second frame consecutive to the first frame may have a second duration, and the second duration may be shorter than the first duration.

[0010] In an embodiment, during the multi-frequency mode, the first duration of the first frame may be longer than the first duration of the first frame during the normal frequency mode.

[0011] In an embodiment, the driving controller may provide image data signals corresponding to the first display area and the second display area to the data driving circuit during a first frame of the multi-frequency mode, and provide image data signals corresponding to the first display area to the data driving circuit during a second frame of the multi-frequency mode.

[0012] In an embodiment, the driving controller may provide image data signals corresponding to the first display area and the second display area to the data driving circuit in each frame during the normal frequency mode.

[0013] In an embodiment, the scan driving circuit may include multiple driving stages, each of which drives corresponding scan lines among the multiple scan lines, wherein each of the multiple driving stages includes a driving circuit and a masking circuit, wherein the driving circuit outputs a first scan signal to a first output terminal in response to a clock signal and a carry signal from a driving controller, and the masking circuit stops the driving circuit from outputting the first scan signal in response to the masking signal.

[0014] In an embodiment, a first driving stage among the plurality of driving stages may receive the start signal as a carry signal.

[0015] In an embodiment, the driving circuit may output the second scan signal to the second output terminal in response to the clock signal and the carry signal.

[0016] In an embodiment, among the plurality of driving stages, the second scan signal output from the j-th driving stage may be provided to the j+k-th driving stage as a carry signal, where j and k are natural numbers, respectively.

[0017] In an embodiment, the masking signal may include a first masking signal and a second masking signal, wherein the masking circuit includes a first masking circuit electrically connecting the first voltage terminal and the first output terminal in response to the first masking signal and a second masking circuit electrically connecting the first output terminal and the second output terminal in response to the second masking signal.

[0018] In an embodiment, during the multi-frequency mode, the first masking circuit may electrically connect the first voltage terminal and the first output terminal in response to a first masking signal, and during the multi-frequency mode, the second masking circuit may electrically disconnect the first output terminal and the second output terminal in response to a second masking signal.

[0019] In an embodiment of the present invention, a display device includes a display panel, a data driving circuit, a scan driving circuit, and a driving controller. In a plan view, a first non-folding area, a folding area, and a second non-folding area are defined in the display panel, and the display panel includes a plurality of pixels connected to a plurality of data lines and a plurality of scan lines, respectively. The data driving circuit drives the plurality of data lines, and the scan driving circuit drives the plurality of scan lines. The driving controller receives an image signal and a control signal, controls the data driving circuit and the scan driving circuit according to an operation mode, divides the display panel into a first display area and a second display area according to the operation mode, outputs a start signal indicating the start of a frame and a mask signal for indicating the start of the second display area, sets a base driving frequency to a normal frequency when the operation mode is a normal frequency mode, and sets the base driving frequency to a frequency lower than the normal frequency when the operation mode is a multi-frequency mode, and outputs a start signal and a mask signal so that the first display area operates at a first driving frequency and the second display area operates at a second driving frequency lower than the first driving frequency. The scan driving circuit sequentially drives the plurality of scan lines in synchronization with the start signal, and stops driving a scan line corresponding to the second display area among the plurality of scan lines in response to the mask signal.

[0020] In an embodiment, the first driving frequency may be higher than a basic driving frequency of the multi-frequency mode, and the second driving frequency may be lower than the basic driving frequency of the multi-frequency mode.

[0021] In an embodiment, during the multi-frequency mode, a first frame may have a first duration, a second frame consecutive to the first frame may have a second duration, and the second duration may be shorter than the first duration.

[0022] In an embodiment, during the multi-frequency mode, the image data signal to be provided to the first display area may be a moving image signal, and the image data signal to be provided to the second display area may be a still image signal.

[0023] In an embodiment, the display panel may be folded with reference to a folding axis extending in a predetermined direction in the folding region.

[0024] In an embodiment, the scan driving circuit may include a plurality of driving stages, each of which drives a corresponding scan line among the plurality of scan lines, wherein each of the plurality of driving stages includes a driving circuit and a masking circuit, wherein the driving circuit outputs a first scan signal to a first output terminal and outputs a second scan signal to a second output terminal in response to a clock signal and a carry signal from a driving controller, and the masking circuit stops the driving circuit from outputting the first scan signal in response to the masking signal.

[0025] In an embodiment, a first driving stage among the plurality of driving stages may receive the start signal as a carry signal.

[0026] In an embodiment, the masking signal may include a first masking signal and a second masking signal, wherein the masking circuit includes a first masking circuit electrically connecting the first voltage terminal and the first output terminal in response to the first masking signal and a second masking circuit electrically connecting the first output terminal and the second output terminal in response to the second masking signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention. In the drawings:

[0028] Figure 1A is a perspective view of an embodiment of a display device according to the present invention;

[0029] Figure 1B is a perspective view of an embodiment of a display device according to the present invention;

[0030] Figure 2 is a diagram for explaining an embodiment of the operation of the display device in the normal frequency mode;

[0031] Figure 3 is a diagram for explaining an embodiment of an operation of a display device in a multi-frequency mode;

[0032] Figure 4 is a block diagram of an embodiment of a display device according to the present invention;

[0033] Figure 5 is an equivalent circuit diagram of an embodiment of a pixel according to the present invention;

[0034] Figure 6 Is used to explain Figure 3 A timing diagram of the operation of a pixel of a display device;

[0035] Figure 7 is a block diagram of an embodiment of a scan driving circuit according to the present invention;

[0036] Figure 8 yes Figure 7 A circuit diagram of an embodiment of a j-th driver stage among the plurality of driver stages shown in FIG;

[0037] Figure 9 yes Figure 7 A timing diagram of an embodiment of the operation of the j-1th driving stage, the jth driving stage and the j+1th driving stage in the scan driving circuit shown in FIG;

[0038] Figure 10 The example shows the normal frequency mode from Figure 4 The drive controller shown in FIG provides a signal to the scan drive circuit and an image data signal to the data drive circuit;

[0039] Figure 11 The example shows the multi-frequency mode from Figure 4 The drive controller shown in FIG provides a signal to the scan drive circuit and an image data signal to the data drive circuit;

[0040] Figure 12 exemplarily shows a first scanning signal output from a scanning driving circuit in a multi-frequency mode;

[0041] Figures 13 to 15 The example shows the multi-frequency mode from Figure 4 The drive controller shown in FIG provides a signal to the scan drive circuit and an image data signal to the data drive circuit; and

[0042] Figure 16 The example shows the multi-frequency mode from Figure 4 The driving controller shown in FIG provides a start signal to the scan driving circuit. DETAILED DESCRIPTION

[0043] It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected to or coupled to the other element or layer, or intervening third elements may be present.

[0044] In the accompanying drawings, similar reference numerals refer to similar elements. In addition, in the accompanying drawings, the thickness, proportion and size of the elements are exaggerated for the effective description of the technical content. The wording "and / or" includes any and all combinations of one or more of the related items.

[0045] Phrases such as first and second may be used to describe various components, but these components should not be limited by these phrases. These phrases are only used to distinguish one element from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of this disclosure. Unless the context clearly indicates otherwise, as used herein, the singular forms "a," "an," and "the" may be intended to include the plural forms.

[0046] Additionally, terms such as "under," "lower," "on," and "upper" are used to explain the relationship of items shown in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0047] It will also be understood that the terms “includes” and / or “including”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the embodiments pertain. In addition, it will be understood that, unless expressly defined as such herein, terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

[0049] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0050] Figure 1A is a perspective view of an embodiment of a display device DD according to the present invention. Figure 1Bis a perspective view of an embodiment of a display device DD according to the present invention. Figure 1A The display device DD is shown in the unfolded state, and Figure 1B The display device DD is shown in a folded state.

[0051] Figure 1A and Figure 1B The display device DD is exemplarily shown as a mobile phone. However, the present invention is not limited to this. The display device DD may include a tablet personal computer (PC), a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a game console, or a watch-type electronic device. The embodiments of the present invention can be used not only in large electronic devices such as televisions or outdoor billboards, but also in small and medium-sized electronic devices such as personal computers, notebook computers, kiosks, vehicle navigation units, or cameras. These are listed as embodiments only, and the display device DD can also be applied to other electronic devices without departing from the concept of the present invention.

[0052] The display device DD may include a display area DA and a non-display area NDA. The display device DD may display an image through the display area DA. When the display device DD is in an unfolded state, the display area DA may include a plane defined by a first direction DR1 and a second direction DR2. The thickness direction of the display device DD may be parallel to a third direction DR3 intersecting the first direction DR1 and the second direction DR2. Therefore, the front surface (or top surface) and the rear surface (or bottom surface) of the components constituting the display device DD may be defined with reference to the third direction DR3. The non-display area NDA may also be referred to as a frame area. In an embodiment, the display area DA may be in a quadrilateral shape. For example, the non-display area NDA may surround the display area DA.

[0053] The display area DA may include a first non-folding area NFA1, a folding area FA, and a second non-folding area NFA2. The folding area FA may be folded with reference to a folding axis FX extending in a first direction DR1.

[0054] When the display device DD is folded, the first non-folding area NFA1 and the second non-folding area NFA2 may face each other. Therefore, in the fully folded state, the display area DA may not be exposed to the outside, and this may be referred to as inward folding. However, the operation of the display device DD is not limited thereto.

[0055] In an embodiment of the present invention, when the display device DD is folded, for example, the first non-folding area NFA1 and the second non-folding area NFA2 may be opposite to each other. Therefore, in a fully folded state, the first non-folding area NFA1 may be exposed to the outside, and this may be referred to as an outward fold.

[0056] The display device DD can be operated inward or outward. In an alternative embodiment, both inward and outward folding operations are possible for the display device DD. In this case, the same area of ​​the display device DD can be folded inward or outward. In an alternative embodiment, a certain area of ​​the display device DD can be folded inward, while another area can be folded outward.

[0057] Figure 1A and Figure 1B One folding area and two non-folding areas are exemplarily shown, but the number of folding areas and non-folding areas is not limited thereto. In an embodiment, for example, the display device DD may include a plurality of non-folding areas greater than two and a plurality of folding areas arranged between adjacent non-folding areas.

[0058] Figure 1A and Figure 1B The folding axis FX is shown as being parallel to the short axis of the display device DD, but the present invention is not limited thereto. In an embodiment, the folding axis FX may extend along the long axis of the display device DD (e.g., in a direction parallel to the second direction DR2). In this case, the first non-folding area NFA1, the folding area FA, and the second non-folding area NFA2 may be arranged sequentially along the first direction DR1.

[0059] A plurality of display areas DA1 and DA2 may be defined in the display area DA of the display device DD. Figure 1A , two display areas DA1 and DA2 are exemplarily shown, but the number of the plurality of display areas DA1 and DA2 is not limited thereto.

[0060] The plurality of display areas DA1 and DA2 may include a first display area DA1 and a second display area DA2. In an embodiment, for example, the first display area DA1 may be an area where a first image IM1 is displayed, and the second display area DA2 may be an area where a second image IM2 is displayed, but the present invention is not limited thereto. In an embodiment, for example, the first image IM1 may be a moving image, and the second image IM2 may be a still image or an image with a long changing period (such as text information).

[0061] The display device DD in the embodiment can operate differently according to the operation mode. The operation mode may include a normal frequency mode and a multi-frequency mode. The display device DD sets the basic driving frequency (BDF) to the normal frequency (NF) during the normal frequency mode. Therefore, both the first display area DA1 and the second display area DA2 can be driven at the normal frequency (NF). The display device DD in the embodiment can set the basic driving frequency (BDF) to a frequency lower than the normal frequency (NF) (NF>BDF) during the multi-frequency mode. During the multi-frequency mode, the display device DD can drive the first display area DA1 displaying the first image IM1 at the first driving frequency and drive the second display area DA2 displaying the second image IM2 at the second driving frequency. In the embodiment, the first driving frequency (DF1) is higher than the basic driving frequency (BDF) (DF1>BDF), and the second driving frequency (DF2) is lower than the basic driving frequency (BDF) (DF2<BDF). The first driving frequency (DF1) may be higher than the second driving frequency (DF2) (DF1>DF2). In the embodiment, the first driving frequency (DF1) may be higher than the normal frequency (NF) (DF1>NF>BDF).

[0062] The size of each of the first display area DA1 and the second display area DA2 may be preset and can be changed by the application program. In the embodiment, the first display area DA1 may correspond to the first non-folded area NFA1, and the second display area DA2 may correspond to the second non-folded area NFA2. Additionally, a part of the folded area FA may correspond to the first display area DA1, and another part of the folded area FA may correspond to the second display area DA2.

[0063] In the embodiment, the first display area DA1 may correspond to a part of the first non-folded area NFA1, and the second display area DA2 may correspond to another part of the first non-folded area NFA1, the folded area FA, and the second non-folded area NFA2. In other words, the area of the second display area DA2 may be larger than the area of the first display area DA1.

[0064] In the embodiment, the first display area DA1 may correspond to a part of the first non-folded area NFA1, the folded area FA, and the second non-folded area NFA2, and the second display area DA2 may correspond to another part of the second non-folded area NFA2. In other words, the area of the first display area DA1 may be larger than the area of the second display area DA2.

[0065] As Figure 1BAs shown in FIG, in a state in which the first folding area FA is folded, the first display area DA1 may correspond to the first non-folding area NFA1, and the second display area DA2 may correspond to the folding area FA and the second non-folding area NFA2.

[0066] Figure 1A and Figure 1B A foldable display device DD is shown as an example of a display device, but the present invention is not limited thereto. In embodiments, the present invention may also be applied to, for example, an unfolded display device, a display device having two or more folding areas, or a rollable display device.

[0067] Figure 2 is a diagram for explaining an embodiment of an operation of the display device DD in a normal frequency mode. Figure 3 is a diagram for explaining the operation of the display device DD in the multi-frequency mode.

[0068] Reference Figure 2 In the normal frequency mode NFM, the first display area DA1 and the second display area DA2 of the display device DD are driven at a normal frequency. In one embodiment, the normal frequency may be 120 Hz, for example. In the normal frequency mode NFM, for example, images from the first frame F1 to the 120th frame F120 may be displayed in the first display area DA1 and the second display area DA2 for one second.

[0069] Reference Figure 3 In multi-frequency mode (MFM), the driving frequency of the first display area DA1 of the display device DD may be a first driving frequency lower than the normal frequency, and the driving frequency of the second display area DA2 may be a second driving frequency lower than the normal frequency. When the normal frequency is 120 Hz, the first driving frequency and the second driving frequency are as shown in Table 1 below.

[0070] [Table 1]

[0071] First driving frequency Second driving frequency 80Hz 40Hz 90Hz 30Hz 102Hz 18Hz 110Hz 10Hz 118Hz 2Hz 119Hz 1Hz

[0072] In an embodiment, Figure 3As shown in , when the first driving frequency in the multi-frequency mode MFM is 119 Hz and the second driving frequency is 1 Hz, for example, for 1 second, the first image IM1 from the first frame F1 to the 119th frame F119 is displayed on the first display area DA1, and only the second image IM2 in the first frame F1 is displayed on the second display area DA2. In other words, in the multi-frequency mode MFM, for 1 second, the first image IM1 corresponding to 119 frames is displayed on the first display area DA1, and the second image IM2 corresponding to the first frame F1 is displayed on the second display area DA2. In the multi-frequency mode MFM, no image is displayed on the second display area DA2, and thus power consumption can be reduced. In addition, in the multi-frequency mode MFM, an image with a first driving frequency of 119 Hz, which is close to a normal frequency, is displayed, and thus degradation in the display quality of the display device DD can be minimized, and power consumption can also be reduced.

[0073] Figure 4 is a block diagram of an embodiment of a display device DD according to the present invention.

[0074] Reference Figure 4 , the display device DD includes a display panel DP, a driving controller 100 , a data driving circuit 200 and a voltage generator 300 .

[0075] The driving controller 100 receives the image signal RGB and the control signal CTRL and generates the image data signal DATA, the data format of which is converted to match the specification of the interface with the data driving circuit 200. The driving controller 100 outputs the scan control signal SCS and the data control signal DCS.

[0076] The data driving circuit 200 receives a data control signal DCS and an image data signal DATA from the driving controller 100. The data driving circuit 200 converts the image data signal DATA into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm (m is a natural number), which will be described later. The data signal is an analog voltage corresponding to the grayscale value of the image data signal DATA.

[0077] The voltage generator 300 generates voltages required for the operation of the display panel DP. In the present embodiment, the voltage generator 300 generates a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT.

[0078] The display panel DP includes a plurality of first scan lines SL0 to SLn (n is a natural number), a plurality of second scan lines SWL2 to SWLn+1, a plurality of light emission control lines EML1 to EMLn, a plurality of data lines DL1 to DLm, and pixels PX. The display panel DP may further include a scan drive circuit SD. In an embodiment, the scan drive circuit SD is arranged on a first side of the display panel DP. The plurality of first scan lines SL0 to SLn, the plurality of second scan lines SWL2 to SWLn+1, and the plurality of light emission control lines EML1 to EMLn extend from the scan drive circuit SD in a first direction DR1.

[0079] A plurality of first scan lines SL0 to SLn, a plurality of second scan lines SWL2 to SWLn+1, and a plurality of light emission control lines EML1 to EMLn are arranged to be spaced apart from each other in the second direction DR2. A plurality of data lines DL1 to DLm are connected from the data driving circuit 200 in the second direction DR2 (e.g., Figure 4 the opposite direction (for example, Figure 4 The layers extend in a downward direction (in a lower direction) and are arranged to be spaced apart from each other in the first direction DR1.

[0080] The plurality of pixels PX are electrically connected to a plurality of first scan lines SL0 to SLn, a plurality of second scan lines SWL2 to SWLn+1, a plurality of light emission control lines EML1 to EMLn, and a plurality of data lines DL1 to DLm. Each of the plurality of pixels PX may be electrically connected to four scan lines. In an embodiment, as Figure 4 As shown in , for example, the pixels PX in the first row can be connected to the first scan line SL0, the first scan line SL1, the second scan line SWL2, and the light emission control line EML1. In addition, the pixels PX in the second row can be connected to the first scan line SL1, the first scan line SL2, the second scan line SWL3, and the light emission control line EML2.

[0081] Each of the plurality of pixels PX includes an organic light emitting diode ED (refer to Figure 5 ) and a pixel circuit unit PXC (refer to Figure 5 The pixel circuit unit PXC may include a plurality of transistors and capacitors. The scan driving circuit SD may include transistors formed by the same process as that of the pixel circuit unit PXC.

[0082] Each of the plurality of pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT.

[0083] The scan driving circuit SD receives a scan control signal SCS from the driving controller 100. In response to the scan control signal SCS, the scan driving circuit SD may output a first scan signal to a plurality of first scan lines SL0 to SLn and a second scan signal to a plurality of second scan lines SWL2 to SWLn+1. The circuit configuration and operation of the scan driving circuit SD will be described in detail later.

[0084] exist Figure 4 In the example shown in , the scan drive circuit SD can output light emission control signals to the plurality of light emission control lines EML1 to EMLn. In another embodiment, the display device DD may further include a light emission drive circuit for generating the light emission control signals. In this case, the scan drive circuit SD can output first scan signals to be provided to the plurality of first scan lines SL0 to SLn and second scan signals to be provided to the plurality of second scan lines SWL2 to SWLn+1, and the light emission drive circuit can output light emission control signals to be provided to the plurality of light emission control lines EML1 to EMLn.

[0085] The driving controller 100 in the embodiment divides the display panel DP into a first display area DA1 (see FIG. 1 ) and a second display area DA2 (see FIG. 1 ) based on the image signals RGB, and outputs at least one masking signal indicating the start of the second display area DA2. The at least one masking signal may be included in the scan control signal SCS.

[0086] Figure 5 is an equivalent circuit diagram of an embodiment of a pixel PXij according to the present invention.

[0087] Figure 5 It is shown as an example with Figure 4 An equivalent circuit diagram of a pixel PXij (i and j are natural numbers) connected to the i-th data line DLi among the multiple data lines DL1 to DLm, the j-1-th first scan line SLj-1 and the j-th first scan line SLj among the multiple first scan lines SL0 to SLn, the j+1-th second scan line SWLj+1 among the multiple second scan lines SWL2 to SWLn+1, and the j-th light emission control line EMLj among the multiple light emission control lines EML1 to EMLn.

[0088] Figure 4 Each of the plurality of pixels PX shown in FIG may have Figure 5. In the present embodiment, the pixel circuit unit PXC of the pixel PXij includes a first transistor T1 to a seventh transistor T7 and a capacitor Cst. In addition, each of the first transistor T1 to the seventh transistor T7 is a p-type transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, the present invention is not limited thereto, and the first transistor T1 to the seventh transistor T7 may be an n-type transistor having an oxide semiconductor as a semiconductor layer. In an embodiment, at least one of the first transistor T1 to the seventh transistor T7 may be an n-type transistor, and the rest may be p-type transistors. In addition, the circuit configuration of the pixel in the embodiment of the present invention is not limited to Figure 5 The configuration of the pixel circuit unit PXC may be modified and practiced.

[0089] Reference Figure 5 In the embodiment, a pixel PXij of the display device includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitor Cst, and at least one light emitting diode ED. This embodiment explains an example in which one pixel PXij includes one light emitting diode ED.

[0090] The j-1th first scan line SLj-1, the jth first scan line SLj, the j+1th second scan line SWLj+1, and the jth light emission control line EMLj can transmit the j-1th first scan signal SCj-1, the jth first scan signal SCj, the j+1th second scan signal SWj+1, and the jth light emission control signal EMj, respectively. The i-th data line DLi transmits a data signal Di. The data signal Di may have a value similar to that input to the display device DD (refer to FIG. Figure 4 ) corresponding to the voltage level of the image signal RGB. The first driving voltage line VL1, the second driving voltage line VL2 and the third driving voltage line VL3 can transmit the first driving voltage ELVDD, the second driving voltage ELVSS and the initialization voltage VINT respectively.

[0091] The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via the fifth transistor T5, a second electrode electrically connected to the anode of the light emitting diode ED via the sixth transistor T6, and a gate electrode connected to one end of the capacitor Cst. The first transistor T1 receives the data signal Di transmitted through the i-th data line DLi according to the switching operation of the second transistor T2 and provides a driving current Id to the light emitting diode ED.

[0092] The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the j-th first scan line SLj. The second transistor T2 can be turned on according to the j-th first scan signal SCj transmitted through the j-th first scan line SLj and transmits the data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1.

[0093] The third transistor T3 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the j-th first scan line SLj. The third transistor T3 can be turned on in response to the j-th first scan signal SCj transmitted via the j-th first scan line SLj, and is connected to the gate electrode and the second electrode of the first transistor T1, thereby diode-connecting the first transistor T1.

[0094] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to a third driving voltage line VL3 transmitting an initialization voltage VINT, and a gate electrode connected to the j-1th first scan line SLj-1. The fourth transistor T4 can be turned on in response to the j-1th first scan signal SCj-1 transmitted via the j-1th first scan line SLj-1 and transmit the initialization voltage VINT to the gate electrode of the first transistor T1 to perform an initialization operation for initializing the voltage of the gate electrode of the first transistor T1.

[0095] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1 , a second electrode connected to the first electrode of the first transistor T1 , and a gate electrode connected to the j-th light emission control line EMLj.

[0096] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light emitting diode ED, and a gate electrode connected to the j-th light emission control line EMLj.

[0097] The fifth transistor T5 and the sixth transistor T6 may be turned on substantially simultaneously according to the jth light emission control signal EMj transmitted through the jth light emission control line EMLj, and by this, the first driving voltage ELVDD is compensated and transmitted to the light emitting diode ED through the diode-connected first transistor T1.

[0098] The seventh transistor T7 includes a first electrode connected to the second electrode of the fourth transistor T4 , a second electrode connected to the second electrode of the sixth transistor T6 , and a gate electrode connected to the j+1th second scan line SWLj+1.

[0099] As described above, one end of the capacitor Cst is connected to the gate electrode of the first transistor T1, and the other end is connected to the first driving voltage line VL1. The cathode of the light emitting diode ED may be connected to the second driving voltage line VL2 for transmitting the second driving voltage ELVSS. The structure of the pixel PXij in the embodiment is not limited to Figure 5 The structure shown in FIG, and the number of transistors and capacitors included in one pixel and the connection relationship thereof can be modified in various ways.

[0100] Figure 6 Is used to explain Figure 5 Reference will be made to a timing diagram of an embodiment of the operation of a pixel PXij of a display device DD. Figure 5 and Figure 6 The operation of the display device DD in the embodiment is described.

[0101] Reference Figure 5 and Figure 6 During the initialization period within one frame F, a j-1th first scan signal SCj-1 of a low level is provided through the j-1th first scan line SLj-1. The fourth transistor T4 is turned on in response to the j-1th first scan signal SCj-1 of the low level, and the initialization voltage VINT is transmitted to the gate electrode of the first transistor T1 through the fourth transistor T4 to initialize the first transistor T1.

[0102] Next, during the data programming and compensation period, when a low-level j-th first scan signal SCj is provided via the j-th first scan line SLj, the third transistor T3 is turned on. The first transistor T1 is diode-connected and forward-biased due to the turned-on third transistor T3. Furthermore, the second transistor T2 is turned on by the low-level j-th first scan signal SCj. A compensation voltage is then applied to the gate electrode of the first transistor T1, where the compensation voltage is the data signal Di provided by the i-th data line DLi minus the threshold voltage of the first transistor T1. In other words, the gate voltage applied to the gate electrode of the first transistor T1 may be the compensation voltage.

[0103] The first driving voltage ELVDD and the compensation voltage are applied to both ends of the capacitor Cst, and charges corresponding to a voltage difference between the both ends may be stored in the capacitor Cst.

[0104] The seventh transistor T7 is turned on by receiving the low-level j+1th second scan signal SWj+1 through the j+1th second scan line SWLj+1. A portion of the driving current Id may leak through the seventh transistor T7 as a bypass current Ibp of the seventh transistor T7.

[0105] Even when the minimum current of the first transistor T1 displaying a black image flows as the drive current Id, the black image may not be displayed correctly when the light-emitting diode ED emits light. Therefore, due to the bypass current Ibp, the seventh transistor T7 in the pixel PXij in the embodiment of the present invention can disperse part of the minimum current of the first transistor T1 to a current path other than the current path on the organic light-emitting diode side. Here, the minimum current of the first transistor T1 means the current of the first transistor T1 is turned off under the condition that the gate-source voltage of the first transistor T1 is less than the threshold voltage. In this way, under the condition that the first transistor T1 is turned off, the minimum drive current (for example, a current of 10 picoamperes (pA) or less) is transmitted to the light-emitting diode ED to represent a black brightness image. When the minimum drive current for displaying a black image flows, the bypass effect of the bypass current Ibp is large. However, when a large drive current for displaying an image such as a typical image or a white image flows, there is a small effect of the bypass current Ibp. Therefore, when a driving current for displaying a black image flows, the light emission current Ied of the light-emitting diode ED has the minimum current required to reliably display a black image. The light emission current Ied of the light-emitting diode ED is the current obtained by subtracting the bypass current Ibp leaked through the seventh transistor T7 from the driving current Id. Therefore, contrast can be improved by achieving a precise black brightness image using the seventh transistor T7. In this embodiment, the bypass signal is the low-level j+1th second scan signal SWj+1, but is not limited thereto.

[0106] Next, during the light emission period, the j-th light emission control signal EMj supplied from the j-th light emission control line EMLj changes from a high level to a low level. During the light emission period, the fifth transistor T5 and the sixth transistor T6 are turned on by the j-th light emission control signal EMj. Then, a drive current Id is generated according to the voltage difference between the gate voltage of the gate electrode of the first transistor T1 and the first drive voltage ELVDD. The drive current Id is supplied to the light emitting diode ED through the sixth transistor T6, and then a light emission current Ied flows to the light emitting diode ED.

[0107] Figure 7 is a block diagram of an embodiment of a scan driving circuit SD according to the present invention.

[0108] Reference Figure 7 , the scan driving circuit SD includes a plurality of driving stages ST0 to STn+1.

[0109] Each of the plurality of driving stages ST0 to STn+1 is driven by Figure 4The driving controller 100 shown in FIG receives a scanning control signal SCS. The scanning control signal SCS includes a start signal FLM, a first clock signal CLK1, a second clock signal CLK2, and a mask signal. The mask signal may include a first mask signal MS1 and a second mask signal MS2. Each of the plurality of driving stages ST0 to STn+1 receives a first voltage VGL and a second voltage VGH. The first voltage VGL and the second voltage VGH may be obtained from Figure 4 The voltage generator 300 shown in FIG.

[0110] During the multi-frequency mode MFM, the first masking signal MS1 and the second masking signal MS2 may be used to mask some of the plurality of driving stages ST0 to STn+1 (ie, the second display area DA2 (refer to FIG. 1 ) at a predetermined level. Figure 1A ) corresponds to the driving stage) outputting the first scanning signal and the second scanning signal.

[0111] In an embodiment, the plurality of driving stages ST0 to STn+1 respectively output a plurality of first scan signals SC0 to SCn, and respectively output a plurality of second scan signals SW0 to SWn+1. The plurality of first scan signals SC0 to SCn may be provided to Figure 4 The plurality of first scan lines SL0 to SLn shown in FIG, and the plurality of second scan signals SW2 to SWn+1 can be provided to Figure 4 The plurality of second scan lines SWL2 to SWLn+1 are shown in FIG.

[0112] Figure 4 The display panel DP shown in FIG includes only the plurality of second scan lines SWL2 to SWLn+1, but does not include the second scan lines SWL0 and SWL1. Therefore, the second scan signal SW0 and the second scan signal SW1 output from the driving stage ST0 and the driving stage ST1 are respectively supplied only to the next driving stage ST1 and the next driving stage ST2, but not to the display panel DP.

[0113] The driver stage ST0 may receive the start signal FLM as a carry signal. Each of the plurality of driver stages ST1 to STn+1 has a dependent connection relationship with the previous driver stage so that the second scan signal output from the previous driver stage is received as a carry signal. In an embodiment, for example, the driver stage ST1 receives the second scan signal SW0 output from the previous driver stage ST0 as a carry signal, and the driver stage ST2 receives the second scan signal SW1 output from the previous driver stage ST1 as a carry signal. Figure 7It is shown that the j-th second scanning signal SWj outputted from the j-th driving stage STj is provided as a carry signal of the j+1-th driving stage (STj+1), but the present invention is not limited thereto. In an embodiment, the j-th second scanning signal SWj outputted from the j-th driving stage STj may be provided as a carry signal of the j+k-th driving stage (STj+k) (wherein j and k are natural numbers, respectively).

[0114] Figure 8 It is shown as an example Figure 7 The j-th driving stage STj (wherein j is a positive integer) among the plurality of driving stages ST0 to STn+1 shown in FIG. Figure 7 Each of the plurality of driving stages ST0 to STn+1 shown in FIG may include the same circuit configuration as the j-th driving stage STj. Hereinafter, the j-th driving stage STj may also be referred to as the driving stage STj.

[0115] Reference Figure 8 The driving stage STj includes a driving circuit DC, a masking circuit, first to fifth input terminals IN1 to IN5, first and second voltage terminals V1 and V2, and first and second output terminals OUT1 and OUT2. The masking circuit may include first and second masking circuits MSC1 and MSC2.

[0116] The driving circuit DC includes transistors PT1 to PT7 and capacitors PC1 and PC2 .

[0117] The driving circuit DC receives the first clock signal CLK1, the second clock signal CLK2 and the carry signal CRj-1 through the first input terminal IN1 to the third input terminal IN3. The driving circuit DC receives the first voltage VGL and the second voltage VGH through the first voltage terminal V1 and the second voltage terminal V2. The driving circuit DC outputs the j-th first scan signal SCj and the j-th second scan signal SWj through the first output terminal OUT1 and the second output terminal OUT2, respectively. The j-th second scan signal SWj can be provided to the next driver stage STj+1 as the carry signal CRj. The carry signal CRj-1 received through the third input terminal IN3 can be Figure 7 The j-1th second scan signal SWj-1 is outputted by the previous driving stage STj-1 shown in FIG. Figure 7 The carry signal of the driving stage ST0 shown in FIG. 1 may be the start signal FLM.

[0118] Figure 7The first input terminal IN1 of each of some driving stages (for example, odd-numbered driving stages) among the plurality of driving stages ST0 to STn+1 shown in FIG receives the first clock signal CLK1, and the second input terminal IN2 of each of the some driving stages (for example, odd-numbered driving stages) receives the second clock signal CLK2. In addition, Figure 7 The first input terminal IN1 of each of some driving stages (for example, even-numbered driving stages) among the multiple driving stages ST0 to STn+1 shown in the figure receives the second clock signal CLK2, and the second input terminal IN2 of each of some driving stages (for example, even-numbered driving stages) receives the first clock signal CLK1.

[0119] The transistor PT1 is connected between the third input terminal IN3 and the first node N1 and includes a gate electrode connected to the first input terminal IN1. The transistor PT2 is connected between the second voltage terminal V2 and the third node N3 and includes a gate electrode connected to the second node N2. The transistor PT3 is connected between the third node N3 and the first node N1 and includes a gate electrode connected to the second input terminal IN2.

[0120] Transistor PT4 is connected between the second node N2 and the first input terminal IN1 and includes a gate electrode connected to the first node N1. Transistor PT5 is connected between the second node N2 and the first voltage terminal V1 and includes a gate electrode connected to the first input terminal IN1. Transistor PT6 is connected between the second voltage terminal V2 and the second output terminal OUT2 and includes a gate electrode connected to the second node N2. Transistor PT7 is connected between the second output terminal OUT2 and the second input terminal IN2 and includes a gate electrode connected to the first node N1.

[0121] The capacitor PC1 is connected between the first node N1 and the second output terminal OUT2. The capacitor PC2 is connected between the second voltage terminal V2 and the second node N2.

[0122] The first masking circuit MSC1 includes a first masking transistor MT1. The first masking circuit MSC1 stops (or masks) the output of the j-th first scan signal SCj in response to a first masking signal MS1 received through the fourth input terminal IN4. The first masking transistor MT1 is connected between the second voltage terminal V2 and the first output terminal OUT1 and includes a gate electrode connected to the fourth input terminal IN4.

[0123] The second masking circuit MSC2 includes a second masking transistor MT2 . The second masking transistor MT2 is connected between the first output terminal OUT1 and the second output terminal OUT2 , and includes a gate electrode connected to the fifth input terminal IN5 .

[0124] Figure 9 yes Figure 7 1 is a timing diagram of an embodiment of operations of the j-1th driving stage STj-1, the j-th driving stage STj, and the j+1th driving stage STj+1 in the scan driving circuit SD shown in FIG.

[0125] Reference Figure 7 、 Figure 8 and Figure 9 , the first clock signal CLK1 and the second clock signal CLK2 have the same frequency as each other and are converted to an active level (eg, a low level) in different horizontal periods H. The horizontal period H indicates that the display panel DP (refer to Figure 4 ) is driven for a time period in which pixels PX in one row in the first direction DR1 are driven.

[0126] When the first masking signal MS1 has the second level (e.g., a high level), the first masking transistor MT1 is turned off, and thus the second voltage terminal V2 and the first output terminal OUT1 remain electrically separated from each other. When the second masking signal MS2 has the first level (e.g., a low level), the second masking transistor MT2 is turned on, and thus the first output terminal OUT1 and the second output terminal OUT2 remain electrically connected to each other.

[0127] The j-1th driving stage STj-1 operates as follows.

[0128] The j-1th driving stage STj- 1 receives the second clock signal CLK2 through the first input terminal IN1 and receives the first clock signal CLK1 through the second input terminal IN2 .

[0129] When the second clock signal CLK2 received through the first input terminal IN1 in the j-2th horizontal period Hj-2 is at a low level, the transistor PT1 in the drive circuit DC is turned on. When the transistor PT1 is turned on, the low-level carry signal CRj-2 is transmitted to the first node N1 through the transistor PT1. When the second clock signal CLK2 is at a low level, the transistor PT5 is turned on and the second node N2 is discharged to the first voltage VGL. When the second node N2 is at a low level, the transistor PT6 is turned on and a high-level j-1th second scan signal SWj-1 is output from the second output terminal OUT2. In addition, when the first node N1 is at a low level, the transistor PT7 is turned on, and the second output terminal OUT2 is maintained at a high level by the first clock signal CLK1 received by the second input terminal IN2.

[0130] When the second clock signal CLK2 is at a high level during the j-1th horizontal period Hj-1, transistor PT5 is turned off, and the second node N2 changes to a high level via the on-state transistor PT4, turning off transistor PT6. When the first clock signal CLK1 received through the second input terminal IN2 is at a low level, the first node N1 changes to a low level via the capacitor PC1, transistor PT7 turns on, and then the second output terminal OUT2 can output the j-1th second scan signal SWj-1 at a low level. Since the second masking transistor MT2 is turned on by the low-level second masking signal MS2, the j-1th first scan signal SCj-1 is also activated to a low level. In other words, during the j-1th horizontal period Hj-1, the j-1th driver stage STj-1 outputs the low-level j-1th first scan signal SCj-1 and the low-level j-1th second scan signal SWj-1.

[0131] In the jth horizontal period Hj, when the first masking signal MS1 transitions from high level to low level and the second masking signal MS2 transitions from low level to high level, the first masking transistor MT1 in the first masking circuit MSC1 is turned on and the second masking transistor MT2 in the second masking circuit MSC2 is turned off.

[0132] The j-th driving stage STj operates as follows.

[0133] The j-th driving stage STj receives the first clock signal CLK1 through the first input terminal IN1 and receives the second clock signal CLK2 through the second input terminal IN2.

[0134] When the first clock signal CLK1 is at a low level during the j-1th horizontal period Hj-1, the transistor PT1 is turned on. When the transistor PT1 is turned on, the low-level carry signal CRj-1 (i.e., the j-1th second scan signal SWj-1) is transmitted to the first node N1 through the transistor PT1. When the first clock signal CLK1 is at a low level, the transistor PT5 is turned on and the second node N2 is discharged to the first voltage VGL. When the second node N2 is at a low level, the transistor PT6 is turned on and a high-level j-th second scan signal SWj is output from the second output terminal OUT2. In addition, when the first node N1 is at a low level, the transistor PT7 is turned on, and the second output terminal OUT2 is maintained at a high level by the second clock signal CLK2 received by the second input terminal IN2.

[0135] When the first clock signal CLK1 is at a high level during the j-th horizontal period Hj, the second node N2 changes to a high level via the on-state transistor PT4, turning off the transistor PT6. When the second clock signal CLK2 received through the second input terminal IN2 is at a low level, the first node N1 changes to a low level via the capacitor PC1, turning on the transistor PT7, and then the second output terminal OUT2 can output the j-th second scan signal SWj at a low level. Here, since the second masking transistor MT2 is turned off by the high-level second masking signal MS2 and the first masking transistor MT1 is turned on by the low-level first masking signal MS1, the j-th first scan signal SCj remains at a high level. In other words, during the j-th horizontal period Hj, the j-th driver stage STj outputs the high-level j-th first scan signal SCj and the low-level j-th second scan signal SWj.

[0136] The j+1th driving stage STj+1 operates as follows.

[0137] The j+1th driving stage STj+1 receives the second clock signal CLK2 through the first input terminal IN1 and receives the first clock signal CLK1 through the second input terminal IN2 .

[0138] When the second clock signal CLK2 received through the first input terminal IN1 is at a low level, the transistor PT1 in the drive circuit DC is turned on. When the transistor PT1 is turned on, the high-level carry signal CRj is transmitted to the first node N1 through the transistor PT1. When the first node N1 is at a high level, the transistors PT3, PT4, and PT7 remain in the off state.

[0139] When the second clock signal CLK2 is at a low level during the j+1th horizontal period Hj+1, transistor PT5 is turned on. The second node N2 is maintained at a low level by the on-state transistor PT5, and transistor PT6 is turned on. Therefore, a high-level j+1th second scan signal SWj+1 can be output. Because the first masking transistor MT1 is turned on by the low-level first masking signal MS1, the j+1th first scan signal SCj+1 is maintained at a high level. In other words, during the j+1th horizontal period Hj+1, the j+1th driver stage STj+1 outputs a high-level j+1th first scan signal SCj+1 and a high-level j+1th second scan signal SWj+1.

[0140] Figure 10 The example shows the normal frequency mode NFM from Figure 4 The driving controller 100 shown in FIG. 1 supplies a signal to the scan driving circuit SD and an image data signal DATA to the data driving circuit 200 .

[0141] Reference Figure 4 、 Figure 7 and Figure 10 In the normal frequency mode NFM, the start signal FLM is activated to a low level 120 times per second. In other words, the start signal FLM is activated to a low level at the start time of each frame from the first frame F1 to the 120th frame F120. During the normal frequency mode NFM, the first mask signal MS1 may be maintained at a high level, and the second mask signal MS2 may be maintained at a low level. The duration of one frame in the normal frequency mode NFM may be a first duration (e.g., 8.34 ms).

[0142] The driving controller 100 may sequentially provide a data signal DSA1 corresponding to the first frame F1 to a data signal DSA120 corresponding to the 120th frame F120 as the image data signal DATA to the data driving circuit 200 .

[0143] Figure 11 The first display area DA1 (see Figure 1A ) has a first driving frequency of 80 Hz and the second display area DA2 (see Figure 1A ) is 40 Hz, Figure 4 The driving controller 100 shown in FIG. 1 supplies a signal to the scan driving circuit SD and an image data signal DATA to the data driving circuit 200 .

[0144] Reference Figure 4 、 Figure 7 and Figure 11 , the display device DD in the multi-frequency mode MFM makes the basic driving frequency (BDF) lower than the normal frequency (NF). In an embodiment, when the normal frequency (NF) is 120 Hz, the basic driving frequency (BDF) is 60 Hz, for example. When the basic driving frequency (BDF) is 60 Hz, the duration of one frame is 16.67 milliseconds (ms). The display device DD can display an image on the first display area DA1 (refer to FIG. 1 ) and the second display area DA2 (refer to FIG. 1 ) of the display panel DP during a duration (16.67 ms) corresponding to the basic driving frequency (BDF) in a full frame of the multi-frequency mode MFM, and display an image on the first display area DA1 of the display panel DP during a duration (for example, 8.34 ms) lower than the basic driving frequency (BDF) in a half frame. In the full frame, the image is displayed on the first display area DA1 and the second display area DA2, and in the half frame, the image is displayed only on the first display area DA1.

[0145] like Figure 11 As shown in FIG, when in the multi-frequency mode MFM, the first display area DA1 (refer to Figure 1A ) has a first driving frequency of 80 Hz and the second display area DA2 (refer to Figure 1A ) is 40 Hz, the start signal FLM is activated to a low level 80 times per second. In other words, the start signal FLM is activated to a low level at the start time of each frame from the first frame F1 to the 80th frame F80.

[0146] When the first display area DA1 (refer to Figure 1A ) has a first driving frequency of 80 Hz, and the second display area DA2 (refer to Figure 1A ) is 40 Hz, the duration of each of the odd-numbered frames F1, F3, F5, ..., and F79 and the duration of each of the even-numbered frames F2, F4, F6, ..., and F80 are different from each other. In an embodiment, the duration of each of the odd-numbered frames F1, F3, F5, ..., and F79 is 16.67 ms, and the duration of each of the even-numbered frames F2, F4, F6, ..., and F80 is 8.34 ms. In other words, the duration of the first frame F1 in the multi-frequency mode MFM is the same as the first duration (e.g., 16.67 ms) that is the duration of the base driving frequency (BDF), and the duration of the second frame F2 consecutive to the first frame F1 is a second duration that is shorter than the first duration.

[0147] When the first driving frequency is 80 Hz and the second driving frequency is 40 Hz in the multi-frequency mode MFM, for 1 second, the first image IM1 is displayed in the first display area DA1 in the first frame F1 to the 80th frame F80, and the second image IM2 can be displayed in the second display area DA2 in the odd-numbered frames F1, F3, ..., and F79 among the first frame F1 to the 80th frame F80. In other words, the second image IM2 is not displayed in the second display area DA2 in the even-numbered frames F2, F4, ..., and F80.

[0148] When the kth driving stage STk among the plurality of driving stages ST0 to STn+1 in the scan driving circuit SD corresponds to the start position of the second display area DA2, the first masking signal MS1 may transition to a low level and the second masking signal MS2 may transition to a high level to mask the plurality of first scan signals SCk to SCn and the plurality of second scan signals SWk+1 to SWn+1 output from the plurality of driving stages STk to STn+1 in the even-numbered frames F2, F4, ..., and F80 of the multi-frequency mode MFM. The plurality of driving stages STk to STn+1 may not activate the plurality of first scan signals SCk to SCn and the plurality of second scan signals SWk+1 to SWn+1 to a low level in response to the low-level first masking signal MS1 and the high-level second masking signal MS2. When the even-numbered frame (e.g., F2) ends and the next odd-numbered frame (e.g., F3) begins, the first masking signal MS1 transitions to a high level and the second masking signal MS2 transitions to a low level to prepare for the new frame.

[0149] Figure 12 A plurality of first scan signals SC0 to SC3840 output from the scan driving circuit SD in the multi-frequency mode MFM are exemplarily shown.

[0150] Figure 12 The first display area DA1 (refer to Figure 1A ) has a first driving frequency of 80 Hz and the second display area DA2 (refer to Figure 1A ) is 40Hz, Figure 7 The scan driving circuit SD shown in FIG. 8 outputs a plurality of first scan signals SC0 to SC3840 .

[0151] Assumptions Figure 1A The first display area DA1 shown in FIG. 1 includes pixels in the 0th to 1920th rows, and the second display area DA2 includes pixels in the 1921st to 3840th rows.

[0152] Reference Figure 4 、 Figure 7 and Figure 12 , the start signal FLM in the multi-frequency mode MFM is activated to a low level 80 times per second. In other words, in each frame from the first frame F1 to the 80th frame F80, the start signal FLM is activated to a low level.

[0153] When the first display area DA1 (see Figure 1A ) is 80 Hz, and the second display area DA2 (see Figure 1A) is 40 Hz, the duration of each of the odd-numbered frames F1, F3, F5, ... and F79 is 16.67 ms, and the duration of each of the even-numbered frames F2, F4, F6, ... and F80 is 8.34 ms.

[0154] In odd-numbered frames F1 , F3 , F5 , . . . , and F79 of the multi-frequency mode MFM, the plurality of driving stages ST0 to STn in the scan driving circuit SD may sequentially output first scan signals SC0 to SCn.

[0155] When it is assumed that the 1921st driving stage ST1921 among the multiple driving stages ST0 to ST3840 in the scan driving circuit SD corresponds to the starting position of the second display area DA2, the multiple driving stages ST0 to ST1920 sequentially activate the multiple first scanning signals SC0 to SC1920 to a low level in the even-numbered frames F2, F4, F6, ... and F80 of the multi-frequency mode MFM, and the multiple driving stages ST1921 to ST3840 maintain the first scanning signal SC1921 at a high level.

[0156] In this manner, the plurality of driver stages ST0 to ST1920 corresponding to the first display area DA1 among the plurality of driver stages ST0 to ST3840 in the scan drive circuit SD operate sequentially for each frame, and a first image IM1 can be displayed in the first display area DA1. The plurality of driver stages ST1921 to ST3840 corresponding to the second display area DA2 among the plurality of driver stages ST0 to ST3840 in the scan drive circuit SD operate sequentially only in some frames (e.g., odd-numbered frames F1, F3, and F5), and a second image IM2 can be displayed on the second display area DA2. In addition, the plurality of driver stages ST1921 to ST3840 corresponding to the second display area DA2 among the plurality of driver stages ST0 to ST3840 in the scan drive circuit SD do not operate in some frames (e.g., even-numbered frames F2, F4, F6, ..., F80), thereby reducing power consumption.

[0157] Figure 13 The first display area DA1 (refer to Figure 1A ) is 119 Hz, and the second display area DA2 (refer to Figure 1A ) is 1Hz, Figure 4 The driving controller 100 shown in FIG. 1 supplies a signal to the scan driving circuit SD and an image data signal DATA to the data driving circuit 200 .

[0158] Reference Figure 4 、 Figure 7 and Figure 13 , the start signal FLM in the multi-frequency mode MFM is activated to a low level 119 times per second. In other words, in each frame from the first frame F1 to the 119th frame F119, the start signal FLM is activated to a low level.

[0159] When the first display area DA1 (refer to Figure 1A ) is 119 Hz, and the second display area DA2 (refer to Figure 1A ) is 1 Hz, the duration of the first frame F1 and the duration of each of the other frames F2 to F119 are different from each other. In an embodiment, for example, the duration of the first frame F1 is 16.67 ms, and the duration of each of the second frame F2 to the 119th frame F119 is 8.34 ms.

[0160] When the kth driving stage STk among the plurality of driving stages ST0 to STn+1 in the scan driving circuit SD corresponds to the start position of the second display area DA2, the first masking signal MS1 may transition to a low level, and the second masking signal MS2 may transition to a high level, so as to mask the plurality of first scan signals SCk to SCn and the plurality of second scan signals SWk to SWn+1 output from the plurality of driving stages STk to STn+1 in the plurality of frames F2 to F119 of the multi-frequency mode MFM. The plurality of driving stages STk to STn+1 may maintain the plurality of first scan signals SC0 to SCn and the plurality of second scan signals SW0 to SWn+1 at a high level in response to the low-level first masking signal MS1 and the high-level second masking signal MS2. In an embodiment, for example, when the second frame F2 ends and the third frame F3 begins, the first masking signal MS1 transitions to a high level, and the second masking signal MS2 transitions to a low level to prepare for the new frame.

[0161] During the multi-frequency mode MFM, the display device DD may set the basic driving frequency (BDF) to 60 Hz lower than 120 Hz as the normal frequency (NF). Table 2 below exemplarily shows power consumption in milliwatts (mW) according to driving frequencies of the display device DD.

[0162] [Table 2]

[0163] Driving frequency Still Image dynamic image 120Hz 528.1mW 538.9mW 60Hz 304.4mW 336.2mW

[0164] As recognized from Table 2, when a still image or a moving image is displayed on both the first display area DA1 and the second display area DA2 of the display device DD, the driving frequency is reduced from 120 Hz to 60 Hz, which results in a reduction in power consumption.

[0165] In addition, if Figure 13As shown in FIG, when the first driving frequency (DF1) of the first display area DA1 displaying a moving image is set to 119 Hz and the second driving frequency (DF2) of the second display area DA2 displaying a still image is set to 1 Hz, degradation of display quality can be minimized. In other words, power consumption can be reduced without reducing the display quality of the image displayed on the display panel DP.

[0166] Figure 14 The first display area DA1 (see Figure 1A ) has a first driving frequency of 128 Hz, and the second display area DA2 (see Figure 1A ) is 64Hz, Figure 4 The driving controller 100 shown in FIG. 1 supplies a signal to the scan driving circuit SD and an image data signal DATA to the data driving circuit 200 .

[0167] Reference Figure 4 、 Figure 7 and Figure 14 , the display device DD in the multi-frequency mode MFM makes the basic driving frequency (BDF) lower than the normal frequency (NF). In an embodiment, when the normal frequency (NF) is 120 Hz, the basic driving frequency (BDF) is, for example, 96 Hz. When the basic driving frequency (BDF) is 96 Hz, the duration of one frame is 10.41 ms. The display device DD can display an image in the first display area DA1 (refer to FIG. 1 ) and the second display area DA2 (refer to FIG. 1 ) of the display panel DP during a duration (10.41 ms) corresponding to the basic driving frequency (BDF) in a full frame of the multi-frequency mode MFM, and display an image in the first display area DA1 of the display panel DP during a duration (for example, 5.2 ms) lower than the basic driving frequency (BDF) in a half frame. A full frame is a frame in which an image is displayed in both the first display area DA1 and the second display area DA2, and a half frame is a frame in which an image is displayed only in the first display area DA1.

[0168] like Figure 14 As shown in FIG, when in the multi-frequency mode MFM, the first display area DA1 (refer to Figure 1A ) has a first driving frequency of 128 Hz and the second display area DA2 (refer to Figure 1A ) is 64 Hz, the start signal FLM is activated to a low level 128 times per second. In other words, the start signal FLM is activated to a low level at the start time of each frame from the first frame F1 to the 128th frame F128.

[0169] When the first display area DA1 (refer to Figure 1A) has a first driving frequency of 128 Hz, and the second display area DA2 (refer to Figure 1A ) is 64 Hz, the duration of each of the odd-numbered frames F1, F3, F5, ..., and F127 and the duration of each of the even-numbered frames F2, F4, F6, ..., and F128 are different from each other. In an embodiment, for example, the duration of each of the odd-numbered frames F1, F3, F5, ..., and F127 is 10.41 ms, and the duration of each of the even-numbered frames F2, F4, F6, ..., and F128 is 5.2 ms. In other words, the duration of the first frame F1 in the multi-frequency mode MFM is the same as the first duration (e.g., 10.41 ms) that is the duration of the base driving frequency (BDF), and the duration of the second frame F2 subsequent to the first frame F1 is a second duration that is shorter than the first duration.

[0170] When the first driving frequency is 128 Hz and the second driving frequency is 64 Hz in the multi-frequency mode MFM, for 1 second, the first image IM1 is displayed in the first display area DA1 in the first frame F1 to the 128th frame F128, and the second image IM2 can be displayed in the second display area DA2 in the odd-numbered frames F1, F3, ..., and F127 among the first frame F1 to the 128th frame F128. In other words, the second image IM2 is not displayed in the second display area DA2 in the even-numbered frames F2, F4, ..., and F128.

[0171] When the kth driving stage STk among the plurality of driving stages ST0 to STn+1 in the scan driving circuit SD corresponds to the start position of the second display area DA2, the first masking signal MS1 may transition to a low level and the second masking signal MS2 may transition to a high level to mask the plurality of first scan signals SCk to SCn and the plurality of second scan signals SWk+1 to SWn+1 output from the plurality of driving stages STk to STn+1 in the even-numbered frames F2, F4, ..., and F128 of the multi-frequency mode MFM. The plurality of driving stages STk to STn+1 may not activate the plurality of first scan signals SCk to SCn and the plurality of second scan signals SWk+1 to SWn+1 to a low level in response to the low-level first masking signal MS1 and the high-level second masking signal MS2. When the even-numbered frame (e.g., F2) ends and the next odd-numbered frame (e.g., F3) begins, the first masking signal MS1 transitions to a high level and the second masking signal MS2 transitions to a low level to prepare for the new frame.

[0172] Figure 15 The first display area DA1 (see Figure 1A) has a first driving frequency of 144 Hz, and the second display area DA2 (see Figure 1A ) is 30Hz, Figure 4 The driving controller 100 shown in FIG. 1 supplies a signal to the scan driving circuit SD and an image data signal DATA to the data driving circuit 200 .

[0173] Reference Figure 4 、 Figure 7 and Figure 15 , the display device DD in the multi-frequency mode MFM makes the basic driving frequency (BDF) lower than the normal frequency (NF). In an embodiment, when the normal frequency (NF) is 120 Hz, the basic driving frequency (BDF) is, for example, 96 Hz. When the basic driving frequency (BDF) is 96 Hz, the duration of one frame is 10.41 ms. The display device DD can display an image in the first display area DA1 (refer to FIG. 1 ) and the second display area DA2 (refer to FIG. 1 ) of the display panel DP during a duration (10.41 ms) corresponding to the basic driving frequency (BDF) in a full frame of the multi-frequency mode MFM, and display an image in the first display area DA1 of the display panel DP during a duration (for example, 5.2 ms) lower than the basic driving frequency (BDF) in a half frame. A full frame is a frame in which an image is displayed in both the first display area DA1 and the second display area DA2, and a half frame is a frame in which an image is displayed only in the first display area DA1.

[0174] like Figure 15 As shown in FIG, when in the multi-frequency mode MFM, the first display area DA1 (refer to Figure 1A ) has a first driving frequency of 144 Hz and the second display area DA2 (refer to Figure 1A ) is 30 Hz, the start signal FLM is activated to a low level 144 times per second. In other words, the start signal FLM is activated to a low level at the start time of each frame from the first frame F1 to the 144th frame F144.

[0175] When the first display area DA1 (refer to Figure 1A ) has a first driving frequency of 144 Hz and the second display area DA2 (refer to Figure 1A ) is 30 Hz, the duration of the first frame F1 and the duration of each of the other frames F2 to F144 are different from each other. In an embodiment, for example, the duration of the first frame F1 is 10.41 ms, and the duration of each of the second frame F2 to the 144th frame F144 is 5.2 ms.

[0176] During the multi-frequency mode MFM, the display device DD may reduce power consumption by setting the basic driving frequency (BDF) to 96 Hz, which is lower than 120 Hz as the normal frequency (NF).

[0177] In addition, when the first driving frequency (DF1) of the first display area DA1 displaying a moving image is set to 144 Hz, and the second driving frequency (DF2) of the second display area DA2 displaying a still image is set to 30 Hz, degradation in display quality can be minimized. In other words, power consumption can be reduced without reducing the display quality of the image displayed on the display panel DP.

[0178] Figure 16 The example shows the multi-frequency mode MFM from Figure 4 The driving controller 100 shown in FIG. 1 is to provide a start signal to the scan driving circuit SD.

[0179] When the normal frequency is 120 Hz, the basic driving frequency in the multi-frequency mode MFM can be set to 60 Hz. When the basic driving frequency (BDF) is 60 Hz, the duration of the full frame FF is 16.67 ms, and the duration of the half frame HF is 8.34 ms. The full frame FF is the first display area DA1 (see Figure 1A ) and the second display area DA2 (see Figure 1A ) is a frame in which all of the display area DA1 is driven, and the half frame HF is a frame in which only the first display area DA1 is driven.

[0180] The period FT1 of the start signal FLM1 includes one full frame FF and one half frame HF, and its duration is 25.5 ms.

[0181] The first driving frequency (DF1) of the first display area DA1 may be calculated as Equation 1 below.

[0182] DF1=1000ms / ((FFT+HFT) / (1+HFN)) (1)

[0183] The second driving frequency (DF2) of the second display area DA2 may be calculated as Equation 2 below.

[0184] DF2=1000ms / (FFT+HFT) (2)

[0185] In Equation 1 and Equation 2, FFT represents the duration of a full frame FF, HFT represents the duration of a half frame HF, and HFN represents the number of half frames HF in the period FT1.

[0186] Since the basic driving frequency is 60 Hz, the duration of the full frame FF in the period FT1 of the start signal FLM1 is 16.67 ms, the duration of the half frame HF is 8.34 ms, and the number of half frames HF is 1, so the first driving frequency (DF1) of the first display area DA1 is 1000 ms / ((16.67 ms+8.34 ms) / (1+1))=80 Hz, and the second driving frequency (DF2) of the second display area DA2 is 1000 ms / (16.67 ms+8.34 ms)=40 Hz.

[0187] The period FT2 of the start signal FLM2 includes one full frame FF and two half frames HF1 and HF2, and its duration is 33.3 ms.

[0188] Since the basic driving frequency is 60 Hz, the duration of the full frame FF in the period FT2 of the start signal FLM2 is 16.67 ms, the duration of the half frame HF is 8.34 ms, and the number of half frames HF is 2, the first driving frequency (DF1) of the first display area DA1 is 1000 ms / ((16.67 ms+16.68 ms) / (1+2))=90 Hz, and the second driving frequency (DF2) of the second display area DA2 is 1000 ms / (16.67 ms+16.68 ms)=30 Hz.

[0189] The period FT3 of the start signal FLM3 includes one full frame FF and 118 half frames HF1, HF2, . . . and HF118, and its duration is 1000 ms.

[0190] Since the basic driving frequency is 60 Hz, the duration of the full frame FF in the period FT3 of the start signal FLM3 is 16.67 ms, the duration of the half frame HF is 8.34 ms, and the number of half frames HF1, HF2, ... and HF118 is 118, the first driving frequency (DF1) of the first display area DA1 is 1000 ms / ((16.67 ms+983.32 ms) / (1+118))=119 Hz, and the second driving frequency (DF2) of the second display area DA2 is 1000 ms / (16.67 ms+983.32 ms)=1 Hz.

[0191] Table 3 below exemplarily shows a first driving frequency (DF1) of the first display area DA1 and a second driving frequency (DF2) of the second display area DA2 according to the number of half frames (HF) in the period of the start signal FLM when the basic driving frequency (BDF) is 60 Hz and the ratio of the length of the first display area DA1 to the length of the second display area DA2 in the second direction DR2 is 1:1. Table 3 shows the calculation results assuming that the basic driving frequency (BDF) is 60 Hz, the duration of a full frame is 16.66 ms, and the duration of a half frame (HF) is 8.33 ms.

[0192] [Table 3]

[0193]

[0194] Table 4 below exemplarily shows a first driving frequency (DF1) of the first display area DA1 and a second driving frequency (DF2) of the second display area DA2 according to the number of half frames (HF) in the period of the start signal FLM when the basic driving frequency (BDF) is 96 Hz and the ratio of the length of the first display area DA1 to the length of the second display area DA2 in the second direction DR2 is 1:1. Table 4 shows the calculation results assuming that the basic driving frequency (BDF) is 96 Hz, the duration of the full frame is 10.41 ms, and the duration of the half frame (HF) is 5.2 ms.

[0195] [Table 4]

[0196]

[0197] Table 5 below exemplarily shows a first driving frequency (DF1) of the first display area DA1 and a second driving frequency (DF2) of the second display area DA2 according to the number of half frames (HF) in the period of the start signal FLM when the basic driving frequency (BDF) is 120 Hz and the ratio of the length of the first display area DA1 to the length of the second display area DA2 in the second direction DR2 is 1:1. Table 5 shows the calculation results assuming that the basic driving frequency (BDF) is 120 Hz, the duration of the full frame is 8.34 ms, and the duration of the half frame (HF) is 4.17 ms.

[0198] [Table 5]

[0199]

[0200]

[0201] A display device having such a configuration can drive the display panel at a lower-than-normal drive frequency to reduce power consumption, and can also drive a first display area displaying a moving image and a second display area displaying a still image at different frequencies. Specifically, the first drive frequency for the first display area displaying the moving image is higher than the second drive frequency for the second display area displaying the still image. This allows power consumption to be reduced while minimizing degradation in the display quality of the moving image.

[0202] Although exemplary embodiments of the present invention have been described, it will be understood that the present invention should not be limited to these exemplary embodiments, but that various changes and modifications may be made by those skilled in the art within the spirit and scope of the present invention as defined in the appended claims. In addition, the embodiments disclosed in the inventive concept are not intended to limit the technical spirit of the inventive concept, and the protection scope of the present invention should be interpreted based on the appended claims, and it will be understood that all technical spirits included in the equivalent scope of the present invention are included within the protection scope of the present invention.

Claims

1. A display device, comprising: a display panel including a plurality of pixels respectively connected to a plurality of data lines and a plurality of scan lines; a data driving circuit, wherein the data driving circuit drives the plurality of data lines; a scan driving circuit, wherein the scan driving circuit drives the plurality of scan lines; as well as A drive controller, wherein the drive controller: Receive image signals and control signals, controlling the data driving circuit and the scan driving circuit according to an operation mode, dividing the display panel into a first display area and a second display area according to the operation mode, outputting a start signal indicating the start of one frame and a mask signal for indicating the start of the second display area, When the operation mode is the normal frequency mode, the basic driving frequency is set to the normal frequency, and When the operation mode is a multi-frequency mode, a basic driving frequency is set to a frequency lower than a normal frequency and the start signal and the masking signal are output, so that the first display area operates at a first driving frequency and the second display area operates at a second driving frequency lower than the first driving frequency, The scan driving circuit sequentially drives the plurality of scan lines in synchronization with the start signal, and stops driving the scan line corresponding to the second display area among the plurality of scan lines in response to the mask signal. The first driving frequency is higher than the basic driving frequency of the multi-frequency mode, and the second driving frequency is lower than the basic driving frequency of the multi-frequency mode.

2. The display device according to claim 1, wherein During the multi-frequency mode, a first frame has a first duration, and a second frame consecutive to the first frame has a second duration, and the second duration is shorter than the first duration.

3. The display device according to claim 2, wherein: The first duration of the first frame during the multi-frequency mode is longer than the first duration of the first frame during the normal frequency mode.

4. The display device according to claim 2, wherein The driving controller provides image data signals corresponding to the first display area and the second display area to the data driving circuit during the first frame of the multi-frequency mode, and provides image data signals corresponding to the first display area to the data driving circuit during the second frame of the multi-frequency mode.

5. The display device according to claim 1, wherein The driving controller provides image data signals corresponding to the first display area and the second display area to the data driving circuit in each frame during the normal frequency mode. The display device according to claim 1 , wherein: The scan driving circuit includes a plurality of driving stages, each of which drives a corresponding scan line among the plurality of scan lines. Wherein, each of the plurality of driving stages comprises: a driving circuit that outputs a first scanning signal to a first output terminal in response to a clock signal and a carry signal from the driving controller; and A masking circuit is configured to stop the driving circuit from outputting the first scanning signal in response to the masking signal.

7. The display device according to claim 6, wherein: A first driving stage among the plurality of driving stages receives the start signal as the carry signal.

8. The display device according to claim 7, wherein: The driving circuit outputs a second scanning signal to a second output terminal in response to the clock signal and the carry signal.

9. The display device according to claim 8, wherein Among the plurality of driving stages, the second scan signal output from the j-th driving stage is supplied to the j+k-th driving stage as the carry signal, wherein j and k are natural numbers, respectively.

10. The display device according to claim 8, wherein The mask signal includes a first mask signal and a second mask signal, Wherein, the masking circuit includes: a first masking circuit electrically connecting a first voltage terminal and the first output terminal in response to the first masking signal; and A second masking circuit electrically connects the first output terminal and the second output terminal in response to the second masking signal.

11. The display device according to claim 10, wherein: During the multi-frequency mode, the first masking circuit electrically connects the first voltage terminal and the first output terminal in response to the first masking signal, and During the multi-frequency mode, the second masking circuit electrically disconnects the first output terminal and the second output terminal in response to the second masking signal.

12. A display device comprising: a display panel in which a first non-folding area, a folding area, and a second non-folding area are defined in a plan view, and the display panel includes a plurality of pixels respectively connected to a plurality of data lines and a plurality of scan lines; a data driving circuit, wherein the data driving circuit drives the plurality of data lines; a scan driving circuit, wherein the scan driving circuit drives the plurality of scan lines; as well as A drive controller, wherein the drive controller: Receive image signals and control signals, controlling the data driving circuit and the scan driving circuit according to an operation mode, dividing the display panel into a first display area and a second display area according to the operation mode, outputting a start signal indicating the start of one frame and a mask signal for indicating the start of the second display area, When the operation mode is the normal frequency mode, the basic driving frequency is set to the normal frequency, When the operation mode is a multi-frequency mode, the basic driving frequency is set to a frequency lower than the normal frequency and the start signal and the masking signal are output, so that the first display area operates at a first driving frequency and the second display area operates at a second driving frequency lower than the first driving frequency, The scan driving circuit sequentially drives the plurality of scan lines in synchronization with the start signal, and stops driving the scan line corresponding to the second display area among the plurality of scan lines in response to the mask signal. The first driving frequency is higher than the basic driving frequency of the multi-frequency mode, and the second driving frequency is lower than the basic driving frequency of the multi-frequency mode.

Images