High electron mobility transistor and high voltage semiconductor device

Abstract

A high electron mobility transistor includes a substrate, a III-V channel layer, a III-V barrier layer, a III-V cap layer, a source electrode, a first drain electrode, a second drain electrode, and a connection. The III-V channel layer, the III-V barrier layer, and the III-V cap layer are sequentially disposed on the substrate. The source electrode is disposed on one side of the III-V cap layer, and the first drain electrode and the second drain electrode are disposed on another side of the III-V cap layer. A bottom surface of the first drain electrode is separated from a bottom surface of the second drain electrode, and a composition of the first drain electrode is different from a composition of the second drain electrode. The connection is electrically connected to the first drain electrode and the second drain electrode.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and in particular to a high electron mobility transistor and a high voltage semiconductor device. Background Technology

[0002] In semiconductor technology, III-V group semiconductor compounds can be used to form various integrated circuit devices, such as high-power field-effect transistors (FETs), high-frequency transistors, or high electron mobility transistors (HEMTs). HEMTs are a type of transistor with a two-dimensional electron gas (2-DEG), where the 2-DEG is adjacent to the junction (i.e., heterojunction) between two materials with different band gaps. Because HEMTs do not use doped regions as carrier channels but rather use 2-DEGs, they possess several attractive characteristics compared to known metal-oxide-semiconductor field-effect transistors (MOSFETs), such as high electron mobility and the ability to transmit signals at high frequencies.

[0003] For known HEMTs, an ohmic contact is formed between the drain electrode and the underlying semiconductor layer to reduce the contact resistance between them. However, during the formation of this ohmic contact, the metal in the drain electrode often reacts with the underlying semiconductor layer to form spiking defects. This results in a larger local electric field near the spiking defects, leading to unwanted leakage current and increasing the cutoff current (Iout) of the semiconductor device. OFF This reduces breakdown voltage and reliability. Summary of the Invention

[0004] In view of this, it is necessary to propose an improved high electron mobility transistor to overcome the shortcomings of known high electron mobility transistors.

[0005] According to an embodiment of the present invention, a high electron mobility transistor is provided, comprising a substrate, a group III-V channel layer, a group III-V barrier layer, a group III-V capping layer, a source electrode, a first drain electrode, a second drain electrode, and a connection portion. The group III-V channel layer, the group III-V barrier layer, and the group III-V capping layer are sequentially disposed on the substrate. The source electrode is disposed on one side of the group III-V capping layer, and the first drain electrode and a second drain electrode are disposed on the other side of the group III-V capping layer. The bottom surface of the first drain electrode is separate from the bottom surface of the second drain electrode, and the composition of the first drain electrode is different from that of the second drain electrode. The connection portion is electrically connected to the first drain electrode and the second drain electrode.

[0006] According to another embodiment of the present invention, a high-voltage semiconductor device is provided, comprising a semiconductor layer, a semiconductor capping layer, a source electrode, at least two drain electrodes, and an interlayer dielectric layer. A gate structure is disposed on the semiconductor layer. The source electrode is disposed on one side of the semiconductor capping layer, and the drain electrode is disposed on the other side of the semiconductor capping layer, wherein the drain electrode includes a Schottky contact metal and an ohmic contact metal. The interlayer dielectric layer is disposed between the Schottky contact metal and the ohmic contact metal.

[0007] According to an embodiment of the present invention, by providing a first drain electrode and a second drain electrode that are laterally separated from each other, and by forming a Schottky contact between the first drain electrode and the underlying semiconductor layer, and an ohmic contact between the second drain electrode and the underlying semiconductor layer, the surface electric field distribution of the high-voltage semiconductor device can be improved, thereby reducing the device's cutoff current (Ik). OFF This also avoids excessively increasing the contact area between the bottom surface of the drain electrode and the semiconductor layer, thus preventing an increase in the on-resistance (R) of the semiconductor device. ON The increase of ). Attached Figure Description

[0008] To facilitate understanding, the accompanying drawings and detailed textual descriptions are provided while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which illustrate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale; therefore, the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0009] Figure 1 This is a schematic cross-sectional view of a high-voltage semiconductor device having multiple drain electrodes, as illustrated in an embodiment of the present invention.

[0010] Figure 2 According to an embodiment of the present invention, along Figure 1 A top view of a high-voltage semiconductor device, drawn along the A-A' tangent.

[0011] Figure 3 This is a schematic cross-sectional view of a high-voltage semiconductor device having multiple drain electrodes, as illustrated in an embodiment of the present invention.

[0012] Figure 4 This is a schematic cross-sectional view of a high-voltage semiconductor device having multiple drain electrodes, as illustrated in an embodiment of the present invention.

[0013] Figure 5 This is a cross-sectional schematic diagram of a high-voltage semiconductor device having a III-V channel layer, a III-V barrier layer, a III-V capping layer, and an interlayer dielectric layer disposed on a substrate, according to an embodiment of the present invention.

[0014] Figure 6 This is a cross-sectional schematic diagram of a high-voltage semiconductor device having a gate electrode and a first drain electrode disposed in an interlayer dielectric layer according to an embodiment of the present invention.

[0015] Figure 7 This is a cross-sectional schematic diagram of a high-voltage semiconductor device having a source contact hole and a second drain contact hole in the interlayer dielectric layer according to an embodiment of the present invention.

[0016] Figure 8 This is a schematic cross-sectional view of a high-voltage semiconductor device having a source electrode and a second drain electrode disposed in an interlayer dielectric layer according to an embodiment of the present invention.

[0017] Figure 9 This is a flowchart of a method for manufacturing a high-voltage semiconductor device according to an embodiment of the present invention.

[0018] The annotations in the attached figures are explained as follows:

[0019] 10: High electron mobility transistor; 10': High electron mobility transistor;

[0020] 10": High electron mobility transistor; 100: Substrate; 102: Buffer layer; 104: III-V channel layer;

[0021] 106: III-V barrier layer; 112: III-V capping layer; 114: Etch stop layer; 116: Passivation layer;

[0022] 120: Two-dimensional electron gas region; 122: Two-dimensional electron gas cutoff region; 124: First interlayer dielectric layer;

[0023] 126: Second interlayer dielectric layer; 128: Insulating structure; 130: Gate contact hole; 132: Source contact hole;

[0024] 134: First drain contact hole; 136: Second drain contact hole; 138: Opening; 140: Gate electrode;

[0025] 142: First drain electrode; 142': First drain electrode; 143: Bottom surface; 143': Bottom surface;

[0026] 144: Source electrode; 146: Field plate; 148: Second drain electrode; 150: Conductive plug

[0027] 150': Conductive plug; 152: Conductive wire; 154: Third interlayer dielectric layer; 160: Stack structure;

[0028] 200: Method; 202: Step; 204: Step; 206: Step; 208: Step; 210: Step

[0029] L GD Distance; L DD : distance; L' DD : Distance; W: Base width; W': Base width Detailed Implementation

[0030] This invention provides several different embodiments for implementing various features of the invention. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following description of "a first feature forming on or above a second feature" can mean "the first feature and the second feature are in direct contact," or it can mean "there are other features between the first feature and the second feature," such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of this invention may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and not to indicate any correlation between different embodiments and / or configurations.

[0031] Furthermore, for the spatially related descriptive terms mentioned in this invention, such as "below," "low," "down," "above," "above," "below," "top," "bottom," and similar terms, for ease of description, their use is to describe the relative relationship between one element or feature and another (or more) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the semiconductor device during use and operation. As the orientation of the semiconductor device varies (rotation 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should be interpreted in a similar manner.

[0032] Although the present invention uses terms such as first, second, third, etc., to describe various elements, components, regions, layers, and / or sections, it should be understood that such elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the elements, nor do they represent the arrangement order of one element with another, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be named as a second element, component, region, layer, or section.

[0033] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, the meaning of "about" or "substantially" may be implied even without specific specification.

[0034] In this invention, a "group III-V semiconductor" refers to a compound semiconductor comprising at least one group III element and at least one group V element. The group III element may be boron (B), aluminum (Al), gallium (Ga), or indium (In), while the group V element may be nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). Further, a "group III-V semiconductor" may include: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs), analogues thereof, or combinations of the above compounds, but is not limited thereto. In addition, depending on the requirements, III-V semiconductors may also include dopants to form III-V semiconductors with specific conductivity types, such as N-type or P-type III-V semiconductors.

[0035] Although the invention is described below by way of specific embodiments, the inventive principles of the invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted; these omitted details fall within the scope of knowledge of those skilled in the art.

[0036] This invention relates to a high-voltage semiconductor device or a high electron mobility transistor (HEMT), such as a power switching transistor that can be used as a voltage converter. Compared to silicon power transistors, III-V HEMTs have a wider bandgap, resulting in lower on-state resistance (R0). ON It features low switching loss.

[0037] Figure 1 This is a schematic cross-sectional view of a high-voltage semiconductor device according to an embodiment of the present invention. Figure 1As shown, a high-voltage semiconductor device, such as an enhancement-mode high electron mobility transistor 10, is disposed on a substrate 100. A buffer layer 102, a III-V channel layer (or III-V channel layer) 104, a III-V barrier layer (or III-V barrier layer) 106, a passivation layer 116, and at least one interlayer dielectric layer (e.g., a first interlayer dielectric layer 124, a second interlayer dielectric layer 126, and a third interlayer dielectric layer 154) may be disposed on both sides of the III-V channel layer 104 and the III-V barrier layer 106.

[0038] The stack structure 160 includes a III-V capping layer 112 and an etch stop layer 114 stacked sequentially, disposed on the surface of the III-V barrier layer 106, and covered by a first interlayer dielectric layer 124. A gate electrode 140 can be disposed within a gate contact hole 130 of the first interlayer dielectric layer 124. Because the stack structure 160 can be exposed from the gate contact hole 130, the gate electrode 140 is electrically connected to the underlying stack structure 160.

[0039] The source electrode 144 can be disposed on one side of the stack structure 160 and oriented within the source contact hole 132 in the first interlayer dielectric layer 124, forming an ohmic contact with the underlying semiconductor layer, such as the III-V channel layer 104. A field plate 146 can be disposed along the top surface of the second interlayer dielectric layer 126, extending over the stack structure 160. The field plate 146 can be electrically connected to the source electrode 144 to modulate the electric field distribution within the semiconductor layer (e.g., the III-V channel layer 104 and / or the III-V barrier layer 106). According to one embodiment of the invention, the field plate 146 and the source electrode 144 can be formed using the same deposition process, and therefore can have the same composition, but are not limited thereto.

[0040] In one embodiment, the gate electrode 140 and the source electrode 144 may be made of conductive materials, such as metals, alloys, metal nitrides, or semiconductor materials. In some embodiments, the metal may include other suitable conductive materials such as gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), and molybdenum (Mo), or combinations thereof.

[0041] At least two drain electrodes, such as a first drain electrode 142 and a second drain electrode 148, may be disposed opposite to the source electrode 144 on the other side of the stack structure 160. The first drain electrode 142 may be disposed within a first drain contact hole 134 of the first interlayer dielectric layer 124, and the composition of the first drain electrode 142 may be the same as that of the gate electrode 140, for example, including a Schottky contact metal composition. In one embodiment, the bottom surface 143 of the first drain electrode 142 may be disposed on the passivation layer 116. In a preferred embodiment, the bottom surface 143 of the first drain electrode 142 may be selectively electrically connected to an underlying semiconductor layer, such as a III-V barrier layer 106, to form a Schottky contact. According to an embodiment of the present invention, the first drain electrode 142 may penetrate the passivation layer 116 and be electrically connected to the underlying semiconductor layer, but the present invention is not limited thereto. In this invention, Schottky contact metal refers to a metal, alloy, or stacked layer thereof that can form a Schottky contact with a semiconductor layer in contact with it, such as TiN, W, Pt, Ni, or Ni / Au, but is not limited thereto. Furthermore, the second drain electrode 148 can be disposed within the second drain contact hole 136 of the first interlayer dielectric layer 124, and the second drain contact hole 136 is laterally separated from the first drain contact hole 134. The composition of the second drain electrode 148 can differ from the compositions of the gate electrode 140 and the first drain electrode 142, but have the same composition as the first source electrode 144. For example, the composition of the second drain electrode 148 can include an ohmic contact metal. The bottom surface of the second drain electrode 148 can be electrically connected to the underlying semiconductor layer, such as the III-V channel layer 104, to form an ohmic contact. In this invention, ohmic contact metal refers to a metal, alloy, or stacked layer thereof that can form an ohmic contact with a semiconductor layer in contact with it, such as Ti / Al, Ti / Al / Ti / TiN, Ti / Al / Ti / Au, Ti / Al / Ni / Au, or Ti / Al / Mo / Au, but is not limited thereto.

[0042] Furthermore, the first drain electrode 142 can be electrically connected to the second drain electrode 148, for example, through a connection portion disposed above the first drain electrode 142. For instance, the connection portion may include a conductive plug 150 and a conductive wire 152, wherein the conductive plug 150 can be disposed in an opening 150 of the second interlayer dielectric layer 126, and the conductive wire 152 can be disposed oriented on the top surface of the second interlayer dielectric layer 126. According to one embodiment of the present invention, the connection portion (e.g., conductive plug 150 or conductive wire 152) and the second drain electrode 148 can be formed by the same deposition process, and therefore may have the same composition, but are not limited thereto. According to other embodiments, the composition of the connection portion (e.g., conductive plug 150 or conductive wire 152) may be the same as the composition of the first drain electrode 142, but different from the composition of the second drain electrode 148. Furthermore, the composition of the connection portion may also be selected from other metals or alloys, and may differ from the composition of the first drain electrode 142 and the second drain electrode 148.

[0043] According to one embodiment of the present invention, the bottom surface 143 of the first drain electrode 142 may be higher than the bottom surface of the second drain electrode 148, such that the bottom surface 143 of the first drain electrode 142 and the bottom surface of the second drain electrode 148 can each contact different semiconductor layers. Furthermore, a first interlayer dielectric layer 124 may be disposed between the first drain electrode 142 and the second drain electrode 148, and a second interlayer dielectric layer 126 may be disposed between the conductive plug 150 and the second drain electrode 148.

[0044] According to an embodiment of the present invention, since the first drain electrode 142 and the second drain electrode 148 are respectively located in the separately disposed first drain contact hole 134 and second drain contact hole 136, the bottom surface width W of the first drain electrode 142 and the distance L between the first drain electrode 142 and the second drain electrode 148 are... DD It can be controlled independently; in addition, the bottom surface width W of the first drain electrode 142 and the distance L between the stack structure 160 and the first drain electrode 142 are also controllable. GD It can also be controlled independently. In other words, increasing or decreasing the bottom width W of the first drain electrode 142 does not necessarily increase or decrease the distance L. DD or distance L GD Since increasing the bottom width W of the first drain electrode 142 typically increases the on-resistance, and in order to reduce the electric field distribution of the high-voltage semiconductor device and thus reduce the cutoff current of the high-voltage semiconductor device without increasing the on-resistance, according to an embodiment of the present invention, the distance L between the first drain electrode 142 and the stack structure 160 can be arbitrarily set without changing the bottom width W. GDThis optimizes the electric field distribution (or potential distribution) within the III-V barrier layer 106 and the III-V channel layer 104, thereby reducing the cutoff current of the high-voltage semiconductor device.

[0045] According to one embodiment of the present invention, the substrate 100 may be a silicon substrate, a silicon carbide (SiC) substrate, an alumina (Al2O3) substrate (or sapphire substrate), an aluminum nitride (AlN) ceramic substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, but is not limited thereto. In another embodiment, the substrate 100 further comprises one or more insulating material layers and / or other suitable material layers (e.g., semiconductor layers) and a core layer. The insulating material layer may be an oxide, nitride, oxynitride, or other suitable insulating material. The core layer may be silicon carbide (SiC), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), zinc oxide (ZnO) or gallium oxide (Ga2O3), or other suitable ceramic material. In one embodiment, the single or multiple insulating material layers and / or other suitable material layers cover the core layer. According to one embodiment of the present invention, the aforementioned III-V channel layer 104 may comprise one or more III-V semiconductor layers. The composition of the III-V semiconductor layers may be GaN, AlGaN, InGaN, or InAlGaN, but is not limited thereto. The buffer layer 102 may be used to reduce the degree of stress or lattice mismatch present between the substrate 100 and the III-V channel layer 104. The III-V channel layer 104 may also be one or more doped III-V semiconductor layers, such as a p-type III-V semiconductor layer. For the p-type III-V semiconductor layer, the dopant may be C, Fe, Mg, or Zn, or is not limited thereto. The aforementioned III-V barrier layer 106 may comprise one or more III-V semiconductor layers, and its composition may differ from that of the III-V semiconductor layer 104. For example, the III-V barrier layer 106 may comprise AlN, Al y Ga 1-yN (0 < y < 1) or a combination thereof. According to one embodiment, the III-V channel layer 104 may be an undoped GaN layer, while the III-V barrier layer 106 may be an essentially N-type AlGaN layer. Due to the discontinuous bandgap between the III-V channel layer 104 and the III-V barrier layer 106, by stacking the III-V channel layer 104 and the III-V barrier layer 106 together, electrons are concentrated at the heterojunction between the III-V channel layer 104 and the III-V barrier layer 106 due to the piezoelectric effect, thus creating a thin layer with high electron mobility, i.e., a two-dimensional electron gas (2-DEG) region 120. In contrast, the region covered by the III-V capping layer 112, since no two-dimensional electron gas is formed, can be considered as a two-dimensional electron gas cutoff region 122. According to one embodiment of the present invention, since the first drain electrode 142 does not penetrate into the III-V barrier layer 106, a two-dimensional electron gas region 120 can be formed below the first drain electrode 142. The III-V capping layer 112 may comprise one or more III-V semiconductor layers, and the composition of the III-V semiconductor layers may be GaN, AlGaN, InGaN, or InAlGaN, but is not limited thereto. Furthermore, the III-V capping layer 112 may also be one or more doped III-V semiconductor layers, such as a P-type III-V semiconductor layer. For the P-type III-V semiconductor layer, the dopant may be C, Fe, Mg, or Zn, but is not limited thereto. According to one embodiment of the present invention, the III-V capping layer 112 may be a P-type GaN layer. According to one embodiment of the present invention, the etch stop layer 114 may comprise a metal nitride, such as titanium nitride, and there may be different etch rates between the etch stop layer 114 and the first interlayer dielectric layer 124. According to one embodiment of the present invention, the passivation layer 116 may be a thin dielectric layer with a thickness between 0.5 nm and 10 nm, which can be used to eliminate or reduce surface defects present on the sidewalls of the III-V channel layer 104 and the top surface of the III-V barrier layer 106, thereby improving the electron mobility of the two-dimensional electron gas region 120. According to one embodiment of the present invention, the passivation layer 116 may be silicon nitride (SiN), silicon oxynitride (SiON), aluminum nitride (AlN), aluminum oxide (Al2O3), or silicon oxide (SiO2), but is not limited thereto. The first interlayer dielectric layer 124, the second interlayer dielectric layer 126, and the third interlayer dielectric layer 154 may have the same or different compositions, such as SiN, AlN, Al2O3, SiON, or SiO2, but are not limited thereto.

[0046] Figure 2 According to an embodiment of the present invention, along Figure 1A top view of a high-voltage semiconductor device, drawn along the A-A' tangent. (See diagram below.) Figure 2 As shown, the gate electrode 140, source electrode 144, first drain electrode 142, and second drain electrode 148 can be arranged in parallel, such that their major axes are parallel to each other. According to one embodiment of the present invention, the gate electrode 140 and the first drain electrode 142 are strip-shaped, while the source electrode 144 and the second drain electrode 148 are annular, but this is not a limitation. According to one embodiment of the present invention, the gate electrode 140, source electrode 144, first drain electrode 142, and second drain electrode 148 can be arbitrarily selected as strip-shaped or annular. Furthermore, according to one embodiment of the present invention, one of the source electrode 144 and the second drain electrode 148 can be circular; therefore, the other of the source electrode 144 and the second drain electrode 148, the first drain electrode 142, and the gate electrode 140 can surround the periphery of the circular electrode to form a concentric electrode.

[0047] Figure 3 This is a schematic cross-sectional view of a high-voltage semiconductor device having multiple drain electrodes, as illustrated in an embodiment of the present invention. Figure 2 The high-voltage semiconductor device shown can be, for example, an enhancement-mode high electron mobility transistor 10', whose structure is similar to... Figure 1 The enhanced high electron mobility transistor 10 is shown. However, Figure 2 The illustrated embodiments and Figure 1 The main difference in the illustrated embodiments is that, Figure 2 The first drain electrode 142 shown extends into the III-V barrier layer 106, which allows the first drain electrode 142 to more effectively control the electric field distribution (or potential distribution) within the III-V barrier layer 106 and the III-V channel layer 104, thereby achieving the effect of reducing the cutoff current of the high-voltage semiconductor device.

[0048] Figure 4 This is a schematic cross-sectional view of a high-voltage semiconductor device having multiple drain electrodes, as illustrated in an embodiment of the present invention. Figure 4 The high-voltage semiconductor device shown can be, for example, an enhancement-mode high electron mobility transistor 10", whose structure is similar to... Figure 1 The enhanced high electron mobility transistor 10 is shown. However, Figure 4 The illustrated embodiments and Figure 1 The main difference in the illustrated embodiments is that, Figure 4The illustrated enhancement-mode high electron mobility transistor 10" includes a plurality of first drain electrodes 142, 142', and each first drain electrode 142, 142' can form a Schottky contact with the underlying semiconductor layer, such as a III-V barrier layer 106. The first drain electrodes 142' can be disposed adjacent to each other, and their bottom surfaces 143, 143' can be separated from each other by a distance L'. DD Depending on the specific requirements, the bottom surface width W' of the first drain electrode 142' can be the same as or different from the bottom surface width W of the first drain electrode 142. The first drain electrode 142' can be electrically connected to the first drain electrode 142 and the second drain electrode 148, for example, through a conductive plug 150' disposed on the top of the first drain electrode 142'. By providing multiple first drain electrodes 142, 142', the distribution of the electric field can be adjusted more flexibly.

[0049] To enable those skilled in the art to implement the invention, the following describes in more detail the method for manufacturing the high-voltage semiconductor device of the present invention.

[0050] Figure 5 This is a schematic cross-sectional view of a high-voltage semiconductor device having a III-V channel layer, a III-V barrier layer, a gate structure, and an interlayer dielectric layer disposed on a substrate, according to an embodiment of the present invention. Figure 5As shown, in one process stage of the high electron mobility transistor 20, a buffer layer 102, a III-V channel layer 104, a III-V barrier layer 106, a stack structure 160, a passivation layer 116, and a first interlayer dielectric layer 124 may be sequentially stacked on the substrate 100. Contact holes, such as gate contact holes 130 and first drain contact holes 134, may be disposed in the first interlayer dielectric layer 124 to expose the underlying passivation layer 116. According to an embodiment of the present invention, the stacked layers on the substrate 100 can be formed by any suitable means, such as molecular-beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD), or other suitable deposition methods. The buffer layer 102 may include a plurality of sub-semiconductors, and its overall resistance is higher than that of other layers on the substrate 100. Specifically, the proportion of certain elements in the buffer layer 102, such as metal elements, gradually changes from the substrate 100 toward the III-V channel layer 104. For example, if the substrate 100 and the III-V channel layer 104 are a silicon substrate and a GaN layer, respectively, the buffer layer 102 can be an aluminum gallium nitride (Al₂O₃) layer with a gradually varying composition. x Ga 1-x N), and along the direction from the substrate 100 toward the III-V channel layer 104, the X value will decrease from 0.9 to 0.15 in a continuous or stepwise manner.

[0051] Figure 6 This is a schematic cross-sectional view of a high-voltage semiconductor device having a gate electrode and a first drain electrode disposed in an interlayer dielectric layer according to an embodiment of the present invention. Figure 6 As shown, a conductive layer, such as a composite conductive layer including a Schottky contact metal, can be formed on the top surface of the first interlayer dielectric layer 124, within the gate contact hole 130, and within the first drain contact hole 134 via a suitable deposition process. Subsequently, photolithography and etching processes are performed to pattern the conductive layer, thereby forming the gate electrode 140 and the first drain electrode 142. According to one embodiment of the present invention, for gate contact holes 130 and first drain contact holes 134 with small opening areas, the conductive layer may completely fill the contact holes 130 and first drain contact holes 134, but this is not a limitation.

[0052] Next, a second interlayer dielectric layer can be deposited to cover the first interlayer dielectric layer 124, the gate electrode 140, and the first drain electrode 142.

[0053] Figure 7 This is a schematic cross-sectional view of a high-voltage semiconductor device having a source contact hole and a second drain contact hole in the interlayer dielectric layer according to an embodiment of the present invention. Figure 8 As shown, after forming the second interlayer dielectric layer 126, photolithography and etching processes can be used to form separately disposed source contact holes 132 and drain contact holes 136 in the first interlayer dielectric layer 124 and the second interlayer dielectric layer 126. The bottoms of the source contact holes 132 and the drain contact holes 136 can extend into the III-V channel layer 104, but are not limited thereto. Subsequently, another photolithography and etching process can be performed to form an opening 138 in the second interlayer dielectric layer 126, so that the top surface of the first drain electrode 142 can be exposed from the opening 138.

[0054] Figure 8 This is a schematic cross-sectional view of a high-voltage semiconductor device having a source electrode and a second drain electrode disposed in an interlayer dielectric layer according to an embodiment of the present invention. Figure 8 As shown, a conductive layer, such as a composite conductive layer including an ohmic contact metal, can be formed on the top surface of the second interlayer dielectric layer 126 and within the source contact hole 132, the second drain contact hole 136, and the opening 138 via a suitable deposition process. Subsequently, photolithography and etching processes are performed to pattern the conductive layer, thereby forming the source electrode 144, field plate 146, second drain electrode 148, conductive plug 150, and conductive interconnect 152. According to one embodiment of the invention, for the opening 138 with a small opening area, the conductive layer may completely fill the opening 138; while for the source contact hole 132 and the second drain contact hole 136 with a larger opening area, the conductive layer may conformally cover the sidewalls of the contact holes 132 and 136, but is not limited thereto.

[0055] Next, a third interlayer dielectric layer can be deposited over the second interlayer dielectric layer 126, the source electrode 144, the field plate 146, the second drain electrode 148, the conductive plug 150, and the conductive interconnect 152 to obtain, as shown in the figure. Figure 1 The high electron mobility transistor 10 is shown.

[0056] Figure 9 This is a flowchart illustrating a method for manufacturing a high-voltage semiconductor device according to an embodiment of the present invention. Figure 9As shown, according to an embodiment of the present invention, a method 200 for fabricating a high electron mobility transistor may include: step 202: providing a semiconductor substrate on which a group III-V channel layer, a group III-V barrier layer, a group III-V capping layer, and an interlayer dielectric layer are sequentially stacked; step 204: forming a gate contact hole and a first drain contact hole in the interlayer dielectric layer; step 206: forming a gate electrode and a first drain electrode, respectively located within the gate contact hole and the first drain contact hole; step 208: forming a source contact hole and a second drain contact hole in the interlayer dielectric layer; step 210: forming a source electrode and a second drain electrode, respectively located within the source contact hole and the second drain contact hole, and the second drain electrode is electrically connected to the first drain electrode.

[0057] According to the above embodiments of the present invention, by providing a first drain electrode and a second drain electrode with their bottom surfaces laterally separated from each other, and the first drain electrode forming a Schottky contact with the underlying semiconductor layer, while the second drain electrode forming an ohmic contact with the underlying semiconductor layer, the distance between the first drain electrode and the gate structure can be arbitrarily set without changing the width of the bottom surface of the first drain electrode. This not only improves the distribution of the surface electric field of the high-voltage semiconductor device and reduces the device's cutoff current, but also avoids excessively increasing the contact area between the bottom surface of the first drain electrode and the underlying semiconductor layer, thereby avoiding an increase in the on-resistance of the high-voltage semiconductor device.

[0058] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A high electron mobility transistor, characterized in that, include: The first, third, and fifth genus channel layer, the first, third, and fifth genus barrier layer, and the first, third, and fifth genus cap layer are sequentially arranged on a base; A source electrode is disposed on one side of the group III-V capping layer; A first drain electrode and a second drain electrode are disposed on the opposite side of the group III-V capping layer relative to the source electrode, wherein the bottom surface of the first drain electrode is laterally separated from the bottom surface of the second drain electrode, and there is a lateral distance between the bottom surfaces of the first and second drain electrodes. Both the first and second drain electrodes are laterally separated from the group III-V capping layer, and the composition of the first drain electrode differs from the composition of the second drain electrode. A connection portion is electrically connected to the first drain electrode and the second drain electrode.

2. The high electron mobility transistor as described in claim 1, characterized in that, The bottom surface of the first drain electrode is higher than the bottom surface of the second drain electrode.

3. The high electron mobility transistor as described in claim 1, characterized in that, The bottom surfaces of the first drain electrode and the second drain electrode each contact different layers.

4. The high electron mobility transistor as described in claim 1, characterized in that, The first drain electrode and the group III-V barrier layer include a Schottky contact, the second drain electrode and the group III-V channel layer include an ohmic contact, and the ohmic contact metal penetrates the group III-V barrier layer.

5. The high electron mobility transistor as described in claim 1, characterized in that, The connection portion includes a conductive plug or a conductive wire, wherein the composition of the connection portion is the same as the composition of the first drain electrode or the composition of the second drain electrode.

6. The high electron mobility transistor as claimed in claim 1, characterized in that, Also includes: An inter-dielectric layer is disposed on the group III-V barrier layer and includes a first drain contact hole and a second drain contact hole, wherein the first drain contact hole is separated from the second drain contact hole; The first drain electrode is disposed in the first drain contact hole; as well as The second drain electrode is disposed inside the second drain contact hole.

7. The high electron mobility transistor as described in claim 6, characterized in that, The interlayer dielectric layer also includes a gate contact hole disposed on the top surface of the III-V capping layer.

8. The high electron mobility transistor as claimed in claim 7, characterized in that, It also includes a gate electrode disposed in the gate contact hole, wherein the composition of the gate electrode is the same as that of the first drain electrode.

9. The high electron mobility transistor as claimed in claim 1, characterized in that, The material of the first drain electrode includes TiN, W, Pt, Ni, or Ni / Au.

10. The high electron mobility transistor as claimed in claim 1, characterized in that, The material of the second drain electrode includes Ti / Al, Ti / Al / Ti / TiN, Ti / Al / Ti / Au, Ti / Al / Ni / Au, or Ti / Al / Mo / Au.

11. A high-voltage semiconductor device, characterized in that, include: A semiconductor layer is disposed on a substrate; A semiconductor capping layer is disposed on the semiconductor layer; A source electrode is disposed on one side of the semiconductor capping layer; At least two drain electrodes are laterally separated from each other by a distance from each other on their bottom surfaces and are disposed on the other side of the semiconductor capping layer relative to the source electrode, and are both laterally separated from the semiconductor capping layer, wherein each of the at least two drain electrodes includes a Schottky contact metal and an ohmic contact metal. as well as An interlayer dielectric layer is disposed between the Schottky contact metal and the ohmic contact metal.

12. The high-voltage semiconductor device as claimed in claim 11, characterized in that, The Schottky contact metal is electrically connected to the ohmic contact metal.

13. The high-voltage semiconductor device as claimed in claim 11, characterized in that, It also includes a gate electrode electrically connected to the semiconductor capping layer, wherein the composition of the gate electrode is the same as that of the Schottky contact metal.

14. The high-voltage semiconductor device as claimed in claim 11, characterized in that, It also includes a conductive plug disposed on the Schottky contact metal, wherein the conductive plug is electrically connected to the Schottky contact metal and the ohmic contact metal.

15. The high-voltage semiconductor device as claimed in claim 14, characterized in that, The composition of the conductive plug is the same as that of the ohmic contact metal or the Schottky contact metal.

16. The high-voltage semiconductor device as claimed in claim 14, characterized in that, It also includes another interlayer dielectric layer disposed on top of the interlayer dielectric layer, wherein the other interlayer dielectric layer is disposed between the conductive plug and the ohmic contact metal.

17. The high-voltage semiconductor device as claimed in claim 16, characterized in that, It also includes a conductive wire disposed on the surface of the other interlayer dielectric layer, wherein the conductive wire is electrically connected to the conductive plug and the ohmic contact metal.

18. The high-voltage semiconductor device as claimed in claim 11, characterized in that, The semiconductor layer includes a III-V channel layer and a III-V barrier layer sequentially disposed on the substrate. The Schottky contact metal penetrates the interlayer dielectric layer, and the ohmic contact metal penetrates the interlayer dielectric layer and the III-V barrier layer.

19. The high-voltage semiconductor device as claimed in claim 11, characterized in that, The Schottky contact metal and the semiconductor layer include a Schottky contact, and the ohmic contact metal and the semiconductor layer include an ohmic contact.

20. The high-voltage semiconductor device as claimed in claim 11, characterized in that, The at least two drain electrodes also include another Schottky contact metal, which is separate from the Schottky contact metal and the ohmic contact metal.

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