Reconfiguration of ADC for different data rates

Abstract

This invention relates to ADC reconfiguration for different data rates. A receiver having an analog-to-digital converter (ADC) is disclosed. The ADC can be reconfigured based on a data rate of the receiver. For example, more portions of each time-interleaved ADC can be enabled to support a higher data rate of the receiver, while fewer portions of the ADC can be used to support a lower data rate of the receiver.

Description

[0001] This application is a divisional application of Chinese patent application No. 202010692323.7, filed on July 17, 2020, entitled "ADC Reconfiguration for Different Data Rates". The priority date of the parent application is July 22, 2019. Technical Field

[0002] This disclosure generally relates to receiver devices, and more specifically to receiver devices including reconfigurable analog-to-digital converters (ADCs) based on the receiver's data rate. Background Technology

[0003] High-speed communication systems transmit data over communication links at high data rates (e.g., 10 GS / s and higher). Receiving devices in high-speed communication systems may include analog-to-digital converters (ADCs) to convert received analog signals into digital form for digital signal processing. As signaling speeds increase, the sampling rate of the ADCs included in the receiving devices will continue to increase to enable the receiving devices to recover data from analog signals. Summary of the Invention

[0004] Embodiments of this disclosure include a receiver having a time-interleaved analog-to-digital converter (ADC). The time-interleaved ADC can be reconfigured according to the data rate configured for the receiver. In one embodiment, each time-interleaved ADC includes a plurality of sub-ADCs, wherein each sub-ADC samples the analog input signal at a different phase to generate digital samples of the analog input signal.

[0005] Depending on the receiver's configured data rate, different sets of sub-ADCs can be enabled for each time-interleaved ADC. For example, more sub-ADCs in each time-interleaved ADC can be used to support a higher data rate for the receiver, while fewer sub-ADCs can be used to support a lower data rate. Therefore, the time-interleaved ADC can be scaled according to the receiver's desired data rate.

[0006] The features and advantages described in this specification are not exhaustive, and in particular, many additional features and advantages will be apparent to those skilled in the art from the accompanying drawings, description, and claims. Furthermore, it should be noted that the language used in this specification has been chosen primarily for readability and guidance purposes and may not have been selected to define or limit the subject matter of the invention. Attached Figure Description

[0007] The disclosed embodiments have advantages and features that will become more apparent from the specific embodiments, the appended claims, and the accompanying drawings (or illustrations). A brief description of the drawings is given below.

[0008] Figure 1 It is a high-speed communication system including a receiver according to an embodiment.

[0009] Figure 2A It operates at the first data rate according to the implementation method. Figure 1 Detailed block diagram of the analog-to-digital converter (ADC) and clock generator in the receiver.

[0010] Figure 2B This is a detailed block diagram of the sub-ADC according to the implementation method.

[0011] Figure 3 It operates at the second data rate according to the implementation method. Figure 1 Detailed block diagram of the ADC and clock generator in the receiver.

[0012] Figure 4 It operates at a third data rate according to the implementation method. Figure 1 Detailed block diagram of the ADC and clock generator in the receiver.

[0013] Figure 5 It operates at the fourth data rate according to the implementation method. Figure 1 Detailed block diagram of the ADC and clock generator in the receiver.

[0014] Figure 6 This is a flowchart describing a method for reconfiguring an ADC according to an implementation method. Detailed Implementation

[0015] The accompanying drawings and the following description relate to embodiments by way of example only. It should be noted that, based on the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily considered as feasible alternatives that can be employed without departing from the claimed principles. Reference will now be made in detail to several embodiments, examples of which are illustrated in the accompanying drawings. Note that similar or analogous reference numerals may be used in the drawings where feasible and may indicate similar or analogous functions.

[0016] receiver architecture

[0017] Figure 1This is a high-speed communication system including a receiver 100 according to one embodiment. The receiver 100 includes an analog section 101 and a digital section 103. The analog section 101 of the receiver 100 is coupled to a communication channel 102 and receives an analog channel signal 104 from a remote transmitter (not shown) through the communication channel 102. The communication channel 102 may be, for example, an electrical communication channel found on a computing board carrying single-ended or differential signals. The communication channel 102 may also be, for example, an optical communication channel.

[0018] Analog channel signal 104 is generated at the transmitter based on digital data. Receiver 100 recovers digital data 142 from channel signal 104 at its digital section 103. In some embodiments, receiver 100 may be a standalone device or part of a larger device such as an application-specific integrated circuit (ASIC). The analog section 101 of receiver 100 includes an analog front-end (AFE) 110, analog-to-digital converters (ADCs) 120A-120N, a phase-locked loop (PLL) 105, and a clock generator 190A-190N. The digital section 103 of receiver 100 includes a multiplexer 130, a digital finite impulse response (DFIR) filter 134, a data decision circuit 140, and a feedback loop circuit 150. The feedback loop circuit 150 includes a signal reconstruction circuit 160, a timing error circuit 170, and a phase control circuit 180. Each of these components can be implemented using hardware circuitry to generate signals, and lines connecting these components transmit signals from one component to another.

[0019] AFE 110 uses analog processing techniques to preprocess the received channel signal 104 to generate an analog input signal 112. The channel signal 104 may be suboptimal due to channel impairments such as insertion loss, crosstalk, inter-symbol interference, and optical dispersion, and AFE 210 uses analog processing to reduce some of these suboptimal aspects. Examples of analog processing techniques include gain adjustment or continuous-time equalization filters. In other embodiments, AFE 110 may simply be an input terminal that receives the channel signal 104 and passes it to generate the analog input signal 212 without signal processing.

[0020] The inputs of ADCs 120A-120N are coupled to the outputs of AFE 110. Each ADC 120 converts the analog input signal 112 into a digital input sample 122 by sampling the analog input signal 112 and then rounding or quantizing the sampled input signal 112 to its nearest digital value. Each digital value represents a different voltage level of the sampled input signal 112. Each ADC 120 outputs an M-bit digital code in binary form.

[0021] The sampling phase of each ADC 120 is controlled by its own sampling clock signal 192. For example, ADC 120A generates sample 122A with the phase of sampling clock signal 192A, and ADC 120B generates sample 122B with the phase of sampling clock signal 192B, and so on. Each of the sampling clock signals 192A-192N has a different phase from each other, which causes each corresponding ADC 120 to sample the analog input signal 112 with a different phase.

[0022] Multiplexer 130 receives digital input samples 122A-122N from ADCs 120A-120N and selects one digital input sample 122A-122N at a time for its output. Multiplexer 130 selects among the digital input samples 122A-122N in a cyclic manner, such that all digital input samples 122A-122N are interleaved to form a continuous digital sample stream. The digital sample stream is output via digital input signal 132.

[0023] DFIR filter 134 receives a digital input signal 132 indicating digital samples and filters the digital input signal 132 into a filtered digital input signal 136. DFIR filter 134 is a filter whose impulse response has a finite duration. DFIR filter 134 produces a filtered digital input signal 136 whose value is equal to a weighted sum of the delayed samples indicated by digital input signal 132. DFIR filter 134 may include multiple taps, where each tap represents a different delayed sample. Each tap is weighted and summed to produce the filtered digital input signal 136. The number and weights of the taps can be varied according to the tuning requirements of receiver 100.

[0024] The decision circuit 140 receives a filtered digital input signal 136 and performs data determination on the logic data values ​​represented by digital samples of the filtered digital input signal 136 to recover data 242. The recovered data 142 can be single-bit data (e.g., NRZ) or multi-bit data (e.g., PAM-4). In one embodiment, the data decision circuit 140 includes a digital comparator that compares each value of the filtered digital input signal 136 with a threshold and uses the comparison result as the recovered data 142. In one embodiment, the data decision circuit 140 is a digital signal processor (DSP) that uses a digital signal processing algorithm to recover data 142 from the filtered digital input signal 136. Examples of the data decision circuit 140 include adaptive equalizers, decision feedback equalizers (DFE), and maximum likelihood sequence detectors (MLSD) (e.g., Viterbi decoders). The data decision circuit 140 may also be referred to as a data recovery circuit.

[0025] Feedback loop circuit 150 is coupled to the output of DFIR 134 and the output of data determination circuit 140. Feedback loop circuit 150 receives the filtered digital input signal 136 and the recovered data 142, and uses these two inputs to generate digital phase control signals 182A-182N. Under high-speed signaling, the sampling phase of ADCs 120A-120N can have a substantial impact on the accuracy of the data 142 recovered by receiver 100. Feedback loop circuit 150 generates digital phase control signals 182 through continuous and interlocked feedback to ensure the correct phase of the sampling clock signals 192A-192N. As previously described, feedback loop circuit 150 may include signal reconstruction circuit 160, timing error circuit 170, and phase control circuit 180.

[0026] Signal reconstruction circuit 160 receives the recovered data 142 and generates a reconstructed digital input signal 162 based on the recovered data 142. The reconstructed input signal 162 is a reconstructed and idealized version of the filtered digital input signal 136. In other words, if the sampling phase of ADC 120 is ideal, the reconstructed input signal 162 represents an ideal sample expected to be input to data decision circuit 140. If the phase of sampling clock signal 192 is in its ideal phase and results in an ideal sample, the reconstructed input signal 162 will perfectly match the filtered digital input signal 136. However, when the phase of sampling clock signal 192 is not in its ideal phase, the reconstructed input signal 162 will differ from the filtered digital input signal 136. The reconstructed input signal 162 can also be referred to as a reference signal or a target signal.

[0027] Timing error detector 170 receives the filtered digital input signal 136 and the reconstructed input signal 162, and determines whether a difference exists between the two types of signals. Timing error detector 170 generates a digital timing error signal 172, which indicates the presence and extent of timing error in the sampling of the analog input signal 112. Timing error signal 172 may include a sequence of timing error values, where each timing error value represents a timing error associated with the sampling phase of a particular ADC 120.

[0028] In one implementation, the timing error detector 170 is a minimum mean square error (MMSE) detector. The MMSE detector determines the mean square error (MES) between the filtered digital input signal 136 and the reconstructed input signal 162. The MMSE detector then calculates the gradient (i.e., slope) of the MSE over time and outputs a timing error signal 172 indicating the gradient of the MSE relative to the phase timing error. The gradient represents the direction in which the MSE is moving and how fast the MSE is moving in that direction.

[0029] Phase control circuit 180 receives and processes timing error signal 172 to generate digital phase control signals 182A-182N. Each of the digital phase control signals 182A-182N includes a phase control value representing a target phase of the corresponding sampled clock signal 192A-192N. Phase control circuit 180 includes an interlocked feedback path (not shown) that uses one of the digital phase control signals 182N when generating other digital phase control signals 182A-182M. The interlocked path allows the digital phase control signals 182A-182N to stabilize to their appropriate values ​​within a short time. In one embodiment, as further described below, phase control circuit 180 also generates a clock skew calibration signal 211 that corrects for skew in the sampled clock signal.

[0030] Phase-locked loop 105 generates a latched clock signal 106 that is input to clock generators 190A-190N. PLL 105 generates the latched clock signal 106 based on a reference clock signal 107 received from an oscillator (not shown). PLL 105 can latch the reference clock signal 107 to a desired frequency (e.g., 28 GHz) and output it to clock generators 190A-190N.

[0031] Clock generators 190A-190N generate sampling clock signals 192A-192N based on digital phase control signals 182A-182N and a lock clock signal 106. Specifically, clock generators 190A-190N adjust the phase of sampling clock signals 192A-192N according to the phase control value of digital phase control signals 182A-182N. In one embodiment, clock generators 190A-190N are phase interpolators that shift the pulses of sampling clock signals 192A-192N forward or backward in time. For example, if digital phase control signal 182A changes its value from "7" to "8", clock generator 190A can shift the pulses of sampling clock signals 192A in a direction that increases the phase delay of sampling clock signals 192A. The phase of sampling clock signals 192A-192N is adjusted to reach a steady state, during which the average value of the filtered timing error signal 172 is zero.

[0032] Clock generator architecture

[0033] Figure 2A This is a detailed block diagram of the ADC 120 and clock generator 190 in a receiver 100 according to one embodiment. Figure 2AAs shown, clock generator 190 includes circuitry for generating a sampled clock signal 192. In one embodiment, the circuitry of clock generator 190 includes a plurality of phase interpolators 201, a clock divider 203, and a clock delay 204. Note that in other embodiments, clock generator 190 may have the same characteristics as... Figure 2A The components shown are different components.

[0034] In one embodiment, phase interpolator 201 includes phase interpolator 201A and phase interpolator 201B, which have inputs for receiving a locked clock signal 106 generated by phase-locked loop 105. The locked clock signal 106 received by phase interpolator 201 is used by phase interpolator 201 and clock divider 203 to generate a reference clock signal for sampling clock signal 192. For example, phase interpolator 210 could be a 14G phase interpolator. Although in Figure 2A Only two phase interpolators are shown, but the clock generator 190 can have any number of phase interpolators.

[0035] Each phase interpolator 201 generates multiple clock signals (e.g., two clock signals) based on the locked clock signal 106. In one embodiment, the clock signals generated by the two phase interpolators 201A and 201B have the same frequency. For example, the clock signals generated by the phase interpolators 201A and 201B are 14 GHz clock signals.

[0036] Although the clock signals generated by phase interpolator 201 have the same frequency, multiple clock signals have different phases. For example, phase interpolator 201A generates clock signal 202A with a 270-degree phase shift and clock signal 202B with a 90-degree phase shift, and phase interpolator 201B generates clock signal 202C with a 180-degree phase shift and clock signal 202D with a 0-degree phase shift. Each 90-degree phase shift of the 14GHz clock signal generated by phase interpolator 201 represents 1UI. In one embodiment, 1UI refers to the baud rate. For example, the baud rate of 56G PAM4 is 28G, so the 1UI of 56G PAM4 is 90 degrees of 14G. The baud rate of 28GHz is 28G, so 1UI is still 90 degrees of 14G.

[0037] In one implementation, clock divider 203 includes multiple clock divider circuits 203. Clock divider 203 also divides the clock signal generated by phase interpolator 201 to generate eight-phase clock signals (e.g., a 7GHz clock signal). For example, each clock divider circuit 203 splits the clock signal input from the corresponding phase interpolator in phase interpolator 201 into two halves, and also splits the phase of the input clock signal into two halves. As a result, in one example, the clock signals generated by clock divider 203 have phases separated by 45 degrees.

[0038] Clock divider 203 may include clock divider circuit 203A and clock divider circuit 203B. The input of clock divider circuit 203A receives the clock signal generated by phase interpolator 201A. The input of clock divider circuit 203B receives the clock signal generated by phase interpolator 201B. Since each clock divider circuit 203 receives two clock signals, each clock divider circuit 203 generates four clock signals with different phases. Because the four clock signals generated by phase interpolator 201 are phase-shifted by 90 degrees, the clock divider circuit 203 generates eight phase clocks with a 45-degree phase difference.

[0039] For example, clock divider circuit 203A generates clock signals with a 135-degree phase shift and clock signals with a 315-degree phase shift (180 degrees away from the 135-degree phase shift) based on clock signal 202A with a 270-degree phase shift. Clock divider circuit 203A also generates clock signals with a 45-degree phase shift and clock signals with a 225-degree phase shift (e.g., 180 degrees away from the 45-degree phase shift) based on clock signal 202B with a 90-degree phase shift.

[0040] The clock divider circuit 203B generates a clock signal with a 90-degree phase shift and a clock signal with a 270-degree phase shift (e.g., 180 degrees away from the 90-degree phase shift) based on a clock signal 202C with a 180-degree phase shift. The clock divider 203B also generates a clock signal with a 0-degree phase shift and a clock signal with a 180-degree phase shift (e.g., 180 degrees away from the 0-degree phase shift) based on a clock signal 202D with a 0-degree phase shift.

[0041] As described above, the clock generator 190 also includes a clock delay unit 204. The input of the clock delay unit 204 is connected to the output of the clock divider 203. The output of the clock delay unit 204 is connected to, for example... Figure 2AThe ADC 120 is shown. In one embodiment, clock delay 204 receives the clock signal generated by clock divider 203 and corrects for skew in the clock signal. The corrected clock signal with a different sampling phase is the sampling clock signal 192 used by ADC 120 to sample the analog input signal 112. Clock delay 204 corrects for offset in the sampling clock signal based on clock skew calibration signal 211. Clock skew calibration signal 211 can be received from the digital portion 103 of receiver 100. Specifically, clock skew calibration signal 211 is received from phase controller 180.

[0042] like Figure 2A As shown, clock delay unit 204 includes multiple clock delay circuits T_nd (e.g., clock delay circuits T_7d to T_0d), where n is a positive integer. In one embodiment, the clock delay circuits T_nd are arranged in a non-sequential order. Figure 2A In the arrangement shown, clock delay circuit T_7d is the last clock delay circuit and also the first clock delay circuit, wherein each adjacent clock delay circuit is separated by a 45-degree phase difference. Each clock delay circuit T_nd receives the corresponding clock signal from the clock divider 204 and corrects the skew of each clock signal based on the clock skew calibration signal 211.

[0043] As described above, the clock divider 203 generates eight different sampled clock signals 192, each clock signal having a different phase from the other clock signals. Therefore, the clock delayer 204 includes eight clock delay circuits T_d, each receiving a corresponding clock signal from the eight different clock signals and correcting for skew in the received clock signal. For example, clock delay circuit T_7d receives a clock signal with minimal phase (e.g., 0-degree phase shift), clock delay circuit T_6d receives a clock signal with a 45-degree phase shift, clock delay circuit T_5d receives a clock signal with a 90-degree phase shift, clock delay circuit T_4d receives a clock signal with a 135-degree phase shift, clock delay circuit T_3d receives a clock signal with a 180-degree phase shift, clock delay circuit T_2d receives a clock signal with a 225-degree phase shift, clock delay circuit T_1d receives a clock signal with a 270-degree phase shift, and clock delay circuit T_0d receives a clock signal with a 315-degree phase shift.

[0044] like Figure 2AAs shown, each clock delay circuit T_nd outputs a calibrated clock signal ADCCK. For example, clock delay circuit T_7d outputs a calibrated clock signal ADCCK_7D, clock delay circuit T_6d outputs a calibrated clock signal ADCCK_6D, clock delay circuit T_5d outputs a calibrated clock signal ADCCK_5D, clock delay circuit T_4d outputs a calibrated clock signal ADCCK_4D, clock delay circuit T_3d outputs a calibrated clock signal ADCCK_3D, clock delay circuit T_2d outputs a calibrated clock signal ADCCK_2D, clock delay circuit T_1d outputs a calibrated clock signal ADCCK_1D, and clock delay circuit T_0d outputs a calibrated clock signal ADCCK_10. In one embodiment, the calibrated clock signals ADCCK collectively form the sampling clock signal 192.

[0045] ADC architecture

[0046] like Figure 2A As shown, according to one embodiment, each ADC 120 includes a track-and-hold device 205, a sub-ADC 205, and an ADC interface 209. The track-and-hold device 205 receives an analog input signal 112 and a sampling clock signal 192 as its inputs. The track-and-hold device 205 tracks the analog input signal 112 and holds that value for a period of time. Figure 2A As shown, the tracking and holding device 205 includes multiple tracking and holding circuits TH (e.g., tracking and holding circuits TH_7d to TH_0d). Each tracking and holding circuit TH receives a corresponding sampling clock signal from the analog input signal 112 and the sampling clock signal 192.

[0047] In one implementation, each track-and-hold circuit TH periodically samples the voltage level of the analog input signal 112 according to the sampling clock signal 192 received by the track-and-hold circuit TH, and generates a sampled input signal as the result of the sampling. For example, track-and-hold circuit TH_7d samples the analog input signal 112 according to the sampling clock signal ADCCK_7D, track-and-hold circuit TH_6d samples the analog input signal 112 according to the sampling clock signal ADCCK_6D, and so on. Similar to the clock delay circuit T_nd, the track-and-hold circuits TH are arranged in a non-sequential order.

[0048] Each track and hold circuit TH can be implemented by a switch connected to a capacitor. When the switch is closed, the track and hold circuit TH is in "track" mode and tracks the analog input signal 112. When the switch is open, the last instantaneous value of the tracked analog input signal 112 is held in the capacitor, and the track and hold circuit TH is in "hold" mode.

[0049] The tracking phase of each track and hold circuit TH is controlled by pulses of the sampling clock signal received by the track and hold circuit TH. When the sampling clock signal is high, the track and hold circuit TH samples the analog input signal 112. When the sampling clock signal is low, the track and hold circuit TH keeps the sampled value constant.

[0050] like Figure 2A As shown, the tracking and holding device 205 is connected to multiple sub-ADCs 207 included in the ADC 120. (As...) Figure 2A As shown, the sub-ADCs 207 are arranged in parallel. The sub-ADCs 207 include ADC_7D to ADC_0D, with each sub-ADC connected to a corresponding track-and-hold circuit in the track-and-hold circuit TH. For example, the input of ADC_7D is connected to the output of track-and-hold circuit TH7D, the input of ADC_6D is connected to the output of track-and-hold circuit TH6D, and so on. Therefore, each sub-ADC 207 receives a sampled analog input signal from the track-and-hold circuit TH connected to it and generates a digital sample of the sampled analog input signal. Each sub-ADC 207 operates at a data rate corresponding to the frequency of the sampling clock signal 192. In this example, assuming the sampling clock signal 192 is a 7GHz clock signal, each sub-ADC 207 operates at 7Gbps.

[0051] Reference Figure 2B A detailed block diagram of sub-ADC 207 is shown. In one embodiment, each sub-ADC 207 includes multiple time-interleaved successive approximation (SAR) ADC slices. Figure 2B As shown, time-interleaved SAR ADC chips are arranged in parallel. Each SAR ADC generates digital samples of the sampled analog input signal received by the sub-ADC from its corresponding track-and-hold circuit TH. The combination of digital samples generated by the SAR ADC chips forms the digital sample generated by the sub-ADC.

[0052] In one implementation, each SAR ADC chip included in sub-ADC 207 operates at a data rate based on the data rate of sub-ADC 207 and the number of SAR ADC chips included in sub-ADC 207. For example, assuming sub-ADC 207 operates at 7 Gbps and includes eight SAR ADC chips, each SAR ADC chip operates at a data rate of 875 Mbps, with a total of 513 signals being switched.

[0053] Return to reference Figure 2AAs described above, ADC 120 also includes an ADC interface 209. ADC interface 209 is coupled to the output of sub-ADC 207. ADC interface 209 receives digital samples of the sampled analog input signal output from sub-ADC 207. ADC interface 209 aligns the digital samples to output digital input sample 122. In one embodiment, the output digital input sample 122 has a resolution of at least 8 bits.

[0054] In one implementation, the ADC interface 209 aligns digital samples based on an interface clock signal 212. The ADC interface 209 can receive multiple interface clock signals 212, each corresponding to one of the sub-ADCs 207. The interface clock signal 212 is typically slower than the desired clock rate of the receiver 100. For example, the interface clock signal 212 is 64 times slower than the desired clock rate of the receiver 100. If a 56 GHz baud rate is configured for the receiver 100, the interface clock signal 212 is, for example, 875 MHz.

[0055] like Figure 2A As shown, the ADC interface 209 includes a set of registers 213 (e.g., flip-flops). Each register includes an input that is connected to a corresponding interface clock signal in the interface clock signal 212 and to the output of a corresponding sub-ADC in the sub-ADC 207. As will be further described below, registers 213 and interface clock signal 212 can be used to shut down portions of the ADC interface 209 according to the configured data rate of the receiver 100.

[0056] In one embodiment, each of the plurality of phase interpolators 201, clock divider 203, clock delay circuit Td, track and hold circuit TH, and sub-ADC 207 also includes a register. The register stores the value of the associated component that enables (e.g., turns on) or disables (e.g., turns off) the register.

[0057] ADC reconfiguration

[0058] In one implementation, the time-interleaved ADC 120 can be reconfigured based on the data rate configured for the receiver 100. The receiver 100 can be configured to operate at different data rates, such as a maximum data rate (e.g., 56G), a minimum data rate (8G), and one or more intermediate data rates between the maximum and minimum data rates (e.g., 28G and 15G). Each time-interleaved ADC 120 can be reconfigured based on the data rate configured for the receiver 100 by enabling or disabling certain portions of the ADC 120 and clock generator 190. For example, if the receiver 100 is configured to receive data at the maximum data rate, all components included in the ADC 120 (e.g., track-and-hold circuitry TH, sub-ADC 207, and the entire ADC interface 209) can be enabled, and all components of the clock generator 190 (e.g., phase interpolator 201, clock divider 203, and clock delay circuitry Td) can be enabled. Conversely, as further described below, if receiver 100 is configured to operate at a data rate lower than the maximum data rate, only a portion of the components included in ADC 120 and a portion of clock generator 190 may be enabled.

[0059] When receiver 100 is set to maximum data rate, ADC 120 is set to maximum data rate mode. In this example, assuming the maximum data rate of receiver 100 is 56Gbps, then the maximum data rate mode of ADC 120 is 56Gbps mode. However, in other implementations, the maximum data rate may be different.

[0060] During the maximum data rate mode of the ADC 120, such as Figure 2A As shown, all components of each ADC 120 and clock generator 190 are enabled. That is, during maximum data rate mode, the entire set of sub-ADCs included in each ADC 120 (e.g., the first set), the entire set of track-and-hold circuitry, and the entire portion of the ADC interface 209 are enabled. Similarly, during maximum data rate mode, all phase interpolators, clock divider 203, and clock delay circuit Td in clock generator 190 are enabled.

[0061] In one implementation, to enable all components of ADC 102 and clock generator 190, registers containing the values ​​that enable these components store values ​​for all components in ADC 102 and clock generator 190. Specifically, the phase interpolator 201, clock divider circuit 203, clock delay circuit Td, track and hold circuit TH, sub-ADC 207, and the entire ADC interface 209 have registers that store values ​​indicating the enabling of these components.

[0062] In maximum data rate mode, ADC 120 has a data rate of 56 Gbps, where clock generator 190 generates eight 7 GHz clocks. The 7 GHz clock signals are sent to eight track and hold circuits TH, and all eight sub-ADCs 207 operate at a data rate of 7 Gbps, with each SAR chip included in sub-ADC 207 operating at a data rate of 875 Mbps.

[0063] ADC 120 can also be reconfigured to support lower data rates as described above. By enabling reconfiguration of ADC 120, receiver 100 can support legacy communication standards. ADC 120 can be reconfigured by enabling only a portion of ADC 120 and clock generator 190 and disabling the rest of ADC 120 and clock generator 190. To disable a portion of ADC 120 and clock generator 190, the registers of the components of ADC 120 and clock generator 190 store values ​​that turn the components off.

[0064] Figure 3 This is an example of receiver 100 operating at a data rate lower than its maximum data rate. In this example, receiver 100 operates at half its maximum data rate. In the embodiment described herein, the maximum data rate of receiver 100 is 56 Gbaud. Therefore, receiver 100 operates at 28 Gbaud, and Figure 3 The ADC 120 shown is reconfigured to a first intermediate data rate mode (e.g., 28Gbps rate).

[0065] Assuming the receiver's data rate is half of the maximum data rate, then... Figure 3 As shown, during the first intermediate data rate mode, half of the ADC 120 and clock generator 190 are enabled and the other half are disabled to achieve the desired data rate (e.g., 28 Gbps). Figure 3 In this process, the clock generator 190 and ADC 120 are reconfigured so that a single phase interpolator and a second set of sub-ADCs 207 (e.g., four sub-ADCs 207) are used in the first intermediate data rate mode.

[0066] like Figure 3As shown, the second set of phase interpolators 201B and ADCs 207, including sub-ADC 0D, sub-ADC 4D, sub-ADC 2D, and sub-ADC 6D, is enabled (e.g., turned on), and the remaining set of phase interpolators 201A and the remaining set of sub-ADCs 7D, sub-ADC 3D, sub-ADC 5D, and sub-ADC 1D is disabled (e.g., powered off). The second set of ADCs 207 enabled during the first intermediate data rate mode is a subset of the first set of ADCs 207 enabled during the maximum data rate mode. Furthermore, because a single phase interpolator is used during the first intermediate data rate mode, instead of relying on two phase interpolators to generate the clock signal for the enabled portion of the sub-ADC 207, ADC 120 exhibits improved phase linearity.

[0067] In addition, a portion of the enabled set connected to the enabled phase interpolator 201B and sub-ADC 207, including clock divider 203B, clock delay circuits T_0d, T_4d, T_2d, and T_6d, track-and-hold circuits TH_0d, TH_4d, TH_2d, and TH_6d, and a portion of the ADC interface 209, is also enabled. Conversely, the remaining portion of the disabled set connected to the disabled phase interpolator 201A and sub-ADC 207, including clock divider 203A, clock delay circuits T_7d, T_3d, T_5d, and T_1d, track-and-hold circuits TH_7d, TH_3d, TH_5d, and TH_1d, and a portion of the ADC interface 209, is also disabled. As described above, the clock generator 190 and ADC 120 are enabled or disabled based on values ​​stored in the component's registers.

[0068] In one implementation method Figure 3 The illustration shows the lower half of ADC 120 and clock generator 190 enabled, while the upper half of ADC 120 and clock generator 190 disabled. However, in other embodiments, the upper half of ADC 120 and clock generator 190 is enabled, while the lower half of ADC 120 and clock generator 190 is disabled.

[0069] Figure 4 This is another example of receiver 100 operating at a different intermediate data rate than its maximum data rate. In this example, receiver 100 operates at a second intermediate data rate that is lower than the first intermediate data rate. For example, receiver 100 operates at a 15G baud rate. Figure 4 The ADC 120 shown is reconfigured to the second intermediate data rate mode.

[0070] In the second intermediate data rate mode, clock generator 190 and ADC 120 are reconfigured to enable a single phase interpolator and a third set of sub-ADCs. In one embodiment, the third set of sub-ADCs includes two sub-ADCs, such as sub-ADC 0D and sub-ADC 4D. Phase interpolator 201B is also enabled (e.g., turned on). Conversely, phase interpolator 201A and sub-ADC 7D, sub-ADC 3D, sub-ADC 5D, sub-ADC 1D, sub-ADC 2D, and sub-ADC 6D are disabled (e.g., turned off). Although ADC_0D and ADC_4D are enabled, in other embodiments, any other sub-ADC connected to phase interpolator 201B can be used in the second intermediate data rate mode.

[0071] In addition, the clock divider 203B, clock delay circuits T_0d and T_4d, track-and-hold circuits TH_0d and TH_4d, and a portion of the ADC interface 209, connected to the enabled phase interpolator 201B and the third set of sub-ADCs, are also enabled. Conversely, the clock divider 203A, clock delay circuits T_7d, T_3d, T_5d, T_1d, T_2d and T_6d, track-and-hold circuits TH_7d, TH_3d, TH_5d, TH_1d, TH_2d and TH_6d, and a portion of the ADC interface 209, connected to the disabled phase interpolator 201A and the disabled portion of the sub-ADC 207, are also disabled.

[0072] Figure 5 This is an example of receiver 100 operating at its minimum data rate. For example, receiver 100 operates at a baud rate of 8 Gbps. Figure 5 The ADC 120 shown has been reconfigured to minimum data rate mode.

[0073] In minimum data rate mode, clock generator 190 and ADC 120 are reconfigured to use a single phase interpolator and a fourth set of sub-ADCs 207. In one embodiment, the fourth set of sub-ADCs 207 includes a single sub-ADC 207. For example, in minimum data rate mode, phase interpolator 201B and sub-ADC 0D are enabled (e.g., turned on), and phase interpolator 201A and sub-ADCs 7D, 6D, 5D, 4D, 3D, 2D, and 1D are disabled (e.g., turned off). Although ADC_0D is enabled, in other embodiments, any other sub-ADC connected to phase interpolator 201B can be used in minimum data rate mode.

[0074] In addition, the clock divider 203B, clock delay circuit T_0d, track-and-hold circuit TH_0d, and a portion of the ADC interface 209 connected to the enabled phase interpolator 201B and sub-ADC 6D are also enabled. Conversely, the clock divider 203A, clock delay circuits T_7d, T_6d, T_5d, T_4d, T_3d, T_2d, and T_1d, track-and-hold circuits TH_7d, TH_6d, TH_5d, TH_4d, TH_3d, TH_2d, and TH_1d, and a portion of the ADC interface 209 connected to the disabled phase interpolator 201A and sub-ADC 207 are also disabled.

[0075] Figure 6 This is a flowchart describing a method for reconfiguring the ADC120 of receiver 100 according to one embodiment. Note that in other embodiments, other than... Figure 6 Other steps besides those shown.

[0076] In one implementation, receiver 100 determines 601 the data rate at which receiver 100 will receive data. Based on the determined data rate, receiver 100 enables 601 at least one sub-ADC among a plurality of sub-ADCs included in each time-interleaved ADC 120 of receiver 100, and disables at least one sub-ADC among a plurality of sub-ADCs included in each time-interleaved ADC 120 of receiver 100.

[0077] Additional configuration considerations

[0078] Throughout this specification, multiple instances can implement components, operations, or structures described as single instances. While individual operations of one or more methods are shown and described as separate operations, one or more individual operations may be executed concurrently and are not required to be executed in the order shown. Structures and functions presented as separate components in the example configuration can be implemented as combined structures or components. Similarly, structures and functions presented as single components can be implemented as separate components. These and other variations, modifications, additions, and improvements fall within the scope of this document's subject matter.

[0079] As used herein, any reference to "one embodiment" or "implementation" means that a particular element, feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0080] Some implementations can be described using the expressions “coupled” and “connected” and their derivatives. For example, the term “coupled” can be used to describe some implementations to indicate that two or more elements are in direct physical or electrical contact. However, the term “coupled” can also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other. Implementations are not limited to this context.

[0081] As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” or any other variation thereof are intended to cover non-exclusive inclusion. For example, a process, method, article, or apparatus that includes a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such a process, method, article, or apparatus. Furthermore, unless expressly stated otherwise, “or” means inclusive or rather than exclusive. For example, conditions A or B satisfy any of the following: A is true (or exists) and B is false (or does not exist); A is false (or does not exist) and B is true (or exists); and both A and B are true (or exist).

[0082] Additionally, the terms "a" or "an" are used to describe elements and components of the embodiments described herein. This is done merely for convenience and to give the general meaning of this disclosure. The description should be understood to include one or at least one, and the singular includes the plural unless clearly intended otherwise.

[0083] Having read this disclosure, those skilled in the art will understand, through the principles disclosed herein, alternative structures and functional designs for a receiver with an adjustable sampling clock. Therefore, although specific embodiments and applications have been shown and described, it is to be understood that the disclosed embodiments are not limited to the specific structures and components disclosed herein. Various modifications, alterations, and variations that will be apparent to those skilled in the art may be made to the arrangement, operation, and details of the methods and apparatus disclosed herein without departing from the spirit and scope defined in the appended claims.

Claims

1. A receiver, comprising: Multiple clock generators, each clock generator including a clock signal generator that generates multiple sampled clock signals having multiple sampled phases, each of the multiple sampled clock signals having a corresponding sampled phase among the multiple sampled phases; as well as A plurality of time-interleaved analog-to-digital converters (ADCs), each of the plurality of time-interleaved ADCs including a plurality of sub-ADCs for sampling an analog input signal, wherein each of the plurality of sub-ADCs samples the analog input signal at a sampling phase corresponding to the sub-ADC among the plurality of sampling phases, so as to convert the sampled analog input signal into a digital sample; Wherein, in response to the receiver being configured to operate at a data rate that is a portion of the maximum data rate of the receiver among a plurality of data rates, a portion of the plurality of sub-ADCs of at least one of the plurality of time-interleaved ADCs is enabled to sample the analog input signal at the data rate, and the remaining portions of the plurality of sub-ADCs are disabled; and Wherein, in response to the data rate being half of the receiver's maximum data rate, the portion of the plurality of sub-ADCs that are enabled to sample the analog input signal at the data rate includes half of the plurality of sub-ADCs of all time-interleaved ADCs in the plurality of time-interleaved ADCs.

2. The receiver according to claim 1, wherein, In response to the receiver being configured to operate at a data rate that is part of the receiver’s maximum data rate, a portion of the plurality of clock signal generators among the plurality of clock generators is enabled.

3. The receiver according to claim 2, wherein, The clock signal generator of each of the plurality of clock generators includes: A plurality of phase interpolators receive a reference clock signal, each of the plurality of phase interpolators generating a plurality of clock signals based on the reference clock signal, wherein each of the plurality of clock signals has a different sampling phase; Multiple clock dividers, each of which receives multiple clock signals from a corresponding phase interpolator among multiple phase interpolators, and generates a portion of the multiple sampled clock signals of the clock generator having the multiple sampled phases. Each of the plurality of clock signal generators includes a corresponding phase interpolator among the plurality of phase interpolators and a corresponding clock divider among the plurality of clock dividers.

4. The receiver according to claim 2, wherein, In response to the receiver being configured to operate at a data rate that is part of the receiver’s maximum data rate, the remainder of the plurality of clock signal generators are disabled.

5. The receiver according to claim 4, wherein, In response to the data rate being half of the receiver's maximum data rate, the enabled portion of the plurality of clock generators includes half of the plurality of clock generators.

6. The receiver according to claim 5, wherein, The remaining half of the sub-ADCs of all time-interleaved ADCs and the remaining half of the clock signal generators of all time-interleaved ADCs are disabled.

7. The receiver according to claim 4, wherein, In response to the data rate being the minimum data rate of the receiver, the enabled portion of the plurality of sub-ADCs includes one of the plurality of sub-ADCs included in each of the plurality of time-interleaved ADCs, and one of the plurality of clock generators is enabled.

8. The receiver according to claim 7, wherein, The remaining sub-ADCs and the remaining clock signal generators in all of the multiple time-interleaved ADCs are disabled.

9. The receiver according to claim 1, wherein, Each of the plurality of sub-ADCs comprises a plurality of time-interleaved successive approximation SARADC chips.

10. The receiver according to claim 1, wherein, Each of the multiple time-interleaved ADCs further includes: An ADC interface that receives digital samples of the sampled analog input signal from the plurality of sub-ADCs and aligns the digital samples for output.

11. The receiver according to claim 10, wherein, In response to the receiver being configured to operate at the data rate, a portion of the enabled portion of the ADC interface connected to the plurality of sub-ADCs is enabled, and the remaining portion of the enabled portion of the ADC interface not connected to the plurality of sub-ADCs is disabled.

12. The receiver according to claim 11, wherein, Each of the plurality of sub-ADCs includes a register for storing values ​​that enable or disable the sub-ADC, and the clock signal generator of each of the plurality of clock generators includes a register for storing values ​​that enable or disable the clock signal generator.

13. A method of receiving a receiver, the receiver comprising a plurality of clock generators and a plurality of time-interleaved analog-to-digital converters (ADCs), the ADCs comprising a plurality of sub-ADCs, the method comprising: A clock signal generator is used to generate multiple sampled clock signals with multiple sampling phases, each of the multiple sampled clock signals having a corresponding sampling phase among the multiple sampling phases; The analog input signal is sampled by each of the plurality of sub-ADCs at one of the plurality of sampling phases corresponding to the sub-ADC, so as to convert the sampled analog input signal into a digital sample. as well as In response to the receiver being configured to operate at a data rate that is a portion of the maximum data rate of the receiver among a plurality of data rates, at least one of the plurality of time-interleaved ADCs is enabled for a portion of the plurality of sub-ADCs of the time-interleaved ADC to sample the analog input signal at the data rate and the remainder of the plurality of sub-ADCs is disabled. Wherein, in response to the data rate being half of the receiver's maximum data rate, the portion of the plurality of sub-ADCs that are enabled to sample the analog input signal at the data rate includes half of the plurality of sub-ADCs of all time-interleaved ADCs in the plurality of time-interleaved ADCs.

14. The method according to claim 13, wherein, In response to the receiver being configured to operate at a data rate that is part of the receiver’s maximum data rate, a portion of the plurality of clock signal generators among the plurality of clock generators is enabled.

15. The method according to claim 14, wherein, The clock signal generator of the clock generator includes multiple phase interpolators and multiple clock dividers, and the method further includes: A reference clock signal is received at the plurality of phase interpolators; Each of the plurality of phase interpolators generates a plurality of clock signals based on the reference clock signal, wherein each of the plurality of clock signals has a different sampling phase; The plurality of clock signals are received from a corresponding phase interpolator among the plurality of phase interpolators through each of the plurality of clock dividers, and A portion of the plurality of sampled clock signals having the plurality of sampled phases is generated by each of the plurality of clock dividers.

16. The method of claim 14, further comprising: In response to the receiver being configured to operate at a data rate that is part of the receiver’s maximum data rate, the remainder of the plurality of clock signal generators are disabled.

17. The method of claim 14, wherein, Enabling a portion of the plurality of sub-ADCs and enabling a portion of the plurality of clock signal generators includes: In response to the data rate being half of the receiver's maximum data rate, half of the sub-ADCs of each of the plurality of time-interleaved ADCs are enabled, and half of the clock signal generators of the plurality of clock signal generators are enabled.

18. The method of claim 17, further comprising: Disable the remaining half of the multiple sub-ADCs of all time-interleaved ADCs in a multi-time-interleaved ADC; and Disable the remaining half of the clock signal generators.

19. The method of claim 14, wherein, Enabling a portion of the plurality of sub-ADCs and enabling a portion of the plurality of clock signal generators includes: In response to the data rate being the minimum data rate of the receiver, one of the multiple sub-ADCs included in each of the multiple time-interleaved ADCs is enabled, and one of the multiple clock signal generators is enabled.

20. The method of claim 19, further comprising: Disable the remaining sub-ADCs of all time-interleaved ADCs in the plurality of time-interleaved ADCs, and disable the remaining plurality of clock signal generators.

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