Method and apparatus for managing access to interrupt events in a CPLD
By managing interrupt events through the interrupt register list and priority sorting in the CPLD, the efficiency problem of the CPU when handling multiple peripheral device interrupt requests is solved, achieving fast response and efficient processing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUAXIN INFOTECH LTD
- Filing Date
- 2021-09-27
- Publication Date
- 2026-06-05
AI Technical Summary
In existing technologies, when a CPU processes interrupt requests from multiple peripheral devices, it needs to continuously query status information, resulting in invalid queries taking up time and reducing the CPU's efficiency and response speed.
Interrupt events are managed using the interrupt register list method in CPLD. Interrupt requests are processed by sorting and prioritizing, and interrupt signals are aggregated to the CPU. When the CPU processes interrupts, it masks new requests to ensure that high-priority interrupts are processed in priority order.
It enables fast interrupt address lookup, reduces interrupt handling time, improves CPU processing efficiency and response speed, and ensures that multiple interrupt requests are processed in logical order.
Smart Images
Figure CN113886041B_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention generally relate to the field of communications, and more particularly to an access management method and apparatus for interruption events. Background Technology
[0002] In current circuit designs, interrupt polling and handling primarily employ a time-sharing control approach. Each peripheral device provides one or more status information entries. The CPU sequentially reads and checks the status information of each peripheral device. If the peripheral device requests service, it provides the service and then clears the status information. Otherwise, it skips the request and checks the status of the next peripheral device. After checking all peripheral devices, the process returns to the beginning of the polling process until a stop command is issued. The CPU needs to continuously read and check the status words, regardless of whether a peripheral device has requested service. This repeated polling consumes significant CPU time, and most of these polls are ineffective.
[0003] When a peripheral device needs to request service, it sends an interrupt request to the CPU. The CPU responds to the peripheral device interrupt, suspends its current program, and switches to executing a service routine for that peripheral device. After the interrupt is handled, the CPU returns to its original program. Using this interrupt method for data transfer can significantly improve CPU utilization. However, even with this interrupt method, the CPU still needs to poll for the interrupt. Since multiple peripheral devices share a single interrupt request, polling must be performed within the interrupt service routine, wasting considerable CPU interrupt handling time. Furthermore, each peripheral device needs to be assigned an interrupt request number.
[0004] This method improves CPU utilization but reduces CPU efficiency, wastes unnecessary time in the CPU's interrupt handler, and cannot respond to peripheral device interrupt requests in the fastest possible time. Summary of the Invention
[0005] According to an embodiment of the present invention, a method and apparatus for access management of interrupt events in a CPLD are provided.
[0006] In a first aspect of the invention, a method for access management of interrupt events in a CPLD is provided. The method includes:
[0007] S01: The interrupt register in the CPLD operates on the access management of each burst event in the form of an interrupt register list;
[0008] S02: The interrupt register in the CPLD sorts the interrupt register list;
[0009] S03: The interrupt register in the CPLD is mapped upwards and finally summarized at the top level. The CPLD monitors the bits that are 1, converts them to hexadecimal form, determines the address of the interrupt in the interrupt register, and forms the interrupt address register.
[0010] S04: The CPLD sends an interrupt signal to the CPU, and the CPU uses the interrupt handling mechanism to process it.
[0011] Furthermore, the interrupt register sorts the interrupt register list, including: the interrupt register sorts the interrupt register list according to priority, with lower addresses having higher priorities, as shown in Table 1.
[0012] Table 1
[0013]
[0014]
[0015]
[0016] Furthermore, the address of the interrupt register includes:
[0017] L1: Address = X + a + 1 = X + 8 0 *a+8 0
[0018] L2: Address = X + (a + 1) * 8 + (b + 1) = X + 8 1 *a+8 0 *b+8 1 +8 0
[0019] L3: Address = X + [(a+1)*8 + (b+1)]*8 + (c+1) = X + 8 2 *a+8 1 *b+8 0 *c+8 2 +8 1 +8 0
[0020] L4: Address = X + {[(a+1)*8+(b+1)]*8+(c+1)}*8+(d+1)
[0021] =X+8 3 *a+8 2 *b+8 1 *c+8 0 *d+8 3 +8 2 +8 1 +8 0 .........
[0023] Ln: Address = X + 8 n -1*a+8 n -2*b+8 n -3*c+...8 n -n*z+8 n -1+8 n -2+8 n -3+...+8 n -n
[0024] =X+8n-1*a+8n-2*b+8n-3*c+...8n-n*z+(8n-1) / 7
[0025] Where: a, b, c, d... represent the bits in the corresponding level.
[0026] The minimum total number of interrupt registers required is shown in Table 2:
[0027] Table 2
[0028]
[0029] Where: N is the number of interrupt events; n is the register level, 8 n-1 <N<8 n .
[0030] [N] is the floor function, also known as the Gaussian function;
[0031] L1: The interrupt level is 1
[0032] L2: The interruption level is 2.
[0033] L3: The interruption level is 3.
[0034] ...
[0035] Ln: The interruption level is n
[0036] It can be simplified as follows:
[0037] Total number of interrupt registers = n + [N / 8] n-1 ]+[N / 8 n-2 ]+…+[N / 8 n-(n-1 )]
[0038] =n+[(N / 8)*(1-1 / 8)] n ) / (1-1 / 8)]
[0039] =n+[(N / 7)*(1-1 / 8)] n )]
[0040] ≈n + [N / 7]
[0041] Furthermore, the interrupt handling mechanism includes:
[0042] S041: The CPU receives the interrupt signal from the CPLD and responds to the interrupt. When processing the interrupt, the masking signal is pulled low, indicating that the CPU will no longer receive new interrupts.
[0043] S042: During CPU interrupt handling, the CPLD retains the corresponding interrupt and does not change the contents of the interrupt address register.
[0044] S043: After the CPU finishes processing the interrupt event, the CPU will pull the masking signal high, and the CPU can then process the next interrupt request sent by the CPLD.
[0045] Furthermore, in S043, after the CPU finishes processing the interrupt event, the contents of the interrupt address register in the CPLD are cleared.
[0046] In a second aspect of the invention, an access management device for interrupt events in a CPLD is provided. The device includes:
[0047] Register module: includes interrupt register module and interrupt address register;
[0048] The interrupt register is used to manage access to each burst event in the form of an interrupt register list, and the interrupt register list is sorted as shown in Table 3.
[0049] Table 3
[0050]
[0051]
[0052]
[0053] The interrupt address register is used to map the interrupt register to the upper layer, and finally summarizes it to the top layer. The CPLD monitors the bits that are 1, converts them into hexadecimal form, determines the address of the interrupt in the interrupt register, and forms the interrupt address register.
[0054] CPU module: Used to receive interrupt signals sent by CPLD and process them using an interrupt handling mechanism.
[0055] Furthermore, the address of the interrupt register includes:
[0056] L1: Address = X + a + 1 = X + 8 0 *a+8 0
[0057] L2: Address = X + (a + 1) * 8 + (b + 1) = X + 8 1 *a+8 0 *b+8 1 +8 0
[0058] L3: Address = X + [(a+1)*8 + (b+1)]*8 + (c+1) = X + 8 2 *a+8 1 *b+8 0 *c+8 2 +8 1 +8 0
[0059] L4: Address = X + {[(a+1)*8+(b+1)]*8+(c+1)}*8+(d+1)
[0060] =X+8 3 *a+8 2 *b+8 1 *c+8 0 *d+8 3 +8 2 +8 1 +8 0 .........
[0062] Ln: Address = X + 8 n -1*a+8 n -2*b+8 n -3*c+...8 n -n*z+8 n -1+8 n -2+8 n -3+...+8 n -n
[0063] =X+8n-1*a+8n-2*b+8n-3*c+...8n-n*z+(8n-1) / 7
[0064] Where: a, b, c, d... are the bits in the corresponding level.
[0065] The minimum number of interrupt registers required in total is shown in Table 4:
[0066] Table 4
[0067]
[0068] Where: N is the number of interrupt events; n is the register level, 8 n-1 <N<8n .
[0069] [N] is the floor function, also known as the Gaussian function;
[0070] L1: The interrupt level is 1
[0071] L2: The interruption level is 2.
[0072] L3: The interruption level is 3.
[0073] ...
[0074] Ln: The interruption level is n
[0075] It can be simplified to:
[0076] Total number of interrupt registers = n + [N / 8] n-1 ]+[N / 8 n-2 ]+…+[N / 8 n-(n-1 )]
[0077] =n+[(N / 8)*(1-1 / 8)] n ) / (1-1 / 8)]
[0078] =n+[(N / 7)*(1-1 / 8)] n )]
[0079] ≈n + [N / 7]
[0080] Furthermore, the interrupt handling mechanism includes:
[0081] S1: The CPU receives the interrupt signal from the CPLD and responds to the interrupt. When processing the interrupt, the masking signal is pulled low, indicating that the CPU will no longer receive new interrupts.
[0082] S2: During CPU interrupt handling, the CPLD retains the corresponding interrupt and does not change the contents of the interrupt address register.
[0083] S3: After the CPU finishes processing the interrupt event, the CPU will pull the masking signal high, and the CPU can then process the next interrupt request sent by the CPLD.
[0084] Furthermore, in S3, after the CPU finishes processing the interrupt event, the contents of the interrupt address register in the CPLD are cleared.
[0085] The above-mentioned English abbreviations are explained as follows:
[0086] CPU: Central Processing Unit
[0087] CPLD: Complex Programming Logic Device
[0088] This invention can quickly query interrupt addresses and make interrupts traceable. When multiple interrupts occur simultaneously, high-priority interrupts can be processed in logical order, reducing interrupt processing time and improving CPU processing efficiency.
[0089] It should be understood that the description in the Summary of the Invention is not intended to limit the key or essential features of the embodiments of the present invention, nor is it intended to restrict the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description
[0090] The above and other features, advantages, and aspects of the various embodiments of the present invention will become more apparent from the accompanying drawings and the following detailed description. Wherein:
[0091] Figure 1 A flowchart illustrating an access management method for interrupt events in a CPLD according to an embodiment of the present invention is shown;
[0092] Figure 2 A flowchart of the interrupt handling mechanism according to an embodiment of the present invention is shown;
[0093] Figure 3 A hardware connection block diagram according to an embodiment of the present invention is shown;
[0094] Figure 4 A block diagram of an access management device for interrupt events in a CPLD according to an embodiment of the present invention is shown. Detailed Implementation
[0095] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0096] Figure 3 In this configuration, the switch supports 48 gigabit optical modules, each with three interrupt signals: SFP_PRESENT_N, SFP_TX_FAULT, and SFP_RX_LOS. These 48 * 3 = 144 interrupts are connected to the CPLD.
[0097] According to the SFF-8431 specification:
[0098] 1. Tx_Fault: Tx_Fault is the module output. A high output value indicates that the module transmitter has detected a fault condition related to laser operation or safety. If Tx_Fault is not triggered, the Tx_Fault contact signal will be held low by the module and may be connected to the ground signal within the module. The Tx_Fault output is an open drain / collector and should be pulled to Vcc_Host in the host with a resistance ranging from 4.7kΩ to 10kΩ.
[0099] 2.MoD_ABS
[0100] Mod_ABS connects to either the optical module's transmit or receive signal ground level in the SFP+ module. The host can pull this contact to the mains voltage using a resistor from 4.7kΩ to 10kΩ. When the SFP+ module is not in the host slot, Mod_ABS is considered "high". In the SFP MSA (info-8074i), this contact has the same function but is called MOD_DEFO.
[0101] 3. Rx_LOS
[0102] A high Rx_LOS value indicates that the optical signal level is below the relevant standard. Rx_LOS is an open drain / collector output, but it can also be used as an input to the monitoring circuitry within the module. A resistor with a nominal 3.3V mains voltage should have a resistance value between 4.7kΩ and 10kΩ, and a resistor with a nominal 2.5V mains voltage should have a resistance value between 4.7kΩ and 7.2kΩ.
[0103] The relevant interrupt registers are allocated as shown in Table 5:
[0104] Table 5
[0105]
[0106] Next, registers are allocated for detecting interrupt input pins and enabling interrupts, as shown in Table 6:
[0107] Table 6
[0108]
[0109]
[0110] Set the interrupt address register to 0x7f.
[0111] The next step is to dejitter the signal to prevent accidental interruption:
[0112]
[0113]
[0114]
[0115] Next, an array is generated to store the interrupt register list; a total of 72 registers are generated to store the interrupt registers.
[0116] --Register Definition
[0117] --type describing the byte array consisting of 8byte matrix array
[0118] type matrix_int is array(72downto 0)of std_logic_vector(7downto 0);
[0119] signal Int: matrix_int;
[0120] 144 interrupt signals are monitored, but an interrupt occurs when a signal changes:
[0121]
[0122]
[0123] When an interrupt occurs, the interrupt register in the CPLD manages access to each burst event by operating the interrupt register list.
[0124] The interrupt register list is sorted, with lower addresses indicating higher priorities, as shown in Table 7.
[0125] Table 7
[0126]
[0127] The interrupt register is mapped upwards and eventually aggregated at the top level. The CPLD monitors the bits that are 1 in the register.
[0128]
[0129]
[0130]
[0131]
[0132]
[0133] Then convert it to hexadecimal form to determine the address in the interrupt register where the interrupt occurred:
[0134] Int_num <= 64*a + 8*b + c;
[0135] Reg_0x7f<=conv_std_logic_vector(Int_num,8);
[0136] The CPLD sends an interrupt signal to the CPU. The CPU receives the interrupt signal and responds to the interrupt. When processing the interrupt with interrupt number 4, the mask signal is pulled low, indicating that the CPU will no longer receive new interrupts.
[0137] During CPU interrupt handling, the CPLD retains the corresponding interrupt and does not change the contents of the interrupt address register.
[0138] After the CPU processes the interrupt event, the CPLD clears the contents of the interrupt address register by clearing the interrupt reset value.
[0139]
[0140]
[0141] The CPU pulls the shield signal high to indicate that it can receive the next interrupt. The CPLD sends the next interrupt request to the CPU. After receiving the request, the CPU responds to the interrupt and pulls the shield signal low.
[0142] The interrupt address register is updated in real time according to the masking signal provided by the CPU. The CPU reads the interrupt number in the CPLD through the I2C interface and executes the corresponding interrupt operation.
[0143] Based on the same inventive concept, this invention also proposes an access management device for interrupt events in a CPLD. The implementation of this device can be found in the implementation of the method described above; details that are repeated will not be repeated. Figure 4 As shown, the device 100 includes:
[0144] Register module 101 includes interrupt register module 1011 and interrupt address register module 1012;
[0145] The interrupt register module is used to manage access to each burst event in the form of an interrupt register list and to sort the interrupt register list;
[0146] The interrupt address register module is used to map interrupt registers to higher layers, ultimately summarizing them at the top level. The CPLD monitors the bits that are 1, converts them to hexadecimal form, and determines the address of the interrupt in the interrupt register, thus forming the interrupt address register. CPU module 102: is used to receive interrupt signals sent by the CPLD and process them using the interrupt handling mechanism.
[0147] The interrupt event access management device proposed in this invention can quickly query interrupt addresses and make interrupts traceable. When multiple interrupts occur simultaneously, high-priority interrupts can be processed in logical order, reducing interrupt processing time and improving CPU processing efficiency.
[0148] While the spirit and principles of the invention have been described with reference to several specific embodiments, it should be understood that the invention is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined for benefit; such division is merely for ease of description. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
[0149] Regarding the limitation of the scope of protection of this invention, those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solution of this invention are still within the scope of protection of this invention.
Claims
1. A method for access management of interrupt events in a CPLD, characterized in that, The method includes: S01: The interrupt register in the CPLD operates on the access management of each burst event in the form of an interrupt register list; S02: The interrupt register in the CPLD sorts the interrupt register list according to priority; the lower the address, the higher the priority. S03: The interrupt register in the CPLD is mapped to the upper layer and finally summarized to the top layer. The CPLD monitors the bits that are 1, converts them into hexadecimal form, determines the address of the interrupt in the interrupt register, and forms the interrupt address register. S04: The CPLD sends an interrupt signal to the CPU, and the CPU uses the interrupt handling mechanism to process it.
2. The access management method for interrupt events in a CPLD according to claim 1, characterized in that, The interrupt handling mechanism of S04 includes: S041: The CPU receives and responds to the interrupt signal sent by the CPLD. When processing the interrupt, the shielding signal is pulled low, and the CPU will no longer receive new interrupts. S042: During CPU interrupt handling, the CPLD retains the corresponding interrupt and does not change the contents of the interrupt address register. S043: After the CPU finishes processing the interrupt event, the CPU will pull the masking signal high, and the CPU can process the next interrupt request sent by the CPLD.
3. The access management method for interrupt events in a CPLD according to claim 2, characterized in that, After the CPU finishes processing the interrupt event in S043, the contents of the interrupt address register in the CPLD are cleared.
4. An access management device for interrupt events in a CPLD, characterized in that, The device includes: Register module: includes interrupt register module and interrupt address register; The interrupt register is used to manage access to each burst event in the form of an interrupt register list, and the interrupt register list is sorted by priority, with lower addresses having higher priorities; The interrupt address register is used to map the interrupt register to the upper layer, and finally summarizes it to the top layer. The CPLD monitors the bits that are 1, converts them into hexadecimal form, determines the address of the interrupt in the interrupt register, and forms the interrupt address register. CPU module: Used to receive interrupt signals sent by CPLD and process them using an interrupt handling mechanism.
5. The access management device for interrupt events in a CPLD according to claim 4, characterized in that, The interrupt handling mechanism includes: S1: The CPU receives the interrupt signal sent by the CPLD and responds to the interrupt. When processing the interrupt, the masking signal is pulled low, and the CPU will no longer receive new interrupts. S2: During CPU interrupt handling, the CPLD retains the corresponding interrupt and does not change the contents of the interrupt address register. S3: After the CPU finishes processing the interrupt event, the CPU will pull the masking signal high, and the CPU can then process the next interrupt request sent by the CPLD.
6. The access management device for interrupt events in a CPLD according to claim 5, characterized in that, After the CPU finishes processing the interrupt event in S3, the contents of the interrupt address register in the CPLD are cleared.