Display device

Abstract

A display device is provided. The display device includes: a substrate having a display area; a plurality of pixel circuits arranged in the display area, each of the pixel circuits including a thin-film transistor; a plurality of display elements respectively connected to the pixel circuits; and a composite layer disposed between the pixel circuits and the display elements, the composite layer including a first inorganic insulating layer, a first organic insulating layer and a second inorganic insulating layer stacked in sequence.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2020-0081671, filed on July 2, 2020, which is incorporated herein by reference for all purposes, as fully set forth herein. Technical Field

[0002] One or more embodiments of the invention generally relate to a display device. Background Technology

[0003] Typically, a display device includes a display element and electronic devices configured to control electrical signals applied to the display element. The electronic devices include thin-film transistors (TFTs), storage capacitors, and multiple wirings.

[0004] In recent years, the uses of display devices have diversified. Furthermore, display devices have become thinner and lighter, thus expanding their applications. As display devices are used in various ways, the methods for designing their shapes are also increasing.

[0005] The information disclosed in this background section is only for understanding the background of the inventive concept, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0006] Display devices constructed according to one or more embodiments of the invention can improve flexibility and robustness against external impacts.

[0007] Additional features of the inventive concept will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of the inventive concept.

[0008] The display device according to an embodiment includes: a substrate having a display area; a plurality of pixel circuits disposed in the display area, each of the plurality of pixel circuits including a thin-film transistor; a plurality of display elements respectively connected to the plurality of pixel circuits; and a composite layer disposed between the plurality of pixel circuits and the plurality of display elements, the composite layer including a first inorganic insulating layer, a first organic insulating layer and a second inorganic insulating layer stacked in sequence.

[0009] The thickness of each of the first and second inorganic insulating layers can be approximately [thickness value missing]. to approximately Within a certain range, the thickness of the first organic insulating layer can be approximately to approximately Within the range.

[0010] The strength of each of the first and second inorganic insulating layers can be in the range of about 80 GPa to about 200 GPa, and the strength of the first organic insulating layer can be in the range of about 1 GPa to about 10 GPa.

[0011] The composite layer may also include a lower organic insulating layer disposed between the multiple pixel circuits and the first inorganic insulating layer.

[0012] The composite layer may also include an upper organic insulating layer disposed between the second inorganic insulating layer and the plurality of display elements.

[0013] The composite layer may also include a second organic insulating layer and a third inorganic insulating layer stacked in sequence.

[0014] The display device may also include: an inorganic material layer disposed in the display area and including an opening or groove in a region located between a plurality of pixel circuits; and an organic material layer filling the opening or groove.

[0015] An opening or slot can surround each of multiple pixel circuits.

[0016] An opening or slot may surround at least a portion of a plurality of pixel circuits.

[0017] The display device may also include: an inorganic material layer disposed in the display area and including openings or slots in the area between a plurality of pixel circuits; and an organic interlayer insulating layer disposed in substantially the entire display area and filling the openings or slots.

[0018] A display device according to another embodiment includes: a substrate including a display area and a peripheral area located outside the display area; a circuit layer disposed in the display area of ​​the substrate, the circuit layer including a first pixel circuit and a second pixel circuit; a display element layer disposed on the circuit layer, the display element layer including a first display element connected to the first pixel circuit and a second display element connected to the second pixel circuit; and a composite layer disposed between the circuit layer and the display element layer, the composite layer including a first inorganic insulating layer, a first organic insulating layer and a second inorganic insulating layer, wherein the circuit layer further includes an inorganic material layer having an opening or a groove in the region between the first pixel circuit and the second pixel circuit.

[0019] The first organic insulating layer can be disposed between the first inorganic insulating layer and the second inorganic insulating layer.

[0020] Display devices may also include layers of organic material that fill openings or grooves.

[0021] The display device may also include connecting lines arranged on an organic material layer to overlap with openings or slots, wherein the connecting lines may extend to the upper surface of the inorganic material layer.

[0022] Display devices may also include an organic interlayer insulating layer that is distributed across substantially the entire display area and fills openings or slots.

[0023] In a plan view, an opening or slot can surround each of the first pixel circuit and the second pixel circuit.

[0024] An opening or slot can surround at least the first pixel circuit and the second pixel circuit together.

[0025] The composite layer may also include an additional organic insulating layer.

[0026] The thickness of each of the first and second inorganic insulating layers can be approximately [thickness value missing]. to approximately Within a certain range, the thickness of the first organic insulating layer can be approximately to approximately Within the range.

[0027] The strength of each of the first and second inorganic insulating layers can be in the range of about 80 GPa to about 200 GPa, and the strength of the first organic insulating layer can be in the range of about 1 GPa to about 10 GPa.

[0028] It will be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the invention as claimed. Attached Figure Description

[0029] The accompanying drawings illustrate one or more embodiments of the invention and, together with the description, serve to explain the inventive concept. The drawings are included to provide a further understanding of the invention and are incorporated in and form part of this specification.

[0030] Figure 1 This is a schematic plan view of a display device according to an embodiment.

[0031] Figure 2A and Figure 2B This is an equivalent circuit diagram of the pixel circuit for driving pixels according to an embodiment.

[0032] Figure 3 This is a schematic cross-sectional view of the display area of ​​a display device according to an embodiment.

[0033] Figure 4 This is a schematic cross-sectional view of a portion of a display device according to an embodiment.

[0034] Figure 5 This is a schematic cross-sectional view of a portion of a display device according to an embodiment.

[0035] Figure 6This is a schematic cross-sectional view of a portion of a display device according to an embodiment.

[0036] Figure 7 This is a schematic cross-sectional view of a portion of a display device according to an embodiment.

[0037] Figure 8 This is a schematic cross-sectional view of a portion of a display device according to an embodiment.

[0038] Figure 9 This illustrates an embodiment. Figure 7 and Figure 8 A plan view of the slot or opening shown.

[0039] Figure 10 This illustrates an embodiment. Figure 7 and Figure 8 A plan view of the slot or opening shown.

[0040] Figure 11 This is a schematic diagram of a display device according to an embodiment.

[0041] Figure 12 This is a schematic diagram of a display device according to an embodiment.

[0042] Figure 13 The results of testing the impact resistance of a display device according to an embodiment are shown. Detailed Implementation

[0043] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of one or more different embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms as non-limiting examples of apparatuses or methods employing one or more of the inventive concepts disclosed herein. However, it will be apparent that different embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring different exemplary embodiments. Furthermore, different embodiments may differ, but are not necessarily exclusive. For example, the specific shape, construction, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0044] Unless otherwise stated, the one or more embodiments shown are to be understood as exemplary features providing different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as “elements”) of different embodiments may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0045] Crosshairs and / or shading are typically used in accompanying drawings to clearly define the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, scale, commonalities between the elements shown, or any other characteristics, properties, etc. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. A particular process sequence may be performed in a manner different from that described when exemplary embodiments can be implemented differently. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Moreover, the same reference numerals denote the same elements.

[0046] When a component or layer is referred to as being "on," "connected to," or "bonded to" another component or layer, the component or layer may be directly on, directly connected to, or directly bonded to the other component or layer, or there may be intermediate components or intermediate layers. However, when a component or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another component or layer, there are no intermediate components or intermediate layers. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without intermediate components. Furthermore, the D1, D2, and D3 axes are not limited to the three axes of a Cartesian coordinate system (such as the x, y, and z axes) but can be interpreted in a broader sense. For example, the D1, D2, and D3 axes can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0047] Although the terms "first," "second," etc., may be used here to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the publicly stated teachings, the first element discussed below may be referred to as the second element.

[0048] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., in a “sidewall”) may be used herein to describe the relationship of an element as shown in the accompanying drawings to other elements. In addition to the orientations depicted in the drawings, spatial relative terms are intended to also include different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features would then be positioned “above” said other elements or features. Thus, the exemplary term “below” can include both above and below orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0049] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising” and / or “including” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and are thus used to interpret the inherent biases in measurements, calculated values, and / or provided values ​​that will be recognized by those skilled in the art.

[0050] Different embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of one or more idealized embodiments and / or intermediate structures. Thus, variations in the shapes illustrated will be expected, for example, due to manufacturing techniques and / or tolerances. Therefore, the one or more embodiments disclosed herein should not be construed as limited to the shapes of the specifically shown areas, but will include deviations in shape caused, for example, by manufacturing processes. In this way, the areas shown in the drawings can be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, thus not intended to be limiting.

[0051] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless clearly defined herein.

[0052] Figure 1 This is a schematic plan view of the display device 10 according to an embodiment.

[0053] Reference Figure 1 Various components forming the display device 10 are arranged on the substrate 100. The substrate 100 may include a display area DA and a peripheral area DPA surrounding the display area DA.

[0054] Pixels P are arranged in the display area DA of the substrate 100. Pixels P can all be implemented as display elements, such as organic light-emitting diodes (OLEDs). Pixels P can all emit, for example, red, green, blue, or white light. The display area DA can be covered by a sealing member to protect it from external air or moisture.

[0055] The pixel circuitry for driving pixel P can be electrically connected to external circuitry arranged in the peripheral region DPA. The first scan drive circuit SDRV1, the second scan drive circuit SDRV2, the terminal PAD, the drive voltage supply line 11, and the common voltage supply line 13 can be arranged in the peripheral region DPA.

[0056] The first scan driving circuit SDRV1 can apply scan signals to each pixel circuit for driving pixel P via scan line SL. Additionally, the first scan driving circuit SDRV1 can apply emission control signals to each pixel circuit via emission control line EL. The second scan driving circuit SDRV2 can be opposite the first scan driving circuit SDRV1, with the display area DA located between them. The second scan driving circuit SDRV2 can be substantially parallel to the first scan driving circuit SDRV1. Some pixel circuits of pixel P can be electrically connected to the first scan driving circuit SDRV1, and the remaining pixel circuits of pixel P can be electrically connected to the second scan driving circuit SDRV2. In some embodiments, the second scan driving circuit SDRV2 can be omitted.

[0057] Terminal PADs can be disposed on one side of the substrate 100. The terminal PADs can be exposed without being covered by an insulating layer and can be electrically connected to the display circuit board 30. The display driver 32 can be disposed on the display circuit board 30.

[0058] The display driver 32 can generate control signals to be transmitted to the first scan drive circuit SDRV1 and the second scan drive circuit SDRV2. The display driver 32 can generate data signals and transmit the generated data signals to the pixel circuit of pixel P via the fan-out wiring FW and the data line DL connected to the fan-out wiring FW.

[0059] The display driver 32 can drive voltage ELVDD (see...) Figure 2A ) is supplied to drive voltage supply line 11, and the common voltage ELVSS (see Figure 2A The driving voltage ELVDD can be applied to the pixel circuit of pixel P via the driving voltage line PL connected to the driving voltage supply line 11, and the common voltage ELVSS can be applied to the counter electrode of the display element connected to the common voltage supply line 13.

[0060] The drive voltage supply line 11 can extend along the x-direction from the bottom of the display area DA. The common voltage supply line 13 can partially surround the display area DA and have an opening on one side of the display area DA.

[0061] Figure 2A and Figure 2B This is an equivalent circuit diagram of a pixel circuit PC for driving pixel P according to an embodiment.

[0062] Reference Figure 2A The pixel circuit PC can be connected to the display element ED to realize the light emission of the pixel. The pixel circuit PC includes a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The switching thin-film transistor T2 is connected to the scan line SL and the data line DL, and is configured to transmit the data signal Dm input via the data line DL to the driving thin-film transistor T1 according to the scan signal Sn input via the scan line SL.

[0063] The storage capacitor Cst is connected to the switching thin-film transistor T2 and the drive voltage line PL, and is configured to store a voltage corresponding to the difference between the voltage received from the switching thin-film transistor T2 and the drive voltage ELVDD supplied to the drive voltage line PL.

[0064] The driving thin-film transistor T1 can be connected to the driving voltage line PL and the storage capacitor Cst, and can be configured to control the driving current flowing from the driving voltage line PL to the display element ED based on the voltage value stored in the storage capacitor Cst. The display element ED can emit light with a specific brightness according to the driving current.

[0065] Figure 2A An exemplary pixel circuit PC comprising two thin-film transistors and a storage capacitor is shown, but the inventive concept is not limited thereto.

[0066] Reference Figure 2B The pixel circuit PC may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, and a second initialization thin-film transistor T7.

[0067] although Figure 2B An exemplary diagram illustrates a pixel circuit PC comprising signal lines SL, SL-1, SL+1, EL, and DL, an initialization voltage line VL, and a drive voltage line PL, configured for each pixel circuit PC; however, the inventive concept is not limited thereto. In another embodiment, at least one of the signal lines (i.e., scan line SL, previous scan line SL-1, next scan line SL+1, transmit control line EL, and data line DL) and the initialization voltage line VL may be shared by adjacent pixel circuit PCs.

[0068] The drain electrode of the driving thin-film transistor T1 can be electrically connected to the display element ED via the emitter control thin-film transistor T6. The driving thin-film transistor T1 is configured to receive the data signal Dm according to the switching operation of the switching thin-film transistor T2 and supply driving current to the display element ED.

[0069] The gate electrode of the switching thin-film transistor T2 is connected to the scan line SL, and the source electrode of the switching thin-film transistor T2 is connected to the data line DL. The drain electrode of the switching thin-film transistor T2 can be connected to the source electrode of the driving thin-film transistor T1, and is connected to the driving voltage line PL via the operation control thin-film transistor T5.

[0070] The switching thin-film transistor T2 is turned on according to the scan signal Sn received via the scan line SL, and performs a switching operation to transmit the data signal Dm received from the data line DL to the source electrode of the driving thin-film transistor T1.

[0071] The gate electrode of the compensation thin-film transistor T3 can be connected to the scan line SL. The source electrode of the compensation thin-film transistor T3 can be connected to the drain electrode of the driving thin-film transistor T1, and is connected to the pixel electrode of the display element ED via the emitter control thin-film transistor T6. The drain electrode of the compensation thin-film transistor T3 can be connected to any electrode of the storage capacitor Cst, the source electrode of the first initialization thin-film transistor T4, and the gate electrode of the driving thin-film transistor T1. The compensation thin-film transistor T3 is turned on according to the scan signal Sn received via the scan line SL, and connects the gate electrode and drain electrode of the driving thin-film transistor T1 to each other to provide a diode connection for the driving thin-film transistor T1.

[0072] The gate electrode of the first initialization thin-film transistor T4 can be connected to the previous scan line SL-1. The drain electrode of the first initialization thin-film transistor T4 can be connected to the initialization voltage line VL. The source electrode of the first initialization thin-film transistor T4 can be connected to any electrode of the storage capacitor Cst, the drain electrode of the compensation thin-film transistor T3, and the gate electrode of the driving thin-film transistor T1. The first initialization thin-film transistor T4 can be turned on according to the previous scan signal Sn-1 received via the previous scan line SL-1, and perform an initialization operation to transmit the initialization voltage Vint to the gate electrode of the driving thin-film transistor T1, so as to initialize the voltage of the gate electrode of the driving thin-film transistor T1.

[0073] The gate electrode of the operating control thin-film transistor T5 can be connected to the emitter control line EL. The source electrode of the operating control thin-film transistor T5 can be connected to the drive voltage line PL. The drain electrode of the operating control thin-film transistor T5 is connected to the source electrode of the driving thin-film transistor T1 and the drain electrode of the switching thin-film transistor T2.

[0074] The gate electrode of the emitter control thin-film transistor T6 can be connected to the emitter control line EL. The source electrode of the emitter control thin-film transistor T6 can be connected to the drain electrode of the driving thin-film transistor T1 and the source electrode of the compensation thin-film transistor T3. The drain electrode of the emitter control thin-film transistor T6 can be electrically connected to the pixel electrode of the display element ED. The operation control thin-film transistor T5 and the emitter control thin-film transistor T6 are simultaneously turned on according to the emitter control signal En received via the emitter control line EL, and the driving voltage ELVDD is transmitted to the display element ED, so that the driving current flows through the display element ED.

[0075] The gate electrode of the second initialization thin-film transistor T7 can be connected to the next scan line SL+1. The source electrode of the second initialization thin-film transistor T7 can be connected to the pixel electrode of the display element ED. The drain electrode of the second initialization thin-film transistor T7 can be connected to the initialization voltage line VL. The second initialization thin-film transistor T7 can be turned on according to the next scan signal Sn+1 received via the next scan line SL+1, and initialize the pixel electrode of the display element ED.

[0076] although Figure 2B An exemplary illustration shows a first initialization thin-film transistor T4 and a second initialization thin-film transistor T7 connected to the previous scan line SL-1 and the next scan line SL+1, respectively; however, the inventive concept is not limited thereto. In another embodiment, each of the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 may be connected to the previous scan line SL-1 and may be driven according to the previous scan signal Sn-1.

[0077] The other electrode of the storage capacitor Cst can be connected to the drive voltage line PL. Any electrode of the storage capacitor Cst can be connected to the gate electrode of the driving thin-film transistor T1, the drain electrode of the compensation thin-film transistor T3, and the source electrode of the first initialization thin-film transistor T4.

[0078] The counter electrode (e.g., cathode) of the display element ED receives a common voltage ELVSS. The display element ED receives a drive current from the driving thin-film transistor T1 and emits light.

[0079] The inventive concept is not limited to a specific number and specific circuit design of thin-film transistors and storage capacitors in the pixel circuit PC. In other embodiments, the number and circuit design of thin-film transistors and storage capacitors in the pixel circuit PC can be varied.

[0080] Figure 3 It is according to the embodiment along Figure 1 A schematic cross-sectional view taken from line I-I'.

[0081] Reference Figure 3 Multiple pixels P1 and P2 can be arranged in the display area DA of the display device 10. Pixels P1 and P2 may include a first pixel P1 and a second pixel P2. The first pixel P1 may include a first pixel circuit PC1 and a first organic light-emitting diode (OLED) 1 serving as a display element connected to the first pixel circuit PC1. The second pixel P2 may include a second pixel circuit PC2 and a second organic light-emitting diode (OLED) 2 serving as a display element connected to the second pixel circuit PC2. The first organic light-emitting diode (OLED) 1 may include a first pixel electrode 121a, a first emitting layer 122a, and a counter electrode 123, and the second organic light-emitting diode (OLED) 2 may include a second pixel electrode 121b, a second emitting layer 122b, and a counter electrode 123.

[0082] In the illustrated embodiment, the display element is shown as an organic light-emitting diode, but in another embodiment, various display elements (such as inorganic light-emitting devices or quantum dot light-emitting devices) may be used as the display element.

[0083] The display device 10 according to the illustrated embodiment includes a composite layer 200 located between a first pixel circuit PC1 and a second pixel circuit PC2 and a first organic light-emitting diode OLED1 and a second organic light-emitting diode OLED2. The composite layer 200 includes a first inorganic insulating layer 210, a first organic insulating layer 220, and a second inorganic insulating layer 230 stacked sequentially. The composite layer 200 can be configured to significantly reduce the transmission of external shocks to the first pixel circuit PC1 and the second pixel circuit PC2. The composite layer 200 will be described in detail below.

[0084] The components included in the display device 10 will be described below. The display device 10 may include a substrate 100, a barrier layer 101, a buffer layer 111, a circuit layer PCL, a composite layer 200, and a display element layer EDL, which are stacked in sequence.

[0085] The substrate 100 may include an insulating material, such as glass, quartz, or polymer resin. In some embodiments, the substrate 100 may include alternating inorganic and organic insulating layers. The substrate 100 may include a flexible substrate that is bendable, foldable, or rollable.

[0086] A buffer layer 111 may be disposed on a substrate 100 and may reduce or prevent the influence of foreign matter, moisture, or ambient air from below the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 111 may comprise inorganic materials (such as oxides or nitrides), organic materials, or organic-inorganic composite materials, and may have a single-layer structure or a multi-layer structure comprising inorganic and / or organic materials. In some embodiments, the buffer layer 111 may comprise silicon oxide (SiO2). x ) or silicon nitride (SiN) x In some embodiments, the buffer layer 111 may include silicon oxide (SiO2). x ) and / or silicon nitride (SiN) x ) stacked bodies.

[0087] A barrier layer 101 may be disposed between the substrate 100 and the buffer layer 111 to prevent the infiltration of external air. The barrier layer 101 may include silicon oxide (SiO2). x ) or silicon nitride (SiN) x ).

[0088] The circuit layer PCL can be disposed on the buffer layer 111 and can include a first pixel circuit PC1 and a second pixel circuit PC2, a first gate insulating layer 112, a second gate insulating layer 113, an interlayer insulating layer 115, and a planarization layer 117. The first pixel circuit PC1 can include a first thin-film transistor TFT1 and a first storage capacitor Cst1. The second pixel circuit PC2 can include a second thin-film transistor TFT2 and a second storage capacitor Cst2. The construction of the second pixel circuit PC2 is substantially the same as that of the first pixel circuit PC1; therefore, the description of the first pixel circuit PC1 can be applied to the second pixel circuit PC2.

[0089] The first thin-film transistor (TFT) 1 can be disposed on the buffer layer 111. The first TFT 1 includes a first semiconductor layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The first TFT 1 can be connected to a first organic light-emitting diode (OLED) 1 and can be configured to drive the first OLED 1.

[0090] The first semiconductor layer A1 may be disposed on the buffer layer 111 and may comprise polycrystalline silicon. In another embodiment, the first semiconductor layer A1 may comprise amorphous silicon. In yet another embodiment, the first semiconductor layer A1 may comprise an oxide of at least one selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The first semiconductor layer A1 may comprise a channel region and impurity-doped source and drain regions.

[0091] The first gate insulating layer 112 may cover the first semiconductor layer A1. The first gate insulating layer 112 may include an inorganic insulating material, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y The inorganic insulating layer 112 may comprise a single layer or multiple layers containing the aforementioned inorganic insulating materials, such as aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO).

[0092] The first gate electrode G1 can be disposed on the first gate insulating layer 112, such that the first gate electrode G1 is stacked with the first semiconductor layer A1. The first gate electrode G1 may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single layer or multiple layers. For example, the first gate electrode G1 may include a single Mo layer.

[0093] The second gate insulating layer 113 may cover the first gate electrode G1. The second gate insulating layer 113 may include an inorganic insulating material, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y The inorganic insulating layer 113 may comprise a single layer or multiple layers containing the aforementioned inorganic insulating materials, such as aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO).

[0094] The first upper electrode CE2 of the first storage capacitor Cst1 can be disposed on the second gate insulating layer 113. The first upper electrode CE2 can be stacked with the first gate electrode G1 disposed below it. The first gate electrode G1 and the first upper electrode CE2, which are stacked on top of each other and have the second gate insulating layer 113 therebetween, can constitute the first storage capacitor Cst1. In this case, the first gate electrode G1 can be used as the first lower electrode CE1 of the first storage capacitor Cst1.

[0095] The first upper electrode CE2 may comprise aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may comprise a single layer or multiple layers comprising the aforementioned materials. In some embodiments, the first upper electrode CE2 may comprise a single Mo layer.

[0096] The interlayer insulating layer 115 may cover the first upper electrode CE2. The interlayer insulating layer 115 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y The inorganic insulating layer 115 may comprise a single layer or multiple layers containing the aforementioned inorganic insulating materials, such as aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO).

[0097] In some embodiments, interlayer insulation 115 may include an organic insulating material. Interlayer insulation 115 may include general-purpose polymers (e.g., benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, or vinyl alcohol polymers.

[0098] The data line DL, the first source electrode S1, and the first drain electrode D1 can be disposed on the interlayer insulating layer 115. The data line DL, the first source electrode S1, and the first drain electrode D1 can all comprise conductive materials containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can all comprise a single layer or multiple layers containing the aforementioned materials. For example, the data line DL, the first source electrode S1, and the first drain electrode D1 can all have a Ti / Al / Ti multilayer structure.

[0099] The planarization layer 117 can be arranged to cover the data line DL, the first source electrode S1, and the first drain electrode D1. The planarization layer 117 can provide a flat upper surface, such that components disposed thereon are formed on a flat surface.

[0100] Planarization layer 117 may comprise organic or inorganic materials and may have a single-layer or multi-layer structure. Planarization layer 117 may comprise general-purpose polymers (e.g., benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, or vinyl alcohol polymers. x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y The materials used are aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). When the planarization layer 117 is formed, a layer can be formed, and the layer can be chemically mechanically polished to provide a flat upper surface.

[0101] The first connecting electrode CM1, the second connecting electrode CM2, and the wiring WL can be disposed on the planarization layer 117. Due to the composite layer 200, the wiring WL can be further disposed on the planarization layer 117, which can be advantageous for high integration. The first connecting electrode CM1 can be configured to connect the first pixel circuit PC1 to the first organic light-emitting diode OLED1. More specifically, the planarization layer 117 may include a via exposing one of the first source electrode S1 and the first drain electrode D1, and the first connecting electrode CM1 can contact the first source electrode S1 or the first drain electrode D1 via the via, such that the first connecting electrode CM1 is electrically connected to the first thin-film transistor TFT1. Furthermore, the first pixel electrode 121a of the first organic light-emitting diode OLED1 can be connected to the first connecting electrode CM1. Similarly, the second connecting electrode CM2 can be configured to connect the second pixel circuit PC2 to the second organic light-emitting diode OLED2.

[0102] Composite layer 200 can be disposed on circuit layer PCL. Composite layer 200 can cover first connection electrode CM1, second connection electrode CM2 and wiring WL disposed on planarization layer 117. Composite layer 200 may include a first inorganic insulating layer 210, a first organic insulating layer 220 and a second inorganic insulating layer 230 stacked in sequence. More specifically, composite layer 200 may have a structure in which organic insulating layers are sandwiched between inorganic insulating layers.

[0103] The composite layer 200 can prevent external impacts from being transmitted to the first pixel circuit PC1 and the second pixel circuit PC2. The composite layer 200 can be disposed between the first pixel circuit PC1 and the second pixel circuit PC2 and the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2, which are display elements, so as to prevent impacts transmitted from above the display elements from being transmitted to the first pixel circuit PC1 and the second pixel circuit PC2.

[0104] When only an organic insulating layer is disposed between the first pixel circuit PC1 and the second pixel circuit PC2 and the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2, the impact may be absorbed to some extent due to its characteristics. However, large impacts may not be completely absorbed, and some impact may be transmitted to the first pixel circuit PC1 and the second pixel circuit PC2.

[0105] In the illustrated embodiment, the composite layer 200 includes a first inorganic insulating layer 210 and a second inorganic insulating layer 230, both having high strength, located below and above the first organic insulating layer 220, respectively. In this way, the first inorganic insulating layer 210 and the second inorganic insulating layer 230 can absorb and disperse impacts before they are transmitted to the lower portion of the composite layer 200. In this case, the first organic insulating layer 220 can provide a flat upper surface and absorb impacts.

[0106] The first inorganic insulating layer 210 and the second inorganic insulating layer 230 may both comprise silicon oxide (SiO2). x ), silicon nitride (SiN) x ) and / or silicon oxynitride (SiO) x N y The first organic insulating layer 220 may include a general polymer (e.g., benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, or vinyl alcohol polymers).

[0107] In some embodiments, the strength of each of the first inorganic insulating layer 210 and the second inorganic insulating layer 230 can be in the range of about 80 GPa to about 200 GPa, and the strength of the first organic insulating layer 220 can be in the range of about 1 GPa to about 10 GPa. In this way, the composite layer 200 can disperse and absorb shock.

[0108] In some embodiments, the thickness of each of the first inorganic insulating layer 210 and the second inorganic insulating layer 230 can be approximately to approximately Within a certain range, the thickness of the first organic insulating layer 220 can be approximately to approximately Within a certain range. In this way, composite layer 200 can disperse and absorb impact.

[0109] The composite layer 200 may include a first contact hole CNT1 exposing a first connecting electrode CM1 and a second contact hole CNT2 exposing a second connecting electrode CM2. A first organic light-emitting diode OLED1 and a second organic light-emitting diode OLED2 may be connected to a first pixel circuit PC1 and a second pixel circuit PC2 via the first contact hole CNT1 and the second contact hole CNT2, respectively. The first contact hole CNT1 and the second contact hole CNT2 may be formed by stacking a first inorganic insulating layer 210, a first organic insulating layer 220, and a second inorganic insulating layer 230, and performing photoresist patterning and etching processes thereon.

[0110] The display element layer (EDL) is disposed on the composite layer 200. The first organic light-emitting diode (OLED1) and the second organic light-emitting diode (OLED2) can be disposed in the display element layer (EDL).

[0111] The first pixel electrode 121a and the second pixel electrode 121b may both comprise conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The first pixel electrode 121a and the second pixel electrode 121b may both comprise a reflective layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any mixture thereof. For example, the first pixel electrode 121a and the second pixel electrode 121b may both have a structure in which a layer comprising ITO, IZO, ZnO, or In2O3 is disposed above and / or below the reflective layer. In this case, the first pixel electrode 121a and the second pixel electrode 121b may both have an ITO / Ag / ITO stacked structure.

[0112] The first pixel electrode 121a can be connected to the first connection electrode CM1 via a first contact hole CNT1 defined in the composite layer 200. The second pixel electrode 121b can be connected to the second connection electrode CM2 via a second contact hole CNT2 defined in the composite layer 200.

[0113] The pixel defining layer 119 may cover the edges of the first pixel electrode 121a and the second pixel electrode 121b and includes a first opening OP1 and a second opening OP2 that respectively expose the central portions of the first pixel electrode 121a and the second pixel electrode 121b. The first opening OP1 and the second opening OP2 respectively define the size and shape of the emission regions of the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2 (i.e., pixels P1 and P2).

[0114] The pixel defining layer 119 increases the distance between the edges of the first pixel electrode 121a and the second pixel electrode 121b and the counter electrode 123 above the first pixel electrode 121a and the second pixel electrode 121b, thereby preventing electric arcs or the like from occurring at the edges of the first pixel electrode 121a and the second pixel electrode 121b. The pixel defining layer 119 may include at least one organic insulating material, such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and phenolic resin, and may be formed by spin coating or the like.

[0115] The first emitting layer 122a and the second emitting layer 122b, which are respectively formed corresponding to the first pixel electrode 121a and the second pixel electrode 121b, can be arranged in the first opening OP1 and the second opening OP2 of the pixel limiting layer 119, respectively. The first emitting layer 122a and the second emitting layer 122b can both include high molecular weight materials or low molecular weight materials, and can both emit red light, green light, blue light or white light.

[0116] The organic functional layers can be disposed above and / or below the first emission layer 122a and the second emission layer 122b. Each organic functional layer can comprise a single layer or multiple layers containing organic materials. The organic functional layers can include a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and / or an electron injection layer (EIL). The organic functional layers can be integrally formed corresponding to the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2 disposed in the display area DA.

[0117] Counter electrode 123 is disposed on the first emission layer 122a and the second emission layer 122b. Counter electrode 123 may include a conductive material having a low work function. For example, counter electrode 123 may include a (semi-)transparent layer comprising, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Optionally, counter electrode 123 may further include a layer (such as ITO, IZO, ZnO, or In2O3) located on the (semi-)transparent layer comprising the aforementioned materials. Counter electrode 123 may be integrally formed correspondingly to the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2 disposed in the display area DA.

[0118] A capping layer, including an organic material, can be disposed on the counter electrode 123. The capping layer can protect the counter electrode 123 and improve light extraction efficiency. The capping layer may include an organic material having a refractive index greater than that of the counter electrode 123.

[0119] Furthermore, a thin-film encapsulation layer can be disposed on the display element layer (EDL) as a sealing member. In this way, the first organic light-emitting diode (OLED1) and the second organic light-emitting diode (OLED2) can be sealed by the thin-film encapsulation layer. The thin-film encapsulation layer can prevent external moisture or foreign matter from penetrating into the first organic light-emitting diode (OLED1) and the second organic light-emitting diode (OLED2). The thin-film encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In some embodiments, the thin-film encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence.

[0120] Both the first inorganic encapsulation layer and the second inorganic encapsulation layer may include at least one inorganic insulating material, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y The organic encapsulation layer can be formed using materials such as aluminum oxide (Al₂O₃), titanium oxide (TiO₂), tantalum oxide (Ta₂O₅), hafnium oxide (HfO₂), or zinc oxide (ZnO), and can be formed by chemical vapor deposition (CVD). The organic encapsulation layer can include polymeric materials. Polymeric materials can include silicone resins, acrylic resins, epoxy resins, polyimides, polyethylene, etc.

[0121] Figure 4 This is a schematic cross-sectional view of a portion of a display device according to an embodiment. Figure 4 In, with Figure 3 Elements that are substantially the same will be given the same reference numerals.

[0122] The display device according to the illustrated embodiment includes a first pixel circuit PC1 and a second pixel circuit PC2 disposed in a display area DA of a substrate 100, a first organic light-emitting diode (OLED1) and a second organic light-emitting diode (OLED2) respectively connected to the first pixel circuit PC1 and the second pixel circuit PC2, and a composite layer 200 located between the first pixel circuit PC1 and the second pixel circuit PC2 and the first organic light-emitting diode (OLED1) and the second organic light-emitting diode (OLED2). The composite layer 200 includes a first inorganic insulating layer 210, a first organic insulating layer 220 and a second inorganic insulating layer 230 stacked in sequence.

[0123] In the illustrated embodiment, the composite layer 200 may further include a lower organic insulating layer 221 located below the first inorganic insulating layer 210. The lower organic insulating layer 221 may be disposed on the planarization layer 117 to cover the connecting electrodes CM1 and CM2. Since the composite layer 200 also includes the lower organic insulating layer 221, the impact absorption or dispersion and the flatness of the upper surface of the composite layer 200 can be improved.

[0124] The lower organic insulating layer 221 may include general polymers (e.g., benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers or vinyl alcohol polymers).

[0125] In some embodiments, the strength of each of the first inorganic insulating layer 210 and the second inorganic insulating layer 230 can be in the range of about 80 GPa to about 200 GPa, and the strength of each of the first organic insulating layer 220 and the lower organic insulating layer 221 can be in the range of about 1 GPa to about 10 GPa. In this way, the composite layer 200 can disperse and absorb shock.

[0126] In some embodiments, the thickness of each of the first inorganic insulating layer 210 and the second inorganic insulating layer 230 can be approximately to approximately Within a certain range, the thickness of each of the first organic insulating layer 220 and the lower organic insulating layer 221 can be approximately to approximately Within a certain range. In this way, composite layer 200 can disperse and absorb impact.

[0127] Figure 5 This is a schematic cross-sectional view of a portion of a display device according to an embodiment. Figure 5 In, with Figure 3Elements that are substantially the same will be given the same reference numerals.

[0128] The display device according to the illustrated embodiment includes a first pixel circuit PC1 and a second pixel circuit PC2 disposed in a display area DA of a substrate 100, a first organic light-emitting diode (OLED1) and a second organic light-emitting diode (OLED2) respectively connected to the first pixel circuit PC1 and the second pixel circuit PC2, and a composite layer 200 located between the first pixel circuit PC1 and the second pixel circuit PC2 and the first organic light-emitting diode (OLED1) and the second organic light-emitting diode (OLED2). The composite layer 200 includes a first inorganic insulating layer 210, a first organic insulating layer 220 and a second inorganic insulating layer 230 stacked in sequence.

[0129] In the illustrated embodiment, the composite layer 200 may further include an upper organic insulating layer 223 located above the second inorganic insulating layer 230. The upper organic insulating layer 223 may be disposed between the second inorganic insulating layer 230 and the first pixel electrode 121a of the first organic light-emitting diode OLED1 and the second pixel electrode 121b of the second organic light-emitting diode OLED2. Since the composite layer 200 further includes the upper organic insulating layer 223, the impact absorption or dispersion and the flatness of the upper surface of the composite layer 200 can be improved.

[0130] The upper organic insulating layer 223 may include general polymers (e.g., benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers or vinyl alcohol polymers).

[0131] In some embodiments, the strength of each of the first inorganic insulating layer 210 and the second inorganic insulating layer 230 can be in the range of about 80 GPa to about 200 GPa, and the strength of each of the first organic insulating layer 220 and the upper organic insulating layer 223 can be in the range of about 1 GPa to about 10 GPa. In this way, the composite layer 200 can disperse and absorb shock.

[0132] In some embodiments, the thickness of each of the first inorganic insulating layer 210 and the second inorganic insulating layer 230 can be approximately to approximately Within a certain range, the thickness of each of the first organic insulating layer 220 and the upper organic insulating layer 223 can be approximately to approximately Within a certain range. In this way, composite layer 200 can disperse and absorb impact.

[0133] Figure 6 This is a schematic cross-sectional view of a portion of a display device according to an embodiment. Figure 6 In, with Figure 3 Elements that are substantially the same will be given the same reference numerals.

[0134] The display device according to the illustrated embodiment includes a first pixel circuit PC1 and a second pixel circuit PC2 disposed in a display area DA of a substrate 100, a first organic light-emitting diode OLED1 and a second organic light-emitting diode OLED2 respectively connected to the first pixel circuit PC1 and the second pixel circuit PC2, and a composite layer 200 located between the first pixel circuit PC1 and the second pixel circuit PC2 and the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2.

[0135] The composite layer 200 according to the illustrated embodiment may include a first inorganic insulating layer 210, a first organic insulating layer 220, a second inorganic insulating layer 230, a second organic insulating layer 240, and a third inorganic insulating layer 250 stacked in sequence.

[0136] Since the composite layer 200 further includes a second organic insulating layer 240 and a third inorganic insulating layer 250, the impact absorption or dispersion and the flatness of the upper surface of the composite layer 200 can be improved.

[0137] The second organic insulating layer 240 may include a general polymer (e.g., benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers or vinyl alcohol polymers).

[0138] In some embodiments, the strength of each of the first inorganic insulating layer 210, the second inorganic insulating layer 230, and the third inorganic insulating layer 250 can be in the range of about 80 GPa to about 200 GPa, and the strength of each of the first organic insulating layer 220 and the second organic insulating layer 240 can be in the range of about 1 GPa to about 10 GPa. In this way, the composite layer 200 can disperse and absorb shock.

[0139] In some embodiments, the thickness of each of the first inorganic insulating layer 210, the second inorganic insulating layer 230, and the third inorganic insulating layer 250 can be approximately [missing information]. to approximately Within a certain range, the thickness of each of the first organic insulating layer 220 and the second organic insulating layer 240 can be approximately to approximately Within a certain range. In this way, composite layer 200 can disperse and absorb impact.

[0140] However, the inventive concept is not limited thereto. In one or more other embodiments, the composite layer 200 may further include additional organic insulating layers and additional inorganic insulating layers arranged alternately with each other.

[0141] Figure 7 This is a schematic cross-sectional view of a portion of a display device according to an embodiment. Figure 7 In, with Figure 3 Elements that are substantially the same will be given the same reference numerals.

[0142] The display device according to the illustrated embodiment includes a first pixel circuit PC1 and a second pixel circuit PC2 disposed in a display area DA of a substrate 100, a first organic light-emitting diode (OLED1) and a second organic light-emitting diode (OLED2) respectively connected to the first pixel circuit PC1 and the second pixel circuit PC2, and a composite layer 200 located between the first pixel circuit PC1 and the second pixel circuit PC2 and the first organic light-emitting diode (OLED1) and the second organic light-emitting diode (OLED2). The composite layer 200 includes a first inorganic insulating layer 210, a first organic insulating layer 220 and a second inorganic insulating layer 230 stacked in sequence.

[0143] The display device according to the illustrated embodiment further includes an inorganic material layer 11 having an opening or groove GR in the region between pixel circuits PC1 and PC2, and an organic material layer 161 may fill the opening or groove GR. Furthermore, connecting lines 140 may be arranged on the organic material layer 161.

[0144] In this embodiment, the barrier layer 101, buffer layer 111, first gate insulating layer 112, second gate insulating layer 113, and interlayer insulating layer 115 disposed below the connection line 140 and comprising inorganic material can be collectively referred to as the inorganic material layer IL. The inorganic material layer IL has openings or slots GR in the region between adjacent pixel circuits.

[0145] Figure 7 An inorganic material layer IL is shown exemplarily with a groove GR. More specifically, the barrier layer 101 may be continuous across the first pixel circuit PC1 and the second pixel circuit PC2 of adjacent pixels. The buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 may have openings 111a, 112a, 113a, and 115a, respectively, in the region between adjacent pixels.

[0146] Thus, the barrier layer 101, buffer layer 111, first gate insulating layer 112, second gate insulating layer 113, and interlayer insulating layer 115 may each have a trench GR in the region between adjacent pixels. The trench GR may refer to a groove formed in the inorganic material layer IL.

[0147] The opening in the inorganic material layer IL may refer to the formation of an opening in each of the barrier layer 101, buffer layer 111, first gate insulating layer 112, second gate insulating layer 113 and interlayer insulating layer 115, so that the substrate 100 is exposed.

[0148] In other embodiments, the inorganic material layer IL may include various types of grooves. For example, a portion of the upper surface of the barrier layer 101 may be removed, or the lower surface of the buffer layer 111 may be retained without being removed.

[0149] The width GRW of the groove GR in the inorganic material layer IL can be several μm. For example, the width GRW of the groove GR in the inorganic material layer IL can be in the range of about 5 μm to about 10 μm.

[0150] The openings or trenches GR can be formed by performing separate masking and etching processes on the interlayer insulating layer 115. The openings 111a, 112a, 113a, and 115a of the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 can be formed by etching processes. The etching process can be a dry etching process.

[0151] The opening or groove GR of the inorganic material layer IL can be filled with the organic material layer 161. The connecting line 140 is located above the organic material layer 161 at the location where the organic material layer 161 is present. The opening or groove GR of the inorganic material layer IL and the organic material layer 161 can be at least partially disposed between adjacent pixel circuits.

[0152] The openings or grooves GR in the inorganic material layer IL and the organic material layer 161 can significantly reduce the impact of external impacts on the display device. The inorganic material layer IL has openings or grooves GR in the area between pixel circuits, and the organic material layer 161 fills the openings or grooves GR. Thus, even in the event of an external impact, the possibility of crack propagation becomes extremely low. In addition, since the organic material layer 161 has a lower hardness than the inorganic material layer IL, it absorbs the stress caused by external impacts. Therefore, stress concentration on the connection lines 140 located on the organic material layer 161 can be significantly reduced in an effective manner.

[0153] The organic material layer 161 fills at least a portion of the groove GR located between the first pixel circuit PC1 and the second pixel circuit PC2 in the inorganic material layer IL. In some embodiments, the organic material layer 161 may not completely fill the groove GR, or may not fill a portion of the groove GR.

[0154] However, in order for the organic material layer 161 to absorb external impacts, the organic material layer 161 can completely fill the groove GR. In some embodiments, the organic material layer 161 can extend to the upper surface of the inorganic material layer IL. In this case, due to the properties of the organic material layer 161, the upper surface of the organic material layer 161 can have a raised shape. More specifically, the maximum height h of the organic material layer 161 can be greater than the depth d of the groove GR.

[0155] The angle between the upper surface of the organic material layer 161 and the upper surface of the inorganic material layer 11 can be within 45°. When the slope of the boundary region where the upper surface of the inorganic material layer 11 intersects with the upper surface of the organic material layer 161 is not gentle, conductive material may remain in the corresponding region and not be removed from the boundary region during the process of forming the connecting line 140 by patterning the conductive layer. In this case, the remaining conductive material may cause a short circuit between other conductive layers. Therefore, the upper surface of the organic material layer 161 can be formed with a gentle slope relative to the upper surface of the inorganic material layer 11.

[0156] The organic material layer 161 may include one or more materials selected from acryloyl materials, methacrylate materials, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane.

[0157] The connecting line 140 can be disposed on the organic material layer 161 and configured to connect the first pixel circuit PC1 and the second pixel circuit PC2 to each other. The connecting line 140 can also be located on the inorganic material layer 11 in areas where the organic material layer 161 is not present. The connecting line 140 can be used as wiring to transmit electrical signals to the first pixel circuit PC1 and the second pixel circuit PC2.

[0158] Because the connecting line 140 comprises a material with high elongation, defects such as cracking or breakage in the connecting line 140 can be prevented. In some embodiments, the connecting line 140 may have a Ti / Al / Ti stacked structure. In some embodiments, the elongation of the connecting line 140 may be greater than the elongation of the conductive layer disposed thereunder.

[0159] Figure 8 This is a schematic cross-sectional view of a portion of a display device according to an embodiment. Figure 8 In, with Figure 3 and Figure 7 Elements that are substantially the same will be given the same reference numerals.

[0160] The display device according to the illustrated embodiment includes a first pixel circuit PC1 and a second pixel circuit PC2 disposed in a display area DA of a substrate 100, a first organic light-emitting diode (OLED1) and a second organic light-emitting diode (OLED2) respectively connected to the first pixel circuit PC1 and the second pixel circuit PC2, and a composite layer 200 located between the first pixel circuit PC1 and the second pixel circuit PC2 and the first organic light-emitting diode (OLED1) and the second organic light-emitting diode (OLED2). The composite layer 200 includes a first inorganic insulating layer 210, a first organic insulating layer 220 and a second inorganic insulating layer 230 stacked in sequence.

[0161] The display device according to the illustrated embodiment further includes an inorganic material layer IL' having an opening or groove GR' in the region between the first pixel circuit PC1 and the second pixel circuit PC2, and an organic interlayer insulating layer 115' disposed on the front surface of the substrate 100 to fill the opening or groove GR'.

[0162] In this embodiment, the barrier layer 101, buffer layer 111, first gate insulating layer 112, and second gate insulating layer 113, which include inorganic materials, can be collectively referred to as the inorganic material layer IL'. The inorganic material layer IL' has an opening or a groove GR' in the region between adjacent pixel circuits.

[0163] Figure 8 The inorganic material layer IL' is shown to have a groove GR'. More specifically, the barrier layer 101 may be continuous across the first pixel circuit PC1 and the second pixel circuit PC2 of adjacent pixels. The buffer layer 111, the first gate insulating layer 112, and the second gate insulating layer 113 may have openings 111a, 112a, and 113a, respectively, in the region between adjacent pixels.

[0164] The opening in the inorganic material layer IL' may refer to an opening formed in each of the barrier layer 101, the buffer layer 111, the first gate insulating layer 112, and the second gate insulating layer 113, such that the upper surface of the substrate 100 is exposed. The inorganic material layer IL' may include various types of trenches. For example, a portion of the upper surface of the barrier layer 101 may be removed, or the lower surface of the buffer layer 111 may be retained without being removed.

[0165] The organic interlayer insulating layer 115' can cover the storage capacitors Cst1 and Cst2 over the second gate insulating layer 113. In addition, the organic interlayer insulating layer 115' can fill the opening or trench GR' to prevent crack propagation.

[0166] The organic interlayer insulation layer 115' may include a general polymer (e.g., benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers or vinyl alcohol polymers).

[0167] In the illustrated embodiment, the connecting line 140 may be disposed on the organic interlayer insulating layer 115' and connect the first pixel circuit PC1 and the second pixel circuit PC2 to each other. The connecting line 140 may also have a flat upper surface when the organic interlayer insulating layer 115' provides a flat upper surface. The connecting line 140 may be used as wiring to transmit electrical signals to the first pixel circuit PC1 and the second pixel circuit PC2.

[0168] Figure 9 and Figure 10 This illustrates an embodiment. Figure 7 or Figure 8 A plan view of the opening or slot GR or GR'.

[0169] The openings or grooves GR or GR' of the inorganic material layer can be arranged to at least partially surround the periphery of the pixel circuit. (See reference...) Figure 9 The openings or grooves GR or GR' of the inorganic material layer can be arranged around the periphery of the first pixel circuit PC1 and the periphery of the second pixel circuit PC2. Optionally, refer to Figure 10 The openings or grooves GR or GR' of the inorganic material layer can be arranged to surround multiple pixel circuits. For example, as Figure 10 As shown, the openings or slots GR or GR' of the inorganic material layer are arranged around two pixel circuits, namely, the first pixel circuit PC1 and the second pixel circuit PC2. In other embodiments, the number of pixels grouped by the openings or slots GR or GR' can be varied.

[0170] In a display device, the number of pixel circuits grouped by openings or slots GR or GR' can be the same or can vary depending on their location. For example, openings or slots GR or GR' in the inorganic material layer can be arranged to surround a pixel circuit in an area with a high risk of cracking or stress, and can be arranged to surround multiple pixel circuits in other areas. Optionally, the openings or slots GR or GR' in the inorganic material layer can be partially formed in the display area DA.

[0171] Figure 11 and Figure 12 This is a schematic diagram of a display device according to an embodiment. Figure 11 This shows that the display area DA is folded. Figure 12The display area DA is shown to be curled.

[0172] The display device according to one or more embodiments is robust against external impacts, therefore, as Figure 11 and Figure 12 As shown, the display area DA can be foldable or rollable.

[0173] More specifically, because the composite layer 200, configured to distribute and absorb external shocks, is located between the pixel circuitry and the display element, external shocks can be prevented or at least suppressed from being transmitted to the pixel circuitry even when the display area DA is folded or rolled up. Furthermore, when an opening or groove GR or GR' is provided in the inorganic material layer, the organic material layer 161 or the organic interlayer insulating layer 115' filling the opening or groove GR or GR' can absorb tensile stress caused by bending.

[0174] Figure 13 The results of testing the impact resistance of a display device according to an embodiment are shown. Figure 13 The data shown is obtained by measuring the leakage current between the semiconductor layer and the gate electrode when a pen is dropped from a predetermined height onto the display area DA.

[0175] Figure 13 (a) shows test data for a display device that is a comparative example excluding the grooves in the composite layer and the inorganic material layer. Figure 13 (b) shows a target including Figure 3 Test data for composite layer display devices Figure 13 (c) illustrates a groove (e.g.) in a composite layer and an inorganic material layer. Figure 7 Test data for the display device shown in the figure.

[0176] In such Figure 13 In the comparative example shown in (a), a leakage current of 10 pA or greater occurs when the pen is dropped from a height of 3 cm or higher, but in Figure 13 In case (b), even when the pen is dropped from a height of 5 cm, no leakage current of 10 pA or greater occurs. Furthermore, Figure 13 In case (c), it can be confirmed that even when the pen is dropped from a height of 8 cm, no leakage current of 10 pA or greater will occur. Thus, it can be confirmed that the display device according to the embodiment is robust against external impacts.

[0177] As described above, because the composite layer in which the first inorganic insulating layer, the first organic insulating layer and the second inorganic insulating layer are stacked is located between the pixel circuit and the display element, the display device according to one or more embodiments can be robust against external shocks.

[0178] Furthermore, because the display device according to one or more embodiments includes an inorganic material layer having openings or grooves in the area between pixels and an organic material layer filling the openings or grooves, the display device according to one or more embodiments can be flexible and robust against external impacts.

[0179] Although one or more specific embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but is limited to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to those skilled in the art.

Claims

1. A display device, the display device comprising: The substrate has a display area; A plurality of pixel circuits are arranged in the display area, each of the plurality of pixel circuits including a thin-film transistor; A planarization layer, covering the thin-film transistor and comprising an organic material; The connecting electrode is configured to be in direct contact with the planarization layer and connected to the thin-film transistor; Multiple display elements are respectively connected to the multiple pixel circuits; A composite layer is disposed between the planarization layer and the plurality of display elements, the composite layer comprising a first inorganic insulating layer, a first organic insulating layer and a second inorganic insulating layer stacked sequentially; An inorganic material layer is disposed in the display area and includes openings or slots in the area between the plurality of pixel circuits; An organic interlayer insulating layer is disposed throughout the entire display area and fills the opening or the slot; as well as Connecting lines are arranged on the flat upper surface of the organic interlayer insulating layer and connect adjacent pixel circuits among the plurality of pixel circuits. The first inorganic insulating layer covers the connecting electrode and the connecting wire and is disposed on the planarization layer.

2. The display device according to claim 1, wherein: The thickness of each of the first and second inorganic insulating layers is in the range of 1,000 Å to 3,000 Å; and The thickness of the first organic insulating layer is in the range of 10,000 Å to 20,000 Å.

3. The display device according to claim 1, wherein, The strength of each of the first and second inorganic insulating layers is in the range of 80 GPa to 200 GPa; and The strength of the first organic insulating layer is in the range of 1 GPa to 10 GPa.

4. The display device according to claim 1, wherein, The composite layer further includes a lower organic insulating layer disposed between the plurality of pixel circuits and the first inorganic insulating layer.

5. The display device according to claim 1, wherein, The composite layer also includes an upper organic insulating layer disposed between the second inorganic insulating layer and the plurality of display elements.

6. The display device according to claim 1, wherein, The composite layer also includes a second organic insulating layer and a third inorganic insulating layer stacked in sequence.

7. The display device according to claim 1, wherein, The opening or the slot surrounds each of the plurality of pixel circuits.

8. The display device according to claim 1, wherein, The opening or the slot surrounds at least a portion of the plurality of pixel circuits.

9. A display device, the display device comprising: The substrate includes a display area and a peripheral area located outside the display area; A circuit layer is disposed in the display area of ​​the substrate, the circuit layer including a first pixel circuit and a second pixel circuit; A planarization layer is disposed on the circuit layer and comprises an organic material; The connecting electrode is configured to be in direct contact with the planarization layer and connected to the first pixel circuit; A display element layer is disposed on the circuit layer, the display element layer including a first display element connected to the first pixel circuit and a second display element connected to the second pixel circuit; as well as A composite layer is disposed between the planarization layer and the display element layer, the composite layer comprising a first inorganic insulating layer, a first organic insulating layer, and a second inorganic insulating layer. The circuit layer further includes an inorganic material layer having an opening or groove in the region between the first pixel circuit and the second pixel circuit; an organic interlayer insulating layer disposed throughout the entire display area and filling the opening or groove; and a connecting line disposed on the flat upper surface of the organic interlayer insulating layer and connecting the first pixel circuit and the second pixel circuit. The first inorganic insulating layer covers the connecting electrode and the connecting wire and is disposed on the planarization layer.

10. The display device according to claim 9, wherein, The first organic insulating layer is disposed between the first inorganic insulating layer and the second inorganic insulating layer.

11. The display device according to claim 9, wherein, The connecting line overlaps with the opening or the slot.

12. The display device according to claim 9, wherein, In the plan view, the opening or the slot surrounds each of the first pixel circuit and the second pixel circuit.

13. The display device according to claim 9, wherein, The opening or the slot at least surrounds the first pixel circuit and the second pixel circuit together.

14. The display device according to claim 9, wherein, The composite layer also includes an additional organic insulating layer.

15. The display device according to claim 9, wherein: The thickness of each of the first and second inorganic insulating layers is in the range of 1,000 Å to 3,000 Å; and The thickness of the first organic insulating layer is in the range of 10,000 Å to 20,000 Å.

16. The display device according to claim 9, wherein: The strength of each of the first and second inorganic insulating layers is in the range of 80 GPa to 200 GPa; and The strength of the first organic insulating layer is in the range of 1 GPa to 10 GPa.

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