Memory, programming method and programming verification method of memory, and memory system

Abstract

Embodiments of the present disclosure disclose a memory, a programming method and a programming verification method for the memory, and a memory system. The programming verification method includes: obtaining an i-th verification result of an i-th programming verification operation; wherein, the programming state range verified by the i-th programming verification operation is from an n-th state to an (n + k)-th state, i and n are positive integers, k is a natural number, and the (n + k)-th state is less than or equal to the highest programming state of the memory; determining a programming state range to be verified by an (i + 1)-th programming verification operation according to the verification sub-result of the n-th state and the verification sub-result of the (n + k)-th state in the i-th verification result; and performing the (i + 1)-th programming verification operation according to the determined programming state range to be verified by the (i + 1)-th programming verification operation.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to, but are not limited to, the semiconductor field, and in particular, to a memory, a programming method and a programming verification method for a memory, and a memory system. Background Art

[0002] Flash memories are widely used as storage media for portable electronic devices such as mobile phones and digital cameras. Flash memories typically use single-transistor memory cells that allow for high memory density, high reliability, and low power consumption. By programming a charge storage structure (e.g., a floating gate or a charge trap) or other physical phenomena (e.g., phase change or ferroelectricity), a change in the threshold voltage of a memory cell determines the data state (e.g., data value) of each memory cell.

[0003] In the related art, after applying a programming pulse to a memory for programming, a programming verification operation needs to be performed. The number of times of applying the programming pulse and the number of times of performing the programming verification operation are important factors determining the programming time. Therefore, how to shorten the programming time while ensuring the programming quality has become an urgent problem to be solved. Summary of the Invention

[0004] Embodiments of the present disclosure provide a memory, a programming method and a programming verification method for a memory, and a memory system.

[0005] According to a first aspect of the embodiments of the present disclosure, a programming verification method for a memory is provided, including:

[0006] Obtaining an i-th verification result of an i-th programming verification operation; wherein, the programming state range verified by the i-th programming verification operation is from an n-th state to an (n + k)-th state, i and n are positive integers, k is a natural number, and the (n + k)-th state is less than or equal to the highest programming state of the memory;

[0007] Determining a programming state range to be verified by an (i + 1)-th programming verification operation according to the verification sub-result of the n-th state and the verification sub-result of the (n + k)-th state in the i-th verification result;

[0008] Performing the (i + 1)-th programming verification operation according to the determined programming state range to be verified by the (i + 1)-th programming verification operation.

[0009] In some embodiments, the determining a programming state range to be verified by an (i + 1)-th programming verification operation according to the verification sub-result of the n-th state and the verification sub-result of the (n + k)-th state in the i-th verification result includes:

[0010] Determining the lowest programming state to be verified by the (i + 1)-th programming verification operation according to the verification sub-result of the n-th state in the i-th verification result;

[0011] Determine the highest programming state to be verified in the (i + 1)-th programming verification operation according to the verification sub-result of the (n + k)-th state in the i-th verification result.

[0012] In some embodiments, the verification sub-result of the n-th state in the i-th verification result includes: the i-th statistical data of the n-th state, which is used to count the number of failed bits in programming the n-th state.

[0013] The determining of the lowest programming state to be verified in the (i + 1)-th programming verification operation according to the verification sub-result of the n-th state in the i-th verification result includes:

[0014] Determine the number of failed bits in programming the n-th state according to the i-th statistical data of the n-th state.

[0015] When the number of failed bits in programming the n-th state is less than a first preset value, determine that the lowest programming state to be verified in the (i + 1)-th programming verification operation is the (n + 1)-th state; when the number of failed bits in programming the n-th state is greater than or equal to the first preset value, determine that the lowest programming state to be verified in the (i + 1)-th programming verification operation is the n-th state.

[0016] Or,

[0017] When the ratio of the number of failed bits in programming the n-th state to the number of bits with the target state being the n-th state is less than a first preset ratio, determine that the lowest programming state to be verified in the (i + 1)-th programming verification operation is the (n + 1)-th state; when the ratio of the number of failed bits in programming the n-th state to the number of bits with the target state being the n-th state is greater than or equal to the first preset ratio, determine that the lowest programming state to be verified in the (i + 1)-th programming verification operation is the n-th state.

[0018] In some embodiments, the programming verification method further includes:

[0019] Obtain the number of cycles of the storage unit to be programmed.

[0020] Determine the value range of the first preset value or the value range of the first preset ratio according to the number of cycles.

[0021] In some embodiments, the value range of the first preset value is within the range allowed by the error correction code error correction mechanism performed on the memory.

[0022] In some embodiments, the verification sub-result of the (n + k)-th state in the i-th verification result includes: the i-th statistical data of the (n + k)-th state, which is used to count the number of successful bits in programming the (n + k)-th state.

[0023] Determining the highest programming state to be verified in the (i + 1)-th programming verification operation according to the verification sub-result of the (n + k)-th state in the i-th verification result includes:

[0024] Determining the number of successfully programmed bits for programming the (n + k)-th state according to the i-th statistical data of the (n + k)-th state;

[0025] When the number of successfully programmed bits for programming the (n + k)-th state is greater than a second preset value and the (n + k)-th state is less than the highest programming state of the memory, determining that the highest programming state to be verified in the (i + 1)-th programming verification operation is the (n + k + 1)-th state; when the number of successfully programmed bits for programming the (n + k)-th state is less than or equal to the second preset value, determining that the highest programming state to be verified in the (i + 1)-th programming verification operation is the (n + k)-th state;

[0026] Or,

[0027] When the ratio of the number of successfully programmed bits for programming the (n + k)-th state to the number of bits with the target state being the (n + k)-th state is greater than a second preset ratio, determining that the highest programming state to be verified in the (i + 1)-th programming verification operation is the (n + k + 1)-th state; when the ratio of the number of successfully programmed bits for programming the (n + k)-th state to the number of bits with the target state being the (n + k)-th state is less than or equal to the second preset ratio, determining that the highest programming state to be verified in the (i + 1)-th programming verification operation is the (n + k)-th state.

[0028] In some embodiments, the programming verification method further includes:

[0029] Obtaining the step size of the incremental step pulse programming and / or the programming voltage slope; determining the value range of the second preset value or the second preset ratio according to the step size and / or the programming voltage slope; wherein, the programming verification method is applied to the incremental step pulse programming method;

[0030] Or,

[0031] Obtaining the number of cycles of the memory cell to be programmed; determining the value range of the second preset value or the value range of the second preset ratio according to the number of cycles.

[0032] In some embodiments, the value range of the second preset ratio is 2% to 3%.

[0033] In some embodiments, determining the range of programming states to be verified in the (i + 1)-th programming verification operation according to the verification sub-result of the n-th state and the verification sub-result of the (n + k)-th state in the i-th verification result includes:

[0034] Sampling the verification sub-results of the n-th state and the verification sub-results of the (n + k)-th state in the i-th verification result respectively to obtain the i-th sampling statistical data of the n-th state and the i-th sampling statistical data of the (n + k)-th state;

[0035] Determine the lowest programming state to be verified in the (i + 1)-th programming verification operation according to the i-th sampling statistical data of the n-th state;

[0036] Determine the highest programming state to be verified in the (i + 1)-th programming verification operation according to the i-th sampling statistical data of the (n + k)-th state.

[0037] According to a second aspect of the embodiments of the present disclosure, there is provided a programming method for a memory, including:

[0038] Apply the (i + 1)-th programming pulse to the memory storage unit to be programmed;

[0039] During the application of the (i + 1)-th programming pulse, according to the verification sub-results of the n-th state and the verification sub-results of the (n + k)-th state in the i-th verification result of the i-th programming verification operation, count the number of failed bits in the programming of the n-th state in the i-th programming operation and count the number of successful bits in the programming of the (n + k)-th state to obtain the i-th counting result; wherein, the programming state range verified by the i-th programming verification operation is from the n-th state to the (n + k)-th state, i and n are positive integers, k is a natural number, and the (n + k)-th state is less than or equal to the highest programming state of the memory;

[0040] Determine the programming state range to be verified in the (i + 1)-th programming verification operation according to the i-th counting result; wherein, the programming state range verified by the i-th programming verification operation is from the n-th state to the (n + k)-th state, i and n are positive integers, k is a natural number, and the (n + k)-th state is less than or equal to the highest programming state of the memory;

[0041] Execute the (i + 1)-th programming verification operation according to the determined programming state range to be verified in the (i + 1)-th programming verification operation.

[0042] In some embodiments, the i-th counting result includes: the number of failed bits in programming the n-th state in the i-th programming operation;

[0043] The determining the programming state range to be verified in the (i + 1)-th programming verification operation according to the i-th counting result includes:

[0044] When the number of failed bits in programming the n-th state is less than a first preset value, determine that the lowest programming state to be verified in the (i + 1)-th programming verification operation is the (n + 1)-th state; when the number of failed bits in programming the n-th state is greater than or equal to the first preset value, determine that the lowest programming state to be verified in the (i + 1)-th programming verification operation is the n-th state;

[0045] Or,

[0046] When the ratio of the number of failed bits programmed for the n-th state to the number of bits with the target state being the n-th state is less than the first preset ratio, determine that the lowest programming state to be verified for the (i + 1)-th programming verification operation is the (n + 1)-th state; when the ratio of the number of failed bits programmed for the n-th state to the number of bits with the target state being the n-th state is greater than or equal to the first preset ratio, determine that the lowest programming state to be verified for the (i + 1)-th programming verification operation is the n-th state.

[0047] In some embodiments, the i-th counting result includes: the number of successfully programmed bits for the (n + k)-th state in the i-th programming operation;

[0048] Determining the range of programming states to be verified for the (i + 1)-th programming verification operation according to the i-th counting result includes:

[0049] When the number of successfully programmed bits for the (n + k)-th state is greater than a second preset value and the (n + k)-th state is less than the highest programming state of the memory, determine that the highest programming state to be verified for the (i + 1)-th programming verification operation is the (n + k + 1)-th state; when the number of successfully programmed bits for the (n + k)-th state is less than or equal to the second preset value, determine that the highest programming state to be verified for the (i + 1)-th programming verification operation is the (n + k)-th state;

[0050] Or,

[0051] When the ratio of the number of successfully programmed bits for the (n + k)-th state to the number of bits with the target state being the (n + k)-th state is greater than a second preset ratio, determine that the highest programming state to be verified for the (i + 1)-th programming verification operation is the (n + k + 1)-th state; when the ratio of the number of successfully programmed bits for the (n + k)-th state to the number of bits with the target state being the (n + k)-th state is less than or equal to the second preset ratio, determine that the highest programming state to be verified for the (i + 1)-th programming verification operation is the (n + k)-th state.

[0052] In some embodiments, counting the number of failed bits for programming the n-th state and the number of successfully programmed bits for programming the (n + k)-th state in the i-th programming operation according to the verification sub-results of the n-th state and the (n + k)-th state in the i-th verification result of the i-th programming verification operation to obtain the i-th counting result includes:

[0053] Sampling the verification sub-results of the n-th state and the (n + k)-th state in the i-th verification result respectively to obtain the i-th sampling sample data of the n-th state and the i-th sampling sample data of the (n + k)-th state;

[0054] Based on the i-th sampling sample data in the n-th state and the i-th sampling sample data in the n + k-th state, count the number of failed bits in the programming of the n-th state and the number of successful bits in the programming of the n + k-th state in the i-th programming operation, and obtain the i-th counting result.

[0055] According to a third aspect of the embodiments of the present disclosure, there is provided a memory, including:

[0056] A memory cell array, the memory cell array including a plurality of memory cell rows;

[0057] A plurality of word lines, the plurality of word lines being respectively coupled to the plurality of memory cell rows; and

[0058] A peripheral circuit, the peripheral circuit being coupled to the plurality of word lines and configured to perform a programming verification operation on a selected memory cell row among the plurality of memory cell rows, the selected memory cell row being coupled to a selected word line, wherein, in order to perform the programming verification operation, the peripheral circuit is configured to:

[0059] Obtain an i-th verification result of the i-th programming verification operation; wherein the programming state range verified by the i-th programming verification operation is from the n-th state to the n + k-th state, i and n are positive integers, k is a natural number, and the n + k-th state is less than or equal to the highest programming state of the memory;

[0060] Determine the programming state range to be verified by the (i + 1)-th programming verification operation according to the verification sub-result of the n-th state and the verification sub-result of the n + k-th state in the i-th verification result;

[0061] Execute the (i + 1)-th programming verification operation according to the determined programming state range to be verified by the (i + 1)-th programming verification operation.

[0062] According to a fourth aspect of the embodiments of the present disclosure, there is provided a memory, including:

[0063] A memory cell array, the memory cell array including a plurality of memory cell rows;

[0064] A plurality of word lines, the plurality of word lines being respectively coupled to the plurality of memory cell rows; and

[0065] A peripheral circuit, the peripheral circuit being coupled to the plurality of word lines and configured to perform a programming operation on a selected memory cell row among the plurality of memory cell rows, the selected memory cell row being coupled to a selected word line, wherein, in order to perform the programming operation, the peripheral circuit is configured to:

[0066] Apply an (i + 1)-th programming pulse to the memory storage unit to be programmed;

[0067] During the application of the (i + 1)-th programming pulse, according to the verification sub-results of the n-th state and the (n + k)-th state in the i-th verification result of the i-th programming verification operation, the number of failed bits in the programming of the n-th state in the i-th programming operation and the number of successful bits in the programming of the (n + k)-th state are counted to obtain the i-th counting result; wherein, the programming state range verified by the i-th programming verification operation is from the n-th state to the (n + k)-th state, i and n are positive integers, k is a natural number, and the (n + k)-th state is less than or equal to the highest programming state of the memory;

[0068] According to the i-th counting result, determine the programming state range to be verified by the (i + 1)-th programming verification operation;

[0069] Execute the (i + 1)-th programming verification operation according to the determined programming state range to be verified by the (i + 1)-th programming verification operation.

[0070] According to a fifth aspect of the embodiments of the present disclosure, there is provided a memory system, including:

[0071] One or more memories as described in the third aspect or the fourth aspect of the embodiments of the present disclosure;

[0072] A memory controller coupled to the memory and configured to control the memory.

[0073] In the related art, usually according to empirical values, a fixed starting moment (start loop) is determined for each programming state to be verified. For example, after applying the 3rd programming pulse (i.e., applying the 3rd programming pulse), start performing programming verification (PV2) on the 2nd state. Then, the verification starting loop of the 2nd state is 3. In this way, the programming state range to be verified in each programming verification operation is fixed. However, when the programming speed changes, this fixed starting moment determined according to empirical values may not be the most suitable verification starting moment. Specifically, when the set verification starting moment is earlier than the most suitable verification starting moment, starting this programming verification too early will extend the time of the programming verification operation, and thus extend the programming duration. When the set verification starting moment is later than the most suitable verification starting moment, an over-program phenomenon may occur, thereby reducing the programming quality.

[0074] Compared with the fixed programming state range to be verified for each programming verification operation, in the embodiments of the present disclosure, according to the verification result of the i-th programming verification operation, the programming state range to be verified for the (i + 1)-th programming verification operation to be performed after applying the next programming pulse is determined. That is, the programming state range to be verified for the next programming verification operation is determined according to the result of the previous programming verification operation, and the starting moment of each programming state to be verified can be dynamically determined. This method is not only simple but also can improve the accuracy of the starting moment of each programming state to be verified. On the one hand, it can reduce the increase in programming duration caused by setting the programming verification starting moment too early, which is beneficial to shortening the programming duration. On the other hand, it can reduce over-programming caused by setting the programming verification starting moment too late, which is beneficial to ensuring better programming quality.

[0075] In addition, compared with the need to manually set different fixed starting moments separately when programming the same programming state in different units (such as blocks or word lines), the embodiments of the present disclosure do not require manual setting of fixed starting moments, and can track the differences in the programming performance of the memory through the verification results, and then automatically determine the programming state range to be verified for each programming verification operation. The method is simple and can timely adjust the programming state range to be verified for the programming verification operation according to the memory performance, which is beneficial to improving the programming quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] Figure 1 is a threshold voltage distribution diagram of a programming operation shown according to an exemplary embodiment;

[0077] Figure 2 is a flowchart of a programming verification method shown according to an exemplary embodiment;

[0078] Figure 3 is a flowchart of a programming method shown according to an exemplary embodiment;

[0079] Figure 4 is a partial flowchart of a programming method shown according to an exemplary embodiment;

[0080] Figure 5 is a schematic diagram of a memory shown according to an exemplary embodiment;

[0081] Figure 6 is a partial cross-sectional view of a memory cell array including NAND memory strings shown according to an exemplary embodiment;

[0082] Figure 7 is a block diagram of a memory including a memory cell array and a peripheral circuit shown according to an exemplary embodiment;

[0083] Figure 8Schematic diagram of another memory shown according to an exemplary embodiment;

[0084] Figure 9a Block diagram of a memory system shown according to an exemplary embodiment;

[0085] Figure 9b Block diagram of another memory system shown according to an exemplary embodiment;

[0086] Figure 10a Schematic diagram of a memory card shown according to an exemplary embodiment;

[0087] Figure 10b Schematic diagram of a solid state drive (SSD) shown according to an exemplary embodiment. Detailed implementation

[0088] To make the objectives, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure will be further elaborated in detail below in conjunction with the accompanying drawings and embodiments. Although exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation manners set forth herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present disclosure and to be able to fully convey the scope of the present disclosure to those skilled in the art.

[0089] In the following paragraphs, the present disclosure will be described more specifically by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will be clearer according to the following description and claims. It should be noted that the drawings are all in very simplified forms and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present disclosure.

[0090] It can be understood that the meanings of "on...", "above..." and "overhead..." in the present disclosure should be interpreted in the broadest manner, so that "on..." not only means "on" something with no intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of being "on" something with intervening features or layers therebetween.

[0091] In the embodiments of the present disclosure, the term "A is connected to B" includes the situation where A and B are connected to each other in contact, or the situation where there are other components interposed between A and B and A is connected to B non-contactly.

[0092] In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It can be understood that "first", "second", etc. can be interchanged with a specific order or sequence when permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0093] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer can extend over the entirety of a structure below or above, or can have a scope that is less than the scope of the structure below or above. In addition, the layer can be a region of a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of a continuous structure, or the layer can be between any horizontal planes at the top and bottom surfaces of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include a plurality of sub-layers. For example, an interconnect layer can include one or more conductor and contact sub-layers (wherein interconnect lines and / or via contacts are formed), and one or more dielectric sub-layers.

[0094] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this disclosure belongs. The terms used herein are for the purpose of describing the embodiments of the present disclosure only and are not intended to limit the present disclosure.

[0095] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0096] A NAND memory belongs to a non-volatile memory device. It adopts a non-linear macro cell mode internally and has advantages such as large capacity and fast rewrite speed, and is suitable for storing a large amount of data. NAND memories are widely used in embedded products, such as digital cameras, memory cards for MP3 players, and small-sized USB flash drives.

[0097] In the development of NAND memories, the storage units of early NAND memory chips were mostly single-level cells (SLCs), that is, one storage unit stores 1 bit of data. At this time, each storage unit has two states, specifically 0 and 1.

[0098] With the development of NAND memories, the storage cells of NAND memory chips have gradually evolved from single-level cells to multi-level cells (MLCs), i.e., one storage cell stores 2 bits of data. Subsequently, triple-level cells (TLCs) were introduced, i.e., one storage cell stores 3 bits of data, and even quad-level cells (QLCs), i.e., one storage cell stores 4 bits of data. Correspondingly, the number of states of the storage cells in NAND memory chips has changed from 2 to 4, 8, or even 16.

[0099] The operations of a NAND memory include three parts: an erase operation, a program (write) operation, and a read operation. The erase operation can be performed in units of blocks, and the program and read operations can be performed in units of pages. For the program operation of a NAND memory, the process is, for example, divided into three steps: applying a voltage program (i.e., applying a program pulse), program verify (PV), and scanning the verification result.

[0100] For a NAND memory, the program duration (t PROG ) is an important indicator for measuring the performance of the NAND memory. Therefore, researchers have been committed to studying how to improve the program speed and shorten the program duration while ensuring the program quality (e.g., ensuring the read budget window). Since the duration of the applied program pulse cannot be changed, the number of applied program pulses, the number of program verification operations, the time for each program verification operation, and the time for scanning the verification result are all important factors determining the program duration.

[0101] Taking a TLC storage cell as an example, a TLC storage cell has 1 erase state and 7 program states, and its program states are sequentially denoted as L1, L2, L3, L4, L5, L6, and L7 from the first state to the seventh state. The traditional programming method for a TLC is to start the program verification operation for each state between two adjacent applications of program pulses. The problem with this method is that after applying the first program pulse, in fact, only a very small number of storage cells reach the L1 state, and no storage cells reach the L2, L3, L4, L5, L6, and L7 states. If the program verification operation for at least any one of the states L2 to L7 is started at this time, it will increase the number of program verification operations and the time for the program verification operation, and may even cause the time for the program verification operation and scanning the verification result to occupy at least more than half of the entire programming process, seriously reducing the program speed.

[0102] To improve the program speed, Table 1 shows the start time corresponding to each program verification state in the improved related program verification method.

[0103] Program Verification (PV) Start Time (start loop) PV1 1 PV2 3 PV3 4 PV4 5 PV5 7 PV6 9 PV7 11

[0104] Table 1 Programming verification operations and start time table for different programming states

[0105] Among them, PV1 represents the programming verification operation for the first state (L1), PV2 represents the programming verification operation for the second state (L2), PV3 represents the programming verification operation for the third state (L3), PV4 represents the programming verification operation for the fourth state (L4), PV5 represents the programming verification operation for the fifth state (L5), PV6 represents the programming verification operation for the sixth state (L6), and PV7 represents the programming verification operation for the seventh state (L7).

[0106] The start time of the programming verification operation can be defined by which programming pulse the programming verification operation starts after. For example, the start time of the programming verification operation for the first state is 1, which means that after applying the first programming pulse and before applying the second programming pulse, the programming verification for the first state starts.

[0107] When performing a programming operation, all storage units to be programmed start programming from the erased state. Usually, after applying several programming pulses, the threshold voltage of the storage unit to be programmed can reach a higher programming state. Therefore, in the related art, the programming speed can be increased by reducing the number of programming verifications.

[0108] Specifically, in the related art, in the improved programming method, after the programming pulses applied in the early stage, the programming verification operation for a higher programming state can be omitted. Referring to Table 1, this programming verification method uses a fixed start time to control when to start the programming verification for each programming state. For example, the start time of the programming verification operation for the third state is set to 4, that is, after applying the first 3 programming pulses, the third state is not verified, but after applying the fourth programming pulse, the programming verification operation for the third state (i.e., PV3) starts.

[0109] Compared with performing programming verification for each state after each application of a programming pulse, although the improved method described above reduces the number of programming verifications to a certain extent, considering that there are differences in programming characteristics when the units being programmed simultaneously are different, for each state, setting the same starting time for all dies, blocks, or word lines (WL) will still result in errors. Therefore, to ensure programming quality, when setting the starting time of the programming verification operation for each programming state, sufficient margin needs to be reserved, and when the units being programmed are different, corresponding fixed starting times for programming verification operations need to be set separately for each unit according to empirical values. This method will consume a large amount of circuit resources and increase the test time.

[0110] In addition, the programming characteristics of NAND are also affected by many other factors. For example, as conditions such as the number of cycles (cycling) or temperature change, the performance of each memory cell will change, resulting in different programming performances of NAND. By setting a fixed starting time for each programming verification operation, these changes in programming characteristics cannot be traced. Therefore, the fixed starting time is not the most suitable starting time. When the fixed starting time set for the programming verification operation is earlier than the most suitable starting time, starting this programming verification too early will extend the time of the verification operation, and thus extend the programming duration. When the fixed starting time set for the programming verification operation is later than the most suitable starting time, over-programming may occur, thereby reducing the programming quality.

[0111] Taking TLC as an example, Figure 1 FIG. shows a threshold voltage distribution diagram of a memory performing a programming operation according to an exemplary embodiment. It should be noted that TLC has 7 programming states, Figure 1 and only shows the programming of 5 programming states (i.e., L1 to L5) as an example.

[0112] Referring to Figure 1 as shown, Figure 1 FIG. shows 8 sub-curves, namely FIGS. (a), (b), (c), (d), (e), (f), (g), and (h) in sequence. Each sub-curve includes 5 curves, and each curve represents the distribution of memory cells with the same target programming state after applying a programming pulse. Among them, V th1 、V th2 、V th3 、V th4 、V th5 、V th6 and V th7respectively represent: the starting threshold voltage of the first state, the starting threshold voltage of the second state, the starting threshold voltage of the third state, the starting threshold voltage of the fourth state, the starting threshold voltage of the fifth state, the starting threshold voltage of the sixth state, and the starting threshold voltage of the seventh state. Specifically:

[0113] Figure (a) shows the threshold voltage distribution curve obtained by performing the first programming verification operation on the storage cell after applying the first programming pulse starting from the erased state. The first programming verification operation includes the programming verification (PV1) for the first state, that is, the programming state range verified by the first programming verification operation is L1.

[0114] Figure (b) shows the threshold voltage distribution curve obtained by performing the second programming verification operation on the storage cell after applying the next programming pulse based on Figure (a), that is, Figure (b) shows the threshold voltage distribution curve obtained by performing the second programming verification operation on the storage cell after applying the second programming pulse starting from the erased state. The second programming verification operation includes the programming verification (PV1) for the first state, that is, the programming state range verified by the second programming verification operation is L1.

[0115] It can be understood that if the starting time of executing PV2 is set to 2, combined with Figure 1 the curve shown in (b), it can be seen that after applying the second programming pulse, the threshold voltages of the storage cells are all less than the threshold voltage of the second state. Therefore, there is no need to perform programming verification on the second state after applying the second programming pulse.

[0116] That is, compared with setting the starting time of the programming verification operation for the second state to 3 (as shown in Figure 1 (c)), the scheme of setting the starting time of the programming verification for the second state to 2 will increase the programming verification time, and thus increase the programming time. That is to say, when the fixed starting time set for the programming verification operation is earlier than the most suitable starting time, starting this programming verification too early will extend the verification operation time, and thus extend the programming duration.

[0117] Figure (c) shows the threshold voltage distribution curve obtained by performing the third programming verification operation on the storage cell after applying the next programming pulse based on Figure (b), that is, Figure (c) shows the threshold voltage distribution curve obtained by performing the third programming verification operation on the storage cell after applying the third programming pulse starting from the erased state. It should be emphasized that the third programming verification operation includes the programming verification (PV1) for the first state and the programming verification (PV2) for the second state, and the programming state range verified by the third programming verification operation is from L1 to L2.

[0118] Figure (d) shows the threshold voltage distribution curve obtained by performing the 4th programming verification operation on the memory cell after applying the next programming pulse based on Figure (c). That is, Figure (d) shows the threshold voltage distribution curve obtained by performing the 4th programming verification operation on the memory cell after applying the 4th programming pulse starting from the erased state. The 4th programming verification operation includes the programming verification (PV1) for the 1st state and the programming verification (PV2) for the 2nd state. The programming state range verified by the 4th programming verification operation is from L1 to L2.

[0119] Figure (e) shows the threshold voltage distribution curve obtained by performing the 5th programming verification operation on the memory cell after applying the next programming pulse based on Figure (d). That is, Figure (e) shows the threshold voltage distribution curve obtained by performing the 5th programming verification operation on the memory cell after applying the 5th programming pulse starting from the erased state. The 5th programming verification operation includes the programming verification (PV1) for the 1st state, the programming verification (PV2) for the 2nd state, and the programming verification (PV3) for the 3rd state. The programming state range verified by the 5th programming verification operation is from L1 to L3.

[0120] It can be understood that if the starting time of executing PV2 is set to 5, combined with Figure 1 the curve shown in (e), it can be seen that after applying the 5th programming pulse, the threshold voltages of some memory cells have exceeded the threshold voltage of the 3rd state, that is, over-programming occurs. Therefore, starting the programming verification for the 2nd state after applying the 5th programming pulse will result in over-programming.

[0121] That is, compared with setting the starting time of the programming verification operation for the 2nd state to 3 (as shown in Figure 1 (c)), setting the starting time of the programming verification for the 2nd state to 5 will result in over-programming and reduce the programming quality. That is to say, when the fixed starting time set for the programming verification operation is later than the most suitable starting time, over-programming may occur, thereby reducing the programming quality.

[0122] Figure (f) shows the threshold voltage distribution curve obtained by performing the 6th programming verification operation on the memory cell after applying the next programming pulse based on Figure (e). That is, Figure (e) shows the threshold voltage distribution curve obtained by performing the 6th programming verification operation on the memory cell after applying the 6th programming pulse starting from the erased state. The 6th programming verification operation includes the programming verification (PV1) for the 1st state, the programming verification (PV2) for the 2nd state, and the programming verification (PV3) for the 3rd state. The programming state range verified by the 6th programming verification operation is from L1 to L3.

[0123] Figure (g) shows the threshold voltage distribution curve obtained by performing the 7th programming verification operation on the memory cell after applying the next programming pulse based on Figure (f), that is, Figure (g) shows the threshold voltage distribution curve obtained by performing the 7th programming verification operation on the memory cell after applying the 7th programming pulse starting from the erased state. The 7th programming verification operation includes the programming verification (PV2) for the 2nd state, the programming verification (PV3) for the 3rd state, and the programming verification (PV4) for the 4th state. The programming state range verified by the 7th programming verification operation is from L2 to L4.

[0124] Figure (h) shows the threshold voltage distribution curve obtained by performing the 8th programming verification operation on the memory cell after applying the next programming pulse based on Figure (g), that is, Figure (h) shows the threshold voltage distribution curve obtained by performing the 8th programming verification operation on the memory cell after applying the 8th programming pulse starting from the erased state. The 8th programming verification operation includes the programming verification (PV2) for the 2nd state, the programming verification (PV3) for the 3rd state, and the programming verification (PV4) for the 4th state. The programming state range verified by the 8th programming verification operation is from L2 to L4. And so on until the programming is completed.

[0125] From Figure 1 It can be seen that after applying the programming pulse, the threshold voltages of memory cells in different programming states will move simultaneously. When the threshold voltage of a memory cell reaches its target threshold voltage, a programming inhibition condition can be applied to this memory cell so that when the next programming pulse is applied, the threshold voltage of the memory cell that has reached the target threshold voltage will no longer move. It can be understood that during the application of the next programming pulse, the threshold voltage of the memory cell that has not reached the target threshold voltage will increase, and the threshold voltage distribution curve will move towards a higher threshold voltage direction.

[0126] Exemplarily, the threshold voltage range of a higher programming state can be predicted based on the information obtained from the programming verification of a lower programming state.

[0127] Specifically: As shown in (c), (d), and (e) in Figure 1 For (c) in Figure 1 the highest programming state for which the programming verification is performed is the 2nd state. Then, based on the verification result obtained from the programming verification operation (PV2) for the 2nd state, it is possible to predict how many memory cells with the target programming state of the 3rd state can reach their target state after applying the next programming pulse.

[0128] For example, if among the storage cells whose target state is the 2nd state, only a very small number of storage cells, or even no storage cells, have reached the 2nd state, then it can be predicted that after applying the next programming pulse, no storage cells whose target programming state is the 3rd state will be able to reach the 3rd state, that is, the 3rd state will not be programmed successfully. Therefore, there is no need to start the programming verification operation for the 3rd state after applying the next programming pulse. In this way, the number of programming states that need to be verified in the next programming verification operation can be reduced, which is beneficial to shorten the programming verification time, reduce the number of verification results to be processed, and improve programming efficiency.

[0129] For example, if more storage cells with a target state of the second state have reached the second state, it can be predicted that after applying the next programming pulse, there will be storage cells with a target programming state of the third state that can reach the third state. Therefore, it is necessary to start programming verification operations on the third state after applying the next programming pulse. In this way, the occurrence of over-programming can be reduced and the programming quality can be improved.

[0130] In view of this, the present disclosure provides a memory programming verification method according to an embodiment of the present invention. Figure 2 As shown, the programming verification method includes the following steps:

[0131] S100: Obtaining an i-th verification result of an i-th programming verification operation; wherein the programming state range verified by the i-th programming verification operation is from the n-th state to the n+k-th state, i and n are positive integers, k is a natural number, and the n+k-th state is less than or equal to the highest programming state of the memory;

[0132] S110: Determine a programming state range to be verified in an (i+1)th program-verification operation according to a verification sub-result of the nth state and a verification sub-result of the (n+k)th state in the (i)th verification result;

[0133] S120: performing an (i+1)th program-verification operation according to the determined programming state range that needs to be verified in the (i+1)th program-verification operation.

[0134] Exemplarily, the memory may include a storage array consisting of multiple storage cells, and the storage cells may include single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), or cells with more levels, etc.

[0135] In S100 , the i-th program verification operation may be understood as a program verification operation performed on the memory cell to be programmed after applying the i-th program pulse and before applying the (i+1)-th program pulse, starting from the erased state.

[0136] The programming state range verified by the i-th programming verification operation is from the n-th state to the (n + k)-th state. That is, the lowest state verified by the i-th programming verification operation is the n-th state, and the highest state is the (n + k)-th state. Moreover, the i-th programming verification operation needs to verify the states between the n-th state and the (n + k)-th state.

[0137] The i-th verification result is used to represent the programming result of the storage unit to be programmed after applying i programming pulses. The i-th verification result may include at least one of the following: the first type of indication information indicating whether each verified storage unit is programmed successfully; the second type of indication information indicating whether each verified storage unit is programmed failed; the third type of indication information indicating the number of storage units that reach the target programming state.

[0138] In S110, the verification sub-result of the n-th state is used to represent the result obtained by programming and verifying the storage units with the target programming state of the n-th state during the i-th programming verification operation. The verification sub-result of the n-th state may include at least one of the following: the first type of indication information indicating whether each storage unit with the target programming state of the n-th state is programmed successfully; the second type of indication information indicating whether each storage unit with the target programming state of the n-th state is programmed failed; the third type of indication information indicating the number of storage units that reach the target programming state of the n-th state.

[0139] Similarly, the verification sub-result of the (n + k)-th state is used to represent the result obtained by programming and verifying the storage units with the target programming state of the (n + k)-th state during the i-th programming verification operation. The verification sub-result of the (n + k)-th state may include at least one of the following: the first type of indication information indicating whether each storage unit with the target programming state of the (n + k)-th state is programmed successfully; the second type of indication information indicating whether each storage unit with the target programming state of the (n + k)-th state is programmed failed; the third type of indication information indicating the number of storage units that reach the target programming state of the (n + k)-th state.

[0140] It should be emphasized that the value of k can be equal to 0. When k is equal to 0, the value of n is equal to the value of n + k, that is, the i-th programming verification operation only verifies the n-th state.

[0141] Taking TLC as an example, the highest programming state of the memory is the 7th state. Therefore, the value of n + k is less than or equal to 7. Taking QLC as an example, the highest programming state of the memory is the 15th state. Therefore, the value of n + k is less than or equal to 15.

[0142] When programming and verifying different programming states, the starting verification levels are different. In S110, determining the programming state range to be verified by the (i + 1)-th programming verification operation may include determining the verification level range of the (i + 1)-th programming verification operation.

[0143] In some embodiments, S110 includes:

[0144] Determine the lowest programming state to be verified in the (i + 1)-th programming verification operation according to the verification sub-result of the n-th state in the i-th verification result.

[0145] Determine the highest programming state to be verified in the (i + 1)-th programming verification operation according to the verification sub-result of the (n + k)-th state in the i-th verification result.

[0146] In S120, programming verification can be performed on all storage units within the range of programming states to be verified in the (i + 1)-th programming verification operation for the target state.

[0147] Alternatively, in S120, programming verification for the (i + 1)-th time can also be performed only on the storage units within the range of programming states to be verified in the (i + 1)-th programming verification operation for the target state and that were not successfully programmed in the previous programming. In this way, the number of storage units to be verified can be reduced, and the programming verification time can be shortened. It should be emphasized that at this time, in the (i + 1)-th verification result obtained, it includes not only data indicating whether the storage units for which the (i + 1)-th programming verification is performed are successfully programmed, but also information indicating the number of storage units that have been successfully programmed.

[0148] In practical applications, the (i + 1)-th programming verification operation can be performed after applying the (i + 1)-th programming pulse. It can be understood that the steps given by the above programming verification method can be executed cyclically until programming is completed, or until the maximum number of programming verification times that can be performed is reached.

[0149] Compared with the situation where each programming verification operation has a fixed range of programming states to be verified, in the embodiments of the present disclosure, according to the verification result of the i-th programming verification operation, the range of programming states to be verified in the (i + 1)-th programming verification operation performed after applying the next programming pulse is determined, that is, the range of programming states to be verified in the next programming verification operation is determined according to the result of the previous programming verification operation. The starting moment of each programming state to be verified can be dynamically determined, improving the accuracy of the starting moment of each programming state to be verified determined. On the one hand, it can reduce the increase in programming duration caused by setting the starting moment of programming verification too early, which is beneficial to shortening the programming duration; on the other hand, it can reduce over-programming caused by setting the starting moment of programming verification too late, which is beneficial to ensuring better programming quality.

[0150] In addition, compared with the need to manually set different fixed starting moments respectively when programming the same programming state in different units (such as in units of blocks or word lines), in the embodiments of the present disclosure, there is no need to manually set a fixed starting moment. Instead, the difference in the programming performance of the memory is tracked through the verification result, and then the range of programming states to be verified in each programming verification operation is automatically determined. The method is simple and can timely adjust the range of programming states to be verified in the programming verification operation according to the memory performance, which is beneficial to improving the programming quality.

[0151] In some embodiments, the verification sub-result of the n-th state in the i-th verification result includes: the i-th statistical data of the n-th state, which is used to count the number of failed bits in programming the n-th state;

[0152] Determining the lowest programming state that needs to be verified in the (i + 1)-th programming verification operation according to the verification sub-result of the n-th state in the i-th verification result includes:

[0153] Determining the number of failed bits in programming the n-th state according to the i-th statistical data of the n-th state;

[0154] When the number of failed bits in programming the n-th state is less than the first preset value, determining that the lowest programming state that needs to be verified in the (i + 1)-th programming verification operation is the (n + 1)-th state;

[0155] When the number of failed bits in programming the n-th state is greater than or equal to the first preset value, determining that the lowest programming state that needs to be verified in the (i + 1)-th programming verification operation is the n-th state.

[0156] The i-th statistical data of the n-th state may include: data indicating whether the n-th programming verification operation on each storage unit whose target state is the n-th state passes. According to the i-th statistical data of the n-th state, the number of failed bits in the i-th programming operation on the n-th state can be determined.

[0157] Exemplarily, binary coding can be used to represent whether a storage unit is programmed successfully. For example, 0 can be used to represent successful programming, and 1 can be used to represent unsuccessful programming; or 1 can be used to represent successful programming, and 0 can be used to represent unsuccessful programming. In implementation, those skilled in the art can select a suitable way to represent whether a storage unit is programmed successfully according to the actual situation, and the embodiments of the present disclosure do not limit this.

[0158] It can be understood that when the number of failed bits in programming the n-th state is less than the first preset value, it can be considered that the programming of the n-th state is successfully completed. Therefore, in the next programming verification process, there is no need to verify the programming of the n-th state again. In this way, compared with verifying the n-th state every time, the programming verification time can be shortened and the programming speed can be improved.

[0159] When the number of failed bits in programming the n-th state is greater than or equal to the first preset value, it can be considered that the programming of the n-th state has not been successful. Therefore, in the next programming verification process, it is necessary to continue to verify the programming of the n-th state.

[0160] In some embodiments, when the ratio of the number of failed bits programmed to the nth state to the number of bits with the target state being the nth state is less than the first preset ratio, it is determined that the lowest programmed state to be verified in the (i + 1)-th programming verification operation is the (n + 1)-th state; when the ratio of the number of failed bits programmed to the nth state to the number of bits with the target state being the nth state is greater than or equal to the first preset ratio, it is determined that the lowest programmed state to be verified in the (i + 1)-th programming verification operation is the nth state.

[0161] Similarly, when the ratio of the number of failed bits programmed to the nth state to the number of bits with the target state being the nth state is less than the first preset value, it can be considered that the programming of the nth state is successfully completed. Therefore, in the next programming verification process, there is no need to verify the programming of the nth state again. In this way, compared with verifying the nth state every time, the programming verification time can be shortened and the programming speed can be improved.

[0162] When the ratio of the number of failed bits programmed to the nth state to the number of bits with the target state being the nth state is greater than or equal to the first preset value, it can be considered that the programming of the nth state has not been successful. Therefore, in the next programming verification process, it is necessary to continue to verify the programming of the nth state.

[0163] In some embodiments, the method further includes:

[0164] Obtaining the number of cycles of the storage unit to be programmed;

[0165] Determining the value range of the first preset value or the value range of the first preset ratio according to the number of cycles.

[0166] For a memory, one erase operation and one write operation are called one cycle. As the number of cycles increases, the programming performance of the memory may change, resulting in a change in the programming speed. It can be understood that the cycle is defined by the smallest unit of programming. For example, when programming with a block as the smallest unit, the number of cycles of each storage unit in the block is basically the same.

[0167] It should be emphasized that when the memory is programmed with different smallest units, the obtained number of cycles is the number of cycles of the smallest unit for which the programming is performed.

[0168] Compared with providing a fixed first preset value, in the embodiments of the present disclosure, by obtaining the number of cycles of the storage unit to be programmed and determining the first preset value according to the number of cycles, the programming characteristics that change with the number of cycles can be traced during the programming verification process, and then the range of the first preset value can be flexibly adjusted, reducing the slow programming speed caused by improper determination of the first preset value, which is beneficial to improving the programming speed and ensuring better programming quality.

[0169] In some embodiments, the value range of the first preset value is within the range allowed by the error correcting code (ECC) error correction mechanism for the memory.

[0170] It should be emphasized that to ensure the programming quality, the programming verification operation for the nth state needs to be stopped after the programming of the nth state is completed. Due to the existence of the ECC error correction mechanism, when the number of failed bits in the programming of the nth state is within the range allowed by the ECC error correction mechanism, at least some of the failed bits can be corrected through ECC error correction to ensure that correct data can be read from the memory.

[0171] In the embodiments of the present disclosure, since the value range of the first preset value is within the range allowed by the ECC mechanism, when the number of failed bits in the programming of the nth state is less than the first preset value, the failed bits can be corrected through the ECC error correction mechanism to ensure that the programming of the nth state can be successfully completed, and the nth state does not need to be verified in the next programming verification, which is beneficial to reducing the number of programming states to be verified and improving the programming efficiency.

[0172] In some embodiments, the value range of the first preset ratio is from 0.4% to 0.6%. For example, the value of the first preset ratio can be 0.5%.

[0173] In some embodiments, the verification sub-result of the (n + k)th state in the ith verification result includes: the ith statistical data of the (n + k)th state, which is used to count the number of successfully programmed bits for the (n + k)th state.

[0174] Determining the highest programming state to be verified in the (i + 1)th programming verification operation according to the verification sub-result of the (n + k)th state in the ith verification result includes:

[0175] Determine the number of successfully programmed bits for the (n + k)th state according to the ith statistical data of the (n + k)th state;

[0176] When the number of successfully programmed bits for the (n + k)th state is greater than the second preset value and the (n + k)th state is less than the highest programming state of the memory, determine that the highest programming state to be verified in the (i + 1)th programming verification operation is the (n + k + 1)th state;

[0177] When the number of successfully programmed bits for the (n + k)th state is less than or equal to the second preset value, determine that the highest programming state to be verified in the (i + 1)th programming verification operation is the (n + k)th state.

[0178] The ith statistical data of the (n + k)th state may include: data indicating whether the nth programming verification operation for each storage unit whose target state is the (n + k)th state passes. According to the ith statistical data of the (n + k)th state, the number of failed bits in the ith programming operation for the (n + k)th state can be determined.

[0179] When the number of successfully programmed bits for the (n + k)-th state is greater than a second preset value and the (n + k)-th state is less than the highest programmed state of the memory, it can be considered that after the next programming pulse is applied, many memory cells with the target programming state of the (n + k)-th state may reach the target state, and there may be memory cells with the target state of the (n + k + 1)-th state that reach the target state. Therefore, during the next programming verification process, it is necessary to perform a programming verification for the (n + k + 1)-th state to reduce over-programming caused by starting the verification of the (n + k + 1)-th state too late.

[0180] When the number of successfully programmed bits for the (n + k)-th state is less than or equal to the second preset value, it can be considered that the programming of the (n + k)-th state has not been successful, and after the next programming pulse is applied, the probability that a memory cell with the target state of the (n + k + 1)-th state reaches the target state is very low. Therefore, during the next programming verification process, there is no need to start verifying the (n + k + 1)-th state, and the highest state to be verified in the next programming verification operation is still the (n + k)-th state.

[0181] In some embodiments, when the ratio of the number of successfully programmed bits for the (n + k)-th state to the number of bits with the target state of the (n + k)-th state is greater than a second preset ratio, it is determined that the highest programmed state to be verified in the (i + 1)-th programming verification operation is the (n + k + 1)-th state;

[0182] When the ratio of the number of successfully programmed bits for the (n + k)-th state to the number of bits with the target state of the (n + k)-th state is less than or equal to the second preset ratio, it is determined that the highest programmed state to be verified in the (i + 1)-th programming verification operation is the (n + k)-th state.

[0183] Similarly, when the ratio of the number of successfully programmed bits for the (n + k)-th state to the number of bits with the target state of the (n + k)-th state is greater than a second preset value and the (n + k)-th state is less than the highest programmed state of the memory, it can be considered that after the next programming pulse is applied, many memory cells with the target programming state of the (n + k)-th state may reach the target state, and there may be memory cells with the target state of the (n + k + 1)-th state that reach the target state. Therefore, during the next programming verification process, it is necessary to start a programming verification for the (n + k + 1)-th state to reduce over-programming caused by starting the verification of the (n + k + 1)-th state too late.

[0184] When the ratio of the number of successfully programmed bits for the (n + k)-th state to the number of bits with the target state of the (n + k)-th state is less than or equal to the second preset value, we can consider that the programming of the (n + k)-th state has not been successful, and after the next programming pulse is applied, the probability that a memory cell with the target state of the (n + k + 1)-th state reaches the target state is very low. Therefore, during the next programming verification process, there is no need to verify the (n + k + 1)-th state, and the highest state to be verified in the next programming verification operation is still the (n + k)-th state.

[0185] In some embodiments, the method further includes:

[0186] Obtaining the number of cycles of the storage unit to be programmed;

[0187] Determining the value range of the second preset value or the value range of the second preset ratio according to the number of cycles.

[0188] Compared with providing a fixed second preset value, in the embodiments of the present disclosure, by obtaining the number of cycles of the storage unit to be programmed and determining the second preset value according to the number of cycles, the programming characteristics that change with the number of cycles can be traced during the programming verification process, and then the range of the second preset value can be flexibly adjusted, reducing the slow programming speed caused by improper setting of the second preset value, which is beneficial to improving the programming speed and ensuring better programming quality.

[0189] In some embodiments, the value range of the second preset ratio is 2% to 3%. For example, the value of the second preset ratio can be 2.3%.

[0190] In some embodiments, based on the concept of PVS (Program Vt distribution sigma), taking TLC as an example, each programming pulse will shift the threshold voltage distribution by ~2 times of sigma, and the difference between the verification levels of different programming states is about 3 times of sigma. In order to avoid over-programming of the storage unit with the target programming state of the n + k + 1 state after applying the next programming pulse, resulting in its threshold voltage exceeding the target threshold voltage, therefore, the value of the second preset value can be set to outside the positive 2 times of sigma (i.e., 2.3%).

[0191] When the ratio of the number of successful bits for programming the n + k state to the number of bits with the target state of the n + k state is greater than 2.3%, it can be considered that after applying the next programming pulse, many (e.g., 50%) storage units with the target programming state of the n + k state may reach the target state, and since the target threshold voltage distribution of the n + k + 1 state is at the negative 3 times of sigma, there will also start to be cases where the storage units with the target state of the n + k + 1 state reach the target threshold voltage. Therefore, the n + k + 1 state needs to be verified during the next programming verification.

[0192] In some embodiments, the programming verification method is applied to the incremental step pulse programming method, and the programming verification method further includes:

[0193] Obtaining the step size of the incremental step pulse programming and / or the programming voltage slope;

[0194] Determine the value range of the second preset value according to the step size and / or the programming voltage slope; or determine the value range of the second preset ratio according to the step size and the programming voltage slope.

[0195] Exemplarily, the memory can be programmed by means of Incremental Step Pulse Programing (ISPP). It should be noted that when the step size and / or the programming voltage slope change, the change rate of the threshold voltage of the memory cell also changes. Therefore, the value ranges of the second preset value and the second preset ratio can be adjusted correspondingly.

[0196] Specifically, taking the step size as an example, when the step size is large, the threshold voltage of the memory cell increases significantly after each programming pulse is applied. Therefore, the values of the second preset value and the second preset ratio can be relatively small. When the step size is small, the threshold voltage of the memory cell increases slightly after each programming pulse is applied. Therefore, the values of the second preset value and the second preset ratio can be relatively large.

[0197] For example, taking QLC as an example, coarse programming or fine programming can be adopted. The step size of coarse programming is larger than that of fine programming. Therefore, when coarse programming is adopted, the value of the second preset value is smaller than that when fine programming is adopted; or when coarse programming is adopted, the value of the second preset ratio is smaller than that when fine programming is adopted.

[0198] Compared with providing fixed second preset value and second preset ratio, in the embodiments of the present disclosure, by obtaining the step size and / or the programming voltage slope of the incremental step pulse programming, and determining the value range of the second preset value according to the step size and / or the programming voltage slope; or determining the value range of the second preset ratio according to the step size and the programming voltage slope, the ranges of the second preset value and the second preset ratio can be flexibly adjusted, reducing the slow programming speed caused by improper setting of the second preset value and the second preset ratio, which is beneficial to improving the programming speed and ensuring better programming quality.

[0199] In some embodiments, S110 includes:

[0200] Sample the verification sub-results of the nth state and the verification sub-results of the (n + k)th state in the i-th verification result respectively to obtain the i-th sampling statistical data of the nth state and the i-th sampling statistical data of the (n + k)th state;

[0201] Determine the lowest programming state to be verified in the (i + 1)th programming verification operation according to the i-th sampling statistical data of the nth state;

[0202] Determine the highest programming state to be verified for the (i + 1)-th programming verification operation according to the i-th sampling statistic data of the (n + k)-th state.

[0203] During the programming verification operation, the generated verification results can be stored in the page buffer. These data can be used to determine the memory cells to which a programming inhibit voltage needs to be applied during the subsequent application of programming pulses. Specifically, the verification results can be stored in a dedicated latch in the page buffer, and this dedicated latch is only used to temporarily store the verification results of the programming verification operation. Alternatively, the verification results can also be stored in some other latches in the page buffer, and these latches can also be used to store programming data, or programming inhibit information, etc.

[0204] The i-th sampling statistic data of the n-th state may include: statistical data obtained by randomly sampling the verification results of all memory cells with the target programming state being the n-th state and counting the number of failed bits in the sampling results.

[0205] The i-th sampling statistic data of the (n + k)-th state may include: statistical data obtained by randomly sampling the verification results of all memory cells with the target programming state being the (n + k)-th state and counting the number of successful bits in the sampling results.

[0206] Exemplarily, when there are 16 KB of latches in the page buffer for storing the above verification results, 4 KB of the verification results stored in randomly selected latches can be used as the sampling sample data to determine the lowest programming state and the highest programming state to be verified for the (i + 1)-th programming verification operation.

[0207] It can be understood that in some embodiments, 2 KB or 8 KB of the data stored in randomly selected latches can also be used as the sampling sample data to determine the lowest programming state and the highest programming state to be verified for the (i + 1)-th programming verification operation.

[0208] It should be emphasized that when sampling the statistical data of the number of failed bits and the number of successful bits to obtain the i-th sampling statistic data of the n-th state and the i-th sampling statistic data of the (n + k)-th state, it is not limited to obtaining data in units of an entire latch, and partial data in a certain latch can also be obtained as the sampling statistic data.

[0209] After each programming verification operation, the generated verification results include a large amount of data, especially when programming verification is performed on each memory cell to be programmed. Therefore, if the verification results of all memory cells are counted, the time required for counting the number of failed bits and the number of successful bits will be extended, resulting in an increase in the programming time.

[0210] In the embodiments of the present disclosure, by sampling the verification sub-results of the nth state and the verification sub-results of the (n + k)th state respectively, the ith sampling statistical data of the nth state and the ith sampling statistical data of the (n + k)th state are obtained. According to the ith sampling statistical data of the nth state, the lowest programming state to be verified in the (i + 1)th programming verification operation is determined. According to the ith sampling statistical data of the (n + k)th state, the highest programming state to be verified in the (i + 1)th programming verification operation is determined. This can reduce the total amount of data to be counted for each failure bit count and success bit count, which is beneficial to shortening the time for failure bit count and success bit count, improving the determination range of the programming states to be verified in the (i + 1)th programming verification operation, thereby improving the programming speed, shortening the programming duration, and improving the memory performance.

[0211] In the related art, the programming of a memory is typically performed using the following iterative process: applying a programming pulse to a storage cell and verifying in response to the programming pulse whether the storage cell has reached a desired data state (i.e., the target programming state), and repeating the iterative process until the programming verification of the storage cell passes. When the storage cell passes the verification, further programming is prohibited, but other storage cells that have not reached the target programming state can still be programmed for subsequent programming pulses.

[0212] After each verification operation, it is usually necessary to count the number of storage cells that failed the verification in the current programming operation, that is, to perform a fail bit count (FBC). In the related art, in terms of timing, the operations of counting the fail bits and counting the success bits are performed between the current programming operation and the next programming operation, which requires additional time and results in a longer programming time.

[0213] In view of this, Figure 3 is a flowchart of a programming method for a memory shown according to an exemplary embodiment. Referring to Figure 3 as shown, the programming method includes the following steps:

[0214] S200: Applying the (i + 1)th programming pulse to the storage cells to be programmed in the memory;

[0215] S210: During the application of the (i + 1)th programming pulse, according to the verification sub-results of the nth state and the verification sub-results of the (n + k)th state in the ith verification result of the ith programming verification operation, performing a fail bit count for the programming of the nth state in the ith programming operation and a success bit count for the programming of the (n + k)th state to obtain the ith count result; wherein, the range of programming states verified by the ith programming verification operation is from the nth state to the (n + k)th state, i and n are positive integers, k is a natural number, and the (n + k)th state is less than or equal to the highest programming state of the memory;

[0216] S220: Determine the programming state range to be verified for the (i + 1)-th programming verification operation according to the i-th counting result;

[0217] S230: Execute the (i + 1)-th programming verification operation according to the determined programming state range to be verified for the (i + 1)-th programming verification operation.

[0218] In S200, a programming pulse application operation can be performed on the memory cell array through a programming operation circuit in the peripheral circuit of the memory device to control the potential level of the bit lines of the selected memory cell array.

[0219] In S210, during the (i + 1)-th programming pulse, it can include the (i + 1)-th programming preparation operation stage and the (i + 1)-th programming stable execution stage. Among them, the (i + 1)-th programming preparation operation is to perform the preparation operation of the states and data related to the (i + 1)-th programming operation, which corresponds to the stage of applying the (i + 1)-th pass voltage (Vpass) to the selected word line in terms of voltage timing. The (i + 1)-th programming stable execution stage is to control the potential level of the bit lines of the memory cell array in response to the programming data during the programming pulse application operation, which corresponds to the stage of applying the (i + 1)-th programming voltage to the selected word line in terms of voltage timing.

[0220] In some embodiments, after the (i + 1)-th programming preparation operation, that is, after applying the (i + 1)-th pass voltage to the selected word line, the i-th statistical data can be read in the (i + 1)-th programming stable execution stage.

[0221] In S220, the i-th counting result can include the i-th statistical data of the n-th state and the i-th statistical data of the (n + k)-th state in the above programming verification method. Or, the i-th counting result can include the i-th sampling statistical data in the above programming verification method. Thus, to determine the programming state range to be verified for the (i + 1)-th programming verification operation according to the i-th counting result, reference can be made to the programming verification method provided in the embodiments of the present disclosure, which will not be elaborated here.

[0222] Compared with counting the number of failed bits and the number of successful bits between the application of the i-th programming pulse and the (i + 1)-th programming pulse to determine the programming state range to be verified for the (i + 1)-th programming verification operation after the (i + 1)-th programming pulse, the programming method provided in the embodiments of the present disclosure can, during the application of the (i + 1)-th programming pulse, count the number of failed bits and the number of successful bits for the programming results of the n-th state and the (n + k)-th state respectively according to the verification sub-results of the n-th state and the verification sub-results of the (n + k)-th state in the i-th verification result of the i-th programming verification operation to determine the programming state range to be verified for the (i + 1)-th programming verification operation. In this way, the operation of counting the number of failed bits during the iterative process of the entire programming operation does not occupy additional time, thereby saving the execution time of the iterative process of the entire programming operation and improving the efficiency of programming the memory cells.

[0223] Moreover, in the embodiments of the present disclosure, by hiding the failure bit count process during the application of programming pulses, logic overhead can be saved.

[0224] Exemplarily, in terms of timing, S220 can be executed between S210 and S230.

[0225] Preferably, in terms of timing, S220 can overlap with S210. Specifically, S220 can be executed during the application of the (i + 1)-th programming pulse and after obtaining the i-th count result. In this way, the range of programming states that need to be verified in the (i + 1)-th programming verification operation can be hidden during the application of the (i + 1)-th programming pulse. Thus, during the iterative process of the entire programming operation, the operation of determining the range of programming states that need to be verified in the (i + 1)-th programming verification operation does not occupy additional time, thereby further saving the execution time of the iterative process of the entire programming operation and improving the efficiency of programming memory cells.

[0226] In some embodiments, the i-th count result includes: the number of failed bits for programming the n-th state in the i-th programming operation;

[0227] S220 may include:

[0228] When the number of failed bits for programming the n-th state is less than a first preset value, determine that the lowest programming state that needs to be verified in the (i + 1)-th programming verification operation is the (n + 1)-th state;

[0229] When the number of failed bits for programming the n-th state is greater than or equal to the first preset value, determine that the lowest programming state that needs to be verified in the (i + 1)-th programming verification operation is the n-th state.

[0230] In some embodiments, S220 may include:

[0231] When the ratio of the number of failed bits for programming the n-th state to the number of bits with the target state being the n-th state is less than a first preset ratio, determine that the lowest programming state that needs to be verified in the (i + 1)-th programming verification operation is the (n + 1)-th state;

[0232] When the ratio of the number of failed bits for programming the n-th state to the number of bits with the target state being the n-th state is greater than or equal to the first preset ratio, determine that the lowest programming state that needs to be verified in the (i + 1)-th programming verification operation is the n-th state.

[0233] In some embodiments, the i-th count result includes: the number of successful bits for programming the (n + k)-th state in the i-th programming operation;

[0234] S220 may include:

[0235] When the number of successfully programmed bits for the (n + k)-th state is greater than a second preset value and the (n + k)-th state is less than the highest programmed state of the memory, determine that the highest programmed state to be verified in the (i + 1)-th programming verification operation is the (n + k + 1)-th state;

[0236] When the number of successfully programmed bits for the (n + k)-th state is less than or equal to the second preset value, determine that the highest programmed state to be verified in the (i + 1)-th programming verification operation is the (n + k)-th state.

[0237] In some embodiments, S220 may include:

[0238] When the ratio of the number of successfully programmed bits for the (n + k)-th state to the number of bits with the target state being the (n + k)-th state is greater than a second preset ratio, determine that the highest programmed state to be verified in the (i + 1)-th programming verification operation is the (n + k + 1)-th state;

[0239] When the ratio of the number of successfully programmed bits for the (n + k)-th state to the number of bits with the target state being the (n + k)-th state is less than or equal to the second preset ratio, determine that the highest programmed state to be verified in the (i + 1)-th programming verification operation is the (n + k)-th state.

[0240] In some embodiments, S210 may include:

[0241] Respectively sample the verification sub-results of the n-th state and the (n + k)-th state in the i-th verification result to obtain the i-th sampling sample data of the n-th state and the i-th sampling sample data of the (n + k)-th state;

[0242] According to the i-th sampling sample data of the n-th state and the i-th sampling sample data of the (n + k)-th state, count the number of failed bits in the programming of the n-th state and the number of successfully programmed bits in the programming of the (n + k)-th state in the i-th programming operation to obtain the i-th counting result.

[0243] The i-th counting result may include the i-th sampling statistical data of the n-th state and the i-th sampling statistical data of the (n + k)-th state.

[0244] Exemplarily, randomly sample the verification results of all storage units with the target programming state being the n-th state to obtain the i-th sampling sample data of the n-th state, and then count the number of failed bits in the i-th sampling sample data of the n-th state to obtain the i-th sampling statistical data of the n-th state.

[0245] Similarly, randomly sample the verification results of all storage units with the target programming state being the (n + k)-th state to obtain the i-th sampling sample data of the (n + k)-th state, and then count the number of successfully programmed bits in the i-th sampling sample data of the (n + k)-th state to obtain the i-th sampling statistical data of the (n + k)-th state.

[0246] In the embodiments of the present disclosure, by sampling the verification sub-results of the n-th state and the verification sub-results of the (n + k)-th state respectively, the i-th sampling sample data of the n-th state and the i-th sampling sample data of the (n + k)-th state are obtained, and according to the i-th sampling sample data of the n-th state and the i-th sampling sample data of the (n + k)-th state, the i-th counting result is obtained, which can reduce the total amount of data to be counted each time for the failure bit count and the success bit count, is beneficial to shortening the time for the failure bit count and the time for the success bit count, improves the determination range of the programming states to be verified in the (i + 1)-th programming verification operation, thereby improving the programming speed, shortening the programming duration, and improving the memory performance.

[0247] Next, with reference to Figure 4 shown below, taking TLC as an example, a partial flowchart of a programming operation of a three-dimensional NAND memory is shown. The programming method includes the following steps:

[0248] S300: Perform the i-th programming verification to perform programming verification on the memory cells with the target states from the n-th state to the (n + k)-th state (i.e., verify (PVn,..., PVn + k)); where i and n are positive integers, k is a natural number, and the (n + k)-th state is less than or equal to the highest programming state of the memory;

[0249] S310: After performing the i-th programming verification, apply the (i + 1)-th programming pulse; during the application of the (i + 1)-th programming pulse, according to the verification sub-results of the n-th state and the verification sub-results of the (n + k)-th state in the i-th verification result of the i-th programming verification operation, perform a failure bit count on the programming of the n-th state in the i-th programming operation and a success bit count on the programming of the (n + k)-th state respectively, and obtain the i-th counting result;

[0250] S320: According to the i-th counting result, determine whether the number of failure bits when performing programming verification on the n-th state (i.e., PVn) is less than a first preset value;

[0251] S330: According to the i-th counting result, determine whether the number of success bits when performing programming verification on the (n + k)-th state (i.e., PVn + k) is greater than a second preset value;

[0252] When the number of failure bits when performing programming verification on the n-th state (i.e., PVn) is less than the first preset value, and the number of success bits when performing programming verification on the (n + k)-th state (i.e., PVn + k) is greater than the second preset value, it can be determined that the range of programming states to be verified in the (i + 1)-th programming verification operation is from the (n + 1)-th state to the (n + k + 1)-th state. Therefore, jump to execute S331;

[0253] When the number of failed bits during the programming verification of the n-th state (i.e., PVn) is less than the first preset value, and the number of successful bits during the programming verification of the (n + k)-th state (i.e., PVn + k) is less than or equal to the second preset value, it can be determined that the range of programming states to be verified in the (i + 1)-th programming verification operation is from the (n + 1)-th state to the (n + k)-th state. Therefore, jump to execute S332;

[0254] When the number of failed bits during the programming verification of the n-th state (i.e., PVn) is greater than or equal to the first preset value, and the number of successful bits during the programming verification of the (n + k)-th state (i.e., PVn + k) is greater than the second preset value, it can be determined that the range of programming states to be verified in the (i + 1)-th programming verification operation is from the n-th state to the (n + k + 1)-th state. Therefore, jump to execute S341;

[0255] When the number of failed bits during the programming verification of the n-th state (i.e., PVn) is greater than or equal to the first preset value, and the number of successful bits during the programming verification of the (n + k)-th state (i.e., PVn + k) is less than or equal to the second preset value, it can be determined that the range of programming states to be verified in the (i + 1)-th programming verification operation is from the n-th state to the (n + k)-th state. Therefore, jump to execute S342;

[0256] S331: Perform the (i + 1)-th programming verification to perform programming verification on the storage unit with the target state from the (n + 1)-th state to the (n + k + 1)-th state (i.e., verify (PVn + 1,..., PVn + k + 1)); where the (n + k + 1)-th state is less than or equal to the highest programming state of the memory;

[0257] S332: Perform the (i + 1)-th programming verification to perform programming verification on the storage unit with the target state from the (n + 1)-th state to the (n + k)-th state (i.e., verify (PVn + 1,..., PVn + k));

[0258] S341: Perform the (i + 1)-th programming verification to perform programming verification on the storage unit with the target state from the n-th state to the (n + k + 1)-th state (i.e., verify (PVn,..., PVn + k + 1)); where the (n + k + 1)-th state is less than or equal to the highest programming state of the memory;

[0259] S342: Perform the (i + 1)-th programming verification to perform programming verification on the storage unit with the target state from the n-th state to the (n + k)-th state (i.e., verify (PVn,..., PVn + k));

[0260] S350: After completing the (i + 1)-th programming verification, apply a programming pulse, and during the application of the programming pulse, according to the verification sub-results of the lowest state and the highest state in the (i + 1)-th verification result of the (i + 1)-th programming verification operation, perform a failed bit count and a successful bit count on the programming of the lowest state and the highest state in the (i + 1)-th programming operation respectively, to obtain the (i + 1)-th count result.

[0261] It should be emphasized that each time a programming verification is performed, the highest state of the verification must be less than or equal to the highest state that the memory can be programmed to. When the highest state of the next programming verification determined according to S330 is greater than the highest state that the memory can be programmed to, the highest state during the execution of the next programming verification remains the highest state that the memory can be programmed to.

[0262] Taking TLC as an example, the highest state that can be programmed is L7. Then, when the highest state of the i-th programming verification operation is L7 and the number of successful bits of PV7 is greater than the second preset value, the highest state of the (i + 1)-th programming verification operation remains L7.

[0263] Specifically, taking TLC as an example, when i takes the value of 4, n takes the value of 1, and k takes the value of 1, the method includes the following steps:

[0264] Step 1: Perform the 4th programming verification operation (i.e., execute S300). The verification state range of the 4th programming verification operation is from the 1st state to the 2nd state, and obtain the threshold voltage distribution curve as shown in (d) in Figure 1 the figure.

[0265] Step 2: After performing the 4th programming verification, apply the 5th programming pulse. And during the application of the 5th programming pulse, according to the verification sub-results of the lowest state (i.e., the 1st state) and the highest state (i.e., the 2nd state) in the verification result of the 4th programming verification operation, count the number of failed bits and the number of successful bits for the programming of the 1st state and the 2nd state in the 4th programming operation respectively, and obtain the 4th counting result (i.e., execute S310 for the first time);

[0266] Subsequently, according to the 4th counting result, determine the programming state range that the 5th programming verification operation needs to verify. Specifically, step 3 can be executed: According to the 4th counting result, judge whether the number of failed bits when programming and verifying the 1st state in the 4th programming verification operation is less than the first preset value (i.e., execute S320); According to the 4th counting result, judge whether the number of successful bits when programming and verifying the 2nd state is greater than the second preset value (i.e., execute S330);

[0267] Step 4: When the 4th counting result indicates that in the 4th programming verification operation, the number of failed bits when programming and verifying the 1st state is less than the first preset value and the number of successful bits when programming and verifying the 2nd state is greater than the second preset value, jump to execute step 5 (i.e., execute S331);

[0268] When the fourth counting result indicates that in the fourth programming verification operation, the number of failed bits during the programming verification of the first state is less than the first preset value, and the number of successful bits during the programming verification of the second state is less than or equal to the second preset value, jump to execute step six (i.e., execute S332);

[0269] When the fourth counting result indicates that in the fourth programming verification operation, the number of failed bits during the programming verification of the first state is greater than or equal to the first preset value, and the number of successful bits during the programming verification of the second state is greater than the second preset value, jump to execute step seven (i.e., execute S341);

[0270] When the fourth counting result indicates that in the fourth programming verification operation, the number of failed bits during the programming verification of the first state is greater than or equal to the first preset value, and the number of successful bits during the programming verification of the second state is less than or equal to the second preset value, jump to execute step eight (i.e., execute S342);

[0271] Step five: Perform the fifth programming verification operation, where the range of target states to be verified in the fifth programming verification operation is from the second state to the third state; then execute step nine;

[0272] Step six: Perform the fifth programming verification operation, where the target state to be verified in the fifth programming verification operation is the second state; then execute step nine;

[0273] Step seven: Perform the fifth programming verification operation, where the range of target states to be verified in the fifth programming verification operation is from the first state to the third state; then execute step nine;

[0274] Step eight: Perform the fifth programming verification operation, where the range of target states to be verified in the fifth programming verification operation is from the first state to the second state; then execute step nine;

[0275] Step nine: Apply the sixth programming pulse; and, during the application of the sixth programming pulse, count the number of failed bits for the lowest programming state verified in the fifth programming verification operation, and count the number of successful bits for the highest programming state verified in the fifth programming verification operation to obtain the fifth counting result (i.e., execute S350).

[0276] It can be understood that in the actual programming operation process, the above programming method can be cyclically executed until the programming is completed, or until the number of times of applying the programming pulse reaches the maximum number, or until the number of times of performing the programming verification reaches the maximum value.

[0277] Figure 5 is a schematic diagram of a memory 100 shown according to an exemplary embodiment. Refer to Figure 5 As shown, the memory 100 includes:

[0278] A memory cell array 110, the memory cell array 110 including a plurality of memory cell rows;

[0279] A plurality of word lines 120, the plurality of word lines 120 being respectively coupled to the plurality of memory cell rows;

[0280] A peripheral circuit 130, the peripheral circuit 130 being coupled to the plurality of word lines 120 and configured to perform a program verification operation on a selected memory cell row among the plurality of memory cell rows, the selected memory cell row being coupled to a selected word line, wherein, in order to perform the program verification operation, the peripheral circuit 130 is configured to:

[0281] Obtain an i-th verification result of the i-th program verification operation; wherein, the programming state range verified by the i-th program verification operation is from the n-th state to the n + k-th state, i and n are positive integers, k is a natural number, and the n + k-th state is less than or equal to the highest programming state of the memory;

[0282] Determine the programming state range to be verified by the (i + 1)-th program verification operation according to the verification sub-result of the n-th state and the verification sub-result of the n + k-th state in the i-th verification result;

[0283] Perform the (i + 1)-th program verification operation according to the determined programming state range to be verified by the (i + 1)-th program verification operation.

[0284] The memory cell array 110 may be a NAND flash memory cell array, wherein the memory cell array 110 is provided in the form of an array of NAND memory strings 111, and each NAND memory string 111 extends vertically above a substrate (not shown). In some embodiments, each NAND memory string 111 includes a plurality of memory cells 112 coupled in series and vertically stacked. Each memory cell 112 may hold a continuous analog value, e.g., voltage or charge, depending on the number of electrons trapped within the region of the memory cell 112. Each memory cell 112 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0285] In some embodiments, each memory cell 112 is a single-level cell having two possible memory states and thus can store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range.

[0286] In some embodiments, each memory cell 112 is a cell capable of storing more than a single bit of data in more than four memory states. For example, two bits can be stored per cell (also referred to as a multi-level cell), three bits can be stored per cell (also referred to as a triple-level cell), or four bits can be stored per cell (also referred to as a quad-level cell). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programmed levels from an erased state by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used for the erased state.

[0287] As Figure 5 shown, each NAND memory string 111 can include a source select gate (SSG) 113 at its source extreme and a drain select gate (DSG) 114 at its drain extreme. The source select gate 113 and the drain select gate 114 can be configured to activate a selected NAND memory string 111 (a column of the array) during read and program operations.

[0288] In some embodiments, the sources of the NAND memory strings 111 in the same block 115 are coupled via the same source line (SL) 116 (e.g., a common SL). In other words, according to some embodiments, all of the NAND memory strings 111 in the same block 115 have an array common source (ACS).

[0289] According to some embodiments, the drain select gate 114 of each NAND memory string 111 is coupled to a respective bit line 117, and data can be read from or written to the bit line 117 via an output bus (not shown).

[0290] In some embodiments, each NAND memory string 111 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the drain select gate 114) or a deselected voltage (e.g., 0V) to the respective drain select gate 114 via one or more DSG lines 118. And / or, in some embodiments, each NAND memory string 111 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the source select gate 113) or a deselected voltage (e.g., 0V) to the respective source select gate 113 via one or more SSG lines 119.

[0291] As Figure 5As shown, the NAND memory strings 111 can be organized into multiple blocks 115, and each of the multiple blocks 115 can have a common source line 116 (e.g., coupled to ground). In some embodiments, each block 115 is the basic data unit for an erase operation, i.e., all memory cells 112 on the same block 115 are erased simultaneously. To erase the memory cells 112 in a selected block, the source lines coupled to the selected block and the unselected blocks in the same plane as the selected block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)).

[0292] It should be understood that in some examples, the erase operation can be performed at a half-block level, at a quarter-block level, or at a level with any suitable number of blocks or any suitable fraction of a block. The memory cells 112 of adjacent NAND memory strings 111 can be coupled by word lines 120, and the word lines 120 select which row of memory cells 112 is affected by read and program operations.

[0293] In some embodiments, each word line 120 is coupled to a page 130 of the memory cells 112, and the page 130 is the basic data unit for a program operation. The size of a page 130 in bits can be related to the number of NAND memory strings 111 coupled by the word lines 120 in a block 115. Each word line 120 can include multiple control gates (gate electrodes) at each memory cell 112 in the corresponding page 130 and a gate line that couples the control gates. It can be understood that a row of memory cells is a plurality of memory cells 112 located on the same page 130.

[0294] Figure 6 A side view of a cross-section of an exemplary memory cell array 110 including NAND memory strings 111 according to some aspects of the present disclosure is shown. As Figure 6 shown, the NAND memory strings 111 can vertically extend above the substrate 101 through the memory stack layer 102. The substrate 101 can include silicon (e.g., single-crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0295] The memory stack layer 102 can include alternating gate conductive layers 103 and gate-to-gate dielectric layers 104. The number of pairs of gate conductive layers 103 and gate-to-gate dielectric layers 104 in the memory stack layer 102 can determine the number of memory cells 112 in the memory cell array 110.

[0296] The gate conductive layer 103 may include a conductive material, which includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 103 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate conductive layer 103 includes a doped polysilicon layer. Each gate conductive layer 103 may include a control gate surrounding the memory cell 112 and may extend laterally at the top of the memory stack layer 102 as the DSG line 118, extend laterally at the bottom of the memory stack layer 102 as the SSG line 119, or extend laterally between the DSG line 118 and the SSG line 119 as the word line 120.

[0297] As Figure 6 shown, the NAND memory string 111 includes a channel structure 105 extending vertically through the memory stack layer 102. In some embodiments, the channel structure 105 includes a channel hole filled with (one or more) semiconductor materials (e.g., as the semiconductor channel 106) and (one or more) dielectric materials (e.g., as the memory film 107). In some embodiments, the semiconductor channel 106 includes silicon, for example, polysilicon. In some embodiments, the memory film 107 is a composite dielectric layer including a tunneling layer 108, a storage layer 109 (also referred to as a "charge trapping / storage layer"), and a blocking layer 1010. The channel structure 105 may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel 106, the tunneling layer 108, the storage layer 109, and the blocking layer 1010 are radially arranged in this order from the center of the cylinder toward the outer surface of the cylinder. The tunneling layer 108 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 109 may include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer 1010 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film 107 may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0298] According to some embodiments, as Figure 6 shown, wells 414 (e.g., P-wells and / or N-wells) are formed in the substrate 101, and the source extreme of the NAND memory string 111 is in contact with the wells 414. For example, the source line 116 may be coupled to the wells 414 to apply an erase voltage to the wells 414 (i.e., the source of the NAND memory string 111) during an erase operation. In some embodiments, the NAND memory string 111 further includes a channel plug 416 at the drain extreme of the NAND memory string 111. It should be understood that although in Figure 6Although not shown in the figure, additional components that can form the memory cell array 110 include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, and the like.

[0299] Return reference Figure 5 , the peripheral circuit 130 can be coupled to the memory cell array 110 through bit lines 117, word lines 120, source lines 116, SSG lines 119, and DSG lines 118. The peripheral circuit 130 can include any suitable analog, digital, and mixed-signal circuits for facilitating the operation of the memory cell array 110 by applying voltage signals and / or current signals to each target memory cell 112 and sensing voltage signals and / or current signals from each target memory cell 112 via the bit lines 117, word lines 120, source lines 116, SSG lines 119, and DSG lines 118.

[0300] The peripheral circuit 130 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 7 Some exemplary peripheral circuits 130 are shown. The peripheral circuit 130 includes a page buffer / sense amplifier 504, a column decoder / bit line (BL) driver 506, a row decoder / word line (WL) driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuits not shown in the figure may also be included. Figure 7 Additional peripheral circuits not shown in the figure.

[0301] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 110 and program (write) data to the memory cell array 110 according to control signals from the control logic unit 512. In one example, the page buffer / sense amplifier 504 can store a page of programming data (write data) to be programmed into a page 130 of the memory cell array 110. In another example, the page buffer / sense amplifier 504 can perform a programming verification operation to ensure that the data has been correctly programmed into the memory cells 112 coupled to the selected word line 120. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 117 representing the data bits stored in the memory cell 112 and amplify the small voltage swing to an identifiable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic unit 512 and select one or more NAND memory strings 111 by applying bit line voltages generated from the voltage generator 510.

[0302] The row decoder / word line driver 508 can be configured to be controlled by the control logic unit 512, and to select / deselect the blocks 115 of the memory cell array 110 and to select / deselect the word lines 120 of the blocks 115. The row decoder / word line driver 508 can also be configured to drive the word lines 120 using the word line voltage (V WL ) generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the SSG lines 119 and the DSG lines 118. As described in detail below, the row decoder / word line driver 508 is configured to perform an erase operation on the memory cells 112 coupled to the selected word line(s) 120. The voltage generator 510 can be configured to be controlled by the control logic unit 512, and to generate the word line voltage (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltage, and source line voltage to be supplied to the memory cell array 110.

[0303] The control logic unit 512 can be coupled to each of the peripheral circuits described above, and is configured to control the operation of each peripheral circuit. The register 514 can be coupled to the control logic unit 512, and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic unit 512, and acts as a control buffer to buffer the control commands received from a host (not shown) and relay them to the control logic unit 512, and to buffer the status information received from the control logic unit 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518, and acts as a data I / O interface and a data buffer to buffer data and relay it to or from the memory cell array 110.

[0304] It should be emphasized that the peripheral circuit 130 is configured to perform the programming verification operation provided by the embodiments of the present disclosure on the selected memory cell rows among multiple memory cell rows.

[0305] Figure 8 is a schematic diagram of a memory 200 shown according to an exemplary embodiment. Referring to Figure 8 as shown, the memory 200 includes:

[0306] A memory cell array 110, the memory cell array 110 including multiple memory cell rows;

[0307] Multiple word lines 120, the multiple word lines 120 being respectively coupled to the multiple memory cell rows; and

[0308] Peripheral circuit 230 is coupled to a plurality of word lines 120 and is configured to perform a programming operation on a selected memory cell row among a plurality of memory cell rows, the selected memory cell row being coupled to a selected word line. In order to perform the programming operation, the peripheral circuit 230 is configured to:

[0309] Apply a (i + 1)-th programming pulse to the memory cells to be programmed in the memory;

[0310] During the application of the (i + 1)-th programming pulse, according to the verification sub-results of the n-th state and the verification sub-results of the (n + k)-th state in the i-th verification result of the i-th programming verification operation, count the number of failed bits for the programming of the n-th state and count the number of successful bits for the programming of the (n + k)-th state in the i-th programming operation, to obtain an i-th counting result; wherein, the programming state range verified by the i-th programming verification operation is from the n-th state to the (n + k)-th state, i and n are positive integers, k is a natural number, and the (n + k)-th state is less than or equal to the highest programming state of the memory;

[0311] According to the i-th counting result, determine the programming state range to be verified by the (i + 1)-th programming verification operation;

[0312] According to the determined programming state range to be verified by the (i + 1)-th programming verification operation, perform the (i + 1)-th programming verification operation.

[0313] It should be emphasized that the peripheral circuit 230 is configured to perform the programming operation provided by the embodiment of the present disclosure on a selected memory cell row among a plurality of memory cell rows.

[0314] Exemplarily, the structure of the peripheral circuit 230 may be the same as the structure of the peripheral circuit 130.

[0315] Figure 9a is a schematic diagram of a memory system 300 shown according to an exemplary embodiment, Figure 9b is a schematic diagram of another memory system 300 shown according to an exemplary embodiment. Referring to Figure 9a and Figure 9b as shown, the memory system 300 includes:

[0316] One or more memories 100 or memories 200;

[0317] A memory controller 321 coupled to the memory 100 or the memory 200 and configured to control the memory 100 or the memory 200.

[0318] System 300 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein.

[0319] As Figure 9a shown, system 300 can include a host 310 and a storage subsystem 320. The storage subsystem 320 has one or more memories 100 or memories 200, and the storage subsystem further includes a memory controller 321. The host 310 can be a processor (e.g., a central processing unit (CPU)) of an electronic device or a system on a chip (SoC) (e.g., an application processor (AP)). The host 310 can be configured to send data to the memory 100 or the memory 200. Alternatively, the host 310 can be configured to receive data from the memory 100 or the memory 200.

[0320] The memory 100 or the memory 200 can be any memory device disclosed in the present disclosure. The memory 100 or the memory 200 (e.g., a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device)) can have a reduced leakage current from a driving transistor (e.g., a string driver) coupled to an unselected word line during an erase operation, which allows for further scaling down of the driving transistor.

[0321] According to some embodiments, the memory controller 321 is further coupled to the host 310. The memory controller 321 can manage the data stored in the memory 100 or the memory 200 and communicate with the host 310.

[0322] In some embodiments, the memory controller 321 is designed to operate in a low-duty-cycle environment, such as a Secure Digital (SD) card, a CompactFlash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0323] In some embodiments, the memory controller 321 is designed to operate in a high-duty-cycle environment, such as a solid-state drive (SSD) or an embedded multimedia card (eMMC). The SSD or eMMC is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., and enterprise storage arrays.

[0324] The memory controller 321 may be configured to control the operations of the memory 100 or the memory 200, such as read, erase, and program operations. The memory controller 321 may also be configured to manage various functions regarding data stored in or to be stored in the memory 100 or the memory 200, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 321 is further configured to process an error correction code (ECC) regarding data read from or written to the memory 100 or the memory 200.

[0325] The memory controller 321 may also perform any other suitable functions, such as formatting the memory 100 or the memory 200. The memory controller 321 may communicate with an external device (e.g., the host 310) according to a specific communication protocol. For example, the memory controller 321 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0326] The memory controller 321 and one or more memories 100 or 200 may be integrated into various types of storage devices, such as being included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 100 may be implemented and packaged into different types of terminal electronic products.

[0327] In one example as shown in Figure 10a the memory controller 321 and a single memory 100 may be integrated into a memory card 400. The memory card 400 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a SmartMedia (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 400 may also include a memory card connector 410 that couples the memory card 400 to a host (e.g., Figure 9a the host 310 in

[0328] In one example as shown in Figure 10bIn another example shown in the figure, the memory controller 321 and the plurality of memories 100 may be integrated into a solid state drive (SSD) 500. The solid state drive 500 may also include a solid state drive connector 510 that couples the solid state drive 500 to a host (e.g., Figure 9a the host 310 in ). In some embodiments, the storage capacity and / or operating speed of the solid state drive 500 is greater than the storage capacity and / or operating speed of the memory card 400.

[0329] It can be understood that the memory controller 321 may execute the programming verification method or the programming method provided in any embodiment of the present disclosure.

[0330] The description of the above memory device embodiments is similar to the description of the above method embodiments, and has beneficial effects similar to those of the method embodiments. For the technical details not disclosed in the memory device embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure for understanding.

[0331] It should be understood that the "some embodiments" mentioned throughout the specification mean that the specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, the "in some embodiments" or "in other embodiments" that appear throughout the specification do not necessarily refer to the same embodiments. In addition, these specific features, structures or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present disclosure, the order numbers of the above processes do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0332] It should be noted that in this article, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "including a..." does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0333] In several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces. The indirect coupling or communication connection of devices or units can be electrical, mechanical, or other forms.

[0334] The units described above as separate components may or may not be physically separated. The components shown as units may or may not be physical units; they can be located in one place or distributed to multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0335] In addition, each functional unit in the embodiments of the present disclosure can be all integrated in a processing unit, or each unit can be separately used as a unit, or two or more units can be integrated in one unit; the above-mentioned integrated units can be implemented in the form of hardware, or in the form of a combination of hardware and software functional units.

[0336] The above is only the implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A programming verification method for a memory, characterized in that, it includes: Obtaining the i-th verification result of the i-th programming verification operation; wherein, the programming state range verified by the i-th programming verification operation is from the n-th state to the (n + k)-th state, i and n are positive integers, k is an integer greater than 1, and the (n + k)-th state is less than or equal to the highest programming state of the memory; Determining the programming state range to be verified by the (i + 1)-th programming verification operation according to the verification sub-result of the n-th state and the verification sub-result of the (n + k)-th state in the i-th verification result; Performing the (i + 1)-th programming verification operation according to the determined programming state range to be verified by the (i + 1)-th programming verification operation.

2. The programming verification method according to claim 1, characterized in that, The step of determining the programming state range to be verified by the (i + 1)-th programming verification operation according to the verification sub-result of the n-th state and the verification sub-result of the (n + k)-th state in the i-th verification result includes: Determining the lowest programming state to be verified by the (i + 1)-th programming verification operation according to the verification sub-result of the n-th state in the i-th verification result; Determining the highest programming state to be verified by the (i + 1)-th programming verification operation according to the verification sub-result of the (n + k)-th state in the i-th verification result.

3. The programming verification method according to claim 2, characterized in that, The verification sub-result of the n-th state in the i-th verification result includes: the i-th statistical data of the n-th state, which is used to count the number of failed bits for programming the n-th state; The step of determining the lowest programming state to be verified by the (i + 1)-th programming verification operation according to the verification sub-result of the n-th state in the i-th verification result includes: Determining the number of failed bits for programming the n-th state according to the i-th statistical data of the n-th state; When the number of failed bits for programming the n-th state is less than the first preset value, determining that the lowest programming state to be verified by the (i + 1)-th programming verification operation is the (n + 1)-th state; When the number of failed bits for programming the n-th state is greater than or equal to the first preset value, determining that the lowest programming state to be verified by the (i + 1)-th programming verification operation is the n-th state; Or, When the ratio of the number of failed bits for programming the n-th state to the number of bits with the target state being the n-th state is less than the first preset ratio, determining that the lowest programming state to be verified by the (i + 1)-th programming verification operation is the (n + 1)-th state; When the ratio of the number of failed bits for programming the n-th state to the number of bits with the target state being the n-th state is greater than or equal to the first preset ratio, determining that the lowest programming state to be verified by the (i + 1)-th programming verification operation is the n-th state.

4. The programming verification method according to claim 3, characterized in that, The programming verification method further includes: Obtaining the number of cycles of the storage unit to be programmed; Determining the value range of the first preset value or the value range of the first preset ratio according to the number of cycles.

5. The programming verification method according to claim 3, characterized in that, The value range of the first preset value is within the range allowed by the error correction code error correction mechanism for the memory.

6. The programming verification method according to claim 2, wherein, the verification sub-result of the (n + k)-th state in the i-th verification result includes: the i-th statistical data of the (n + k)-th state, which is used to count the number of successfully programmed bits for the (n + k)-th state; the determining of the highest programming state to be verified in the (i + 1)-th programming verification operation according to the verification sub-result of the (n + k)-th state in the i-th verification result includes: determining the number of successfully programmed bits for the (n + k)-th state according to the i-th statistical data of the (n + k)-th state; when the number of successfully programmed bits for the (n + k)-th state is greater than a second preset value and the (n + k)-th state is less than the highest programming state of the memory, determining that the highest programming state to be verified in the (i + 1)-th programming verification operation is the (n + k + 1)-th state; when the number of successfully programmed bits for the (n + k)-th state is less than or equal to the second preset value, determining that the highest programming state to be verified in the (i + 1)-th programming verification operation is the (n + k)-th state; or, when the ratio of the number of successfully programmed bits for the (n + k)-th state to the number of bits with the target state being the (n + k)-th state is greater than a second preset ratio, determining that the highest programming state to be verified in the (i + 1)-th programming verification operation is the (n + k + 1)-th state; when the ratio of the number of successfully programmed bits for the (n + k)-th state to the number of bits with the target state being the (n + k)-th state is less than or equal to the second preset ratio, determining that the highest programming state to be verified in the (i + 1)-th programming verification operation is the (n + k)-th state.

7. The programming verification method according to claim 6, wherein, the programming verification method further includes: obtaining the step size and / or the programming voltage slope of the incremental step pulse programming; determining the value range of the second preset value or the second preset ratio according to the step size and / or the programming voltage slope; wherein, the programming verification method is applied to the incremental step pulse programming method; or, obtaining the number of cycles of the storage unit to be programmed; determining the value range of the second preset value or the value range of the second preset ratio according to the number of cycles.

8. The method according to claim 6, wherein, the value range of the second preset ratio is from 2% to 3%.

9. The programming verification method according to claim 1, wherein, the determining of the programming state range to be verified in the (i + 1)-th programming verification operation according to the verification sub-result of the n-th state and the verification sub-result of the (n + k)-th state in the i-th verification result includes: respectively sampling the verification sub-result of the n-th state and the verification sub-result of the (n + k)-th state in the i-th verification result to obtain the i-th sampling statistical data of the n-th state and the i-th sampling statistical data of the (n + k)-th state; determining the lowest programming state to be verified in the (i + 1)-th programming verification operation according to the i-th sampling statistical data of the n-th state; determining the highest programming state to be verified in the (i + 1)-th programming verification operation according to the i-th sampling statistical data of the (n + k)-th state.

10. A programming method for a memory, wherein, comprising: Apply the (i + 1)-th programming pulse to the memory storage unit to be programmed; During the application of the (i + 1)-th programming pulse, according to the verification sub-results of the n-th state and the verification sub-results of the (n + k)-th state in the i-th programming verification operation, count the number of failed bits for programming the n-th state in the i-th programming operation and count the number of successful bits for programming the (n + k)-th state to obtain the i-th counting result; wherein, the programming state range verified by the i-th programming verification operation is from the n-th state to the (n + k)-th state, i and n are positive integers, k is an integer greater than 1, and the (n + k)-th state is less than or equal to the highest programming state of the memory; According to the i-th counting result, determine the programming state range that the (i + 1)-th programming verification operation needs to verify; According to the determined programming state range that the (i + 1)-th programming verification operation needs to verify, perform the (i + 1)-th programming verification operation.

11. The programming method according to claim 10, wherein, the i-th counting result includes: the number of failed bits for programming the n-th state in the i-th programming operation; The determining, according to the i-th counting result, the programming state range that the (i + 1)-th programming verification operation needs to verify includes: When the number of failed bits for programming the n-th state is less than the first preset value, determine that the lowest programming state that the (i + 1)-th programming verification operation needs to verify is the (n + 1)-th state; When the number of failed bits for programming the n-th state is greater than or equal to the first preset value, determine that the lowest programming state that the (i + 1)-th programming verification operation needs to verify is the n-th state; Or, When the ratio of the number of failed bits for programming the n-th state to the number of bits with the target state being the n-th state is less than the first preset ratio, determine that the lowest programming state that the (i + 1)-th programming verification operation needs to verify is the (n + 1)-th state; When the ratio of the number of failed bits for programming the n-th state to the number of bits with the target state being the n-th state is greater than or equal to the first preset ratio, determine that the lowest programming state that the (i + 1)-th programming verification operation needs to verify is the n-th state.

12. The programming method according to claim 10, wherein, the i-th counting result includes: the number of successful bits for programming the (n + k)-th state in the i-th programming operation; The determining, according to the i-th counting result, the programming state range that the (i + 1)-th programming verification operation needs to verify includes: When the number of successful bits for programming the (n + k)-th state is greater than the second preset value and the (n + k)-th state is less than the highest programming state of the memory, determine that the highest programming state that the (i + 1)-th programming verification operation needs to verify is the (n + k + 1)-th state; When the number of successful bits for programming the (n + k)-th state is less than or equal to the second preset value, determine that the highest programming state that the (i + 1)-th programming verification operation needs to verify is the (n + k)-th state; Or, When the ratio of the number of successful bits for programming the (n + k)-th state to the number of bits with the target state being the (n + k)-th state is greater than the second preset ratio, determine that the highest programming state that the (i + 1)-th programming verification operation needs to verify is the (n + k + 1)-th state; When the ratio of the number of successfully programmed bits in programming the (n + k)-th state to the number of bits whose target state is the (n + k)-th state is less than or equal to the second preset ratio, determine that the highest programmed state to be verified in the (i + 1)-th programming verification operation is the (n + k)-th state.

13. The programming method according to claim 10, wherein, the step of counting the number of failed bits in programming the n-th state and counting the number of successfully programmed bits in programming the (n + k)-th state in the i-th programming operation according to the verification sub-results of the n-th state and the verification sub-results of the (n + k)-th state in the i-th verification result of the i-th programming verification operation to obtain the i-th counting result includes: sampling the verification sub-results of the n-th state and the verification sub-results of the (n + k)-th state in the i-th verification result respectively to obtain the i-th sampling sample data of the n-th state and the i-th sampling sample data of the (n + k)-th state; counting the number of failed bits in programming the n-th state and counting the number of successfully programmed bits in programming the (n + k)-th state in the i-th programming operation according to the i-th sampling sample data of the n-th state and the i-th sampling sample data of the (n + k)-th state to obtain the i-th counting result.

14. A memory, wherein, it includes: a memory cell array including a plurality of memory cell rows; a plurality of word lines respectively coupled to the plurality of memory cell rows; and a peripheral circuit coupled to the plurality of word lines and configured to perform a programming verification operation on a selected memory cell row among the plurality of memory cell rows, the selected memory cell row being coupled to a selected word line, wherein, to perform the programming verification operation, the peripheral circuit is configured to: obtain the i-th verification result of the i-th programming verification operation; wherein, the range of programmed states verified in the i-th programming verification operation is from the n-th state to the (n + k)-th state, i and n are positive integers, k is an integer greater than 1, and the (n + k)-th state is less than or equal to the highest programmed state of the memory; determine the range of programmed states to be verified in the (i + 1)-th programming verification operation according to the verification sub-results of the n-th state and the verification sub-results of the (n + k)-th state in the i-th verification result; perform the (i + 1)-th programming verification operation according to the determined range of programmed states to be verified in the (i + 1)-th programming verification operation.

15. A memory, wherein, it includes: a memory cell array including a plurality of memory cell rows; a plurality of word lines respectively coupled to the plurality of memory cell rows; and a peripheral circuit coupled to the plurality of word lines and configured to perform a programming operation on a selected memory cell row among the plurality of memory cell rows, the selected memory cell row being coupled to a selected word line, wherein, to perform the programming operation, the peripheral circuit is configured to: apply an (i + 1)-th programming pulse to the memory storage unit to be programmed. During the application of the (i + 1)-th programming pulse, based on the verification sub-results of the n-th state and the verification sub-results of the (n + k)-th state in the i-th verification result of the i-th programming verification operation, count the number of failed bits in the programming of the n-th state and count the number of successful bits in the programming of the (n + k)-th state in the i-th programming operation to obtain the i-th counting result; wherein, the programming state range verified by the i-th programming verification operation is from the n-th state to the (n + k)-th state, i and n are positive integers, k is an integer greater than 1, and the (n + k)-th state is less than or equal to the highest programming state of the memory; Based on the i-th counting result, determine the programming state range to be verified by the (i + 1)-th programming verification operation; Execute the (i + 1)-th programming verification operation according to the determined programming state range to be verified by the (i + 1)-th programming verification operation.

16. A memory system, characterized in that, comprising: one or more memories as claimed in claim 14 or 15; a memory controller coupled to the memory and configured to control the memory.

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