Silicon carbide semiconductor device and method for manufacturing the same

Abstract

The silicon carbide semiconductor device (60) has an active region (51) and a terminal structure (53) arranged outside the active region (51). The silicon carbide semiconductor device (60) has a semiconductor substrate (1) of a second conductivity type, a first semiconductor layer (2) of a second conductivity type, a second semiconductor layer (4) of a first conductivity type, a first semiconductor region (6) of a second conductivity type, a second semiconductor region (7) of a first conductivity type, a gate insulating film (9), a gate electrode (10), a first electrode (11) and a second electrode (12). The end (T) of the second semiconductor layer (4) located at the terminal structure (53) has a smaller density of electrons or holes when power is applied, whichever is greater, of 1×10 15 / cm 3 the following.

Description

Technical Field

[0001] The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same. Background Art

[0002] In the past, single crystal silicon (Si) was used as a material for power semiconductor elements that control high withstand voltage and large current. There are several types of silicon power semiconductor elements, and the current situation is that they are used differently according to their uses. For example, PiN diodes (P-intrinsic-N diodes), bipolar transistors, and then IGBTs (Insulated Gate Bipolar Transistors) are so-called bipolar devices. Although these elements can achieve a large current density, they cannot switch at high speed. The use limit of bipolar transistors is a frequency of about several kHz, and the use limit of IGBTs is a frequency of about 20kHz. On the other hand, although power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: Insulated Gate Field Effect Transistors) cannot obtain large currents, they can be used at high speeds of up to several MHz. However, the market has a strong demand for power devices that have both large currents and high speeds, and is committed to improving silicon IGBTs, power MOSFETs, etc., and has now developed to a level that is almost close to the physical property limits of silicon materials.

[0003] In addition, material research from the perspective of power semiconductor elements has also been conducted. Silicon carbide (SiC), as the next generation of power semiconductor elements, is an element with low on-voltage, high-speed characteristics and excellent high-temperature characteristics, so it has received special attention recently. This is because SiC is a chemically very stable material with a band gap as wide as 3eV, and can be used as a semiconductor extremely stably even at high temperatures. In addition, this is because the maximum electric field strength of SiC is more than one order of magnitude greater than that of silicon. SiC is likely to exceed the material limit of silicon, so its future expansion in power semiconductor applications is highly anticipated. In particular, in ultra-high withstand voltage applications such as power and pulse power exceeding 10kV, PiN diodes as bipolar devices are also expected.

[0004] Fig. 20 It is a cross-sectional view showing the structure of a conventional bipolar semiconductor device having an n-type semiconductor substrate. Fig. 20 A PiN diode 161 is shown. Fig. 20The PiN diode 161 shown is formed using a silicon carbide substrate, which is formed by sequentially stacking an n-type buffer layer 102, an n-type drift layer 103, and a p-type anode layer 104 by epitaxial growth on the front surface of an n-type silicon carbide substrate 101. An anode electrode 105 is provided on the p-type anode layer 104, and a cathode electrode 106 is provided on the back surface.

[0005] The p-type anode layer 104 is provided only in the active region 151 through which current flows when the device is turned on, and is not provided in the edge termination region 152. The edge termination region 152 surrounds the active region 151 and has the function of alleviating the electric field concentration at the end of the active region 151 and maintaining a predetermined withstand voltage (withstand voltage). Withstand voltage refers to the limit voltage that does not cause malfunction or destruction of the element. In the edge termination region 152, for example, a withstand voltage structure is provided, and the withstand voltage structure includes a p-type termination region 107 whose impurity concentration is lower as it is arranged on the outside (side surface of the semiconductor substrate).

[0006] As described above, in general, in bipolar power semiconductor elements using silicon carbide semiconductors, there is a structure in which two or more n-type or p-type semiconductor layers are stacked on an n-type silicon carbide substrate. This is because it is difficult to improve the quality and reduce the resistance of a p-type silicon carbide substrate, while an n-type silicon carbide substrate can be more easily manufactured (produced). In addition, for the patterns of the electrode structure and / or MOS structure, mesa structure, terminal structure, etc. of the PiN diode and / or p-channel IGBT, n-GTO (Gate Turn-Off thyristor), the semiconductor layer on the substrate side is thick and the patterning of the substrate is difficult, so it is formed on the side opposite to the substrate side (this side is regarded as the front side).

[0007] Fig.21 Graph showing carrier distribution in a drift layer of a conventional bipolar semiconductor device having an n-type semiconductor substrate. Fig.21 In FIG. 1 , the horizontal axis represents the depth from the surface of the p-type anode layer 104, and the unit is μm. The vertical axis represents the density of electrons or holes, and the unit is cm -3 . Fig.21 The thin lines represent the density of electrons, and the thick lines represent the density of holes. At a depth of 0 μm to 100 μm, since the density of electrons and holes is equal, only the thick lines are drawn. Here, the density of electrons refers to the density of free electrons in each semiconductor layer.

[0008] like Fig.21 As shown, in a bipolar silicon carbide semiconductor element such as a PiN diode using an n-type semiconductor substrate, the density of holes is high in the p-type anode layer 104 on the surface of the drift layer composed of the n-type buffer layer 102, the n-type drift layer 103 and the p-type anode layer 104, and the hole current flows dominantly to the later described Fig. 22 In the direction of arrow B, the density of electrons is high in the n-type buffer layer 102, and the electron current is dominant in the later-described Fig. 22 Flows in the direction of arrow A.

[0009] Fig. 22 1 is a cross-sectional view showing carrier distribution in the drift layer of a conventional bipolar semiconductor device having an n-type semiconductor substrate. The hole density (hDensity) is shown as the carrier distribution. Since the hole mobility of silicon carbide is 1 / 10 of the electron mobility, the carrier density of the p-type anode layer 104 on the surface is greater than the carrier density near the n-type buffer layer 102 on the substrate side in terms of the carrier (electron and hole) density in the drift layer. As a result, conductivity modulation occurs below the p-type anode layer 104 on the surface, and the current is concentrated below the p-type anode layer 104 in the active region 151.

[0010] In addition, it is known that by forming an electrical degradation prevention layer that spatially separates the surface of the mesa from the pn junction interface on the mesa wall or the mesa wall and the periphery of the mesa, the occurrence of stacking faults and the expansion of their area are suppressed, and the increase in forward voltage is suppressed (see Patent Document 1 below). In addition, it is known that a buffer layer formed between an n-type SiC substrate and an n-type drift layer acts as a trap for holes from a p-type anode layer, thereby preventing minority carriers from reaching the substrate, thereby preventing an increase in forward voltage (see Patent Document 2 below).

[0011] Prior art literature

[0012] Patent Literature

[0013] Patent Document 1: Japanese Patent Application Publication No. 2007-165604

[0014] Patent Document 2: Japanese Patent Application Publication No. 2012-4318 Summary of the invention

[0015] Technical issues

[0016] Here, in the channel region, the mobility of electrons is greater than the mobility of holes, and it is expected that a low-resistance IGBT can be produced. Therefore, the development of n-channel IGBTs having a p-type semiconductor substrate has been advanced.

[0017] Fig.23 It is a cross-sectional view showing the structure of a conventional bipolar semiconductor device having a p-type semiconductor substrate. Fig.23 A PiN diode 161 is shown. Fig.23The PiN diode 161 shown is formed using a silicon carbide substrate, which is formed by sequentially stacking a p-type buffer layer 112, a p-type drift layer 113, and an n-type cathode layer 114 by epitaxial growth on the front surface of a p-type silicon carbide substrate 111. The n-type cathode layer 114 is provided only in the active region 151 through which current flows when the device is turned on, and is not provided in the edge termination region 152.

[0018] Fig.24 This is a cross-sectional view showing carrier distribution in the drift layer of a conventional bipolar semiconductor device having a p-type semiconductor substrate. The hole density (hDensity) is shown as carrier distribution. In the drift layer of a bipolar silicon carbide semiconductor device such as a p-channel IGBT using a p-type semiconductor substrate, the electron current is dominant in the vicinity of the p-type buffer layer 112 on the substrate side. Fig.24 In the n-type cathode layer 114 on the surface, the hole current flows in the direction of arrow C. Fig.24 Flows in the direction of arrow D.

[0019] Since the hole mobility of silicon carbide is 1 / 10 of the electron mobility, the carrier density (electrons and holes) in the drift layer is greater near the p-type buffer layer 112 on the substrate side than near the n-type cathode layer 114 on the surface. As a result, conductivity modulation also occurs between the n-type cathode layer 114 on the surface and the end of the edge terminal region 152 of the element, and a portion of the current ( Fig.24 The arrow D′) flows from the edge termination region 152 to the active region 151.

[0020] In bipolar semiconductor devices using silicon carbide semiconductors, there is a phenomenon of forward voltage increase, which increases the on-state voltage due to the conduction of electricity. This is caused by the fact that line defects such as basal plane dislocations in silicon carbide semiconductors expand into surface defects such as stacking faults due to the recombination energy of electrons and holes, and become high-resistance layers.

[0021] Due to the improvement of crystal growth technology in recent years, conductivity modulation is caused, and basal plane dislocations in the drift layer where recombination of electrons and holes occurs are almost not found. However, basal plane dislocations are sometimes introduced into the substrate and / or the surface of the element, or the end of the element due to processing, etc. In this case, in a bipolar silicon carbide semiconductor element using a p-type semiconductor substrate, carriers also exist between the surface of the element active region and the end of the element, and carrier recombination also occurs at the end of the element, resulting in an increase in forward voltage, which has the problem of reduced reliability of the semiconductor element.

[0022] The object of the present invention is to solve the problems caused by the above-mentioned prior art and to provide a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device, which are capable of reducing the recombination of carriers at the end of the element and suppressing the increase in forward voltage in a bipolar silicon carbide semiconductor element using a p-type semiconductor substrate.

[0023] Technical Solution

[0024] In order to solve the above problems and achieve the purpose of the present invention, the silicon carbide semiconductor device of the present invention has the following characteristics. The silicon carbide semiconductor device has an active region and a terminal structure portion, the active region is for current flow, the terminal structure portion is arranged outside the active region, and a voltage-resistant structure surrounding the active region is formed. A first semiconductor layer of the second conductivity type is provided on one main surface side of a semiconductor substrate of the second conductivity type. A second semiconductor layer of the first conductivity type is provided on the surface of the first semiconductor layer on the side opposite to the semiconductor substrate. A first semiconductor region of the second conductivity type is provided on the surface layer of the second semiconductor layer on the side opposite to the semiconductor substrate. A second semiconductor region of the first conductivity type having an impurity concentration higher than that of the second semiconductor layer is provided on the surface layer of the first semiconductor region on the side opposite to the semiconductor substrate. A gate insulating film is provided on the surface of the region of the first semiconductor region sandwiched by the second semiconductor layer and the second semiconductor region. A gate electrode is provided on the gate insulating film. A first electrode in contact with the first semiconductor region and the second semiconductor region is provided. A second electrode is provided on the other main surface side of the first semiconductor layer. The smaller density of electron density or hole density at the end of the second semiconductor layer located at the terminal structure portion when power is applied is 1×10 15 / cm 3 the following.

[0025] In addition, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the hole density at the end of the second semiconductor layer located at the terminal structure portion when power is applied is 1×10 15 / cm 3 the following.

[0026] Furthermore, in the silicon carbide semiconductor device of the present invention, in the above invention, a distance from the active region to an end portion of the terminal structure portion is 1.2 mm or more.

[0027] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, a distance from the active region to an end of the terminal structure portion in a direction perpendicular to an off angle of the semiconductor substrate is 1.2 mm or more.

[0028] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, a short lifetime region is provided between the active region and the end of the terminal structure portion.

[0029] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, a short lifetime region is provided between the active region and the end of the terminal structure portion in a direction perpendicular to the off angle of the semiconductor substrate.

[0030] In addition, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, a third semiconductor layer of the first conductivity type having an impurity concentration higher than the impurity concentration of the second semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer, and vanadium, titanium, boron or nitrogen is added to the third semiconductor layer in the terminal structure portion.

[0031] In addition, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the density of the nitrogen is 1×10 18 / cm 3 The density of boron is 1×10 17 / cm 3 The density of the above vanadium or titanium is 1×10 14 / cm 3 above.

[0032] Furthermore, in the silicon carbide semiconductor device of the present invention, in the above invention, the thickness of the third semiconductor layer is not less than 0.1 μm and not more than 2 μm.

[0033] In addition, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, a third semiconductor layer of the first conductivity type having an impurity concentration higher than the impurity concentration of the second semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer, and damage is provided in the crystal structure of the third semiconductor layer in the terminal structure portion.

[0034] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, nitrogen is added to the first semiconductor layer in the termination structure portion.

[0035] Furthermore, in the silicon carbide semiconductor device of the present invention, in the above invention, the semiconductor substrate and the second electrode are provided only in the active region.

[0036] Furthermore, in the silicon carbide semiconductor device of the present invention, in the above invention, the second electrode is provided only in the active region.

[0037] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the terminal structure portion is provided with an inclined terrace, and the inclined terrace reaches the first semiconductor layer from a surface of the second semiconductor layer on the side opposite to the semiconductor substrate.

[0038] Furthermore, the silicon carbide semiconductor device of the present invention, in the above invention, has a feature that no basal plane dislocation exists in a predetermined region from an end portion of the termination structure portion to the active region.

[0039] In order to solve the above problems and achieve the purpose of the present invention, the manufacturing method of the silicon carbide semiconductor device of the present invention has the following characteristics. A manufacturing method of a silicon carbide semiconductor device, the silicon carbide semiconductor device having: an active region for current flow; and a terminal structure, which is arranged outside the active region and forms a voltage-resistant structure surrounding the active region. First, a first step is performed to form a first semiconductor layer of a second conductivity type on a main surface side of a semiconductor substrate of a second conductivity type. Then a second step is performed to form a second semiconductor layer of a first conductivity type on the surface of the first semiconductor layer on the side opposite to the semiconductor substrate. Then a third step is performed to form a first semiconductor region of a second conductivity type on the surface layer of the second semiconductor layer on the side opposite to the semiconductor substrate. Then a fourth step is performed to form a second semiconductor region of a first conductivity type having an impurity concentration higher than that of the second semiconductor layer on the surface layer of the first semiconductor region on the side opposite to the semiconductor substrate. Then a fifth step is performed to form a gate insulating film on the surface of a region of the first semiconductor region sandwiched by the second semiconductor layer and the second semiconductor region. Then a sixth step is performed to form a gate electrode on the gate insulating film. Then, the seventh step is performed to form a first electrode in contact with the first semiconductor region and the second semiconductor region. Then, the eighth step is performed to form a second electrode on the other main surface side of the first semiconductor layer. The density of holes at the end of the terminal structure portion of the second semiconductor layer is formed to be 1×10 15 / cm 3 the following.

[0040] In addition, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above invention, after the above eighth step, a ninth step is further included for removing a predetermined area from the end of the above terminal structure portion to the above active region by dry etching.

[0041] According to the above invention, the carrier density at the end of the chip becomes the threshold value of stacking fault (SF) expansion 1×10 15 / cm 3As a result, when the semiconductor chip is energized, the expansion of stacking faults (SF) from the end of the chip can be suppressed. Therefore, the increase in forward voltage can be suppressed.

[0042] Effects of the Invention

[0043] According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention, it is possible to reduce recombination of carriers at the end of a bipolar silicon carbide semiconductor element using a p-type semiconductor substrate and suppress an increase in forward voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment.

[0045] Figure 2 It is a plan view showing the structure of the silicon carbide semiconductor device according to the first embodiment.

[0046] Figure 3 is a graph showing the distance dependence of carrier density from the active region.

[0047] Figure 4 This is a graph showing the characteristics of a conventional silicon carbide semiconductor device before and after power is applied.

[0048] Figure 5 This is a graph showing the characteristics of the silicon carbide semiconductor device according to the first embodiment before and after power is applied.

[0049] Figure 6 1 is a cross-sectional view showing a state of the silicon carbide semiconductor device according to the first embodiment during the manufacturing process.

[0050] Figure 7 This is a cross-sectional view showing a state of the silicon carbide semiconductor device according to the first embodiment during the manufacturing process (part 2).

[0051] Figure 8 This is a cross-sectional view showing a state of the silicon carbide semiconductor device according to the first embodiment during the manufacturing process (part 3).

[0052] Fig. 9 This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to a second embodiment.

[0053] Fig.10 This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to a third embodiment.

[0054] Fig.11 This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to a fourth embodiment.

[0055] Fig.12This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to a fifth embodiment.

[0056] Fig.13 This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to a sixth embodiment.

[0057] Fig.14 This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to a seventh embodiment.

[0058] Fig.15 This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to an eighth embodiment.

[0059] Fig.16 This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to a ninth embodiment.

[0060] Fig.17 This is a cross-sectional view showing another structure of the silicon carbide semiconductor device according to Embodiments 1 to 9 (Part 1).

[0061] Fig.18 This is a cross-sectional view showing another structure of the silicon carbide semiconductor device according to Embodiments 1 to 9 (Part 2).

[0062] Fig.19 This is a cross-sectional view showing another structure of the silicon carbide semiconductor device according to Embodiments 1 to 9 (Part 3).

[0063] Fig. 20 It is a cross-sectional view showing the structure of a conventional bipolar semiconductor device having an n-type semiconductor substrate.

[0064] Fig.21 This is a graph showing carrier distribution in a drift layer of a conventional bipolar semiconductor device having an n-type semiconductor substrate.

[0065] Fig. 22 This is a cross-sectional view showing carrier distribution in a drift layer of a conventional bipolar semiconductor device having an n-type semiconductor substrate.

[0066] Fig.23 It is a cross-sectional view showing the structure of a conventional bipolar semiconductor device having a p-type semiconductor substrate.

[0067] Fig.24 This is a cross-sectional view showing carrier distribution in a drift layer of a conventional bipolar semiconductor device having a p-type semiconductor substrate.

[0068] Explanation of symbols

[0069] 1 p-type silicon carbide substrate;

[0070] 2 p-type collector layer

[0071] 3 n-type field stop layer

[0072] 4 n-type drift layer

[0073] 5 n-type carrier accumulation layer

[0074] 6 p-type base region

[0075] 7n + Type emission area

[0076] 8 p + Type contact area

[0077] 9 Gate insulation film

[0078] 10. Gate electrode

[0079] 11. Emitting electrode

[0080] 12 Collector

[0081] 13 p-type termination region

[0082] 14 Low life span area

[0083] 15 Impurity Addition Area

[0084] 16 Anti-doping region

[0085] 17 inclined table

[0086] 18 JFET region

[0087] 20 p-type buffer layer

[0088] 21 p-type drift layer

[0089] 22 n-type cathode layer

[0090] 23 Cathode electrode

[0091] 24 Anode electrode

[0092] 25 n-type terminal region

[0093] 26 p-type field stop layer

[0094] 27 p-type carrier accumulation layer

[0095] 28 n-type base region

[0096] 29 p + Type Source Region

[0097] 30 n + Type contact area

[0098] 31 Source electrode

[0099] 32 Drain electrode

[0100] 34, 134 n-type buffer layer

[0101] 35 p-type gate layer

[0102] 51, 151 Active area

[0103] 52, 152 Edge terminal area

[0104] 53 Terminal structure

[0105] 60 n-channel IGBT

[0106] 61, 161 PiN diode

[0107] 62 MOSFET

[0108] 63 Thyristor

[0109] 101 n-type silicon carbide substrate

[0110] 102 n-type buffer layer

[0111] 103 n-type drift layer

[0112] 104 p-type anode layer

[0113] 105 Anode electrode

[0114] 106 cathode electrode

[0115] 107 p-type termination region

[0116] 111 p-type silicon carbide substrate

[0117] 112 p-type buffer layer

[0118] 113 p-type drift layer

[0119] 114 n-type cathode layer

[0120] 115 cathode electrode

[0121] 116 Anode electrode

[0122] 117 n-type terminal region DETAILED DESCRIPTION

[0123] The following is a detailed description of a preferred embodiment of a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device of the present invention with reference to the accompanying drawings. In this specification and the accompanying drawings, in the layer and / or region marked with n, it means that electrons are the majority carriers, and in the layer and / or region marked with p, it means that holes are the majority carriers. In addition, the "+" marked on n or p means that the impurity concentration is higher than that of the layer and / or region not marked with "+", and the "-" marked on n or p means that the impurity concentration is lower than that of the layer and / or region not marked with "-". In the case where the markings of n or p including "+" or "-" are the same, it means that the concentration is similar but not limited to the same concentration. It should be noted that in the description and drawings of the following embodiments, the same symbols are marked for the same structure, and repeated descriptions are omitted. In addition, in this specification, in the marking of the Miller index, "-" refers to a horizontal line marked on the index immediately following it, and a negative index is indicated by marking "-" before the index.

[0124] (Implementation Method 1)

[0125] As the silicon carbide semiconductor device of the present invention, an n-channel silicon carbide IGBT 60 will be described as an example. Figure 1 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment.

[0126] like Figure 1 As shown, the n-channel silicon carbide IGBT 60 is constructed using a silicon carbide substrate, which is formed by stacking a p-type collector layer (a first semiconductor layer of a second conductivity type) 2, an n-type field stop layer (a third semiconductor layer of a first conductivity type) 3, an n-type drift layer (a second semiconductor layer of a first conductivity type) 4, and an n-type carrier storage layer 5 in sequence on the front surface of a p-type silicon carbide substrate (a semiconductor substrate of a second conductivity type) 1. The n-type field stop layer 3 and the n-type carrier storage layer 5 may not be provided. A p-type base region (a first semiconductor region of a second conductivity type) 6 is selectively provided on the surface of the n-type carrier storage layer 5 (an n-type drift layer 4 when the n-type carrier storage layer 5 is not provided, hereinafter referred to as (4)).

[0127] The p-type silicon carbide substrate 1 is a silicon carbide single crystal substrate doped with, for example, aluminum (Al). The p-type collector layer 2 is a layer provided with an impurity concentration lower than that of the p-type silicon carbide substrate 1. The n-type field stop layer 3 is a layer provided with an impurity concentration higher than that of the n-type drift layer 4. Because the n-type field stop layer 3 can suppress the depletion layer extending from the high-resistance n-type drift layer 4 to the n-type field stop layer 3 when turned off, even if the n-type drift layer 4 is thinned, the depletion layer can be prevented from reaching the p-type collector layer 2. The n-type field stop layer 3 can be a single layer or a multi-layer. In the case where the n-type field stop layer 3 is a multi-layer, the multi-layer can be formed with the same set film thickness and set carrier concentration, or can be stacked with different set film thicknesses and set carrier concentrations.

[0128] Here, the IGBT has an advantage of low on-resistance due to the conductivity modulation effect. In the past, in order to efficiently obtain low on-resistance due to the conductivity modulation effect, as described above, an n-type carrier accumulation layer 5 having the same conductivity type as the n-type drift layer 4 and having an impurity concentration higher than that of the n-type drift layer 4 was provided on the front side of the substrate inside the n-type drift layer 4. Since the n-type carrier accumulation layer 5 becomes a barrier for minority carriers and improves the accumulation effect of minority carriers, the current density between the collector and the emitter increases, and the conductivity modulation effect becomes higher.

[0129] On the front side of the silicon carbide substrate (the side of the p-type base region 6 described later), a MOS gate (insulated gate composed of metal-oxide film-semiconductor) structure (element structure) is provided. The MOS gate includes a p-type base region 6, an n + Type emitter region (second semiconductor region of the first conductivity type) 7, p + The p-type base region 6 is formed by ion implantation and is provided on the n-type carrier storage layer 5 (4). The p-type base region 6 is provided with an n-type JFET region (Junction Field Effect Transistor) 18 that penetrates the p-type base region 6 in the depth direction and reaches the n-type carrier storage layer 5 (4). The impurity concentration of the JFET region 18 is higher than the impurity concentration of the n-type drift layer 4. The JFET region 18 has the function of reducing the JFET resistance and reducing the on-resistance. In the portion of the p-type base region 6 other than the JFET region 18, a channel is formed along the gate electrode 9.

[0130] In addition, n-type base region 6 is selectively provided inside the p-type base region 6. + Inside the p-type base region 6, a p-type emitter region 7 may also be selectively provided. + Type contact area 8. In this case, n + The type emission area 7 can be set larger than p +The contact area is 8 deep. + Type 7 emitter and p + The type contact region 8 is configured separately from the JFET region 18. + The contact area 8 is arranged at a ratio of n + The type emitter region 7 is further away from the JFET region 18 and is + The p-type base region 6 is in contact with the JFET region 18 and the n-type emitter region 7. + On the surface of the portion sandwiched by the type emitter region 7, from the surface of the JFET region 18 to the n + A gate insulating film 9 is provided on the surface of the type emitter region 7. A gate electrode 10 is provided on the surface of the gate insulating film 9. An interlayer insulating film (not shown) is provided so as to cover the gate electrode 10.

[0131] The interlayer insulating film is provided on the front surface of the silicon carbide substrate. A contact hole penetrating the interlayer insulating film in the depth direction exposes n + Type 7 emitter and p + The emitter electrode 11 is connected to the n type contact region 8 via a contact hole penetrating the interlayer insulating film in the depth direction. + Type 7 emitter and p + The gate electrode 10 is electrically insulated from the gate insulating film 9 and the interlayer insulating film. + In the case of the type contact region 8, the emitter electrode 11 is connected to the n + The p-type emitter region 7 is in contact with the p-type base region 6. A collector electrode 12 is provided on the back side of the silicon carbide substrate (ie, the back side of the p-type silicon carbide substrate 1).

[0132] In such a silicon carbide IGBT, when a positive voltage is applied to the gate electrode 10, an inversion layer is formed near the interface of the p-type base region 6 (p-type silicon carbide channel layer) in contact with the gate insulating film 9, and the IGBT becomes turned on. If the electrons flowing out of the channel reach the n-type drift layer 4 from the n-type carrier storage layer 5 between the p-type base region 6, the PNP transistor formed by the p-type base region 6, the n-type drift layer 4 and the p-type collector layer 2 is turned on, and holes are injected from the p-type collector layer 2 into the n-type drift layer 4 to reduce resistance through conduction modulation.

[0133] On the other hand, when reverse current is applied, the depletion layer spreads from the p-type base region 6 to the n-type drift layer 4 via the n-type carrier storage layer 5. At this time, if the electric field is concentrated on the corners or sides of the p-type base region 6, avalanche occurs and the withstand voltage decreases.

[0134] Figure 2 FIG. 1 is a top view showing the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 2 As shown in FIG. 5 , the edge termination region 52 is configured to surround the active region 51. Figure 1 As shown, the p-type base region 6 and the JFET region 18 are provided only in the active region 51 through which current flows when conducting, and are not provided in the edge termination region 52. The termination structure 53 surrounds the active region 51 and is a region extending from the active region 51 to the end T of the p-type silicon carbide substrate (semiconductor chip) 1.

[0135] Figure 3 is a graph showing the distance dependence of carrier density from the active region. Figure 3 In FIG. 5 , the horizontal axis represents the distance from the active region 51 in mm. The vertical axis represents the hole density as the carrier density in cm. -3 .in addition, Figure 3 The current density is 100 A / cm when the carrier lifetime of holes is set to 10 μs. 2 , simulation results at room temperature (around 25℃).

[0136] Here, if the carrier density exceeds the threshold value 1×10 15 / cm 3 , the stacking fault (SF) from the end T of the n-type drift layer 4 will expand. Figure 3 As shown in FIG. 1 , the carrier density at the time of power on in the region 1.2 mm or less from the end T of the chip becomes 1×10 15 / cm 3 The same result is obtained when the carrier density is the electron density. Therefore, in the silicon carbide semiconductor device of the first embodiment, the distance from the active region 51 to the end T of the chip is set to be 1.2 mm or more, so that the smaller density of the electron density or the hole density at the end T of the chip during power-on is 1×10 15 / cm 3 Therefore, when the semiconductor chip is powered on, the expansion of the stacking fault (SF) from the end T of the chip can be suppressed. In addition, in order to cope with high temperature and large current, it is preferred to set the distance from the active region 51 to the end T of the chip to be 1.5 mm or more, and more preferably 2.0 mm or more.

[0137] In order to epitaxially grow the semiconductor layer on the substrate, the silicon carbide substrate is provided with an off angle of 4 degrees. The direction in which the off angle is set (offset direction) is the <11-20> direction. Here, because the expansion direction of the stacking fault is the <1-100> direction perpendicular to the off direction, the distance from the active region 51 to the end T of the chip needs to be at least 1.2 mm in the <1-100> direction.

[0138] Figure 4 This is a graph showing the characteristics of a conventional silicon carbide semiconductor device before and after power is applied. Figure 5Graphs showing the characteristics of the silicon carbide semiconductor device of Embodiment 1 before and after power is applied. Figure 4 and Figure 5 In the figure, the solid line indicates the characteristics before power is applied, and the dotted line indicates the characteristics after power is applied. Figure 4 and Figure 5 In the figure, the horizontal axis represents the forward voltage in V, and the vertical axis represents the forward current density in A / cm 2 Here, in the conventional silicon carbide semiconductor device, the distance from the active region 151 to the end T of the chip is 0.5 mm, and in the silicon carbide semiconductor device of Embodiment 1, the distance from the active region 51 to the end T of the chip (from the active region 51 to the end of the terminal structure portion 53) is greater than 1.2 mm.

[0139] like Figure 4 As shown in FIG. 1 , in conventional silicon carbide semiconductor devices, carrier recombination occurs at the end of the element, resulting in an increase in forward voltage. Figure 4 In the figure, before and after power-on, at a forward current density of 100A / cm 2 When , the increase ΔVf of the forward voltage is 5 V or more, and the forward voltage increases significantly. On the other hand, in the silicon carbide semiconductor device of the first embodiment, since the carrier density at the end of the element is 1×10 15 / cm 3 Therefore, at a forward current density of 100A / cm 2 When the increase ΔVf of the forward voltage is less than 0.01 V, the forward voltage hardly changes, and the increase of the forward voltage can be suppressed.

[0140] (Method for Manufacturing Silicon Carbide Semiconductor Device According to Embodiment 1)

[0141] The method for manufacturing a silicon carbide semiconductor device according to the first embodiment will be described by taking as an example a case where an n-channel IGBT is produced (manufactured) using silicon carbide as a semiconductor material. Figures 6 to 8 This is a cross-sectional view showing a state of the silicon carbide semiconductor device according to the first embodiment during the manufacturing process.

[0142] First, a p-type silicon carbide substrate 1 made of p-type silicon carbide is prepared. Then, a p-type collector layer 2, an n-type field stop layer 3, and an n-type drift layer 4 are stacked by epitaxial growth on the first main surface (front surface) of the p-type silicon carbide substrate 1. The state thus far is described in Figure 6 .

[0143] Then, an n-type carrier storage layer 5 is stacked by epitaxial growth on the surface of the n-type drift layer 4. Then, an ion implantation mask is formed on the surface of the n-type carrier storage layer 5, which opens a portion corresponding to the formation region of the p-type base region 6. Then, p-type impurity ions are implanted using the ion implantation mask as a mask, thereby forming the p-type base region 6. The region of the n-type carrier storage layer 5 sandwiched by the p-type base region 6 becomes the JFET region 18. Then, the ion implantation mask is removed.

[0144] Next, p-type impurity ions are implanted and selectively formed on the surface layer of the p-type base region 6. + Then, an n-type contact region 8 is selectively formed on the surface layer of the p-type base region 6 by photolithography and n-type impurity ion implantation. + Then, a p-type termination region 13 is selectively formed in the surface layer of the p-type base region 6 in the edge termination region 52 by photolithography and p-type impurity ion implantation.

[0145] To form the above n + Type 7 emitter and p + The order of ion implantation of the type contact region 8 can be changed in various ways. Then, activation annealing (heat treatment) is performed to activate the diffusion regions formed by the ion implantation. The state thus far is recorded in Figure 7 .

[0146] Then, the front side (p + The surface on the side of the type base region 6 is thermally oxidized to form a gate insulating film 9. Then, on the gate insulating film 9, for example, a polysilicon (poly-Si) layer is formed as a gate electrode 10 and patterned.

[0147] Next, an interlayer insulating film (not shown) is formed so as to cover the gate electrode 10, patterned, and then heat treated (reflowed). When the interlayer insulating film is patterned, a contact hole is formed and the gate insulating film 9 exposed in the contact hole is removed to expose the gate electrode 10. + Type 7 emitter and p + Type contact area 8. The state so far is recorded in Figure 8 .

[0148] Next, the emitter electrode 11 is formed by, for example, sputtering to fill the contact hole. Then, the collector electrode 12 is formed on the back side of the p-type silicon carbide substrate 1. Then, an emitter wiring (not shown) is formed on the emitter electrode 11. Then, a protective film (not shown) is formed on the front side of the silicon carbide substrate. Then, the silicon carbide substrate is cut (diced) into chips to complete the process. Figure 1 The IGBT shown.

[0149] As described above, according to the first embodiment, the carrier density at the end of the chip becomes the threshold value 1×10 15 / cm 3 As a result, when the semiconductor chip is energized, the expansion of stacking faults (SF) from the end of the chip can be suppressed, thereby suppressing an increase in forward voltage.

[0150] (Implementation Method 2)

[0151] Fig. 9 : is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 2. In Embodiment 2, a low lifetime region 14 is provided in the entire height (thickness) direction of the p-type silicon carbide substrate (semiconductor chip) 1 in the region from the active region 51 to the end T (between the active region 51 and the end of the terminal structure portion 53). In the low lifetime region 14, damage is provided in the crystal structure due to electron beam irradiation. By providing the low lifetime region 14, the lifetime of carriers at the end T of the chip can be shortened, the injection of carriers (holes) into the end of the chip can be suppressed, and the expansion of the stacking fault (SF) from the end of the chip can be suppressed. In addition, because the expansion direction of the stacking fault is the <1-100> direction perpendicular to the deviation direction, it is necessary to provide the low lifetime region 14 in the region from the active region 51 to the end T of the chip at least in the <1-100> direction.

[0152] In addition, the silicon carbide semiconductor device of embodiment 2 can form a short lifetime region 14 by irradiating the region from the active region 51 to the end T of the p-type silicon carbide substrate 1 with electron beams from the front side of the chip, for example, after forming the element structure and before cutting the p-type silicon carbide substrate 1.

[0153] As described above, according to Embodiment 2, a low lifetime region is provided from the active region to the end. Thus, the lifetime of carriers at the end of the chip can be shortened, the injection of carriers (holes) into the end of the chip can be suppressed, and the expansion of stacking faults (SF) from the end of the chip can be suppressed. Therefore, the increase in forward voltage can be suppressed.

[0154] (Implementation 3)

[0155] Fig.10 1 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 3. In Embodiment 3, an impurity added region 15 is provided in an n-type region (n-type field stop layer 3 or n-type drift layer 4) in contact with a p-type region (p-type silicon carbide substrate 1 and p-type collector layer 2) on the side of the p-type silicon carbide substrate 1 between the active region 51 and the end of the terminal structure portion 53. Fig.10An example is shown in which an impurity addition region 15 is provided in the n-type field stop layer 3. The impurity addition region 15 is formed by adding vanadium (V), titanium (Ti), boron (B), nitrogen (N), etc. By providing the impurity addition region 15, the lifetime of carriers at the end T of the chip can be shortened by crystal damage introduced by ion implantation, recombination centers introduced by doping with different types of impurities, or promotion of Auger recombination, and the injection of carriers (holes) from the p-type collector layer 2 to the end of the chip can be suppressed, and the expansion of the stacking fault (SF) from the end of the chip can be suppressed. In addition, the nitrogen density is preferably 1×10 18 / cm 3 Above, the density of boron is 1×10 17 / cm 3 Above, the density of vanadium or titanium is 1×10 14 / cm 3 above.

[0156] In addition, the silicon carbide semiconductor device of the third embodiment is formed by, for example, adding vanadium (V), titanium (Ti), boron (B), nitrogen (N), etc. to the n-type region by ion implantation after forming an n-type region in contact with the p-type region on the side of the p-type silicon carbide substrate 1. The thickness of the n-type region is preferably not less than 0.1 μm and not more than 2 μm.

[0157] As described above, according to Embodiment 3, an impurity addition region is provided in the n-type region that contacts the p-type region on the p-type silicon carbide substrate side from the active region to the end. As a result, the lifetime of carriers at the end of the chip can be shortened, the injection of carriers (holes) from the p-type collector layer 2 to the end of the chip can be suppressed, and the expansion of stacking faults (SF) from the end of the chip can be suppressed. Therefore, the increase in forward voltage can be suppressed.

[0158] (Implementation 4)

[0159] Fig.11 1 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 4. In Embodiment 4, an anti-doped region 16 is provided in a p-type region (p-type silicon carbide substrate 1 and p-type collector layer 2) in contact with an n-type region (n-type field stop layer 3 or n-type drift layer 4) on the p-type silicon carbide substrate 1 side between the active region 51 and the end of the terminal structure portion 53. Fig.11 The embodiment in which the p-type collector layer 2 is provided with an anti-doping region 16 is shown. The anti-doping region 16 is formed by anti-doping the p-type region with impurities that become donors and is a high resistance region. By providing the anti-doping region 16, it is possible to suppress the injection of carriers (holes) from the p-type collector layer 2 into the end T of the chip, and it is possible to suppress the expansion of the stacking fault (SF) from the end of the chip.

[0160] The silicon carbide semiconductor device of the fourth embodiment is formed by, for example, forming a p-type region in contact with an n-type region on the p-type silicon carbide substrate 1 side and then adding a donor impurity such as nitrogen (N) to the p-type region by ion implantation.

[0161] As described above, according to Embodiment 4, a high-resistance counter-doping region is provided in the p-type region that contacts the n-type region on the p-type silicon carbide substrate side from the active region to the end. As a result, it is possible to suppress the injection of carriers (holes) from the p-type collector layer 2 to the end of the chip, and to suppress the expansion of the stacking fault (SF) from the end of the chip. Therefore, it is possible to suppress the increase in forward voltage.

[0162] (Implementation method 5)

[0163] Fig.12 1 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 5. Embodiment 5 removes the p-type silicon carbide substrate 1 and the collector electrode 12 in a region S between the active region 51 and the end of the terminal structure portion 53. Thus, since current does not flow in the removed region S when conducting, it is possible to suppress the injection of carriers (holes) from the p-type silicon carbide substrate 1 into the end T of the chip, and to suppress the expansion of the stacking fault (SF) from the end of the chip.

[0164] The silicon carbide semiconductor device of the fifth embodiment can be formed by, for example, removing the p-type silicon carbide substrate 1 and the collector electrode 12 from the active region 51 to the end T before dicing the p-type silicon carbide substrate 1 after forming the device structure.

[0165] As described above, according to Embodiment 5, the p-type silicon carbide substrate and the collector are removed in the region from the active region to the end. Thus, in this region, the injection of carriers (holes) from the p-type silicon carbide substrate to the end of the chip can be suppressed, and the expansion of the stacking fault (SF) from the end of the chip can be suppressed. Therefore, the increase in forward voltage can be suppressed.

[0166] (Implementation 6)

[0167] Fig.13 1 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 6. In Embodiment 6, the collector 12 is removed in a region S' between the active region 51 and the end of the terminal structure portion 53. As a result, since no current flows in the region S' when it is turned on, it is possible to suppress the injection of carriers (holes) from the p-type silicon carbide substrate 1 into the end T of the chip, and to suppress the expansion of the stacking fault (SF) from the end of the chip.

[0168] In addition, the silicon carbide semiconductor device of the sixth embodiment can be formed, for example, by forming the collector electrode 12 only in the active region 51 when forming the collector electrode 12 on the back surface of the p-type silicon carbide substrate 1. In addition, it can also be formed by removing the collector electrode 12 in the region S' from the active region 51 to the end T before cutting the semiconductor substrate (semiconductor chip) 1 after the element structure is formed.

[0169] In addition, when the p-type silicon carbide substrate 1 is formed as a p-type region by epitaxial growth, ion implantation is performed to form an ohmic contact at the location where the collector 12 is formed. By performing this ion implantation only in the active region 51, even if the collector 12 is formed on the entire surface, the same effect as the embodiment in which the collector 12 is removed from the region S' from the active region 51 to the end T can be obtained.

[0170] As described above, according to Embodiment 6, the collector is removed in the region from the active region to the end. Thus, in this region, the injection of carriers (holes) from the p-type silicon carbide substrate to the end of the chip can be suppressed, and the expansion of the stacking fault (SF) from the end of the chip can be suppressed. Therefore, the increase in forward voltage can be suppressed.

[0171] (Implementation 7)

[0172] Fig.14 1 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 7. In Embodiment 7, a bevel mesa 17 is provided that penetrates the n-type carrier storage layer 5 (4) and reaches the p-type collector layer 2 from the active region 51 to the end of the terminal structure portion 53. This prevents a line defect such as a basal plane dislocation from expanding from the end T of the silicon carbide semiconductor device to a surface defect such as a stacking fault and reaching the active region 51.

[0173] The silicon carbide semiconductor device of the seventh embodiment can also be formed by, for example, forming the n-type carrier storage layer 5 ( 4 ) and then forming the sloped terrace 17 by dry etching.

[0174] As described above, according to Embodiment 7, an inclined terrace is provided between the active region and the end. This can prevent a line defect such as a basal plane dislocation from expanding from the end of the silicon carbide semiconductor device to a surface defect such as a stacking fault and reaching the active region. Therefore, an increase in forward voltage can be suppressed.

[0175] (Implementation 8)

[0176] Fig.152 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 8. In Embodiment 8, a predetermined region S″ between the active region 51 and the end of the terminal structure portion 53 is removed as a whole in the height (thickness) direction of the p-type silicon carbide substrate 1, for example, 10 to 30 μm. Thus, the basal plane dislocation existing at the end T is removed, and it is possible to prevent a line defect such as a basal plane dislocation from expanding into a surface defect such as a stacking fault and reaching the active region 51.

[0177] In addition, the silicon carbide semiconductor device of embodiment 8 can be formed by, for example, removing a predetermined area S" between the active area 51 and the end of the terminal structure part 53 of the p-type silicon carbide substrate 1 by dry etching after cutting the semiconductor substrate (semiconductor chip) 1 after the element structure is formed.

[0178] As described above, according to Embodiment 8, the predetermined region from the end to the active region is removed in its entirety in the height (thickness) direction of the p-type silicon carbide substrate. Thus, the basal plane dislocation present at the end is removed, and it is possible to prevent line defects such as basal plane dislocations from expanding into surface defects such as stacking faults and reaching the active region. Therefore, it is possible to suppress the increase in forward voltage.

[0179] (Implementation method 9)

[0180] Fig.16 1 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 9. In Embodiment 9, a low lifetime region 14 is provided in the entire height (thickness) direction of the p-type silicon carbide substrate 1 between the active region 51 and the end of the terminal structure portion 53. In the low lifetime region 14, the proton (H + ) and the crystal structure is damaged. By providing the low lifetime region 14, the carrier lifetime at the end T of the chip can be shortened, the injection of carriers (holes) into the end of the chip can be suppressed, and the expansion of the stacking fault (SF) from the end of the chip can be suppressed.

[0181] In addition, the silicon carbide semiconductor device of the ninth embodiment can be cut from the side surface ( Fig.16 The region from the active region 51 to the end T of the p-type silicon carbide substrate 1 is irradiated with protons (H + ), thereby forming a low lifetime region 14.

[0182] As described above, according to Embodiment 9, a low lifetime region is provided from the active region to the end. Thus, the lifetime of carriers at the end of the chip can be shortened, the injection of carriers (holes) into the end of the chip can be suppressed, and the expansion of stacking faults (SF) from the end of the chip can be suppressed. Therefore, the increase in forward voltage can be suppressed.

[0183] In the above, in the first to ninth embodiments, the n-channel silicon carbide IGBT 60 is described as an example, but the first to ninth embodiments can also be applied to silicon carbide semiconductor devices of other structures. Figures 17 to 19 It is a cross-sectional view showing another structure of the silicon carbide semiconductor device according to Embodiments 1 to 9.

[0184] Fig.17 An example of a PiN diode 61 is shown. Fig.17 As shown, the PiN diode 61 is formed using a silicon carbide substrate formed by sequentially stacking a p-type buffer layer 20, a p-type drift layer 21, and an n-type cathode layer 22 by epitaxial growth on the front surface of a p-type silicon carbide substrate 1. A cathode electrode 23 is provided on the n-type cathode layer 22, and an anode 24 is provided on the back surface.

[0185] The n-type cathode layer 22 is provided only in the active region through which current flows when turned on, and is not provided in the terminal structure portion 53. The terminal structure portion 53 is provided with a voltage-resistant structure including an n-type terminal region 25 whose impurity concentration decreases toward the outer side (side surface of the semiconductor substrate).

[0186] Fig.18 An example of MOSFET 62 is shown. Fig.18 As shown, the MOSFET 62 is formed by using a silicon carbide substrate in which a p-type field stop layer 26, a p-type drift layer 21, and a p-type carrier storage layer 27 are sequentially stacked by epitaxial growth on the front surface of a p-type semiconductor substrate 1. An n-type base region 28 is provided inside the n-type carrier storage layer 27. In addition, a p-type base region 28 is provided inside the n-type base region 28. + Type source region 29 and n + type contact region 30. Inside the n-type base region 28, a p-type JFET region 18 is provided which penetrates the n-type base region 28 in the depth direction and reaches the p-type carrier storage layer 27.

[0187] In addition, from the n-type base region 28 to the p + A gate insulating film 9 is provided on the surface of the source region 29. A gate electrode 10 is provided on the surface of the gate insulating film 9, and an interlayer insulating film (not shown) is provided in a manner covering the gate electrode 10. + Type source region 29 and n + A source electrode 31 is in contact with the type contact region 30, a source wiring (not shown) is provided on the source electrode 31, and a protective film (not shown) is provided on the source wiring. In addition, a drain electrode 32 is provided on the back surface.

[0188] The n-type base region 28 and the JFET region 18 are provided only in the active region through which current flows when the device is turned on, and are not provided in the terminal structure portion 53. The terminal structure portion 53 is provided with a withstand voltage structure including, for example, an n-type terminal region 25 whose impurity concentration decreases as it is arranged outside (on the side surface of the semiconductor substrate).

[0189] Fig.19 An example of a thyristor 63 is shown. In addition, the same is true for a GTO and / or a GCT (Gate Commutated Turn-off thyristor). Fig.19 As shown, the thyristor 63 is formed by using a silicon carbide substrate formed by sequentially stacking a p-type buffer layer 20, an n-type buffer layer 34, an n-type drift layer 4, a p-type gate layer 35, and an n-type cathode layer 22 on the front surface of a p-type semiconductor substrate 1 by epitaxial growth. + The p+ type contact region 8 is formed through a contact hole penetrating the n type cathode layer 22 in the depth direction to expose the p+ type contact region 8.

[0190] In addition, in p + A gate electrode 10 is provided on the surface of the n-type contact region 8, and an interlayer insulating film (not shown) is provided to cover the gate electrode 10. A cathode electrode 23 in contact with the n-type cathode layer is provided on the front side of the silicon carbide substrate. In addition, an anode electrode 24 is provided on the back side.

[0191] The p-type gate layer 35 is provided only in the active region for flowing current when turned on, and is not provided in the terminal structure portion 53. The terminal structure portion 53 is provided with a voltage-resistant structure including, for example, a p-type terminal region 13 whose impurity concentration decreases toward the outer side (side surface of the semiconductor substrate).

[0192] As described above, the present invention can be variously modified without departing from the gist of the present invention. In the above-mentioned embodiments, for example, the size and / or impurity concentration of each part can be variously set according to the required specifications.

[0193] Industrial Applicability

[0194] As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, and / or ignition devices for automobiles.

Claims

1. A silicon carbide semiconductor device, characterized in that: The silicon carbide semiconductor device comprises an active region and a terminal structure portion, wherein the active region is for current to flow, the terminal structure portion is arranged outside the active region and comprises an edge terminal region surrounding the active region and a region surrounding the edge terminal region and extending to an end of a chip, and the terminal structure portion is formed with a withstand voltage structure, The silicon carbide semiconductor device comprises: a semiconductor substrate of a second conductivity type; A first semiconductor layer of a second conductivity type, which is provided on one main surface side of the semiconductor substrate; A second semiconductor layer of a first conductivity type, which is disposed on a surface of the first semiconductor layer on a side opposite to the semiconductor substrate; A first semiconductor region of a second conductivity type is provided on a surface layer of the second semiconductor layer on a side opposite to the semiconductor substrate; A second semiconductor region of the first conductivity type, which is disposed in a surface layer of the first semiconductor region on a side opposite to the semiconductor substrate and has an impurity concentration higher than that of the second semiconductor layer; a gate insulating film disposed on a surface of a region of the first semiconductor region sandwiched between the second semiconductor layer and the second semiconductor region; a gate electrode disposed on the gate insulating film; a first electrode in contact with the first semiconductor region and the second semiconductor region; as well as a second electrode provided on the other main surface side of the semiconductor substrate, The first semiconductor layer and the second semiconductor layer are arranged to extend from the active region to the end of the chip of the terminal structure part. The smaller density of the electron density or the hole density of the second semiconductor layer at the end of the chip of the terminal structure when power is applied is 1×10 15 / cm 3 the following.

2. The silicon carbide semiconductor device according to claim 1, wherein: The first conductivity type is n-type, the second conductivity type is p-type, and the hole density of the second semiconductor layer at the end of the chip of the terminal structure portion when powered on is 1×10 15 / cm 3 the following.

3. The silicon carbide semiconductor device according to claim 1 or 2, characterized in that: The distance from the active region to the end of the chip of the terminal structure is 1.2 mm or more.

4. The silicon carbide semiconductor device according to claim 1 or 2, characterized in that: In a direction perpendicular to the off angle of the semiconductor substrate, a distance from the active region to an end of the chip of the termination structure portion is 1.2 mm or more.

5. The silicon carbide semiconductor device according to claim 1, wherein: A short lifespan region is provided between the active region and the end of the chip of the terminal structure portion.

6. The silicon carbide semiconductor device according to claim 1, wherein: A short lifespan region is provided between the active region and the end of the chip of the terminal structure in a direction perpendicular to the off angle of the semiconductor substrate.

7. The silicon carbide semiconductor device according to claim 1, wherein: A third semiconductor layer of the first conductivity type having an impurity concentration higher than that of the second semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer. The third semiconductor layer in the termination structure portion is added with vanadium, titanium, boron or nitrogen.

8. The silicon carbide semiconductor device according to claim 7, wherein: The density of nitrogen is 1×10 18 / cm 3 The density of boron is 1×10 17 / cm 3 The density of the vanadium or titanium is 1×10 14 / cm 3 above.

9. The silicon carbide semiconductor device according to claim 8, wherein: The third semiconductor layer has a thickness of 0.1 μm or more and 2 μm or less.

10. The silicon carbide semiconductor device according to claim 1, wherein: A third semiconductor layer of the first conductivity type having an impurity concentration higher than that of the second semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer. Damage is provided in a crystal structure of the third semiconductor layer in the termination structure portion.

11. The silicon carbide semiconductor device according to claim 1, wherein: Nitrogen is added to the first semiconductor layer in the termination structure portion.

12. The silicon carbide semiconductor device according to claim 1, wherein: The semiconductor substrate and the second electrode are only disposed in the active region.

13. The silicon carbide semiconductor device according to claim 1, wherein: The second electrode is only disposed in the active area.

14. The silicon carbide semiconductor device according to claim 1, wherein: The terminal structure portion is provided with an inclined terrace, and the inclined terrace reaches the first semiconductor layer from a surface of the second semiconductor layer on the side opposite to the semiconductor substrate.

15. The silicon carbide semiconductor device according to claim 1, wherein: There is no basal plane dislocation in a predetermined region from the end of the chip to the active region of the termination structure.

16. The silicon carbide semiconductor device according to claim 1, wherein: Damage is provided in the crystal structure of a predetermined region from the end of the chip to the active region of the terminal structure portion.

17. A method for manufacturing a silicon carbide semiconductor device, characterized in that: The silicon carbide semiconductor device comprises an active region and a terminal structure portion, wherein the active region is for current to flow, the terminal structure portion is arranged outside the active region and comprises an edge terminal region surrounding the active region and a region surrounding the edge terminal region and extending to an end of a chip, and the terminal structure portion is formed with a withstand voltage structure, The method for manufacturing a silicon semiconductor device comprises: In a first step, a first semiconductor layer of a second conductivity type is formed on one main surface side of a semiconductor substrate of a second conductivity type; A second step of forming a second semiconductor layer of the first conductivity type on a surface of the first semiconductor layer on the side opposite to the semiconductor substrate; A third step is to form a first semiconductor region of a second conductivity type on a surface layer of the second semiconductor layer on the side opposite to the semiconductor substrate; In a fourth step, a second semiconductor region of the first conductivity type having an impurity concentration higher than that of the second semiconductor layer is formed in a surface layer of the first semiconductor region on the side opposite to the semiconductor substrate; A fifth step is to form a gate insulating film on a surface of a region of the first semiconductor region sandwiched between the second semiconductor layer and the second semiconductor region; The sixth step is to form a gate electrode on the gate insulating film; In a seventh step, a first electrode is formed in contact with the first semiconductor region and the second semiconductor region; and In an eighth step, a second electrode is formed on the other main surface side of the semiconductor substrate. The first semiconductor layer and the second semiconductor layer are arranged to extend from the active region to the end of the chip of the terminal structure part. The density of holes in the second semiconductor layer at the end of the chip of the terminal structure is formed to be 1×10 15 / cm 3 the following.

18. The method for manufacturing a silicon carbide semiconductor device according to claim 17, wherein: After the eighth step, a ninth step of removing a predetermined region from the end of the chip to the active region of the terminal structure by dry etching is further included.

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