Semiconductor device

Abstract

The present invention relates to highly integrated memory cells and semiconductor devices having the same. According to one embodiment, a semiconductor device includes a plurality of memory cells vertically stacked on a base substrate, each of the plurality of memory cells including a bit line oriented vertically from the base substrate, a capacitor horizontally spaced apart from the bit line, an active layer horizontally oriented between the bit line and the capacitor, a word line on at least one of an upper surface and a lower surface of the active layer and horizontally extending in a direction crossing the active layer, and a cap layer between the word line and the bit line and including at least one of a low-k material and an air gap.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0083557, filed on July 7, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to semiconductor devices, and more specifically, to memory cells and semiconductor devices including said memory cells. Background Technology

[0004] In recent years, memory cells have been continuously shrinking in order to increase the net die size of memory devices.

[0005] Although shrinking memory cells should reduce parasitic capacitance (Cb) and increase capacitance, it is difficult to increase the net die size due to the structural limitations of memory cells. Summary of the Invention

[0006] According to embodiments of the present disclosure, a highly integrated memory cell and a semiconductor device having said memory cell are provided.

[0007] According to one embodiment, a semiconductor device includes: a plurality of memory cells vertically stacked on a base substrate, each of the plurality of memory cells including: a bit line oriented vertically from the base substrate; a capacitor horizontally spaced apart from the bit line; an active layer horizontally oriented between the bit line and the capacitor; a word line located on at least one of an upper surface and a lower surface of the active layer and extending horizontally in a direction intersecting the active layer; and a capping layer located between the word line and the bit line, and including at least one of a low-k material and an air gap.

[0008] According to one embodiment, a semiconductor device includes: a base substrate including peripheral circuit units; bit lines oriented perpendicularly from the base substrate; word lines spaced apart from the bit lines and the base substrate and extending horizontally in a direction intersecting the bit lines; and a capping layer including an air gap between the word lines and the bit lines.

[0009] According to one embodiment, a semiconductor device includes: a bit line extending perpendicularly from a base substrate in a first direction; a capacitor spaced apart from the bit line along a second direction parallel to the base substrate; an active layer extending horizontally along a second direction from the bit line to the capacitor; a word line located between the bit line and the capacitor, and extending horizontally in a third direction to contact the active layer; and a capping layer located between the word line and the bit line, wherein the capping layer includes a low-k material and an air gap.

[0010] The capping layer may include a first silicon oxide layer and a second silicon oxide layer surrounding the first silicon oxide layer. The first silicon oxide layer may include carbon-doped silicon oxide with air gaps embedded, and the second silicon oxide layer may include undoped silicon oxide.

[0011] The capping layer may include a silicon oxide layer and a silicon nitride layer surrounding the silicon oxide layer. The silicon oxide layer may include carbon-doped silicon oxide with air gaps embedded, and the silicon nitride layer may include undoped silicon nitride.

[0012] According to embodiments of this disclosure, the overlay layer is formed between the bit line and the word line. Therefore, sufficient physical distance can be ensured between the bit line and the word line.

[0013] According to embodiments of this disclosure, lateral migration of the seam can be suppressed by using an inner lining material. Therefore, perforation of the lettering can be prevented.

[0014] According to embodiments of this disclosure, a low-k material and an air gap are formed between the bit line and the word line. Therefore, the parasitic capacitance between the bit line and the word line can be reduced. Attached Figure Description

[0015] Figure 1A This is a perspective view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 1B It is along Figure 1A The layout is cut off by line A-A'.

[0017] Figure 1C It is along Figure 1B The cross-sectional view taken by line B-B'.

[0018] Figure 1D This is a schematic 3D view of the CPL overlay layer.

[0019] Figure 2 This is a layout diagram of a semiconductor device according to an embodiment of the present disclosure.

[0020] Figure 3This is a view illustrating a semiconductor device according to an embodiment of the present disclosure;

[0021] Figure 4A and Figure 4B This is a view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0022] Figure 5A and Figure 5B This is a view illustrating a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0023] In the following description, embodiments of the present disclosure are illustrated with reference to schematic cross-sectional views, plan views, or block diagrams. Views may be altered or modified according to manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure are not limited to the specific types shown and illustrated herein, but may include changes or modifications resulting from manufacturing processes. For example, areas or regions shown in the figures may be schematically illustrated, and their shapes are provided merely as examples and not to limit the category or scope of the present disclosure.

[0024] According to various embodiments of this disclosure, parasitic capacitance can be reduced while increasing memory cell density by vertically stacking memory cells.

[0025] Figure 1A This is a perspective view illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 1B It is along Figure 1A The layout is cut off by line A-A'. Figure 1C It is along Figure 1B The cross-sectional view taken by line B-B'. Figure 1D This is a schematic 3D view of the CPL overlay layer.

[0026] See Figures 1A to 1DThe semiconductor device 100 may include a base substrate LS, and a memory cell array MCA may be formed on the base substrate LS. The memory cell array MCA may be oriented perpendicular to the base substrate LS. The base substrate LS may include a plane, and the memory cell array MCA may be positioned perpendicular to the plane of the base substrate LS. The memory cell array MCA may be oriented vertically upward from the base substrate LS along a first direction D1. The memory cell array MCA may include a three-dimensional array of memory cells MC. The memory cell array MCA may include a plurality of memory cells MC1, MC2, MC3, and MC4. For example, the memory cell array MCA may include: a first memory cell MC1, a second memory cell MC2, a third memory cell MC3, and a fourth memory cell MC4. The first memory cell MC1 and the third memory cell MC3 may be oriented vertically along the first direction D1. The second memory cell MC2 and the fourth memory cell MC4 may be oriented vertically along the first direction D1. The first memory cell MC1 and the second memory cell MC2 may be oriented horizontally along a third direction D3. The third memory cell MC3 and the fourth memory cell MC4 may be oriented horizontally along a third direction D3. Each memory cell MC1, MC2, MC3, and MC4 of the memory cell array MCA may include a bit line BL, a transistor TR, a capacitor CAP, and a board line PL. The transistor TR and capacitor CAP may be horizontally oriented along a second direction D2. Each memory cell MC1, MC2, MC3, and MC4 may further include a word line WL, and the word line WL may extend along a third direction D3. In each memory cell MC1, MC2, MC3, and MC4, the bit line BL, transistor TR, capacitor CAP, and board line PL may be horizontally positioned along the second direction D2. The memory cell array MCA may include a dynamic random access memory (DRAM) memory cell array. Alternatively, the memory cell array MCA may include: phase-change random access memory (PCRAM), redox-based random access memory (RERAM), or magnetoresistive random access memory (MRAM), and the capacitor CAP may be replaced by another memory element.

[0027] The base substrate LS may include materials suitable for semiconductor processing. The base substrate LS may include at least one or more of conductive, dielectric, and semiconductor materials. Various materials may be formed on the base substrate LS. The base substrate LS may include a semiconductor substrate. The base substrate LS may be formed of a silicon-containing material. The base substrate LS may include: silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multilayer structures thereof. The base substrate LS may include other semiconductor materials, such as germanium. The base substrate LS may include a composite semiconductor substrate, such as a group III / V semiconductor substrate, such as GaAs. The base substrate LS may include a silicon-on-insulator (SOI) substrate.

[0028] According to one embodiment, the base substrate LS may include a peripheral circuitry unit (PC). The PC may include multiple control circuits for controlling the memory cell array (MCA). At least one or more control circuits of the PC may include N-channel transistors, P-channel transistors, complementary metal-oxide-semiconductor (CMOS) circuitry, or combinations thereof. The PC may include, for example, address decoder circuitry, read circuitry, and write circuitry. The PC may also include, for example, planar channel transistors, recessed channel transistors, buried gate transistors, or fin-channel transistors (FinFETs).

[0029] For example, at least one control circuit of the peripheral circuit cell PC may be electrically connected to the bit line BL. The peripheral circuit cell PC may include a sense amplifier (SA), and the sense amplifier (SA) may be electrically connected to the bit line BL. Although not shown, a multilayer metal line MLM may be located between the memory cell array MCA and the base substrate LS, and the peripheral circuit cell PC and the bit line BL may be interconnected via the multilayer metal line MLM.

[0030] A memory cell array (MCA) may include a stack of at least two or more memory cells (MCs). The at least two or more memory cells (MCs) may be stacked perpendicularly on a base substrate (LS) along a first direction (D1).

[0031] Bit line BL can extend from base substrate LS along a first direction D1. The plane of base substrate LS can extend along a second direction D2 and a third direction D3. The first direction D1 can be perpendicular to the second direction D2. Bit line BL can be oriented perpendicularly from base substrate LS. The bottom of bit line BL can be connected to base substrate LS. The bottom of bit line BL can be connected to peripheral circuit cell PC. Bit line BL can be columnar. Bit line BL can be represented as a vertically oriented bit line or a columnar bit line. Bit line BL can include conductive materials. Bit line BL can include: silicon-based materials, metal-based materials, or combinations thereof. Bit line BL can include: polysilicon, metal, metal nitride, metal silicide, or combinations thereof. Memory cells MC vertically stacked on the same line can share a bit line BL. Bit line BL can include: polysilicon, titanium nitride, tungsten, or combinations thereof. For example, bit line BL can include polysilicon or titanium nitride (TiN) doped with N-type impurities. Bit line BL can include a stack of titanium nitride and tungsten (TiN / W). Bit line BL can also include ohmic contacts, such as ohmic contacts made of metal silicides.

[0032] The transistor TR can be arranged along a second direction D2 parallel to the surface of the base substrate LS. The transistor TR can be arranged horizontally. For example, the transistor TR can be horizontally located between the bit line BL and the capacitor CAP. The transistor TR can be located at a higher level than the base substrate LS, and the transistor and the base substrate LS can be spaced apart from each other.

[0033] The transistor TR may include an active layer ACT, a gate dielectric layer GD, and a word line WL. The word line WL may extend along a third direction D3, and the active layer ACT may extend along a second direction D2. The third direction D3 may be perpendicular to the first direction D1. The active layer ACT may be arranged horizontally from the bit line BL. The active layer ACT may be oriented to be parallel to a plane of the base substrate LS.

[0034] The word line WL can have a dual word line structure, with the active layer ACT interposed between them. A gate dielectric layer GD can be formed on each of the upper and lower surfaces of the active layer ACT. The word line WL can include an upper word line WLU and a lower word line WLL. The upper word line WLU can be disposed on the upper surface of the active layer ACT, and the lower word line WLL can be disposed below the lower surface of the active layer ACT. The gate dielectric layer GD can be formed between the upper word line WLU and the upper surface of the active layer ACT (also referred to as the upper gate dielectric layer). The gate dielectric layer GD can also be formed between the lower word line WLL and the lower surface of the active layer ACT (also referred to as the lower gate dielectric layer). The upper word line WLU and the lower word line WLL can be spaced apart from the active layer ACT by their respective upper and lower gate dielectric layers GD.

[0035] The gate dielectric layer (GD) may include: silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The gate dielectric layer (GD) may include, for example, SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, or HfSiON.

[0036] Word lines (WL) can include metals, metal mixtures, metal alloys, or semiconductor materials. Word lines (WL) can include titanium nitride, tungsten, polycrystalline silicon, or combinations thereof. For example, a word line (WL) can include a TiN / W stack of titanium nitride and tungsten. Word lines (WL) can include N-type work function materials or P-type work function materials. N-type work function materials can have a low work function of 4.5 or less, while P-type work function materials can have a high work function of 4.5 or more.

[0037] The upper word line WLU and the lower word line WLL can have different potentials. For example, in each memory cell MC1, MC2, MC3, and MC4, a word line drive voltage can be applied to the upper word line WLU, and a ground voltage can be applied to the lower word line WLL. The lower word line WLL can block interference between the upper word line WLU and memory cells MC placed perpendicularly along the first direction D1. Alternatively, a ground voltage can be applied to the upper word line WLU, and a word line drive voltage can be applied to the lower word line WLL. According to one embodiment, the upper word line WLU and the lower word line WLL can be connected to each other via a contact plug (not shown).

[0038] The active layer ACT may include a semiconductor material such as polycrystalline silicon. The active layer ACT may include multiple impurity regions. The impurity regions may include a first source / drain region SD1 and a second source / drain region SD2. The active layer ACT may include: polycrystalline silicon, undoped polycrystalline silicon, amorphous silicon, or oxide semiconductor materials. The first source / drain region SD1 and the second source / drain region SD2 may be doped with N-type or P-type impurities. The first source / drain region SD1 and the second source / drain region SD2 may be doped with impurities of the same conductivity type. The first source / drain region SD1 and the second source / drain region SD2 may be doped with N-type impurities. The first source / drain region SD1 and the second source / drain region SD2 may be doped with P-type impurities. The first source / drain region SD1 and the second source / drain region SD2 may include impurities selected from at least one of arsenic (As), phosphorus (P), boron (P), indium (In), and combinations thereof. The bit line BL can be electrically connected to a first edge of the active layer ACT, and the capacitor CAP can be electrically connected to a second edge of the active layer ACT. The first edge of the active layer ACT can be provided by a first source / drain region SD1, and the second edge of the active layer ACT can be provided by a second source / drain region SD2. The active layer ACT may also include a channel CH. The channel CH can be defined between the first source / drain region SD1 and the second source / drain region SD2. The upper word line WLU and the lower word line WLL can face each other, and the channel CH is disposed between them.

[0039] The active layer ACT adjacent along the third direction D3 can be supported by a vertical support VSPT. The vertical support VSPT can extend vertically along the first direction D1. The vertical support VSPT can be located between memory cells MC adjacent along the third direction D3. The vertical support VSPT may include a separation layer to separate the active layers ACT placed along the third direction D3 from each other.

[0040] The horizontal support LSPT can be located between adjacent memory cells MC along the first direction D1. The horizontal support LSPT can be located between the lower word line WLL of the upper memory cell MC and the upper word line WLU of the lower memory cell MC. The horizontal support LSPT may not be located between adjacent capacitors CAP along the first direction D1.

[0041] The vertical support VSPT and the horizontal support LSPT can comprise the same material. The vertical support VSPT and the horizontal support LSPT can also comprise an insulating material, such as silicon oxide.

[0042] The capacitor CAP can be positioned horizontally with the transistor TR. The capacitor CAP can extend horizontally from the active layer ACT along a second direction D2. The capacitor CAP can include: a storage node SN, a dielectric layer DE, and a plate node PN. The storage node SN, dielectric layer DE, and plate node PN can be arranged horizontally along the second direction D2. The storage node SN can have a horizontally oriented cylindrical shape, and the plate node PN is shaped to extend above the inner and outer walls of the cylinder of the storage node SN. The dielectric layer DE can surround the plate node PN and be located inside the storage node SN. The plate node ON can be connected to the board line PL. In other words, each plate node can extend from the board line PL inside the corresponding storage node SN, wherein the dielectric layer DE separates the plate node PN from the inner surface of the storage node SN. The storage node SN can be electrically connected to a second source / drain region SD2. A portion of the second source / drain region SD2 can extend into the interior of the storage node SN.

[0043] The capacitor CAP can include a metal-insulator-metal (MIM) capacitor. The storage node SN and the plate node PN can include metal-based materials. The dielectric layer DE can include: silicon oxide, silicon nitride, high-k materials, or combinations thereof. High-k materials can have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) can have a dielectric constant of approximately 3.9, and the dielectric layer DE can include high-k materials with a dielectric constant of 4 or greater. High-k materials can have a dielectric constant of approximately 20 or greater. High-k materials can include: hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). Alternatively, the dielectric layer DE can be formed from a composite layer comprising two or more layers of the aforementioned high-k materials.

[0044] The dielectric layer DE can be formed of a zirconium-based oxide (Zr-based oxide). The dielectric layer DE can have a stacked structure including zirconium oxide (ZrO2). The stacked structure including zirconium oxide (ZrO2) can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack can have a stacked structure in which alumina Al2O3 is stacked on zirconium oxide ZrO2. The ZAZ stack can have a stacked structure in which zirconium oxide ZrO2, alumina Al2O3, and zirconium oxide ZrO2 are stacked sequentially. The ZA stack and the ZAZ stack can be represented as zirconium-based layers (ZrO2-based layers). According to another embodiment, the dielectric layer DE can be formed of a hafnium-based oxide. The dielectric layer DE can have a stacked structure including hafnium oxide (HfO2). Layered structures including hafnium oxide (HfO2) can include: HA (HfO2 / Al2O3) stacks or HAH (HfO2 / Al2O3 / HfO2) stacks. HA stacks can have a layered structure in which alumina (Al2O3) is stacked on top of hafnium oxide (HfO2). HAH stacks can have a layered structure in which hafnium oxide (HfO2), alumina (Al2O3), and hafnium oxide (HfO2) are sequentially stacked. HA stacks and HAH stacks can be represented as hafnium oxide-based layers (HfO2-based layers). In ZA stacks, ZAZ stacks, HA stacks, and HAH stacks, alumina (Al2O3) can have a larger band gap than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Alumina (Al2O3) can have a lower dielectric constant than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE can include a stack of high-k materials and high-bandgap materials, where the high-bandgap material has a larger bandgap than the high-k material. In addition to alumina (Al2O3), the dielectric layer DE can also include silicon oxide (SiO2) as a high-bandgap material. Because the dielectric layer DE includes a high-bandgap material, leakage current can be suppressed. The high-bandgap material can be very thin. The high-bandgap material can have a thickness of about 10 nm or less. The high-bandgap material can be thinner than the high-k material. According to another embodiment, the dielectric layer DE can include a stacked structure in which high-k materials and high-bandgap materials are alternately stacked. For example, the dielectric layer DE can include ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3), or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2). In the above-mentioned stacked structures, the alumina (Al2O3) can be very thin.

[0045] According to another embodiment, the dielectric layer DE may include a stacked structure, a layered structure, or a hybrid structure comprising zirconium oxide, hafnium oxide, and aluminum oxide.

[0046] According to another embodiment, an interface control layer (not shown) may also be formed between the storage node SN and the dielectric layer DE to mitigate leakage current. The interface control layer may include titanium oxide (TiO2). Alternatively, the interface control layer may be formed between the plate node PN and the dielectric layer DE.

[0047] Storage nodes (SN) and plate nodes (PN) can include: metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, storage nodes (SN) and plate nodes (PN) can include: titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten nitride (TiN / W) stacks, or tungsten nitride / tungsten nitride (WN / W) stacks. Plate nodes (PN) can include combinations of metal-based materials and silicon-based materials. For example, a plate node (PN) can be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium can serve as the interstitial material for the cylinders filling the memory nodes (SN), titanium nitride (TiN) can largely function as the plate node for the capacitor (CAP), and tungsten nitride can be a low-resistance material. The bottom of the plate line (PL) can be insulated from the base substrate (LS).

[0048] The storage node SN can have a three-dimensional (3D) structure, and the 3D structure of the storage node SN can be a 3D structure oriented along a second direction D2. As an example of a 3D structure, the storage node SN can have a cylindrical, columnar, or pylinder shape, which is a result of combining a pillar and a cylinder.

[0049] A portion of the dielectric layer DE can be located between the word line WL and the memory node SN.

[0050] See back Figures 1B to 1D The overlay layer CPL can be located between the bit line BL and the word line WL. The overlay layer CPL can be horizontally oriented along a second direction D2 between the bit line BL and the word line WL. The horizontal support LSPT can be located between adjacent overlay layers CPL along a first direction D1 (see...). Figure 1C The vertical support VSPT can be located between adjacent cover layers CPL along the third direction D3 (see...). Figure 1BThe height of the cover layer CPL can be the same as the height of the word line WL. The cover layer CPL may include a separator layer that separates the active layers ACT adjacent along the first direction D1. The active layers ACT adjacent along the first direction D1 and the third direction D3 may be separated by a vertical support VSPT and the cover layer CPL. The cover layer CPL and the word line WL may have the same or different widths along the second direction D2. The cover layer CPL and the first source / drain region SD1 may overlap each other perpendicularly along the first direction D1. The cover layer CPL and the first source / drain region SD1 may be insulated from each other by a gate dielectric layer GD.

[0051] The capping layer CPL can be located at the same level as the word line WL. A first side of the capping layer CPL can directly contact the bit line BL, and a second side of the capping layer CPL can directly contact the word line WL. Each of the first and second side surfaces of the capping layer CPL can include a vertical sidewall. The first side of the capping layer CPL can be formed of different materials. The second side of the capping layer CPL can be formed of only one material. The capping layer CPL can electrically isolate the bit line BL and the word line WL from each other. The capping layer CPL can have a low dielectric constant (low k) to reduce the parasitic capacitance between the bit line BL and the word line WL. The capping layer CPL can include a low-k material capable of reducing the parasitic capacitance between the bit line BL and the word line WL. The capping layer CPL can include materials that are the same as or different from the vertical support VSPT and the horizontal support LSPT. A portion of the capping layer CPL can have etching selectivity relative to the vertical support VSPT and the horizontal support LSPT.

[0052] The capping layer CPL may be located between the word line WL and the bit line BL, and may include at least a low-k material and a seam SV. The capping layer CPL may include various backing materials. For example, the capping layer CPL may include a first backing material CL1 and a second backing material CL2. The first backing material CL1 may include a conformal material, and the second backing material CL2 may include a non-conformal material. The first backing material CL1 and the second backing material CL2 may be different materials. The first backing material CL1 and the second backing material CL2 may have different etching selectivity. During the etching process of the first backing material CL1, the second backing material CL2 may be used as an etching stop layer. The first backing material CL1 may be located between the bit line BL and the word line WL, and the second backing material CL2 may be embedded within the first backing material CL1. The first backing material CL1 may surround a portion of the second backing material CL2. The first backing material CL1 may be cylindrical, and the cylinder of the first backing material CL1 may be filled with the second backing material CL2. The second liner material CL2 may contact the bit line BL, but may not contact the word line WL. The second liner material CL2 may be partially surrounded by the first liner material CL1. The second liner material CL2 may include low-k material embedded in the first liner material CL1.

[0053] The first liner material CL1 may comprise an oxide-based material, and the second liner material CL2 may comprise a material with etch selectivity relative to the oxide-based material. The second liner material CL2 may be a material with greater etch selectivity relative to silicon oxide than relative to conventional silicon nitride (e.g., Si3N4). The etch selectivity between the first liner material CL1 and the second liner material CL2 can be achieved by a dopant, and the dopant may include, for example, carbon. The carbon-doped second liner material CL2 may have etch selectivity relative to the undoped first liner material CL1.

[0054] The first liner material CL1 may include a nitride-based material, and the second liner material CL2 may include a material with high etching selectivity relative to the nitride-based material. The first liner material CL1 may include undoped silicon nitride, and the second liner material CL2 may include carbon-doped silicon nitride or carbon-doped silicon oxide. The carbon-doped silicon nitride may have etching selectivity relative to both carbon-doped silicon nitride and carbon-doped silicon oxide.

[0055] The first liner material CL1 may comprise silicon oxide or silicon nitride, and the second liner material CL2 may comprise at least carbon. The second liner material CL2 may comprise a carbon-doped material, and the first liner material CL1 may comprise an undoped material. The first liner material CL1 may comprise undoped silicon oxide or undoped silicon nitride. The second liner material CL2 may comprise carbon-doped silicon, carbon-doped silicon nitride, or carbon-doped silicon oxide. According to one embodiment, the second liner material CL2 may comprise a low-k material, such as silicon carbide, silicon carbonitride (SiCN), or silicon carbide (SiCO). In one embodiment, the second liner material CL2 may have a dielectric constant of approximately 3.5 or less.

[0056] The second inner liner material CL2 may include a seam CV or a gap. The portion of the second inner liner material CL2 other than the seam SV may be referred to as a gap filler (or main body). The gap filler may not include the seam CV or the gap; that is, the gap filler may be seamless. The seam CV of the second inner liner material CL2 may be positioned to be physically spaced from the upper letter line WLU and the lower letter line WLL. The seam CV may directly contact the position line BL. The seam CV, the second inner liner material CL2, and the first inner liner material CL1 may be located between the position line BL and the upper letter line WLU. According to one embodiment, the second inner liner material CL2 may be seamless. According to one embodiment, the second inner liner material CL2 may include a small seam smaller than the seam CV.

[0057] As described above, the letter BL and the upper letter WLU / lower letter WLL can be physically separated from each other by the overlay layer CPL. Sufficient physical distance can be ensured between the seam CV and the upper letter WLU / lower letter WLL by the second liner material CL2. Since the second liner material CL2 suppresses lateral migration of the seam CV along the second direction D2, perforation of the upper letter WLU / lower letter WLL can be prevented.

[0058] According to one embodiment, the seam CV can maintain an embedded air gap. Therefore, the overlay layer CPL can include a first inner liner material CL1 and a second inner liner material CL2, and the second inner liner material CL2 can include a low-k material and an air gap embedded in the first inner liner material CL1. Because the overlay layer CPL includes an embedded air gap, the parasitic capacitance between the bit line BL and the upper word line WLU / lower word line WLL can be reduced. Because the second inner liner material CL2 includes a low-k material, the parasitic capacitance between the bit line BL and the upper word line WLU / lower word line WLL can be further reduced.

[0059] The first inner liner material CL1 can be thinner than the second inner liner material CL2. In the capping layer CPL, the volume of the second inner liner material CL2 can be larger than the volume of the first inner liner material CL1. As a result, due to the relatively large volume of the second inner liner material CL2, which has an embedded air gap and a lower dielectric constant, the parasitic capacitance between the bit line BL and the upper word line WLU / lower word line WLL can be further reduced.

[0060] The overlay layer CPL can be modified in various ways as described below.

[0061] The capping layer CPL may include a first silicon oxide layer and a second silicon oxide layer surrounding the first silicon oxide layer. The first silicon oxide layer may include carbon-doped silicon oxide, and the second silicon oxide layer may include undoped silicon oxide. The second silicon oxide layer may correspond to a first liner material CL1, and the second silicon oxide layer may correspond to a second liner material CL2. For example, the first silicon oxide layer may include SiCO, and the second silicon oxide layer may include SiO2.

[0062] According to one embodiment, the capping layer CPL may include a silicon oxide layer and a silicon nitride layer surrounding the silicon oxide layer. The silicon oxide layer may include carbon-doped silicon oxide, and the silicon nitride layer may include undoped silicon nitride. The silicon nitride layer may correspond to a first liner material CL1, and the silicon oxide layer may correspond to a second liner material CL2. For example, the silicon oxide layer may include SiCO, and the silicon nitride layer may include Si3N4.

[0063] According to one embodiment, the capping layer CPL may include a silicon nitride layer and a silicon oxide layer surrounding the silicon nitride layer. The silicon nitride layer may include carbon-doped silicon nitride, and the silicon oxide layer may include undoped silicon oxide. The silicon oxide layer may correspond to a first liner material CL1, and the silicon nitride layer may correspond to a second liner material CL2. For example, the silicon nitride layer may include SiCN, and the silicon oxide layer may include SiO2.

[0064] According to one embodiment, the capping layer CPL may include a first silicon nitride layer and a second silicon nitride layer surrounding the first silicon nitride layer. The first silicon nitride layer may include: embedded air gaps, carbon-doped silicon nitride (i.e., carbon-doped silicon nitride including embedded air gaps). The second silicon nitride layer may include undoped silicon nitride. The second silicon nitride layer may correspond to a first liner material CL1, and the first silicon nitride layer may correspond to a second liner material CL2. For example, the first silicon nitride layer may include SiCN, and the second silicon nitride layer may include Si3N4.

[0065] According to one embodiment, the positions or materials of the first liner material CL1 and the second liner material CL2 can vary. For example, the first liner material CL1 may comprise a carbon-doped material having a low dielectric constant, and the second liner material CL2 may comprise silicon oxide. In this case, the first liner material CL1 may comprise: carbon-doped silicon, carbon-doped silicon nitride, or carbon-doped silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), or silicon carbide (SiCO). Although the second liner material CL2 may comprise a seam CV, the migration of the seam CV can be prevented by the first liner material CL1. The first liner material CL1 may be thicker than the second liner material CL2, and the volume of the first liner material CL1 may be larger than that of the second liner material CL2. The second liner material CL2 may comprise an embedded air gap.

[0066] Figure 2 This is a layout diagram of a semiconductor device according to an embodiment of the present disclosure. Figure 2 In the figures, the same reference numerals are used to indicate the same as those in the figures below. Figures 1A to 1D The same components. The semiconductor device 100M can be similar to... Figures 1A to 1D Semiconductor device 100. No detailed description is given for repeating elements. Figure 2 It shows along Figure 1A The layout diagram of the semiconductor device 100M cut off by line A-A' is similar to... Figure 1B Layout diagram.

[0067] See Figure 2 Semiconductor device 100M may include: a bit line BL, an active layer ACT, a word line WL', a capacitor CAP, and a plate line PL. The bit line BL may be vertically oriented along a first direction D1, and the active layer ACT may be horizontally oriented from the bit line BL along a second direction D2. The word line WL' may be horizontally oriented along a third direction D3 intersecting the active layer ACT. A capping layer CPL may be located between the bit line BL and the word line WL'. A vertical support VSPT may be located between adjacent active layers ACT along the third direction D3. Although not shown, it is understood that... Figure 1C As shown, the horizontal support LSPT can be located between adjacent cover layers CPL along the first direction D1. The active layer ACT can include a channel CH and a first source / drain region SD1 and a second source / drain region SD2 on both sides of the channel CH. The capacitor CAP can include: a storage node SN, a dielectric layer DE, and a plate node PN.

[0068] The word line WL' may include a main body WLB that intersects with the adjacent active layer ACT and an extension WLE that extends horizontally from the main body WLB. The main body WLB may extend along a third direction D3, and the extension WLE may extend along a second direction D2. The extension WLE may protrude horizontally from both side surfaces of the main body WLB to the overlay layer CPL and the memory node SN. The word line WL' may have a cross shape.

[0069] The width of the main body WLB along the second direction D2 can be less than Figure 1B The width of the character line WL.

[0070] Figure 3 This is a view illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 3 In the figures, the same reference numerals are used to indicate the same as those in the figures below. Figures 1A to 1D The same components. See also Figure 3 Semiconductor device 100' can be similar to Figures 1A to 1D Semiconductor device 100. No detailed description is given for repeating elements. Figure 3 It is along Figure 1B The cross-sectional view of semiconductor device 100' taken by line B-B' is similar to... Figure 1C Layout diagram.

[0071] Semiconductor device 100' may include a base substrate LS. A memory cell array MCA may be formed beneath the base substrate LS. The memory cell array MCA may be oriented vertically downward from the base substrate LS along a first direction D1. The memory cell array MCA may include a plurality of memory cells MC, and the memory cells MC may be oriented vertically along the first direction D1. Each memory cell MC1, MC2, MC3, and MC4 may include: a bit line BL, a transistor TR, a capacitor CAP, and a board line PL. The transistor TR and capacitor CAP may be oriented horizontally along a second direction D2. Each memory cell MC1, MC2, MC3, and MC4 may further include a word line WL. The word line WL may extend along a third direction D3. In each memory cell MC1, MC2, MC3, and MC4, the bit line BL, transistor TR, capacitor CAP, and board line PL may be horizontally positioned along the second direction D2. The memory cell array MCA may include a dynamic random access memory (DRAM) memory cell array.

[0072] The memory cell array (MCA) may include a stack of at least two or more memory cells (MCs). The memory cells (MCs) may be stacked perpendicularly on the support substrate (SS) along a first direction (D1). Bit lines (BLs) may be connected to the support substrate (SS).

[0073] The supporting substrate SS may include the same material as the base substrate LS. The supporting substrate SS may include: a semiconductor substrate, a metal, a conductive material, an insulating material, or a combination thereof.

[0074] Figure 4A and Figure 4B This is a view illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 4A It is a three-dimensional diagram showing a semiconductor device, and Figure 4B This is a schematic cross-sectional view of a semiconductor device. Figure 4A and Figure 4B In the figures, the same reference numerals are used to indicate the same as those in the figures below. Figures 1A to 1D The same components. See also Figure 4A and Figure 4B Semiconductor device 200 can be similar to Figures 1A to 1D Semiconductor device 100. Detailed descriptions are not given for repeating elements. Although not shown, the layout of semiconductor device 200 can be similar to... Figure 1B Layout diagram.

[0075] Semiconductor device 200 may include a base substrate LS. A memory cell array MCA may be formed on the base substrate LS. The memory cell array MCA may be oriented perpendicularly from the base substrate LS along a first direction D1. The memory cell array MCA may include a plurality of memory cells MC, and the memory cells MC may be oriented perpendicularly along the first direction D1. Each memory cell MC1, MC2, MC3, and MC4 may include: a bit line BL, a transistor TR, a capacitor CAP, and a board line PL. The transistor TR and capacitor CAP may be oriented horizontally along a second direction D2. Each memory cell MC1, MC2, MC3, and MC4 may further include a word line WL, and the word line WL may extend along a third direction D3. In each memory cell MC1, MC2, MC3, and MC4, the bit line BL, transistor TR, capacitor CAP, and board line PL may be horizontally positioned along the second direction D2. The memory cell array MCA may include a dynamic random access memory (DRAM) memory cell array.

[0076] A memory cell array (MCA) may include a stack of at least two or more memory cells (MCs). The memory cells (MCs) may be stacked perpendicularly on a base substrate (LS) along a first direction (D1).

[0077] The transistor TR may include an active layer ACT and a word line WL. The transistor TR may be located between the bit line BL and the capacitor CAP. The transistor TR may be arranged horizontally (LA) along a second direction D2 parallel to the surface of the base substrate LS. For example, the transistor TR may be placed horizontally between the bit line BL and the capacitor CAP.

[0078] The word line WL can extend in the third direction D3, and the active layer ACT can extend in the second direction D2. The third direction D3 can be perpendicular to the first direction D1. The active layer ACT can be arranged horizontally from the bit line BL.

[0079] The word line WL may have a single word line structure located on the upper surface of the active layer ACT. A gate dielectric layer GD may be formed on the surface of the active layer ACT. The word line WL may be disposed above the upper surface of the active layer ACT, and an insulating layer IL may be disposed below the lower surface of the active layer ACT. The gate dielectric layer GD may be formed between the word line WL and the upper surface of the active layer ACT. The gate dielectric layer GD may also be formed between the insulating layer IL and the lower surface of the active layer ACT. The word line WL may include a metal, a metal mixture, a metal alloy, or a semiconductor material. The gate dielectric layer GD may include: silicon oxide, silicon nitride, a high-k material, a ferroelectric material, an antiferroelectric material, or a combination thereof. The insulating layer IL may block interference between the word line WL and memory cells MC placed perpendicularly along the first direction D1. The insulating layer IL may be formed by replacing... Figure 1C The structure is obtained by adding the lower letter WLL.

[0080] In the current embodiment, the overlay layer CPL may be located between the bit line BL and the word line WL. The overlay layer CPL may be oriented along a second direction D2 between the bit line BL and the word line WL. The overlay layer CPL may include a first inner liner material CL1, a second inner liner material CL2, and a seam CV. The overlay layer CPL may be located at the same level as the word line WL. The overlay layer CPL may be horizontally located between the bit line BL and the insulating layer IL. The overlay layers CPL may face each other along a first direction D1, with the active layer ACT disposed between them.

[0081] The second liner material CL2 may include a seam CV or a gap. The seam CV of the second liner material CL2 may be arranged to be physically spaced apart from the letter line WL. The seam CV may directly contact the letter line BL.

[0082] As described above, the bit line BL and the word line WL can be physically separated from each other by the cover layer CPL. Sufficient physical distance can be ensured between the seam CV and the word line WL by the second liner material CL2. Furthermore, since the second liner material CL2 inhibits the lateral migration of the seam CV along the second direction D2, perforation of the word line WL can be prevented by the cover layer CPL.

[0083] According to one embodiment, the seam CV can maintain an embedded air gap. Therefore, since the overlay layer CPL includes an embedded air gap, the parasitic capacitance between the bit line BL and the word line WL can be reduced. Since the second liner material CL2 has a low dielectric constant, the parasitic capacitance between the bit line BL and the word line WL can be further reduced.

[0084] Alternatively, the insulating layer IL can be replaced by the cover layer CPL. For example, the insulating layer IL can be omitted, and the cover layer CPL located below the active layer ACT can extend horizontally.

[0085] According to one embodiment, similar to Figure 3 Semiconductor device 100' and semiconductor device 200 may have a memory cell array MCA located under the base substrate LS.

[0086] Figure 5A and Figure 5B This is a view illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 5A It is a three-dimensional diagram showing a semiconductor device, and Figure 5B This is a schematic cross-sectional view of a semiconductor device. Figure 5A and 5B In the figures, the same reference numerals are used to indicate the same as those in the figures below. Figures 1A to 1D The same components. See also Figure 5A and Figure 5B Semiconductor device 300 can be similar to Figures 1A to 1D Semiconductor device 100. Detailed descriptions are not given for repeating elements. Although not shown, the layout of semiconductor device 300 can be similar to... Figure 1B Layout diagram.

[0087] Semiconductor device 300 may include a base substrate LS, and a memory cell array MCA may be formed on the base substrate LS. The memory cell array MCA may be oriented perpendicularly from the base substrate LS along a first direction D1. The memory cell array MCA may include a plurality of memory cells MC, and the memory cells MC may be oriented perpendicularly along the first direction D1. Each memory cell MC1, MC2, MC3, and MC4 may include: a bit line BL, a transistor TR, a capacitor CAP, and a board line PL. The transistor TR and capacitor CAP may be oriented horizontally along a second direction D2. Each memory cell MC1, MC2, MC3, and MC4 may further include a word line WL, and the word line WL may extend along a third direction D3. In each memory cell MC1, MC2, MC3, and MC4, the bit line BL, transistor TR, capacitor CAP, and board line PL may be horizontally positioned along the second direction D2. The memory cell array MCA may include a dynamic random access memory (DRAM) memory cell array.

[0088] A memory cell array (MCA) may include a stack of at least two or more memory cells (MCs). The memory cells (MCs) may be stacked perpendicularly on a base substrate (LS) along a first direction (D1).

[0089] The transistor TR may include an active layer ACT and a word line WL. The transistor TR may be located between the bit line BL and the capacitor CAP. The transistor TR may be arranged horizontally (LA) along a second direction D2 parallel to the surface of the base substrate LS. For example, the transistor TR may be horizontally located between the bit line BL and the capacitor CAP.

[0090] The word line WL can extend in the third direction D3, and the active layer ACT can extend in the second direction D2. The third direction D3 can be perpendicular to the first direction D1. The active layer ACT can be arranged horizontally from the bit line BL.

[0091] The word line (WL) can have a gate-all-around (GAA) structure surrounding the active layer (ACT). The gate dielectric layer (GD) can be formed on the surface of the active layer (ACT), and the word line (WL) can surround the gate dielectric layer (GD). The word line (WL) can include: metal, metal mixture, metal alloy, or semiconductor material. The gate dielectric layer (GD) can include: silicon oxide, silicon nitride, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. A vertical support member (VSPT) can block interference from vertically arranged word lines (WL).

[0092] In the current embodiment, the overlay layer CPL may be located between the bit line BL and the word line WL. The overlay layer CPL may be oriented along a second direction D2 between the bit line BL and the word line WL. The overlay layer CPL may include a first inner liner material CL1, a second inner liner material CL2, and a seam CV. The overlay layer CPL may be located at the same level as the word line WL. The overlay layers CPL may face each other along the first direction D1, with the active layer ACT disposed between them.

[0093] The second liner material CL2 may include a seam CV or a gap. The seam CV of the second liner material CL2 may be positioned to be physically spaced from the letter line WL. The seam CV may directly contact the letter line BL.

[0094] As described above, the bit line BL and the word line WL can be physically separated from each other by the overlay layer CPL. Sufficient physical distance can be ensured between the seam CV and the word line WL by the second liner material CL2. Furthermore, since the second liner material CL2 suppresses lateral migration of the seam CV along the second direction D2, perforation of the word line WL can be prevented.

[0095] According to one embodiment, the seam CV can maintain an embedded air gap. Therefore, since the overlay layer CPL includes an embedded air gap, the parasitic capacitance between the bit line BL and the word line WL can be reduced. Since the second liner material CL2 has a low dielectric constant, the parasitic capacitance between the bit line BL and the word line WL can also be reduced.

[0096] According to one embodiment, similar to Figure 3 The semiconductor device 100' and the semiconductor device 300 may have a memory cell array MCA located under the base substrate LS.

[0097] Those skilled in the art will recognize that the semiconductor devices according to the various embodiments of the present disclosure as described above are not limited to the embodiments shown in the above embodiments and drawings, and various changes, modifications or substitutions can be made without departing from the scope of the present disclosure.

[0098] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device comprising: Multiple memory cells are vertically stacked on a base substrate; Each of the plurality of memory units includes: Bit lines, which are oriented perpendicularly from the base substrate; A capacitor, which is horizontally spaced from the bit line; An active layer is horizontally oriented between the bit line and the capacitor; A character line, located on at least one of the upper and lower surfaces of the active layer, and extending horizontally in a direction intersecting the active layer; and A cover layer, located between the word line and the bit line, and comprising at least one of a low-k material and an air gap, wherein the cover layer is disposed at the same height as the word line.

2. The semiconductor device according to claim 1, wherein, The overlay is horizontally oriented between the bit line and the word line, and The active layer includes a first source / drain region connected to the bit line and a second source / drain region connected to the capacitor.

3. The semiconductor device according to claim 1, wherein, The covering layer includes: A first lining material, located between the bit line and the word line; and The second lining material is surrounded by the first lining material and includes the low-k material.

4. The semiconductor device according to claim 3, wherein, The low-k material includes materials that have etching selectivity relative to the first liner material.

5. The semiconductor device according to claim 3, wherein, The low-k material includes a carbon-doped material, and wherein the first liner material includes silicon oxide or silicon nitride.

6. The semiconductor device according to claim 3, wherein, The low-k materials include silicon carbide (SiC), silicon carbonitride (SiCN), or silicon carbon oxycarbonate (SiCO).

7. The semiconductor device according to claim 1, wherein, The air gap is physically separated from the word line and is embedded in the cover layer.

8. The semiconductor device according to claim 7, wherein, The air gap is in direct contact with the bit line.

9. The semiconductor device according to claim 1, wherein, The base substrate includes peripheral circuit units connected to the bit lines.

10. The semiconductor device according to claim 1, wherein, The bit line is part of the active layer, and the capacitor is part of the dynamic random access memory cell array.

11. The semiconductor device according to claim 1, wherein, The capacitor includes: Storage nodes are horizontally oriented and connected to the source / drain regions of the active layer; A dielectric layer on the storage node; and Plate-type nodes, which are located on the dielectric layer; and wherein The storage node is shaped like a cylinder.

12. The semiconductor device according to claim 1, wherein, The word lines include: The upper character line is located above the upper surface of the active layer; and The lower character line, which is located below the lower surface of the active layer, and therein Different potentials are applied to the upper word line and the lower word line.

13. The semiconductor device according to claim 1, wherein, The word line includes a single word line located on the upper surface of the active layer, and wherein, The semiconductor device further includes an insulating layer that faces the single word line and is located below the lower surface of the active layer.

14. The semiconductor device according to claim 1, wherein, The word line includes a full surrounding gate structure that surrounds the active layer, and wherein the word line having the full surrounding gate structure extends in a direction intersecting the active layer.

15. The semiconductor device according to claim 1, wherein, The memory cells are stacked vertically upwards from the base substrate.

16. The semiconductor device according to claim 1, wherein, The memory cells are stacked vertically downwards from the base substrate.

17. The semiconductor device according to claim 1, further comprising: A vertical support member that supports the active layer of the memory cell along the direction of the memory cell stacking; as well as A horizontal support member is located between the memory cells along the direction in which the memory cells are stacked.

18. The semiconductor device according to claim 1, wherein, The word lines include: The main body extends in a direction intersecting the active layer; and An extension that protrudes horizontally from both sides of the main body into the cover layer.

19. The semiconductor device of claim 1, comprising a three-dimensional array of memory cells.

20. The semiconductor device according to claim 1, wherein, The covering layer includes: A first liner material, comprising a low-k material located between the bit line and the word line; and A second lining material is surrounded by the first lining material and includes embedded air gaps.

21. The semiconductor device according to claim 20, wherein, The low-k material includes carbon-containing materials, and the second lining material includes silicon oxide or silicon nitride.

22. The semiconductor device according to claim 20, wherein, The low-k materials include silicon carbide (SiC), silicon carbonitride (SiCN), or silicon carbon oxycarbonate (SiCO).

23. A semiconductor device, comprising: A base substrate, which includes peripheral circuit units; Bit lines, which are oriented perpendicularly from the base substrate; Word lines, which are spaced apart from the bit lines and the base substrate, and extend horizontally in a direction intersecting the bit lines; as well as An overlay layer includes an air gap located between the word line and the bit line, wherein the overlay layer is disposed at the same height as the word line.

24. The semiconductor device according to claim 23, wherein, The cover layer comprises a low-k material.

25. The semiconductor device according to claim 23, wherein, The capping layer comprises carbon-doped silicon oxide or carbon-doped silicon nitride.

26. The semiconductor device according to claim 23, wherein, The covering layer includes: A first inner lining material, located between the bit line and the word line; and The second lining material includes the air gap. The first lining material is shaped to surround a portion of the second lining material.

27. The semiconductor device according to claim 26, wherein, The second lining material contacts the bit line but not the word line.

28. The semiconductor device according to claim 26, wherein, The second liner material comprises a carbon-containing material having a low dielectric constant, and wherein the first liner material comprises silicon oxide or silicon nitride.

29. The semiconductor device according to claim 26, wherein, The second liner material includes silicon carbide (SiC), silicon carbonitride (SiCN), or silicon carbon oxycarbonate (SiCO).

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