An adaptive sensitive amplifier circuit and module for low-voltage SRAM
By adaptively controlling the bit line discharge time using an adaptive sensitive amplifier circuit, the power consumption waste and delay problems of SRAM read operations under low voltage are solved, achieving more efficient data readout and lower power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ANHUI UNIV
- Filing Date
- 2022-12-28
- Publication Date
- 2026-06-30
AI Technical Summary
At low voltages, SRAM read operations suffer from wasted power consumption and increased read latency. In particular, the increased design margin due to offset voltage affects the performance of SRAM.
An adaptive sensitive amplifier circuit is adopted, including a sensitive amplification module, a switching module, an error detection circuit module, and a word line control module. By adaptively controlling the discharge time of the bit line, the correctness of the data is quickly determined and the word line is shut down in time, thereby reducing read power consumption.
It significantly reduces SRAM read power consumption, shortens word line turn-on time, and improves data read accuracy and efficiency, especially at low voltages.
Smart Images
Figure CN115938413B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and more specifically, to an adaptive sensitive amplifier circuit for low-voltage SRAM, and a sensitive amplifier module employing this circuit layout. Background Technology
[0002] With the widespread adoption of mobile phones, laptops, and other portable devices, and the rapid development of technologies such as artificial intelligence (AI), new energy, autonomous driving, and quantum science, the high-speed, low-power characteristics of Static Random Access Memory (SRAM) are playing an increasingly important role in circuit design. The demand for higher density, lower power consumption, and faster speeds in SRAM memory chips is becoming increasingly urgent, requiring continuous reduction in device feature size and power supply voltage. However, this shrinking size, coupled with localized process variations, exacerbates the mismatch problem between paired transistors. (See also...) Figure 1 As the operating voltage VDD decreases from 1.2V, the discharge capability of the memory cell becomes weaker and weaker. That is, the discharge speed of SRAM exhibits a tailing phenomenon at low voltage, and the latency required for SRAM read operations becomes larger and larger. This leads to a larger and larger design margin required for SRAM read operation latency. In particular, an overly pessimistic design margin at low voltage greatly increases the read power consumption of the memory array.
[0003] The sense amplifier (SA), as the core circuit of SRAM, largely determines whether the information in the memory cell can be read quickly and correctly. Its main function is to amplify the weak signal difference on the bit lines connected to the memory cell, thereby enabling correct reading. The performance indicators of the sense amplifier mainly include offset voltage, read speed, yield, and power consumption, with offset voltage being the most important parameter. The presence of offset voltage can cause the sense amplifier to incorrectly amplify the information in the memory cell, severely affecting the SRAM's performance. To ensure the accuracy of the read data, it is necessary to increase the design margin of the bit line swing to overcome the impact of offset voltage. However, to meet the design margin for a very small number of memory cells with slow discharge times, the read operations of most memory cells will generate unnecessary power consumption due to excessively long word line on-time. (See [link to relevant documentation]). Figure 2 , Figure 3 . Summary of the Invention
[0004] Therefore, it is necessary to provide an adaptive sensitive amplifier circuit and module for low-voltage SRAM to address the problem of power waste during read operations of existing SRAM at low voltage.
[0005] This invention is achieved using the following technical solution:
[0006] In a first aspect, the present invention provides an adaptive sensitive amplifier circuit for low-voltage SRAM, which is used to adaptively control the discharge time of the bit lines BL / BLB of the memory array and adaptively output correct data.
[0007] The adaptive sensitive amplifier circuit includes a sensitive amplification module, a switching module, an error detection circuit module, and a word line control module.
[0008] The sensitive amplifier module is used to read data from the bit lines BL / BLB. A switching module is connected between the sensitive amplifier module and the memory array, used to switch the connection between the memory array's bit lines BL / BLB and the sensitive amplifier during two consecutive data reads. An error detection circuit module is connected to the output of the sensitive amplifier module, used to compare the even-numbered data reads from the sensitive amplifier module with the previous odd-numbered data reads until the output result signal FLAG is "1", and the correct read data is output to the external combinational logic circuit. A word line control module is connected to the output of the error detection circuit module, used to adjust the enable signal EN acting on the word line buffer WL_Buffer based on the result signal FLAG, thereby controlling the off time of the memory array word line WL and achieving adaptive control of the bit line BL / BLB discharge time.
[0009] This method or process for implementing an adaptive sensitive amplifier circuit for low-voltage SRAM is based on an embodiment of the present disclosure.
[0010] In a second aspect, the present invention discloses a sensitive amplifier module that adopts the adaptive sensitive amplifier circuit layout for low-voltage SRAM as disclosed in the first aspect.
[0011] Compared with the prior art, the present invention has the following beneficial effects:
[0012] 1. This invention adjusts the connection relationship between the bit line BL / BLB and the two input terminals of the sensitive amplifier module by switching the switch module, so as to realize the positive or negative connection of the two, so that the sensitive amplifier module can quickly and continuously read two opposite signals for subsequent error detection circuit to determine whether the read data is correct; compared with the traditional error detection circuit, this invention improves the error detection delay and greatly advances the error detection time.
[0013] 2. In this invention, after the error detection circuit module determines that the sensitive amplification module has read the correct data, it will adaptively output the correct data to the external combinational logic circuit. It will also immediately reduce the enable signal EN acting on the word line buffer WL_Buffer to a low level through the word line control module, thereby turning off the word line WL and stopping the bit line BL / BLB from discharging. This reduces the discharge time of the bit line BL / BLB and significantly reduces the read power consumption of the SRAM. Attached Figure Description
[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0015] Figure 1 The following is a simulation result diagram of the existing SRAM memory cell in the background technology under the condition of 60mV delay due to lower line discharge at VDD=1.2V and VDD=0.5V;
[0016] Figure 2 This is a schematic diagram illustrating the existing problems of read operations in existing SRAM memory cells in the background art;
[0017] Figure 3 This is a schematic diagram illustrating the trend of power consumption and latency of read operations in existing SRAM memory cells as a function of power supply voltage in the background technology.
[0018] Figure 4 This is a structural diagram of an adaptive sensitive amplifier circuit for use with a memory array in low-voltage SRAM, provided in Embodiment 1 of the present invention;
[0019] Figure 5 for Figure 4 Structural diagram of the switching module;
[0020] Figure 6 for Figure 5 A schematic diagram of the working status of the switching module;
[0021] Figure 7 for Figure 4 Structural diagram of the medium-sensitivity amplification module;
[0022] Figure 8 for Figure 4 Structure diagram of the error detection circuit module;
[0023] Figure 9 for Figure 4 Structural diagram of the Chinese character line control module;
[0024] Figure 10 for Figure 4 The timing diagram of the read operation in which the sensitive amplifier circuit determines that the read data is correct on the first error detection;
[0025] Figure 11 for Figure 4 The timing diagram of the read operation in which the sensitive amplifier circuit determines that the read data is correct only after the nth error detection;
[0026] Figure 12 for Figure 4 A schematic diagram comparing the dynamic power consumption of the sensitive amplifier circuit and the traditional solution during read operations at different voltages;
[0027] Figure 13 for Figure 4 A schematic diagram comparing the word line on-time during read operations at different voltages with a traditional solution using a sensitive amplifier circuit.
[0028] Figure 14 for Figure 4 The simulation results of the sensitive amplifier circuit and the existing SRAM memory cell discharge at VDD=0.6V in the background technology are shown in the figure. Detailed Implementation
[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0030] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.
[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.
[0032] Example 1
[0033] See Figure 4This is a structural diagram of an adaptive sensitive amplifier circuit for use with a memory array in low-voltage SRAM, as disclosed in this embodiment.
[0034] like Figure 4 As shown, an adaptive sensitive amplifier circuit for low-voltage SRAM is used to adaptively control the discharge time of the bit lines BL / BLB of the memory array.
[0035] A storage array consists of N columns and M rows of storage cells (BITCELL). Storage cells in the same column share the same bit line BL / BLB.
[0036] It is important to note that the appropriate sensitivity amplifier circuit should be selected based on the number of columns that are enabled in the storage array.
[0037] If the number of columns selected by the storage array each time is 2 i That is, corresponding to 2 i For SRAM with a bit width of 2 bits, the corresponding sensitivity amplifier circuit includes 2 i One sensitive amplification module, 2 i One switching module, 2 i One error detection circuit module and one word line control module; i = 0, 1, 2, ...
[0038] The switching module, sensitive amplification module, and error detection module are connected in a one-to-one correspondence. The k-th switching module, the k-th sensitive amplification module, and the k-th error detection module are connected sequentially, where 1≤k≤2. i The j*2th i The bit line BL / BLB of column +k is connected to the k-th toggle switch, 0≤j≤N / 2 i -1.
[0039] It should be noted that, see Figure 4 The storage array starts from 0, with [0] as the first column and the first row; while the sensitive amplifier circuit starts from 1, with [1] as the first column.
[0040] The sensitive amplifier module is used to read data from the bit lines BL / BLB. A switching module is connected between the sensitive amplifier module and the memory array, used to switch the connection between the memory array's bit lines BL / BLB and the sensitive amplifier during two consecutive data reads. An error detection circuit module is connected to the output of the sensitive amplifier module, used to compare the even-numbered data reads from the sensitive amplifier module with the previous odd-numbered data reads until the output result signal FLAG is "1", and then output the read data to external combinational logic circuitry. A word line control module is connected to the output of the error detection circuit module, used to adjust the enable signal EN acting on the word line buffer WL_Buffer based on the result signal FLAG, thereby controlling the off time of the memory array word lines WL and achieving adaptive control of the bit line BL / BLB discharge time.
[0041] To facilitate the explanation of the structure of each module, one of the switching module, sensitive amplification module, and error detection module will be explained first.
[0042] (I) See Figure 5 This is a structural diagram of the switching module. The switching module includes PMOS transistors KEY1, KEY2, KEY3, and KEY4.
[0043] For KEY1, the source is connected to bit line BL, the gate to the control signal SW, and the drain to the positive input IN of the sensitive amplifier module. For KEY2, the source is connected to bit line BL, the gate to the control signal SWN, and the drain to the negative input INB of the sensitive amplifier module. For KEY3, the source is connected to bit line BLB, the gate to the control signal SWN, and the drain to the positive input IN of the sensitive amplifier module. For KEY4, the source is connected to bit line BLB, the gate to the control signal SW, and the drain to the negative input INB of the sensitive amplifier module.
[0044] It should be noted that the control signal SW is divided into three paths; the first path directly controls KEY1; the second path directly controls KEY4; the third path is converted into a control signal SWN by a signal inverter, and then divided into two paths, one controlling KEY2 and the other controlling KEY3. Therefore, KEY1 and KEY4 have the same on / off state, KEY2 and KEY3 have the same on / off state, and KEY1 and KEY2 have opposite on / off states.
[0045] See Figure 6This diagram illustrates the operating state of the switching module. Specifically, when the control signal SW is low, the control signal SWN is high, bit line BL is connected to the positive input IN of the sensitive amplifier module via KEY1, and bit line BLB is connected to the negative input INB of the sensitive amplifier module via KEY4. When the control signal SW is high, the control signal SWN is low, bit line BL is connected to the negative input INB of the sensitive amplifier module via KEY2, and bit line BLB is connected to the positive input IN of the sensitive amplifier module via KEY3.
[0046] By adjusting the potential of the control signal SW, the polarity of the input voltage of the sensitive amplifier module is quickly switched, thus allowing the bit lines BL / BLB to switch between positive and negative connections when the sensitive amplifier module reads data consecutively. It is important to emphasize that during odd-numbered reads, the bit lines BL / BLB are positively connected to the sensitive amplifier module; during even-numbered reads, the bit lines BL / BLB are negatively connected to the sensitive amplifier module.
[0047] It should be noted that 2 i Each switching module shares the same control signal SW, enabling overall control.
[0048] If the above refers to the k-th switch, then KEY1, KEY2, KEY3, and KEY4 are KEY1[k], KEY2[k], KEY3[k], and KEY4[k], respectively; correspondingly, they are connected to the k-th sensitive amplification module and the j*2-th sensitive amplification module. i The bit lines BL / BLB of column +k, i.e., the positive input IN is IN[k], the negative input INB is INB[k], and the bit line BL is BL[j*2]. i +k-1], bit line BLB is BLB[j*2] i +k-1].
[0049] (II) See Figure 7 This is a structural diagram of the sensitive amplification module. The sensitive amplification module includes 9 PMOS transistors P1 to P9 and 3 NMOS transistors N1 to N3.
[0050] The gate of P1 is connected to the output node OUTN, the source is connected to the power supply VDD, and the drain is connected to the output node OUT. The gate of P2 is connected to the output node OUT, the source is connected to the power supply VDD, and the drain is connected to the output node OUTN. The gate of P3 is connected to the control signal EQ, the source is connected to the power supply VDD, and the drain is connected to the output node OUT. The gate of P4 is connected to the control signal EQ, the source is connected to the power supply VDD, and the drain is connected to the output node OUTN. The gate of P5 is connected to the control signal RD, the source is connected to the output node OUT, and the drain is connected to the positive input IN. The gate of P6 is connected to the control signal RD, the source is connected to the output node OUTN, and the drain is connected to the negative input INB. The gate of P7 is connected to the control signal PRE, the source is connected to the power supply VDD, and the drain is connected to the positive input IN. The gate of P8 is connected to the control signal PRE, the source is connected to the power supply VDD, and the drain is connected to the negative input INB. The gate of P9 is connected to the control signal PRE, the source is connected to the positive input IN of the sensitive amplifier module, and the drain is connected to the negative input INB.
[0051] The gate of N1 is connected to the output node OUTN, the drain is connected to the output node OUT, and the source is connected to the node NET. The gate of N2 is connected to the output node OUT, the drain is connected to the output node OUTN, and the source is connected to the node NET. The gate of N3 is connected to the enable signal SAE, the drain is connected to the node NET, and the source is connected to the power supply ground.
[0052] Specifically, if the voltage on bit line BL is greater than the voltage on bit line BLB, the output node OUT is low level 0; when the voltage on bit line BL is less than the voltage on bit line BLB, the output node OUT is high level 1.
[0053] When the sensitive amplification module reads data in two consecutive steps, before the next read, the output nodes OUT and OUTN are charged to VDD through P3 and P4, and then P5 and P6 are turned on to sense the voltage difference on the bit lines BL and BLB for the second time. This is to avoid the previous amplification read result affecting the error detection read.
[0054] Refer to Table 1 for the impact of the input and offset voltages of the sensitive amplifier module on its output. ①V OFFSET >0, defined as N1 having a stronger driving capability than N2; ②V OFFSET <0 means that the driving capability of N1 is weaker than that of N2.
[0055] Table 1. The Influence of Input and Offset Voltages of the Sensitive Amplifier Module on its Output
[0056]
[0057]
[0058] As shown in Table 1, when the bit line swing and offset voltage have opposite polarities, the reading will always be correct; when they have the same polarity, the bit line swing must be greater than the offset voltage for a correct reading (the bit line swing is defined as |V) BL -V BLB |).
[0059] It should be noted that 2 i Each sensitive amplification module shares the same control signal EQ, the same control signal RD, the same control signal SAE, and the same control signal PRE, enabling overall control.
[0060] If the above refers to the k-th sensitive amplification module, then P1 to P9 are P1[k] to P9[k]; N1 to N3 are N1[k] to N3[k]. The output node OUTN is OUTN[k], the output node OUT is OUT[k], the positive input IN is IN[k], the negative input INB is INB[k], and the node NET is NET[k].
[0061] (III) See Figure 8 This is a structural diagram of the error detection circuit module. The error detection circuit module includes a D flip-flop LATCH, transmission gate TG1, transmission gate TG2, a two-input XOR gate, and transmission gate TG3.
[0062] The input terminal of the D flip-flop LATCH is connected to the output node OUT of the sensitive amplifier module, and the second input terminal is connected to the clock signal LA. The output is split into two paths.
[0063] The input of transmission gate TG1 is connected to one output of the D flip-flop LATCH, and its enable terminal is connected to the enable signal CO. The input of transmission gate TG2 is connected to the output node OUT of the sensitive amplifier module, and its enable terminal is connected to the enable signal CO. One input of the two-input XOR gate is connected to the output of transmission gate TG1, and the other input is connected to the output of transmission gate TG2. The output terminal outputs the result signal FLAG. One input of transmission gate TG3 is connected to the other output of the D flip-flop LATCH, and the other input is connected to the result signal FLAG. The output terminal outputs the data signal Right_OUT.
[0064] Specifically, for an odd number of reads followed by an even number of reads:
[0065] First, consider the odd number of reads. The D flip-flop LATCH controls the latching of the odd number of reads 1st_OUT through the clock signal LA. Both transmission gates TG1 and TG2 are closed, so the two-input XOR gate has no result to compare.
[0066] Then, after an even number of reads, the result 2nd_OUT is read. Then, the transmission gates TG1 and TG2 are opened. 2nd_OUT passes through the transmission gate TG2 to the two-input XOR gate. One output of the D flip-flop LATCH, 1st_OUT, passes through the transmission gate TG1 to the two-input XOR gate. The two-input XOR gate compares the two read results, thus realizing the error detection function.
[0067] If the error detection circuit module determines that the read is correct, it outputs a FLAG signal of "1" to the word line control module, which in turn controls the word line WL to turn off, thus achieving adaptive stopping of discharge for bit lines BL / BLB. Furthermore, when the FLAG signal is "1", it also controls the transmission gate TG3 to open. The other output of the D flip-flop LATCH, 1st_OUT, passes through the transmission gate TG3, thereby adaptively outputting the correct read data Right_OUT.
[0068] Refer to Table 2, which shows the relationship between the error detection results of the error detection circuit module in this embodiment and the bit line swing of the storage cell.
[0069] Table 2 shows the relationship between error detection results and memory cell bit line swing.
[0070]
[0071] As shown in Table 2, 1st_OUT represents the data read from an odd number of times, and 2nd_OUT represents the data read from an even number of times. If they are the same, the output result signal FLAG is "0"; if they are different, the output result signal FLAG is "1".
[0072] Error detection circuits may misjudge a situation where the output is correct, but the flag is "0". However, the energy loss in this case is negligible because the misjudgment is quickly eliminated as the bit line swing increases, and the probability of this situation occurring is extremely small.
[0073] It should be noted that 2 i Each error detection module shares the same clock signal LA.
[0074] If the above is the k-th error detection circuit module, the D flip-flop LATCH is LATCH[k], the transmission gates TG1, TG2, and TG3 are TG1[k], TG2[k], and TG3[k], the two-input XOR gate is XOR[k], the result signal FLAG is FLAG[k], and the data signal Right_OUT is Right_OUT[k].
[0075] That is, the output result signal FLAG[k] and the output data signal Right_OUT[k] of the kth error detection module.
[0076] (iv) See Figure 9This is a structural diagram of the word line control module. The word line control module includes a PMOS transistor MP, a capacitor CAP, and 2... i NMOS transistors M[1]~M[2] i ].
[0077] The gate of the PMOS transistor MP is connected to the precharge signal PRE, the source is connected to the power supply VDD, and the drain is connected to the output node Ctr_OUT. The output node Ctr_OUT outputs the enable signal EN. The upper electrode of the capacitor CAP is connected to the output node Ctr_OUT, and the lower electrode is connected to the power supply ground.
[0078] M[1]~M[2 i The NMOS transistors are connected in series, with the source of the previous NMOS transistor M[h] connected to the drain of the next NMOS transistor M[h+1], where 1 ≤ h ≤ 2. i -1.
[0079] Among them, the gate connection result signal FLAG[k] of the k-th NMOS transistor M[k], the drain connection output node Ctr_OUT of M[1], and M[2] are all connected. i The source terminal of [] is connected to the power supply ground.
[0080] It should be noted that the word line control module, 2 i Each sensitive amplification module shares the same control signal PRE.
[0081] The same row of memory cells shares the same word line WL. The enable signal EN is connected to the M word line buffers WL_Buffer of the M row of memory cells, and is used to control the M word line buffers WL_Buffer in a unified manner.
[0082] Specifically, MP is responsible for charging capacitor CAP before receiving the FLAG signal, keeping the enable signal EN at a high potential, and M[1]~M[2] i [Responsible for receiving FLAG signals and controlling its working state by FLAG signals: when FLAG[1]~FLAG[2] i When all are high level "1", there is a leakage path between the enable signal EN and the power supply ground, causing the enable signal EN level to be low "0", thereby controlling the word line buffer WL_Buffer to stop working and the word line WL to be turned off, thus realizing adaptive control of the discharge time of the bit line BL / BLB.
[0083] In addition, each row's word line (WL) is connected to the row decoder (DEW) via a word line buffer (WL_Buffer); the row decoder is used to select the specific row that the memory array needs to open for calculation. Each column of memory is connected to a column select circuit (MUX), which is controlled by the column decoder to select the specific column that the memory array needs to open for calculation.
[0084] Example 2
[0085] This embodiment 2 discloses timing diagrams for two cases when the sensitive amplifier circuit of embodiment 1 performs a read operation.
[0086] See Figure 10 This is a timing diagram of a read operation that determines the read data is correct during the first error detection, taking a single column as an example.
[0087] Specifically: First, the word line WL is turned on, the bit lines BL / BLB are discharged, and after a short time, the SAE signal is enabled, the sensitive amplification module is started, and the D flip-flop LATCH latches the data to be compared with the error detection read data. The second step involves shutting down P5, P6, and N3, and opening P3 and P4 to recharge the two output nodes of the sensitive amplifier module to VDD, quickly adjusting the polarity of the input voltage of the sensitive amplifier module. Then, the control signal RD controls P5 and P6 to reopen, the SAE signal enables the sensitive amplifier module a second time, and the error detection data is read out. The control signal CO then controls the transmission transistors TG1 and TG2 to open. The XOR gate output signal FLAG is "1", indicating that the first read result is correct. The data is quickly output to the external combinational logic circuit. The result signal FLAG is input to the word line control module. The enable signal EN has a leakage path with the power supply ground, making the EN level low "0", which in turn controls the M word line buffers WL_Buffer to stop working uniformly. The word line WL is turned off, the bit line BL / BLB stops discharging, and the read operation ends.
[0088] See Figure 11 This is a timing diagram of a read operation, taking a single column as an example, where the read data is determined to be correct only after the nth error check.
[0089] Specifically, the first step involves turning on the word line WL and discharging the bit lines BL / BLB. After a short time, the SAE signal is enabled, the sensitive amplifier module starts, and the data is latched by the D flip-flop LATCH for comparison with the error detection data. The second step involves turning off P5, P6, and N3, and turning on P3 and P4 to recharge the two output nodes of the sensitive amplifier module to VDD. The polarity of the input voltage of the sensitive amplifier module is quickly adjusted, and then the control signal RD controls P5 and P6 to turn on again. The SAE signal is enabled a second time, the sensitive amplifier module starts a second time, and the error detection data is read out. Then, the control signal CO controls the transmission transistors TG1 and TG2 to turn on. If the output signal FLAG of the two-input XOR gate is "0", then the data read is incorrect. FLAG is input to the word line control module, the EN level remains high, controlling the word line WL to continue turning on, the bit lines BL / BLB to continue discharging, the swing of the bit lines BL / BLB is further amplified, and the sensitive amplifier module starts again. This cycle repeats until the data is read correctly.
[0090] This embodiment 2 also compares the adaptive sensitive amplifier circuit applied to low-voltage SRAM in embodiment 1 with the traditional SA scheme through simulation, comparing the dynamic power consumption of the two during read operations at different voltages. The comparison diagram is shown below. Figure 12 As shown. The simulation conditions were 1.2V, 1.1V, 1.0V, 0.9V, 0.8V, 0.7V and 0.6V, TTG process angle, 27℃.
[0091] The results show that the adaptive sensitive amplifier circuit design for low-voltage SRAM provided in Example 1 has lower power consumption than the traditional SA scheme at low operating voltage, and the lower the operating voltage, the greater the reduction in power consumption, thus showing better application prospects.
[0092] Similarly, in this embodiment 2, the adaptive sensitive amplifier circuit applied to low-voltage SRAM in embodiment 1 was simulated and compared with the traditional solution SA. The word line turn-on time during read operations under different voltages was compared. The comparison diagram is shown below. Figure 13 As shown. The simulation conditions were 1.2V, 1.1V, 1.0V, 0.9V, 0.8V, 0.7V and 0.6V, TTG process angle, 27℃.
[0093] The results show that the adaptive sensitive amplifier circuit design scheme for low-voltage SRAM provided in Example 1 has a shorter average word line turn-on time than the traditional scheme SA under low operating voltage, which also confirms the simulation results of power consumption above.
[0094] Furthermore, this embodiment 2 also simulates the discharge condition of the adaptive sensitive amplifier circuit applied to low-voltage SRAM in embodiment 1 and the existing SRAM memory cell in the background art at VDD=0.6V. The results are shown in the figure below. Figure 14 As shown in the figure. The results show that most correct results are read in the first 4 reads, and the word line WL is turned off before 6ns during most read operations. In contrast, the traditional method requires all word lines WL to be turned on for 12ns during the read operation. This proves that the proposed method can shorten the turn-on time of word lines WL during the read operation, thereby reducing the read power consumption of SRAM.
[0095] Example 3
[0096] Based on the adaptive sensitive amplifier circuit for low-voltage SRAM disclosed in Embodiment 1, Embodiment 3 also discloses a sensitive amplifier module that adopts the sensitive amplifier circuit layout disclosed in Embodiment 1.
[0097] The modular packaging makes it easier to promote and apply an adaptive sensitive amplifier circuit for low-voltage SRAM.
[0098] The interfaces of the sensitive amplifier module include:
[0099] SW interface, BL[0] interface ~ BL[2] i -1] interface, BLB[0] interface ~ BLB[2 i -1] Interface, EQ interface, RD interface, SAE interface, PRE interface, LA interface, CO interface, Right_OUT[1] interface ~ Right_OUT[2 i ] Interface, EN interface.
[0100] The SW interface is used to transmit control signals SW.
[0101] The BL[0] interface is used to connect to the bit line BL[j*2]. i ] connection; BL[1] interface is used to connect with bit line BL[j*2 i +1] connect; ...; BL[2 i -1] The interface is used to connect to the bit line BL[j*2] i +2 i -1] connection.
[0102] The BLB[0] interface is used to connect to the bit line BLB[j*2]. i ] connection; BLB[1] interface is used to connect with bit line BLB[j*2 i +1] connect; ...; BLB[2 i -1] The interface is used to connect to the bit line BLB[j*2] i +2 i -1] connection.
[0103] The EQ interface is used to transmit the control signal EQ. The RD interface is used to transmit the control signal RD. The SAE interface is used to transmit the enable signal SAE. The PRE interface is used to transmit the control signal PRE. The LA interface is used to transmit the clock signal LA. The CO interface is used to transmit the enable signal CO.
[0104] The Right_OUT[1] interface is used to connect to the data signal Right_OUT[1]; the Right_OUT[2] interface is used to connect to the data signal Right_OUT[2]; ...; Right_OUT[2 i The interface is used to communicate with the data signal Right_OUT[2] i [Connection]. The EN interface is used to transmit the enable signal EN.
[0105] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0106] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.
Claims
1. An adaptive sensitive amplifier circuit for low-voltage SRAM, used for adaptively controlling the bit line BL / BLB discharge time of the memory array and adaptively outputting correct data, characterized in that, The adaptive sensitive amplifier circuit includes: The sensitive amplification module is used to read data on the bit lines BL / BLB; A switching module is connected between the sensitive amplifier module and the storage array. It is used to switch the bit lines BL / BLB of the storage array and the sensitive amplifier in positive / reverse connection when the sensitive amplifier module reads data in two consecutive times. An error detection circuit module, connected to the output of the sensitive amplifier module, compares the even-numbered reads from the sensitive amplifier module with the previous odd-numbered reads until the output signal FLAG is "1", and outputs the correct reads to external combinational logic circuitry; and The word line control module is connected to the output of the error detection circuit module. It is used to adjust the enable signal EN applied to the word line buffer WL_Buffer according to the result signal FLAG, thereby controlling the time when the word line WL of the memory array is turned off, and realizing adaptive control of the bit line BL / BLB discharge time.
2. The adaptive sensitive amplifier circuit for low-voltage SRAM according to claim 1, characterized in that, The switching module, sensitive amplification module, and error detection module are all equipped with 2 i There are three modules, i = 0, 1, 2, ...; the switching module, sensitive amplification module, and error detection module are one-to-one, with the k-th switching module, k-th sensitive amplification module, and k-th error detection module connected sequentially, 1 ≤ k ≤ 2. i .
3. The adaptive sensitive amplifier circuit for low-voltage SRAM according to claim 2, characterized in that, The k-th sensitive amplification module includes: The k-th PMOS transistor P1[k] has its gate connected to the k-th output node OUTN[k], its source connected to the power supply VDD, and its drain connected to the k-th output node OUT[k]. The k-th PMOS transistor P2[k] has its gate connected to the output node OUT[k], its source connected to the power supply VDD, and its drain connected to the output node OUTN[k]. The k-th PMOS transistor P3[k] has its gate connected to the control signal EQ, its source connected to the power supply VDD, and its drain connected to the output node OUT[k]. The k-th PMOS transistor P4[k] has its gate connected to the control signal EQ, its source connected to the power supply VDD, and its drain connected to the output node OUTN[k]. The k-th PMOS transistor P5[k] has its gate connected to the control signal RD, its source connected to the output node OUT[k], and its drain connected to the k-th positive input IN[k]. The k-th PMOS transistor P6[k] has its gate connected to the control signal RD, its source connected to the output node OUTN[k], and its drain connected to the k-th input negative terminal INB[k]. The k-th PMOS transistor P7[k] has its gate connected to the control signal PRE, its source connected to the power supply VDD, and its drain connected to the positive input IN[k]. The k-th PMOS transistor P8[k] has its gate connected to the control signal PRE, its source connected to the power supply VDD, and its drain connected to the negative input INB[k]. The k-th PMOS transistor P9[k] has its gate connected to the control signal PRE, its source connected to the positive input IN[k], and its drain connected to the negative input INB[k]. The k-th NMOS transistor N1[k] has its gate connected to the output node OUTN[k], its drain connected to the output node OUT[k], and its source connected to the k-th node NET[k]. The k-th NMOS transistor N2[k] has its gate connected to output node OUT[k], its drain connected to output node OUTN[k], and its source connected to node NET[k]. The k-th NMOS transistor N3[k] has its gate connected to the enable signal SAE, its drain connected to node NET[k], and its source connected to the power supply ground.
4. The adaptive sensitive amplifier circuit for low-voltage SRAM according to claim 3, characterized in that, The storage array comprises N columns and M rows of storage cells; storage cells in the same column share the same bit line BL / BLB; the j*2nd... i The bit line BL / BLB of column +k is connected to the k-th toggle switch, 0≤j≤N / 2 i -1; The kth switching module includes: The k-th PMOS transistor KEY1[k], the source of KEY1[k] is connected to the j*2-th PMOS transistor. i +k units line BL[j*2 i [+k-1], the gate is connected to the control signal SW, and the drain is connected to the positive input IN[k]; The k-th PMOS transistor KEY2[k] has a source connection bit line BL[j*2]. i [+k-1], the gate is connected to the control signal SWN, and the drain is connected to the input negative terminal INB[k]; The k-th PMOS transistor KEY3[k], the source of KEY3[k] is connected to the j*2-th PMOS transistor. i +k units line BLB[j*2 i +k-1], the gate is connected to the control signal SWN, and the drain is connected to the positive input IN[k]; and The k-th PMOS transistor KEY4[k] has a source connection bit line BLB[j*2]. i +k-1], the gate is connected to the control signal SW, and the drain is connected to the input negative terminal INB[k].
5. The adaptive sensitive amplifier circuit for low-voltage SRAM according to claim 4, characterized in that, The control signal SW is divided into three paths: the first path directly controls KEY1[k]; the second path directly controls KEY4[k]; the third path is converted into a control signal SWN by a signal inverter, and then divided into two paths, one of which controls KEY2[k] and the other path controls KEY3[k].
6. The adaptive sensitive amplifier circuit for low-voltage SRAM according to claim 4, characterized in that, The k-th error detection circuit module includes: The k-th D flip-flop LATCH[k] has one input terminal connected to the output node OUT[k], and the other input terminal connected to the enable signal CO. The output is split into two paths. The input of the k-th transmission gate TG1[k] is connected to one output of the D flip-flop LATCH[k], and the enable terminal is connected to the enable signal CO. The k-th transmission gate TG2[k] has its input connected to the output node OUT[k] and its enable signal CO connected to its enable signal. The k-th two-input XOR gate XOR[k] has one input connected to the output of transmission gate TG1[k], and the other input connected to the output of transmission gate TG2[k]. Its output is the k-th result signal FLAG[k]. The k-th transmission gate TG3[k] has one input terminal connected to the other output of the D flip-flop LATCH[k], another input terminal connected to the result signal FLAG[k], and the output terminal outputs the k-th data signal Right_OUT[k].
7. The adaptive sensitive amplifier circuit for low-voltage SRAM according to claim 6, characterized in that, The word line control module includes: The PMOS transistor MP has its gate connected to the precharge signal PRE, its source connected to the power supply VDD, and its drain connected to the output node Ctr_OUT; the output node Ctr_OUT outputs the enable signal EN. Capacitor CAP, with its upper electrode connected to the output node Ctr_OUT and its lower electrode connected to the power supply ground; and 2 i NMOS transistors M[1]~M[2] i ],M[1]~M[2 i The NMOS transistors are connected in series, with the source of the previous NMOS transistor M[h] connected to the drain of the next NMOS transistor M[h+1], where 1 ≤ h ≤ 2. i -1; where, the gate connection result signal FLAG[k] of the Kth NMOS transistor M[k], the drain connection output node Ctr_OUT of M[1], and M[2 i The source terminal of [] is connected to the power supply ground.
8. The adaptive sensitive amplifier circuit for low-voltage SRAM according to claim 7, characterized in that, The same row of memory cells shares the same word line WL; the enable signal EN is connected to the M word line buffers WL_Buffer of the M row of memory cells, and when the enable signal EN is low, it controls the M word line buffers WL_Buffer to stop working at the same time.
9. The adaptive sensitive amplifier circuit for low-voltage SRAM according to claim 7, characterized in that, 2 i Each switching module shares the same control signal SW; 2 i Each sensitive amplification module shares the same control signal EQ, the same control signal RD, and the same control signal SAE; 2 i Each error detection module shares the same clock signal LA; Word line control module, 2 i Each sensitive amplification module shares the same control signal PRE.
10. A sensitive amplifier module, characterized in that, The layout of the adaptive sensitive amplifier circuit for low-voltage SRAM as described in any one of claims 1-9 is adopted.