Memory and Method of Operating the Same

Abstract

An embodiment of the present application provides a memory and a programming method thereof. The method includes: applying a first programming pulse to a word line of a selected memory cell to perform first programming on the selected memory cell; performing a programming verification on the memory cell that has undergone the first programming; wherein, when the programming verification is the first verification in the current programming cycle, a first verification is performed based on a first sensing duration; when the programming verification is not the first verification in the current programming cycle, a second verification is performed based on a second sensing duration; the second sensing duration is different from the first sensing duration.

Description

Technical Field

[0001] This application relates to the field of memories, and in particular, but not limited to, a memory and an operation method thereof. Background Art

[0002] According to the characteristics of semiconductor memories, they can be classified into volatile memories that lose the data stored therein when the power is turned off, and non-volatile memories that do not lose the data stored therein when the power is turned off. Volatile memories can have fast programming and reading speeds, but cannot store data for a long time; non-volatile memories can achieve long-term data storage, but have relatively slow programming and reading speeds.

[0003] Affected by the process and the inherent characteristics of the device structure, the programming effects of different memory cells during the programming of non-volatile memories are uneven, making it difficult to achieve the desired programming and verification effects. Summary of the Invention

[0004] In view of this, embodiments of this application provide a memory and an operation method thereof.

[0005] In a first aspect, embodiments of this application provide an operation method of a memory, the method including:

[0006] Applying a first programming pulse to the word line of the selected memory cell to perform first programming on the selected memory cell;

[0007] Performing programming verification on the memory cell that has undergone the first programming; wherein,

[0008] When the programming verification is the first verification in the current programming cycle, performing the first verification based on a first sensing duration;

[0009] When the programming verification is not the first verification in the current programming cycle, performing a second verification based on a second sensing duration; the second sensing duration is different from the first sensing duration.

[0010] In some embodiments, the first sensing duration is less than the second sensing duration.

[0011] In some embodiments, the programming verification includes at least two verifications: a first programming verification and a second programming verification, where the first programming verification is the first verification in the current programming cycle;

[0012] Performing programming verification on the memory cell that has undergone the first programming includes:

[0013] Applying a first verification voltage to the word line of the memory cell that has undergone the first programming, and performing the first programming verification based on the first sensing duration;

[0014] Apply a second verification voltage to the word line of the memory cell that has undergone the first programming, and perform the second programming verification based on the second sensing duration.

[0015] In some embodiments, the second verification voltage is greater than the first verification voltage.

[0016] In some embodiments, the memory cell that has undergone the first programming includes a first memory cell and a second memory cell, where the first memory cell and the second memory cell are memory cells with different programmed target states;

[0017] Performing the first verification based on the first sensing duration includes performing a first programming verification on the first memory cell based on the first sensing duration;

[0018] Performing the second verification based on the second sensing duration includes performing a second programming verification on the second memory cell based on the second sensing duration.

[0019] In some embodiments, the at least two verifications further include a third programming verification, and the third programming verification is performed after the first programming verification and the second programming verification;

[0020] Performing a programming verification on the memory cell that has undergone the first programming further includes:

[0021] Apply a third verification voltage to the word line of the memory cell that has undergone the first programming, and perform the third programming verification based on the third sensing duration; where the third sensing duration is different from the first sensing duration.

[0022] In some embodiments, the third sensing duration is the same as the second sensing duration.

[0023] In some embodiments, the programming verification only includes one verification: a fourth programming verification; performing a programming verification on the memory cell that has undergone the first programming includes:

[0024] Performing a fourth programming verification based on the first sensing duration.

[0025] On the other hand, embodiments of the present application further provide a memory, characterized by including:

[0026] A memory cell array including a plurality of memory cells;

[0027] A peripheral circuit configured to:

[0028] Apply a first programming pulse to the word line of the selected memory cell to perform a first programming on the selected memory cell;

[0029] Perform a programming verification on the memory cell that has undergone the first programming; where,

[0030] When the programming verification is the first verification in the current programming cycle, a first verification is performed based on a first sensing duration;

[0031] When the programming verification is not the first verification in the current programming cycle, a second verification is performed based on a second sensing duration; the second sensing duration is different from the first sensing duration.

[0032] In some embodiments, the multiple storage units include a first storage unit and a second storage unit;

[0033] Performing the first verification based on the first sensing duration includes performing a first programming verification on the first storage unit based on the first sensing duration;

[0034] Performing the second verification based on the second sensing duration includes performing a second programming verification on the second storage unit based on the second sensing duration.

[0035] The technical solution provided by the embodiments of the present application can perform one or more verifications on the storage units after programming the memory. For multiple verifications, different programming states are targeted and different sensing durations are used. In this way, on the one hand, the accuracy and comprehensiveness of the verification can be improved; on the other hand, using different sensing durations for verification can reduce the impact of the verification process on storage units in different states and improve the quality of programming. Description of the Drawings

[0036] Figure 1 It is a flowchart of a programming method for a memory provided by an embodiment of the present application;

[0037] Figure 2 It is a schematic diagram of incremental step pulse programming provided by an embodiment of the present application;

[0038] Figure 3 It is an optional schematic diagram of the threshold voltage distribution of a storage unit provided by an embodiment of the present application;

[0039] Figure 4 It is an optional schematic diagram of the threshold voltage distribution of a storage unit provided by an embodiment of the present application;

[0040] Figure 5 It is an optional schematic diagram of the threshold voltage distribution of a storage unit provided by an embodiment of the present application;

[0041] Figure 6 It is a flowchart of a verification based on different sensing durations provided by an embodiment of the present application;

[0042] Figure 7 It is a flowchart of a verification based on different sensing durations provided by an embodiment of the present application;

[0043] Figure 8 Schematic diagram of a memory provided by an embodiment of the present application. Detailed implementation manners

[0044] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the description of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0046] As Figure 1 shown, an embodiment of the present application provides a programming method for a memory, and the method includes:

[0047] Step S101: Apply a first programming pulse to the word line of the selected memory cell to perform first programming on the selected memory cell;

[0048] Step S102: Perform programming verification on the memory cell that has undergone the first programming; wherein, step S102 may include the following two situations:

[0049] When the programming verification is the first verification in the current programming cycle, perform first verification based on a first sensing duration;

[0050] When the programming verification is not the first verification in the current programming cycle, perform second verification based on a second sensing duration; the second sensing duration is different from the first sensing duration.

[0051] In the embodiment of the present application, due to process deviations and performance differences of the memory cells themselves, different threshold voltages may be reached after each application of the programming voltage, and thus different programming states may be entered. Therefore, the memory cell can be verified one or more times after each application of the programming pulse to determine whether the memory cell has been programmed into the target state. And, since the target states of different memory cells are different, programming can be performed through multiple programming cycles, and one to multiple verifications are performed after each programming cycle. For the memory cells that have passed the verification and have entered the target state, programming can be prohibited, and the programming and verification cycles can continue for other memory cells that have not entered the target state.

[0052] Considering that the verification voltages for different states are different, the induction durations used in the verification process can be different. In the embodiments of the present application, the induction durations corresponding to the first programming verification (i.e., the above-mentioned first verification) and the non-first programming verification after applying the programming pulses in each programming cycle can be different. In one embodiment, the first induction duration is less than the second induction duration. That is, the induction duration for the first programming verification is shorter, and such verification conditions are relatively loose, that is, there is a larger margin. For the non-first programming verification, a longer verification duration is used to ensure the accuracy of the verification, that is, to immediately prohibit the continued programming of the memory cells that have reached the target state.

[0053] In this way, on the one hand, the programming efficiency can be improved, and on the other hand, considering the performance of different memory cells, flexible verification can be performed, thereby reducing the occurrence of programming errors.

[0054] In some embodiments, the programming verification includes at least two verifications: the first programming verification and the second programming verification, where the first programming verification is the first verification in the current programming cycle;

[0055] The programming verification for the memory cells that have undergone the first programming further includes:

[0056] Applying a first verification voltage to the word line of the memory cells that have undergone the first programming, and performing the first programming verification based on the first induction duration;

[0057] Applying a second verification voltage to the word line of the memory cells that have undergone the first programming, and performing the second programming verification based on the second induction duration.

[0058] In one embodiment, the second verification voltage is greater than the first verification voltage.

[0059] Exemplarily, a first programming pulse can be applied to the word line of the memory cell to be programmed to perform the first programming on the memory cell; at least two verification pulses are sequentially applied to the word line of the memory cell to verify at least two states of the memory cell; wherein, different induction durations are used when verifying the at least two states; and according to the verification results of the at least two states, the second programming is performed.

[0060] In some embodiments, the first-programmed storage cells include a first storage cell and a second storage cell, where the first storage cell and the second storage cell are storage cells with different programmed target states (i.e., different target states). The first verification based on the first sensing duration includes performing a first programming verification on the first storage cell based on the first sensing duration; the second verification based on the second sensing duration includes performing a second programming verification on the second storage cell based on the second sensing duration. Specifically, during verification, the memory has obtained the target states of the first storage cell and the second storage cell. Therefore, during verification, the verification voltages corresponding to their respective target states can be directly applied to the first storage cell and the second storage cell for verification; if the verification voltages applied to the selected storage cells during the verification stage in the current programming cycle do not include the verification voltages corresponding to the target states of the first storage cell and the second storage cell, then the first storage cell and the second storage cell are not verified. If the verification voltages applied to the selected storage cells during the verification stage in the current programming cycle include the verification voltage corresponding to the target state of the first storage cell but do not include the verification voltage corresponding to the target state of the second storage cell, then the first storage cell is verified, but the second storage cell is not verified. If the verification voltages applied to the selected storage cells during the verification stage in the current programming cycle include the verification voltage corresponding to the target state of the second storage cell but do not include the verification voltage corresponding to the target state of the first storage cell, then the second storage cell is verified, but the first storage cell is not verified.

[0061] In some other embodiments, the at least two verifications further include a third programming verification, and the third programming verification is performed after the first programming verification and the second programming verification;

[0062] Performing a programming verification on the first-programmed storage cells further includes:

[0063] Applying a third verification voltage to the word line of the first-programmed storage cells, and performing the third programming verification based on the third sensing duration; where the third sensing duration is different from the first sensing duration.

[0064] In one embodiment, the third sensing duration is the same as the second sensing duration. That is to say, for different storage cells, there can be one to multiple programming verifications in a programming cycle. Among them, for the first programming verification in a programming, the first sensing duration can be used, and for non-first programming verifications, the same sensing duration can be used.

[0065] It should be noted that the third sensing duration and the second sensing duration can also be different. Specifically, both the third sensing duration and the second sensing duration are less than the first sensing duration.

[0066] Correspondingly, in one embodiment, the programming verification only includes one verification: the fourth programming verification; performing programming verification on the memory cell after the first programming includes:

[0067] Performing the fourth programming verification based on the first sensing duration.

[0068] In one embodiment, one programming process includes multiple programming verification loops, and each programming verification loop includes at least one verification operation; the first verification step in all programming verification loops uses the same sensing duration, for example, it can be the first sensing duration. The sensing durations of the second verification operations in all programming verification loops including at least 2 verification operations are the same, for example, it can be the second sensing duration. The sensing durations of the first verification operation and the second verification operation in all programming verification loops including at least 2 verification operations are different.

[0069] It should be noted that the memory involved in the embodiments of the present application refers to a memory device that can perform operations such as programming, reading, and erasing data. For example: NAND flash memory (NAND Flash Memory), NOR flash memory (NOR Flash Memory), dynamic random access memory (Dynamic Random Access Memory, DRAM), ferroelectric random access memory (Ferroelectric Random Access Memory, FRAM), magnetoresistive random access memory (Magnetoresistive Random Access Memory, MRAM), phase change random access memory (Phase Change Random Access Memory, PCRAM), or resistive random access memory (Resistive Random Access Memory, RRAM), etc. The memory device may include a memory cell array and control logic. Among them, operations such as reading / writing and verification of the memory cell array can be controlled through multiple word lines (Word Line, WL) and multiple bit lines (Bit Line, BL). Each memory cell is connected to a corresponding word line and bit line. The bit line signal can be applied to the source electrode of the memory cell, and the word line signal can be applied to the gate electrode of the memory cell. Here, the memory cell can be a non-volatile memory cell.

[0070] Each memory cell can be a multi-level cell (MLC) that stores 2 bits of data, a triple-level cell (TLC) that stores 3 bits of data, or a quad-level cell (QLC) that stores 4 bits of data. However, the embodiments of the present application are not limited thereto. Exemplarily, some memory cells can be MLCs, while some other memory cells can be TLCs. It should be noted that the above MLC, TLC, and QLC are induced based on a single-level cell (SLC). Specifically, an SLC can include an erased state "1" and a programmed state "0", and an MLC can include an erased state "11", a first state "10", a second state "00", and a third state "01".

[0071] In the embodiments of the present application, the programming method adopted for the selected memory cells in the memory can be incremental-step-pulse programming (ISPP), and the programming of the memory cells is completed by pulse writing and applying a verification critical voltage. Exemplarily, when data needs to be programmed into a memory cell, programming can be performed through a set initial programming pulse. After the pulse ends, the programmed memory cell is verified through a verification voltage to determine whether the memory cell has entered the target programming state. If the memory cell has not reached the current target programming state, that is, it is still in the state before the target programming state, an adjustment value ΔV of the incremental-step-pulse programming will be added to the currently applied initial pulse voltage as a new pulse voltage, and a new round of programming and verification will be performed on the above memory cell according to the new pulse voltage and pulse time until the memory cell is programmed to the correct state, that is, the data is correctly written into the corresponding memory cell.

[0072] In the embodiments of the present application, each memory cell needs to be programmed to its respective required target state, which needs to be achieved through several programming stages. Each programming stage is used to enable the selected memory cells to reach one of multiple programming states respectively until all the above-selected memory cells reach their respective required target states. In the first programming stage, before the initial programming, all memory cells are in the erased state, and then a first programming pulse is applied to perform a programming operation on the selected memory cells. It should be noted that the programming stage in the embodiments of the present application can include multiple programming verification loops, such as two programming verification loops or three programming verification loops, so that the memory cells are programmed to the next state. Among them, a programming verification loop can include one programming operation and at least one verification operation.

[0073] After a programming operation, a verification operation is required. Two verifications can be performed here. The first verification is to determine whether the selected storage cells have reached the programmed state corresponding to the verification voltage of the first verification. If the programmed state corresponding to the verification voltage is the final target state of some storage cells, then if the verification passes, the second verification is not performed on these storage cells, and programming of these storage cells is prohibited during subsequent programming processes. If the verification passes, but the programmed state corresponding to the verification voltage is not the target state of the selected storage cells, then the second programming is continued. If the verification fails, the second programming can be performed on the storage cells that failed the verification. In the above verification, a second verification can also be performed immediately after the first verification. The verification voltage of the second verification corresponds to a different state from the verification voltage of the first verification. Specifically, the verification voltage of the second verification is the next state corresponding to the verification voltage of the first verification. If the verification voltage corresponding to the second verification is the verification voltage of the target state of the storage cells, then if these storage cells pass the second verification, it means they have entered the target state. Therefore, programming of these storage cells can be prohibited throughout subsequent programming stages.

[0074] It should be noted that the above second programming refers to the next programming after the first programming, which can be the programming in the next programming stage or the programming of applying the next programming pulse in the same programming stage as the first programming.

[0075] In this way, when all the storage cells to be programmed have passed the first state, the verification operation corresponding to the first state can be ended. After the next programming stage, the verification operation of the first state is no longer performed, but the storage cells that need to be programmed to the second state or higher states are programmed. For example, there are 64 storage cells to be programmed, among which 32 are to be programmed to the third state (the first group), 16 are to be programmed to the second state (the second group), and another 16 are to be programmed to the first state (the third group). In this way, in the first programming stage, all 64 storage cells are programmed, and through at least one verification and application of the programming voltage until all the storage cells to be programmed enter the first state. Then enter the second programming stage, and perform the programming and verification processes on all the storage cells in the first group and the second group until they all enter the second state, and synchronously prohibit programming of the storage cells in the third group. Then enter the third programming stage, and continue the programming and verification processes on the first group until they all enter the third state, and synchronously prohibit programming of the storage cells in the second group and the third group.

[0076] Such as Figure 2As shown, in the first programming stage, at least one verification is performed after each application of a programming pulse. For example, when the programming pulse is small and no memory cell in the selected memory cells has entered the second state, only the verification of the first state Vv1 can be performed; when the programming pulse is large and some memory cells may enter the second state, then the verification of the first state Vv1 and the verification of the second state Vv2 need to be performed. Among them, if the verification of the first state fails, the programming pulse is repeatedly applied in this programming stage. At this time, the verification of the second state is to find the memory cells that have reached the first state and entered a higher state (for example, they can be fast cells). If the verification of the first state passes, the second programming stage is entered, and the programming pulse is continuously applied, and the verification of the second state Vv2 and the third state Vv3 are performed. This cycle continues, and in this cycle, it is necessary to determine whether a new cycle can be entered based on the verification Vv2 of the second state.

[0077] Exemplarily, taking a double-layer memory cell that can store 2-bit data as an example, it corresponds to four states, namely the erased state "11", the first state "10", the second state "01", and the third state "00". Among them, the threshold voltages corresponding to the above four states increase in sequence. Therefore, the programming pulses required to program to the corresponding states increase in sequence. It should be noted that the values corresponding to the first state to the third state here are only examples, and they can also be other values. For example, the first state is "01" and the second state is "10", which can be specifically set according to requirements. Before programming, all memory cells are set to the erased state, that is, the threshold voltage corresponding to the erased state of the memory cell is less than the threshold voltage corresponding to the first state "10". Then, a programming operation is performed on the selected memory cells in the memory, and electrons in the conductive channel can be injected into the charge storage layer or the floating gate of the memory cell, so that these memory cells are programmed to the corresponding target programming state. If the target programming state of the memory cell is the first state, then through programming, the threshold voltage of the memory cell is to be made greater than the threshold voltage corresponding to the first state "10", so that the data in the memory cell changes from "11" to "10", that is, the programming of the selected memory cell in this programming stage is completed.

[0078] It should be noted that the programming pulses applied in the embodiments of the present application can be on the word lines corresponding to one or more pages of memory cells. Among them, some memory cells only need to be programmed to the first state "10" (that is, the target programming state of these memory cells is the first state), and some memory cells need to be programmed to the third state "00" (that is, the target programming state of these memory cells is the third state). Here, it is necessary to first program all the memory cells to be programmed to the first state "10". In the next programming cycle, the memory cells that have been programmed to the first state "10" (the target state of this memory cell is the first state) are prohibited from being programmed, and other memory cells continue to be programmed to the second state "01" and finally to the third state "00".

[0079] After programming the memory cell, verification is performed. Common verification includes stages such as precharging, sensing, and reading. Among them, in the precharging stage, a voltage can be applied to the bit line through devices such as a voltage generator or a sense amplifier, so as to generate a voltage difference between the bit line and the substrate, that is, between the source and the drain, so that the threshold voltage of the memory cell can be detected according to the change of the voltage subsequently, and then it can be judged whether the verification passes the corresponding programming state. The voltage precharged to the bit line can be changed corresponding to the target programming state of the selected memory cell. The sensing stage corresponds to the process of discharging the bit line and is used to sense the change of the bit line voltage to judge whether the verification passes. The reading stage is to read the verification state into the latch through the sensing circuit connected to the bit line for subsequent interaction with the memory controller. Exemplarily, when verifying the memory cell in the first state, a first verification voltage needs to be applied to the word line corresponding to the memory cell. Here, when the threshold voltage of the programmed memory cell is greater than the above first verification voltage, the memory cell has been programmed to the first state (or has reached the first state); on the contrary, when the threshold voltage of the programmed memory cell is less than the above first verification voltage, the memory cell has not been programmed to the first state and needs to perform the next round of programming and verification. It should be noted that the first state here can be any one of the above first state to the third state, or other target programming states.

[0080] It should be noted that during the programming and verification process, the duration of the sensing stage will affect the verification result. The sensing durations (such as the first sensing duration, the second sensing duration) mentioned in the embodiments of the present application all refer to the duration of the sensing stage in the verification operation of one programming verification cycle. Exemplarily, the first state P n (where n is a positive integer) is the next state of the erased state E, as Figure 3 shown, when the sensing duration is short, only a small number of memory cells reach the first state P n , resulting in a small margin between the first state P n and the erased state E, thus generating an odd-sided margin loss; for example, if the threshold voltage distributions of the programmed memory cells are relatively scattered, then the difference between the minimum threshold voltage of the memory cells in the first state P n and the threshold voltage corresponding to the erased state is small, and such memory cells are prone to read errors during reading. As Figure 4 shown, when the sensing duration is long, more memory cells reach the first state P n , although the first state P nThe margin interval from the erased state E will increase, but some unprogrammed memory cells will be affected, resulting in the loss of the boundary of the erased state E. Exemplarily, for the memory cells in the erased state E, no programming operation is required. However, since multiple programming pulses are applied to the memory cells to be programmed, this will cause the threshold voltage distribution of some memory cells in the erased state E to drift due to the influence of multiple programming voltages. Here, Figure 3 and Figure 4 Vr1 and Vr2 shown respectively refer to the read voltages of the first state P n and the second state P n+1 ; Vv1 and Vv2 respectively refer to the verification voltages of the first state P n and the second state P n+1 .

[0081] Therefore, in the embodiments of the present application, as Figure 5 shown, verifying the first state P n of the memory cells based on a shorter sensing duration can effectively reduce the boundary loss; verifying the second state P n+1 of the memory cells based on a longer sensing duration can increase the margin interval between adjacent states. The second state P n+1 here is the programming state adjacent to the first state P n , and it refers to the programming state in which more electrons are injected into the charge storage layer or floating gate of the memory cells after verification passes. For example, the second state "10" (the second state P n+1 ) of the above MLC is the programming state adjacent to the first state "01" (the first state P n ); the third state "11" (the second state P n+1 ) is the programming state adjacent to the second state "10" (the first state P n ). Finally, according to whether the above memory cells reach the first state P n and / or whether they reach the second state P n+1 , the next round of programming is performed. Similarly, Figure 5 Vr1 and Vr2 shown respectively refer to the read voltages of the first state P n and the second state P n+1 ; Vv1 and Vv2 respectively refer to the verification voltages of the first state P n and the second state P n+1 .

[0082] In summary, for the programming method of the memory provided in the embodiments of the present application, on the one hand, in one programming verification cycle, after the programming operation is performed, two verification pulses are applied separately for verification. The verification voltages corresponding to these two verification pulses can be the verification voltages of the first state and the second state respectively (i.e., the verification voltages corresponding to two adjacent states), and these two verifications can have different sensing durations, so as to facilitate better verification effects for each state. In another embodiment, multiple verifications can also be performed, and each verification has a different verification voltage. When performing verification, it can be first determined whether the current verification is the first verification in the current cycle. If it is the first verification, the first sensing duration is selected. If it is not the first verification, the second sensing duration can be selected. In addition, if there are multiple verifications, different sensing durations can also be used, which is not limited in the embodiments of the present application and can be flexibly set in practical applications.

[0083] After the programming pulse of the first programming and multiple verifications are completed, subsequent second programming is performed according to the verification results. In this way, on the one hand, the accuracy and comprehensiveness of verification can be improved; on the other hand, based on different sensing durations, multiple verifications are performed after each programming, which can reduce the influence of the verification process on memory cells in different states, facilitate subsequent corresponding processing of different memory cells, and thus improve the quality of programming.

[0084] It should be noted that in the embodiments of the present application, passing the verification means that the number of memory cells in the memory that enter the state corresponding to the verification meets a predetermined condition. As Figure 2 shown, the overall programming of the memory in the embodiments of the present application can include multiple programming stages, and each programming stage can include multiple programming verification cycles, so that the memory cells are programmed to the next state. Among them, one programming verification cycle can include one programming operation and at least one verification operation. After each programming verification cycle is completed, an adjustment value ΔV of the incremental step pulse can be added to the next programming pulse.

[0085] In some embodiments, the method further includes:

[0086] During the process of performing the second programming, determine the number of failed bits in the first state.

[0087] Generally, after the verification of the selected memory cells is completed, a round of failed bit count (FBC) needs to be performed to count the number of memory cells that fail to pass the verification in the corresponding verification programming state during this programming operation, so as to make timely adjustments (reprogramming), otherwise relevant data will be lost, which will have an adverse impact on the entire memory. However, performing error bit statistics will take time, thus increasing the programming time.

[0088] In the embodiments of the present application, when performing the next programming operation, the statistics of the number of failed bits in the first verification can be synchronously performed. The above-mentioned second programming is the next programming operation of the first programming. Since the statistics of the number of failed bits are performed after the first verification passes, it does not affect the number of failed bits of the first programming itself, and the programming operation can be performed simultaneously, thus greatly reducing the overall programming time and improving the programming efficiency.

[0089] The embodiments of the present application adopt variable sensing durations to verify different states of different memory cells, which can reduce the overall programming time and improve the programming accuracy.

[0090] In some embodiments, verifying the memory cells to be verified includes:

[0091] Pre-charging the bit line connected to the memory cell to a first line potential voltage;

[0092] Applying a verification voltage to the word line corresponding to the memory cell;

[0093] Based on the sensing duration corresponding to the verification, detecting the induced voltage of the induced node on the bit line; and determining whether the verification passes according to the change of the induced voltage.

[0094] The verification process is mainly determined by sensing the change of the voltage of the induced node corresponding to the bit line connected to the selected memory cell. Among them, the voltage of this induced node changes with the current flowing through the selected memory cell.

[0095] It should be noted that during the sensing stage, the induced voltage on the sensing node SO corresponding to the bit line will change accordingly. The SO node here is a node located in the page buffer. Exemplarily, if the induced voltage corresponding to the memory cell drops below the set voltage within the sensing time, the verification of the memory cell fails; if the induced voltage corresponding to the memory cell does not drop below the set voltage within the sensing time, it indicates that the verification of the memory cell is successful. It can also be understood that within the sensing time, the linear drop rate of the induced voltage corresponding to the memory cell that fails to be verified is faster than that of the induced voltage corresponding to the memory cell that is successfully verified.

[0096] The embodiments of the present application also provide the following examples:

[0097] If a shorter sensing duration is adopted, it will cause boundary loss at the odd side of the memory cell; if a longer sensing duration is adopted, it is difficult for the high state (the second state) to pass, and it will cause a longer programming time and a margin loss of the low state (erase state).

[0098] When the memory performs the verification of the P n state, Pn+1 The verification of the state will be completed in the following sequence, and this subsequence can be named P n+1 -sub state. Therefore, for P n state and P n+1 -sub state verification, different sensing durations can be flexibly applied. Exemplarily, as Figure 6 shown, after the verification starts, first use the first sensing duration, that is, a shorter sensing duration, to verify the selected storage unit. Then, determine whether it is necessary to verify the next state, where the next state is the state adjacent to the current verification state P n . If the next state needs to be verified, use the second sensing duration, that is, a longer sensing duration, to verify the next state of the selected storage unit; if the next state does not need to be verified, the current verification ends. It should be noted that the verification of the current verification state P n and the next state are both located in the same programming verification loop. If the verification ends, continue with the next round of programming verification loop.

[0099] In some other embodiments, as Figure 7 shown, after the verification starts, first determine whether to verify the P n state. If so, use the first sensing duration, that is, a shorter sensing duration, to verify the selected storage unit; if not, use the second sensing duration, that is, a longer sensing duration, to verify the P n+1 -sub state of the selected storage unit. After the verification of the P n state and the P n+1 -sub state of the selected storage unit is completed, sense the verification result. Finally, the verification corresponding to this round of programming ends. Here, using a shorter sensing duration (the first sensing duration) in the verification of the P n state can reduce the number of programming pulses required, thereby improving the margin of the above low state; using a longer sensing duration (the second sensing duration) in the verification of the P n+1 -sub state can obtain a larger boundary margin at the odd edge.

[0100] Furthermore, the number of failed bits of the P n state can be hidden in the next programming pulse after the P n state verification passes. In this way, the boundary loss at the odd edge caused by the short sensing duration during the P n state verification can be compensated.

[0101] Therefore, in the embodiments of the present application, in the P n state and P n+1Applying a flexible sensing duration in the verification of the -sub state can compensate for the boundary loss at the odd edges and the margin loss in the low state; and hide the failure bit count statistics in P n In the next programming pulse after the state verification passes, the programming time can be reduced and the programming efficiency can be improved.

[0102] Such as Figure 8 As shown, an embodiment of the present application provides a memory 10, and the memory 10 includes:

[0103] A memory cell array 200, including a plurality of memory cells 210;

[0104] A peripheral circuit 300, configured to:

[0105] Apply a first programming pulse to the word line of the selected memory cell to perform first programming on the selected memory cell;

[0106] Perform programming verification on the memory cell that has undergone the first programming; wherein,

[0107] When the programming verification is the first verification in the current programming cycle, perform the first verification based on the first sensing duration;

[0108] When the programming verification is not the first verification in the current programming cycle, perform the second verification based on the second sensing duration; the second sensing duration is different from the first sensing duration.

[0109] In the embodiment of the present application, operations such as reading / writing and verification of the memory cell array can be controlled through multiple word lines and multiple bit lines, and each memory cell is connected to a corresponding word line and bit line. The bit line signal can be applied to the source of the memory cell through the peripheral circuit, and the word line signal can be applied to the gate of the memory cell through the peripheral circuit. The memory cell here can be a non-volatile memory cell.

[0110] In some embodiments, the plurality of memory cells include a first memory cell and a second memory cell;

[0111] The performing the first verification based on the first sensing duration includes performing a first programming verification on the first memory cell based on the first sensing duration;

[0112] The performing the second verification based on the second sensing duration includes performing a second programming verification on the second memory cell based on the second sensing duration.

[0113] Due to inherent characteristics and process offsets, the memory cells in a memory cell array can generally be divided into fast cells and slow cells. In the embodiments of the present application, the slow cells are the key factors affecting whether programming and verification pass. Therefore, after the first programming, according to the verification results of at least two states, the peripheral circuit needs to perform a second programming on the memory cells other than those that have entered the second state, which can improve the accuracy of programming.

[0114] The features disclosed in several method or device embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0115] As described above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A method for operating a memory, characterized in that, The method includes: Applying a first programming pulse to a word line of a selected memory cell to perform first programming on the selected memory cell; Performing a programming verification on the memory cell after the first programming; wherein, When the programming verification is the first verification in the current programming cycle, performing a first verification based on a first sensing duration; When the programming verification is not the first verification in the current programming cycle, performing a second verification based on a second sensing duration; the second sensing duration is different from the first sensing duration, and the programming states of the memory cells verified by the first verification and the programming states of the memory cells verified by the second verification are different.

2. The method according to claim 1, characterized in that, The first sensing duration is less than the second sensing duration.

3. The method according to claim 1, wherein The programming verification includes at least two verifications: a first programming verification and a second programming verification, wherein the first programming verification is the first verification in the current programming cycle; Performing a programming verification on the memory cell after the first programming includes: Applying a first verification voltage to the word line of the memory cell after the first programming and performing the first programming verification based on the first sensing duration; Applying a second verification voltage to the word line of the memory cell after the first programming and performing the second programming verification based on the second sensing duration.

4. The method according to claim 3, characterized in that, The second verification voltage is greater than the first verification voltage.

5. The method according to claim 1, characterized in that, The memory cell after the first programming includes a first memory cell and a second memory cell, wherein the first memory cell and the second memory cell are memory cells with different programming target states; Performing the first verification based on the first sensing duration includes performing a first programming verification on the first memory cell based on the first sensing duration; Performing the second verification based on the second sensing duration includes performing a second programming verification on the second memory cell based on the second sensing duration.

6. The method according to claim 3, wherein The at least two verifications further include a third programming verification, and the third programming verification is performed after the first programming verification and the second programming verification; Performing a programming verification on the memory cell after the first programming further includes: Applying a third verification voltage to the word line of the memory cell after the first programming and performing the third programming verification based on a third sensing duration; wherein the third sensing duration is different from the first sensing duration.

7. The method according to claim 6, characterized in that, The third sensing duration is the same as the second sensing duration.

8. The method according to claim 1, wherein The programming verification only includes one verification: a fourth programming verification; performing a programming verification on the memory cell after the first programming includes: Performing a fourth programming verification based on the first sensing duration.

9. A memory, characterized in that, Includes: A memory cell array including a plurality of memory cells; A peripheral circuit configured to: Apply a first programming pulse to a word line of a selected memory cell to perform first programming on the selected memory cell; Perform a programming verification on the memory cell after the first programming; wherein, When the programming verification is the first verification in the current programming cycle, perform a first verification based on a first sensing duration; When the programming verification is not the first verification in the current programming cycle, a second verification is performed based on a second sensing duration; the second sensing duration is different from the first sensing duration, and the programming states of the memory cells verified by the first verification and the programming states of the memory cells verified by the second verification are different.

10. The memory according to claim 9, wherein The plurality of memory cells includes a first memory cell and a second memory cell; The performing the first verification based on the first sensing duration includes performing a first programming verification on the first memory cell based on the first sensing duration; The performing the second verification based on the second sensing duration includes performing a second programming verification on the second memory cell based on the second sensing duration.

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