Shift register unit and display panel

Abstract

This disclosure relates to the field of display technology, and proposes a shift register unit and a display panel. The shift register unit includes an input circuit, a potential sustaining circuit, a first pull-down circuit, and an output circuit. The input circuit is used to transmit the input signal to a first node in response to a signal from a first clock signal terminal, or to transmit the signal from a first power supply terminal to a second node in response to the signal from the first clock signal terminal. The potential sustaining circuit is used to transmit the signal from a second power supply terminal to a third node in response to the signals from the first power supply terminal and the first node. The first pull-down circuit is used to transmit the signal from the second clock signal terminal to a fourth node in response to the signals from the second node and the second clock signal terminal. The output circuit is used to transmit the signal from the first power supply terminal to an output terminal in response to the signal from the third node, or to transmit the signal from the third power supply terminal to an output terminal in response to the signal from the fourth node. The potential sustaining circuit enables the output circuit to output a stable low-level signal.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a shift register unit and a display panel. Background Technology

[0002] In related technologies, the output signal denoising method of the pulse width modulation (PWM) GOOA unit involves coupling the gate potential of the denoising transistor with the clock signal, causing the gate potential of the denoising transistor to be pulled low, thereby turning on the transistor for output. This denoising method is affected by the clock signal frequency. Especially when driven at low frequencies, the turn-on time of the denoising transistor is relatively short, causing the output of the denoising transistor to be floating, thus affecting the stability of the output signal of the denoising transistor.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a shift register unit and a display panel.

[0005] According to one aspect of this disclosure, a shift register unit is provided, comprising: an input circuit connected to an input terminal, a first power supply terminal, a first clock signal terminal, a first node, and a second node, wherein the input circuit is configured to transmit a signal from the input terminal to the first node in response to a signal from the first clock signal terminal, or to transmit a signal from the first power supply terminal to the second node in response to a signal from the first clock signal terminal; a potential sustaining circuit connected to the first node, a third node, the first power supply terminal, and the second power supply terminal, wherein the potential sustaining circuit is configured to transmit a signal from the second power supply terminal to the third node in response to a signal from the first power supply terminal and a signal from the first node; a first pull-down circuit connected to the second node, a fourth node, and the second clock signal terminal, wherein the first pull-down circuit is configured to transmit a signal from the second clock signal terminal to the fourth node in response to a signal from the second node and a signal from the second clock signal terminal; and an output circuit connected to the third node, the fourth node, the first power supply terminal, the third power supply terminal, and an output terminal, wherein the output circuit is configured to transmit a signal from the first power supply terminal to the output terminal in response to a signal from the third node, or to transmit a signal from the third power supply terminal to the output terminal in response to a signal from the fourth node.

[0006] In one exemplary embodiment of this disclosure, the potential maintenance circuit includes: an eleventh transistor, with a first terminal connected to the first node, a second terminal connected to the third node, and a control terminal connected to the first power supply terminal; and a fifth transistor, with a first terminal connected to the third node, a second terminal connected to the second power supply terminal, and a control terminal connected to the first node.

[0007] In one exemplary embodiment of this disclosure, the potential maintenance circuit includes: an eleventh transistor, with a first terminal connected to the first node, a second terminal connected to the third node, and a control terminal connected to the first power supply terminal; a fifth transistor, with a first terminal connected to the third node, a second terminal connected to the fifth node, and a control terminal connected to the first node; and a fourth transistor, with a first terminal connected to the fifth node, and a second terminal and a control terminal connected to the second power supply terminal.

[0008] In one exemplary embodiment of this disclosure, the conduction level of the second power supply terminal is lower than the conduction level of the first power supply terminal.

[0009] In one exemplary embodiment of this disclosure, the conduction level of the third node is greater than the conduction level of the second power supply terminal and less than the conduction level of the first power supply terminal.

[0010] In one exemplary embodiment of this disclosure, the input circuit includes: a first sub-input circuit connected to an input terminal, a first clock signal terminal, and a first node, wherein the first sub-input circuit is configured to transmit a signal from the input terminal to the first node in response to a signal from the first clock signal terminal; a second sub-input circuit connected to the first clock signal terminal, a first power supply terminal, and a second node, wherein the second sub-input circuit is configured to transmit a signal from the first power supply terminal to the second node in response to a signal from the first clock signal terminal; and a second pull-down circuit connected to the first node, the second node, and the first clock signal terminal, wherein the second pull-down circuit is configured to transmit a voltage from the first clock signal terminal to the second node in response to a signal from the first node.

[0011] In an exemplary embodiment of this disclosure, the first sub-input circuit includes: a first transistor, with a first end connected to the input terminal, a second end connected to the first node, and a control terminal connected to the first clock signal terminal; the second sub-input circuit includes: a second transistor, with a first end connected to the first power supply terminal, a second end connected to the second node, and a control terminal connected to the first clock signal terminal; the second pull-down circuit includes: a third transistor, with a first end connected to the first clock signal terminal, a second end connected to the second node, and a control terminal connected to the first node; the first pull-down circuit includes: a sixth transistor, with a first end connected to the second clock signal terminal, a second end connected to the sixth node, and a control terminal connected to the second node; a second capacitor connected between the second node and the sixth node; and a seventh transistor, with a first end connected to the sixth node, a second end connected to the fourth node, and a control terminal connected to the second clock signal terminal.

[0012] In one exemplary embodiment of this disclosure, the output circuit includes: a first sub-output circuit connected to the third node, the output terminal, and the first power supply terminal, wherein the first sub-output circuit is configured to transmit a signal from the first power supply terminal to the output terminal in response to a signal from the third node; a second sub-output circuit connected to the fourth node, the third power supply terminal, and the output terminal, wherein the second sub-output circuit is configured to transmit a signal from the third power supply terminal to the output terminal in response to a signal from the fourth node; and a first pull-up circuit connected to the third node, the third power supply terminal, and the fourth node, wherein the first pull-up circuit is configured to transmit a signal from the third power supply terminal to the fourth node in response to a signal from the third node.

[0013] In one exemplary embodiment of this disclosure, the first sub-output circuit includes: a tenth transistor, with a first terminal connected to the first power supply terminal, a second terminal connected to the output terminal, and a control terminal connected to the third node; the second sub-output circuit includes: a ninth transistor, with a first terminal connected to the output terminal, a second terminal connected to the third power supply terminal, and a control terminal connected to the fourth node; a first capacitor connected between the fourth node and the third power supply terminal; and the first pull-up circuit includes: an eighth transistor, with a first terminal connected to the third power supply terminal, a second terminal connected to the fourth node, and a control terminal connected to the third node.

[0014] According to another aspect of this disclosure, a display panel is also provided, including a gate driving circuit, the gate driving circuit including a plurality of cascaded shift register units as described in any embodiment of this disclosure.

[0015] The shift register unit provided in this disclosure, by setting a potential maintenance circuit between the input circuit and the output circuit, controls the third node to maintain a stable low potential when the input terminal is on. Under the stable low potential control of the third node, the transistor in the output circuit can be prevented from floating due to short on time. Therefore, the output circuit is not easily affected by external signal interference, and the output circuit can output a stable low level, thus solving the problem of unstable output of the noise reduction transistor when driven at low frequency.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 This is a schematic diagram of the structure of a shift register unit according to one embodiment of the present disclosure;

[0019] Figure 2 This is a signal simulation diagram of a portion of a node in a shift register unit according to one embodiment of the present disclosure;

[0020] Figure 3 This is a schematic diagram of the structure of a shift register unit according to another embodiment of the present disclosure;

[0021] Figure 4 This is a schematic diagram of the structure of a shift register unit according to another embodiment of the present disclosure;

[0022] Figure 5 This is a timing diagram of a portion of the signals according to one embodiment of the present disclosure;

[0023] Figure 6 The equivalent circuit diagram of a shift register unit in the first stage according to an embodiment of the present disclosure;

[0024] Figure 7 The equivalent circuit diagram of a shift register unit in the second stage according to one embodiment of the present disclosure;

[0025] Figure 8 The equivalent circuit diagram of a shift register unit in the third stage according to one embodiment of the present disclosure;

[0026] Figure 9The equivalent circuit diagram of a shift register unit in the fourth stage according to one embodiment of the present disclosure;

[0027] Figure 10 The equivalent circuit diagram of the shift register unit in the first half of the fifth stage according to one embodiment of the present disclosure;

[0028] Figure 11 This is an equivalent circuit diagram of the shift register unit in the first half of the fifth stage according to one embodiment of the present disclosure. Detailed Implementation

[0029] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0030] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0031] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0032] Figure 1 This is a schematic diagram of a shift register unit according to one embodiment of the present disclosure. In this exemplary embodiment, the shift register unit can form a gate driving circuit. The EM signal output by the shift register unit can provide an enable signal to a row of pixel units. By cascading multiple shift register units and outputting multiple EM signals, enable signals for reset and compensation stages can be provided to multiple rows of pixel units. Figure 1As shown, the shift register unit may include an input circuit 10, a voltage sustaining circuit 20, a first pull-down circuit 30, and an output circuit 40. The input circuit 10 is connected to an input terminal INPUT, a first power supply terminal VGL, a first clock signal terminal CLK, a first node P1, and a second node P2. The input circuit 10 is used to transmit the signal of the input terminal INPUT to the first node P1 in response to the signal of the first clock signal terminal CLK, or to transmit the signal of the first power supply terminal VGL to the second node P2 in response to the signal of the first clock signal terminal CLK. The voltage sustaining circuit 20 is connected to the first node P1, a third node P3, the first power supply terminal VGL, and a second power supply terminal LVGL. The voltage sustaining circuit 20 is used to transmit the signal of the shift register 40 in response to the signal of the first power supply terminal VGL and the signal of the first node P1. The signal from the second power supply terminal LVGL is transmitted to the third node P3; the first pull-down circuit 30 is connected to the second node P2, the fourth node P4, and the second clock signal terminal CLKB. The first pull-down circuit 30 is used to transmit the signal from the second clock signal terminal CLKB to the fourth node P4 in response to the signal from the second node P2 and the signal from the second clock signal terminal CLKB; the output circuit 40 is connected to the third node P3, the fourth node P4, the first power supply terminal VGL, the third power supply terminal VGH, and the output terminal EM_OUT. The output circuit 40 is used to transmit the signal from the first power supply terminal VGL to the output terminal EM_OUT in response to the signal from the third node P3, or to transmit the signal from the third power supply terminal VGH to the output terminal EM_OUT in response to the signal from the fourth node P4.

[0033] The shift register unit provided in this disclosure, by setting a potential maintenance circuit between the input circuit and the output circuit, controls the third node to maintain a stable low potential when the input terminal is on. Under the stable low potential control of the third node, the transistor in the output circuit can be prevented from floating due to short on time. Therefore, the output circuit is not easily affected by external signal interference, and the output circuit can output a stable low level, thus solving the problem of unstable output of the noise reduction transistor when driven at low frequency.

[0034] like Figure 1As shown in this exemplary embodiment, the input circuit 10 may include: a first sub-input circuit 110, a second sub-input circuit 120, and a second pull-down circuit 130. The output circuit 40 may include: a first sub-output circuit 410, a second sub-output circuit 420, and a first pull-up circuit 430. The first sub-input circuit 110 is connected to the input terminal INPUT, the first clock signal terminal CLK, and the first node P1. The first sub-input circuit 110 is used to transmit the signal of the input terminal INPUT to the first node P1 in response to the signal of the first clock signal terminal CLK. The second sub-input circuit 120 is connected to the first clock signal terminal CLK, the first power supply terminal VGL, and the second node P2. The second sub-input circuit 120 is used to transmit the signal of the first power supply terminal VGL to the second node P2 in response to the signal of the first clock signal terminal CLK. The second pull-down circuit 130 is connected to the first node P1, the second node P2, and the first clock signal terminal CLK. The first pull-down circuit 130 is used to transmit the voltage of the first clock signal terminal CLK to the second node P2 in response to the signal of the first node P1. The first sub-output circuit 410 is connected to the third node P3, the output terminal EM_OUT, and the first power supply terminal VGL. The first sub-output circuit 410 is used to transmit the signal of the first power supply terminal VGL to the output terminal EM_OUT in response to the signal of the third node P3. The second sub-output circuit 420 is connected to the fourth node P4, the third power supply terminal VGH, and the output terminal EM_OUT. The second sub-output circuit 420 is used to transmit the signal of the third power supply terminal VGH to the output terminal EM_OUT in response to the signal of the fourth node P4. The first pull-up circuit 430 is connected to the third node P3, the third power supply terminal VGH, and the fourth node P4. The first pull-up circuit 430 is used to transmit the signal of the third power supply terminal VGH to the fourth node P4 in response to the signal of the third node P3.

[0035] The first clock signal terminal CLK and the second clock signal terminal CLKB can alternately output a conduction level (the conduction level can be, for example, low level). The first power supply terminal VGL and the second power supply terminal LVGL can output a conduction level (e.g., low level), and the third power supply terminal VGH can output a non-conducting level (e.g., high level). When the input terminal INPUT is at a non-conducting level (e.g., high level), the first sub-input circuit 110 transmits the non-conducting level signal of the input terminal INPUT to the first node P1. Thus, during the period when the input terminal INPUT is at a non-conducting level, the second pull-down circuit 130 is turned off, the first node P1 remains at a non-conducting level, the potential maintenance circuit 20 is turned off, causing the third node to remain at a non-conducting level, and the first sub-output circuit 410 is turned off. When the first clock signal terminal CLK is on, the second sub-input circuit 120 is turned on, transmitting the on-level of the first power supply terminal VGL to the second node P2. The first pull-down circuit 30 and the first pull-up circuit 430 are turned off, and the fourth node P4 maintains the non-on level of the previous stage. As a result, the second sub-output circuit 420 is turned off, and the output terminal EM_OUT of the shift register unit maintains the on-level of the previous stage. When the first clock signal terminal CLK is not on, the second sub-input circuit 120 is turned off, the second node P2 maintains the on-level of the previous stage, the first pull-up circuit 430 is turned off, and the first pull-down circuit 30 is turned on, transmitting the on-level of the second clock signal terminal CLKB to the fourth node P4. This causes the second sub-output circuit 420 to turn on, thereby transmitting the non-on level of the third power supply terminal VGH to the output terminal EM_OUT. The shift register unit outputs a non-on level, and the output signal of the shift register unit is shifted compared to the input signal. When the input signal is on, the first clock signal terminal CLK and the second clock signal terminal CLKB alternately output on-level signals, causing the first node P1 to continuously output an on-level signal. This controls the potential maintenance circuit 20 to be on, and the on-level potential maintenance circuit 20 controls the third node P3 to maintain an on-level signal. Thus, on the one hand, the first pull-up circuit 430 is controlled to transmit the non-on-level signal of the third power supply terminal VGH to the fourth node P4, thereby turning off the second sub-output circuit 420. On the other hand, the first sub-output circuit 410 is controlled to maintain a stable on-state, transmitting the on-level signal of the first power supply terminal VGL to the output terminal EM_OUT, so that the shift register unit continuously outputs a stable on-level signal. In this exemplary embodiment, under the control of the potential maintenance circuit 20, the on-time of the first sub-output circuit 410 is guaranteed, so that when the input signal is on-level, the shift register unit can output a stable on-level signal. Figure 2This is a signal simulation diagram of a portion of a shift register unit according to an embodiment of the present disclosure. In the diagram, the horizontal axis represents time, the vertical axis represents the amplitude of the level signal, K1 represents the level signal of the third node P3 obtained without the use of the potential sustaining circuit 20, and K2 represents the level signal of the third node P3 obtained with the use of the potential sustaining circuit 20. Figure 2 It can be seen that after setting the potential maintenance circuit 20, the third node P3 of the shift register unit is less affected by external signal interference and the output signal is stable. Therefore, the first sub-output circuit 410 can output a stable signal.

[0036] Figure 3 This is a schematic diagram of the structure of a shift register unit according to another embodiment of the present disclosure, as shown below. Figure 3 As shown, in an exemplary embodiment of this disclosure, the potential maintenance circuit 20 may include an eleventh transistor M11 and a fifth transistor M5. The first terminal of the eleventh transistor M11 is connected to the first node P1, the second terminal of the eleventh transistor M11 is connected to the third node P3, and the control terminal of the eleventh transistor M11 is connected to the first power supply terminal VGL. The first terminal of the fifth transistor M5 is connected to the third node P3, the second terminal of the fifth transistor M5 is connected to the second power supply terminal LVGL, and the control terminal of the fifth transistor M5 is connected to the first node P1. Taking the eleventh transistor M11 and the fifth transistor M5 as P-type transistors as an example, when the first node P1 is at a high level, the fifth transistor M5 is turned off, and the potential maintenance circuit 20 is turned off. When the first node P1 is low, the eleventh transistor M11 and the fifth transistor M5 are turned on, the potential maintenance circuit 20 is turned on, and the third node P3 writes a stable low-level signal XVGL. Under the voltage division effect of the eleventh transistor M11 and the fifth transistor M5, the XVGL low-level signal is between the second power supply terminal level LVGL and the first power supply terminal level VGL, thereby controlling the first sub-output circuit 410 to output a stable low-level signal.

[0037] Figure 4 This is a schematic diagram of the structure of a shift register unit according to another embodiment of the present disclosure. In another embodiment of the present disclosure, such as... Figure 4As shown, the potential maintenance circuit 20 may include: an eleventh transistor M11, a fifth transistor M5, and a fourth transistor M4. The first terminal of the eleventh transistor M11 is connected to the first node P1, the second terminal of the eleventh transistor M11 is connected to the third node P3, and the control terminal of the eleventh transistor M11 is connected to the first power supply terminal VGL. The first terminal of the fifth transistor M5 is connected to the third node P3, the second terminal of the fifth transistor M5 is connected to the fifth node P5, and the control terminal of the fifth transistor M5 is connected to the first node P1. The first terminal of the fourth transistor M4 is connected to the fifth node P5, and the second terminal and control terminal of the fourth transistor M4 are connected to the second power supply terminal LVGL. Taking the eleventh transistor M11, the fifth transistor M5, and the fourth transistor M4 as P-type transistors, the fourth transistor M4 and the fifth transistor M5 are connected. When the first node P1 is high, the fifth transistor M5 is off, and the potential maintenance circuit 20 is off. When the first node P1 is low, the eleventh transistor M11 and the fifth transistor M5 are turned on, and simultaneously, the second power supply terminal LVGL is a low-level signal, and the fourth transistor M4 is turned on. At this time, the potential maintenance circuit 20 is turned on, thereby writing a stable low-level signal XVGL to the third node P3. Due to the voltage division effect of the eleventh transistor M11, the fifth transistor M5, and the fourth transistor M4, the XVGL low-level signal is between the second power supply terminal level LVGL and the first power supply terminal level VGL, thereby controlling the first sub-output circuit 410 to output a stable low-level signal. It should be understood that in other exemplary embodiments, the potential maintenance circuit 20 may also have other circuit structures.

[0038] like Figure 3 or Figure 4As shown, the first sub-input circuit 110 may include: a first transistor M1, the first terminal of the first transistor M1 is connected to the input terminal INPUT, the second terminal of the first transistor M1 is connected to the first node P1, and the control terminal of the first transistor M1 is connected to the first clock signal terminal CLK; the second sub-input circuit 120 may include: a second transistor M2, the first terminal of the second transistor M2 is connected to the first power supply terminal VGL, the second terminal of the second transistor M2 is connected to the second node P2, and the control terminal of the second transistor M2 is connected to the first clock signal terminal CLK; the second pull-down circuit 130 may include: a third transistor M3, the first terminal of the third transistor M3 is connected to the first clock signal terminal CLK, the second terminal of the third transistor M3 is connected to the second node P2, and the control terminal of the third transistor M3 is connected to the first node P1. The first sub-output circuit 410 may include: a tenth transistor M10, the first terminal of which is connected to the first power supply terminal VGL, the second terminal of which is connected to the output terminal EM_OUT, and the control terminal of which is connected to the third node P3; the second sub-output circuit 420 includes: a ninth transistor M9 and a first capacitor C1, wherein the first terminal of the ninth transistor M9 is connected to the output terminal EM_OUT, the second terminal of which is connected to the third power supply terminal VGH, the control terminal of which is connected to the fourth node P4, and the first capacitor C1 is connected between the fourth node P4 and the third power supply terminal VGH; the first pull-up circuit 430 may include: an eighth transistor M8, the first terminal of which is connected to the third power supply terminal VGH, the second terminal of which is connected to the fourth node P4, and the control terminal of which is connected to the third node P3. The first pull-down circuit 30 may include: a sixth transistor M6, a second capacitor C2, and a seventh transistor M7. The first terminal of the sixth transistor M6 is connected to the second clock signal terminal CLKB, the second terminal of the sixth transistor M6 is connected to the sixth node P6, and the control terminal of the sixth transistor M6 is connected to the second node P2. The second capacitor C2 is connected between the second node P2 and the sixth node P6. The first terminal of the seventh transistor M7 is connected to the sixth node P6, the second terminal of the seventh transistor M7 is connected to the fourth node P4, and the control terminal of the seventh transistor M7 is connected to the second clock signal terminal CLKB. The first transistor M1 through the eleventh transistor M11 may all be P-type transistors. The signal at the first power supply terminal VGL may be low, the signal at the second power supply terminal LVGL may be low, and the signal at the third power supply terminal VGH may be high. It should be understood that in other exemplary embodiments, the shift register circuit may also have other structures. For example, the first transistor M1 to the eleventh transistor M11 may also be N-type transistors, and the first sub-input circuit 110, the second sub-input circuit 120, the first sub-output circuit 410, and the second sub-output circuit 420 may all include multiple cascaded transistors, etc., all of which fall within the protection scope of this disclosure.

[0039] Figure 5 This is a timing diagram of some signals according to one embodiment of the present disclosure. Wherein, CLK is the signal of the first clock signal terminal CLK, CLKB is the signal of the second clock signal terminal CLKB, INPUT is the signal of the input terminal INPUT, OUTPUT is the signal of the output terminal EM_OUT, CN1 is the signal of the first node P1, CN2 is the signal of the second node P2, CN3 is the signal of the third node P3, CN4 is the signal of the fourth node P4, and CN6 is the signal of the sixth node P6. The invalid period of the input terminal INPUT can be a high-level signal, and the duration of the high-level signal can be 3H. The signals of the first clock signal terminal CLK and the second clock signal terminal CLKB can alternate as valid signals, and both are active low, with a low-level duration of 1H. (In conjunction with...) Figures 3-5 The driving method of the shift register unit may include five stages, wherein the first transistor M1 to the eleventh transistor M11 can be P-type transistors, and the first power supply signal terminal and the second power supply signal terminal alternately output low-level active signals.

[0040] In the first stage T1, the first clock signal terminal CLK is a low-level signal, and the second clock signal terminal CLKB is a high-level signal. Figure 6 The equivalent circuit diagram of the shift register unit according to one embodiment of this disclosure in the first stage is shown below. The input terminal INPUT is at a high-level invalid level, causing the first node P1 to remain high in this interval, controlling the fifth transistor M5 to turn off, i.e., the potential maintenance circuit 20 is off. The third node P3 maintains the high-level signal from the previous stage, thereby turning off the eighth transistor M8 and the tenth transistor M10. The first clock signal terminal CLK is at an active level, the second transistor M2 is turned on, and the second node P2 writes VGL, causing the sixth transistor M6 to turn on. The sixth node P6 writes VGH, causing the fourth transistor M4 to turn off. The fourth node P4 maintains VGH, and the ninth transistor M9 is off, thereby maintaining the low level of the output terminal EM_OUT from the previous stage.

[0041] In the second stage T2, the input signal is high, the first clock signal CLK is high, and the second clock signal CLKB is low. Figure 7The equivalent circuit diagram of the shift register unit according to one embodiment of the present disclosure in the second stage is shown below. In this circuit, the first transistor M1 is off, the first node P1 maintains the high-level signal from the previous stage, the third transistor M3 is off, and the fifth transistor M5 is off, thus turning off the potential maintenance circuit 20. The eighth transistor M8 and the tenth transistor M10 are also off. Simultaneously, the first clock signal terminal CLK is high, causing the second transistor M2 to turn off. The second node P2 maintains the VGL low level, causing the sixth transistor M6 to turn on. The low level of the second clock signal terminal CLKB is coupled to the second node P2, fully turning on the sixth transistor M6. The sixth node P6 writes the VGL low level, thereby writing the fourth node P4 to the VGL low level through the seventh transistor M7. The ninth transistor M9 turns on, thus writing the output terminal EM_OUT to a high level, causing the output signal of the shift register unit to be shifted relative to the input signal.

[0042] In the third stage T3, the input signal is high, the first clock signal CLK is low, and the second clock signal CLKB is high. Figure 8 The equivalent circuit diagram of the shift register unit in the third stage according to one embodiment of the present disclosure is shown below. In this circuit, the first node P1 is high, the third transistor M3 is off, the fifth transistor M5 is off due to the high level of the first node P1, and therefore the tenth transistor M10 and the eighth transistor M8 are off. Simultaneously, the second transistor M2 is on, the second node P2 maintains a low level VGL, causing the sixth transistor M6 to be on, the second clock signal terminal CLKB is high, causing the sixth node P6 to be written with a high level, the seventh transistor M7 is off, the fourth node P4 maintains the low level VGL from the previous stage, and the ninth transistor M9 is on, thus maintaining the output terminal EM_OUT at a high level.

[0043] In the fourth stage (T4), the input signals are active low, the first clock signal (CLK) is high, and the second clock signal (CLKB) is low. Figure 9 The equivalent circuit diagram of the shift register unit in the fourth stage according to one embodiment of this disclosure is shown below. In this circuit, the first transistor M1 is off, the first node P1 is maintained at a high potential, the third transistor M3 is off, the fifth transistor M5 is off due to the high level of the first node P1, and therefore the tenth transistor M10 and the eighth transistor M8 are off. Simultaneously, the second transistor M2 is off, the second node P2 maintains a low level VGL, causing the sixth transistor M6 to turn on. The second clock signal terminal CLKB is coupled low to fully enable it. A low level VGL is written to the sixth node P6, the seventh transistor M7 turns on, a low level VGL is written to the fourth node P4, and the ninth transistor M9 turns on. Thus, the output terminal EM_OUT outputs VGH. At this point, the shift register unit completes the shift of the input signal.

[0044] In the fifth stage T5, the input signal is active low, and the first clock signal terminal CLK and the second clock signal terminal CLKB alternately output low-level signals. Figure 10 The present invention provides an equivalent circuit diagram of the shift register unit in the first half of the fifth stage according to an embodiment of the present invention. In the first half of the fifth stage, the first clock signal terminal CLK is a low-level signal, the second clock signal terminal CLKB is a high-level signal, the seventh transistor M7 is off, the first node P1 is a low-level signal, the eleventh transistor M11, the fourth transistor M4, and the fifth transistor M5 are on, and a low-level signal is written to the third node P3. On the one hand, this causes the eighth transistor M8 to turn on, and writes a high-level signal VGH to the fourth node P4, causing the ninth transistor M9 to turn off. On the other hand, this causes the gate of the tenth transistor M10 to maintain a stable low potential, so that the tenth transistor M10 is on for a sufficient time to avoid the output terminal EM_OUT being floating, thereby the output terminal EM_OUT outputs a stable low level VGL. Figure 11The diagram shows the equivalent circuit of a shift register unit according to an embodiment of this disclosure in the first half of the fifth stage. In the second half of the fifth cycle, the first clock signal terminal CLK is high, the second clock signal terminal CLKB is low, the first transistor M1 and the second transistor M2 are off, the first node P1 maintains the low-level signal from the previous stage, the second node P2 is high, the sixth transistor M6 is off, and simultaneously, under the control of the low-level signal of the first node P1, the eleventh transistor M11, the fourth transistor M4, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 operate in the same state as in the first half, enabling the output terminal EM_OUT to output a stable low level VGL. Therefore, this disclosure ensures that the tenth transistor M10 stably outputs a low-level signal by setting the potential maintenance circuit 20. In this exemplary embodiment, the level of the second power supply terminal LVGL can be lower than the level of the first power supply terminal VGL. This is because the voltage divider effect of the eleventh transistor M11, the fifth transistor M5, and / or the fourth transistor M4 causes the level of the third node P3 to be between the level of the second power supply terminal LVGL and the level of the first power supply terminal VGL. Furthermore, in this exemplary embodiment, by adjusting the level of the second power supply terminal LVGL, the duration for which the tenth transistor M10 maintains a low potential can be controlled. This allows the shift register unit provided in this disclosure to solve the output instability problem caused by voltage fluctuations. For example, when the high-level fluctuation of the tenth transistor M10 results in insufficient on-time of the tenth transistor M10, the output level of the second power supply terminal LVGL can be reduced to extend the on-time of the tenth transistor M10, preventing the tenth transistor M10 from entering a floating state and ensuring stable output of the tenth transistor M10. It should be understood that in other exemplary embodiments of this disclosure, the shift register circuit may also have other driving methods, such as the duration of the invalid period of the input terminal INPUT being 5H, and the signal change period of the first clock signal terminal CLK and the second clock signal terminal CLKB being 2H, etc., all of which fall within the protection scope of this disclosure.

[0045] This disclosure also provides a display panel including a gate driving circuit, which includes a plurality of cascaded shift register units as described above. This display panel can be applied to display devices such as televisions, mobile phones, and tablet computers.

[0046] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the generality of this disclosure and include, but are not disclosed herein, common knowledge or customary techniques in the art. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

Claims

1. A shift register unit characterized by comprising: The input circuit is connected with the input end, the first power supply end, the first clock signal end, the first node and the second node, and is configured to transmit a signal of the input end to the first node in response to a signal of the first clock signal end, or transmit a signal of the first power supply end to the second node in response to a signal of the first clock signal end. The potential maintaining circuit is connected with the first node, the third node, the first power supply end and the second power supply end, and is configured to transmit a signal of the second power supply end to the third node in response to a signal of the first power supply end and a signal of the first node. The first pull-down circuit is connected with the second node, the fourth node and the second clock signal end, and is configured to transmit a signal of the second clock signal end to the fourth node in response to a signal of the second node and a signal of the second clock signal end. The output circuit is connected with the third node, the fourth node, the first power supply end, the third power supply end and the output end, and is configured to transmit a signal of the first power supply end to the output end in response to a signal of the third node, or transmit a signal of the third power supply end to the output end in response to a signal of the fourth node. The potential maintaining circuit comprises:

2. The shift register cell of claim 1, wherein, The eleventh transistor has a first end connected with the first node, a second end connected with the third node, and a control end connected with the first power supply end. The fifth transistor has a first end connected with the third node, a second end connected with the second power supply end, and a control end connected with the first node. The potential maintaining circuit comprises:

3. The shift register cell of claim 1, wherein, The eleventh transistor has a first end connected with the first node, a second end connected with the third node, and a control end connected with the first power supply end. The fifth transistor has a first end connected with the third node, a second end connected with the fifth node, and a control end connected with the first node. The fourth transistor has a first end connected with the fifth node, and a second end and a control end connected with the second power supply end. The on level of the second power supply end is lower than the on level of the first power supply end.

4. The shift register cell of claim 2 or 3, wherein, The on level of the third node is greater than the on level of the second power supply end and less than the on level of the first power supply end.

5. The shift register cell of claim 2 or 3, wherein, The input circuit comprises:

6. The shift register cell of claim 1, wherein, The first sub-input circuit is connected with the input end, the first clock signal end and the first node, and is configured to transmit a signal of the input end to the first node in response to a signal of the first clock signal end. The second sub-input circuit is connected with the first clock signal end, the first power supply end and the second node, and is configured to transmit a signal of the first power supply end to the second node in response to a signal of the first clock signal end. The second pull-down circuit is connected with the first node, the second node and the first clock signal end, and is configured to transmit a voltage of the first clock signal end to the second node in response to a signal of the first node.

7. The shift register unit according to claim 6, wherein The first sub-input circuit comprises: ​ A first transistor has a first terminal connected to the input terminal, a second terminal connected to the first node, and a control terminal connected to the first clock signal terminal; The second sub-input circuit comprises: A second transistor has a first terminal connected to the first power supply terminal, a second terminal connected to the second node, and a control terminal connected to the first clock signal terminal; The second pull-down circuit comprises: A third transistor has a first terminal connected to the first clock signal terminal, a second terminal connected to the second node, and a control terminal connected to the first node; The first pull-down circuit comprises: A sixth transistor has a first terminal connected to the second clock signal terminal, a second terminal connected to a sixth node, and a control terminal connected to the second node; A second capacitor is connected between the second node and the sixth node; A seventh transistor has a first terminal connected to the sixth node, a second terminal connected to the fourth node, and a control terminal connected to the second clock signal terminal.

8. The shift register cell of claim 1, wherein, The output circuit comprises: A first sub-output circuit is connected to the third node, an output terminal, and the first power supply terminal, and is configured to transmit a signal of the first power supply terminal to the output terminal in response to a signal of the third node; A second sub-output circuit is connected to the fourth node, a third power supply terminal, and the output terminal, and is configured to transmit a signal of the third power supply terminal to the output terminal in response to a signal of the fourth node; A first pull-up circuit is connected to the third node, the third power supply terminal, and the fourth node, and is configured to transmit a signal of the third power supply terminal to the fourth node in response to a signal of the third node.

9. The shift register unit according to claim 8, wherein The first sub-output circuit comprises: A tenth transistor has a first terminal connected to the first power supply terminal, a second terminal connected to the output terminal, and a control terminal connected to the third node; The second sub-output circuit comprises: A ninth transistor has a first terminal connected to the output terminal, a second terminal connected to the third power supply terminal, and a control terminal connected to the fourth node; A first capacitor is connected between the fourth node and the third power supply terminal; The first pull-up circuit comprises: An eighth transistor has a first terminal connected to the third power supply terminal, a second terminal connected to the fourth node, and a control terminal connected to the third node.

10. A display panel, characterized by, A gate drive circuit comprises a plurality of cascaded shift register units according to any one of claims 1-9.

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