NMOS tube triggered bidirectional silicon controlled rectifier

Abstract

The present invention provides an NMOS transistor-triggered bidirectional silicon-controlled rectifier, comprising: a substrate; a first N-well, a P-well, and a second N-well, arranged in sequence from left to right above the substrate; a first NMOS transistor, comprising an N-type gate and N-type source / drain regions located on both sides of the N-type gate; two P-type doped regions, respectively located in the first N-well and the second N-well; an electrostatic pulse detection circuit, comprising a control port and two voltage ports, each of the voltage ports being electrically connected to a corresponding N-type source / drain region and a corresponding P-type doped region, and the control port being electrically connected to the N-type gate to output a control voltage to the N-type gate to control the on / off of the first NMOS transistor. The present invention reduces the triggering voltage of the bidirectional silicon-controlled rectifier, thereby improving its applicability.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an NMOS tube-triggered bidirectional silicon-controlled rectifier. Background Art

[0002] In the design of anti-static protection for integrated circuits, the anti-static protection design window generally depends on the device's operating voltage and the thickness of the gate oxide layer of the internal protected circuit. However, after the anti-static protection design window is designed based on the device's operating voltage and the thickness of the gate oxide layer of the internal protected circuit, it is often found that the device's trigger voltage exceeds the anti-static protection design window. If the device is directly used in the anti-static protection design, it is easy to cause reliability problems in the device's gate oxide layer. For example, taking the 55nm process platform as an example, the operating voltage of the core device (MOSFET) is 1.2V and the thickness of the gate oxide layer is Therefore, the anti-static protection design window of the core device is usually designed to be 1.32V~5.2V. Through measurement, it is found that the trigger voltage of the core device is 6.7V, which exceeds the anti-static protection design window of the core device. If the core device is directly used for anti-static protection design, it is easy to cause reliability problems in the gate oxide layer of the core device.

[0003] Figure 1 The bidirectional silicon controlled rectifier is triggered by an NMOS tube. In the prior art, an NMOS tube-triggered bidirectional silicon controlled rectifier is proposed. Please refer to Figure 1 The device includes a first voltage port A, a second voltage port K, and a control port D. There is a voltage difference between the first voltage port A and the second voltage port K. The first voltage port A can be connected to a positive voltage or ground, and the second voltage port K can be connected to ground or a positive voltage. The control port D is the gate of the NMOS tube. The device has the characteristics of small area, low trigger voltage, and high secondary breakdown current, and is suitable for anti-static protection design of low-voltage devices. However, when applied to the anti-static protection design of the IO terminal to ground, when one voltage port is grounded and an electrostatic pulse is applied to the other voltage port, the gate of the NMOS tube is actually in a floating state. In general application scenarios, it can be considered that the gate of the NMOS tube is at a low potential at this time. However, in some high-radiation environments, since the gate of the NMOS tube is connected to the power supply VDD, and the gate of the NMOS tube is easily affected by radiation, the potential of the gate of the NMOS tube becomes unstable, thereby causing the NMOS tube to be triggered incorrectly or triggered in time, resulting in damage to the device or loss of function. Therefore, it is necessary to design an electrostatic pulse detection circuit to accurately control the voltage applied to the control port D when the electrostatic pulse arrives to prevent the NMOS tube from being triggered incorrectly or being triggered in time, resulting in damage to the device or loss of function. Summary of the Invention

[0004] The purpose of the present invention is to provide an NMOS tube triggered bidirectional silicon-controlled rectifier, which reduces the triggering voltage of the bidirectional silicon-controlled rectifier and improves its applicability.

[0005] In order to achieve the above object, the present invention provides an NMOS tube triggered bidirectional silicon controlled rectifier, comprising:

[0006] substrate;

[0007] A first N-well, a P-well, and a second N-well are sequentially arranged from left to right above the substrate;

[0008] a first NMOS transistor, comprising an N-type gate and N-type source / drain regions located on both sides of the N-type gate, wherein the N-type gate is located above the P-well, and the N-type source / drain regions on both sides of the N-type gate are located at the junction of the first N-well and the P-well and at the junction of the second N-well and the P-well, respectively;

[0009] Two P-type doped regions, respectively located in the first N-well and the second N-well, and each of the P-type doped regions is isolated from the corresponding N-type source / drain region by a trench isolation structure;

[0010] The electrostatic pulse detection circuit has a control port and two voltage ports. Each of the voltage ports is electrically connected to the corresponding N-type source / drain region and the corresponding P-type doped region, and a voltage difference exists between the two voltage ports. The control port is electrically connected to the N-type gate to output a control voltage to the N-type gate to control the on / off of the first NMOS transistor.

[0011] Optionally, the electrostatic pulse detection circuit includes a first RC circuit, a second RC circuit, a second NMOS tube and a third NMOS tube, wherein the first RC circuit includes a first resistor and a first capacitor connected in series, and the second RC circuit includes a second resistor and a second capacitor connected in series; the gate of the second NMOS tube is connected between the second resistor and the second capacitor, the gate of the third NMOS tube is connected between the first resistor and the first capacitor, the drain of the second NMOS tube and the drain of the third NMOS tube are connected to form the control port; the first resistor, the second capacitor and the source of the second NMOS tube are connected to form one voltage port; the first capacitor, the second resistor and the source of the third NMOS tube are connected to form another voltage port.

[0012] Optionally, the electrostatic pulse detection circuit includes a first RC circuit, a second RC circuit, a first PMOS tube and a second PMOS tube, wherein the first RC circuit includes a first resistor and a first capacitor connected in series, and the second RC circuit includes a second resistor and a second capacitor connected in series; the gate of the first PMOS tube is connected between the first resistor and the first capacitor, the gate of the second PMOS tube is connected between the second resistor and the second capacitor, and the drain of the first PMOS tube and the drain of the second PMOS tube are connected to form the control port; the first resistor, the second capacitor and the source of the first PMOS tube are connected to form one voltage port, and the first capacitor, the second resistor and the source of the second PMOS tube are connected to form another voltage port.

[0013] Optionally, the resistance values ​​of the first resistor and the second resistor are equal, and the capacitance values ​​of the first capacitor and the second capacitor are equal.

[0014] Optionally, the time constant of the first RC circuit and the time constant of the second RC circuit are both 1 nS to 10 nS.

[0015] Optionally, the resistance values ​​of the first resistor and the second resistor are 1KΩ to 10KΩ, and the capacitance values ​​of the first capacitor and the second capacitor are 0.2pF to 2pF.

[0016] Optionally, the trigger voltage is obtained according to the length of the N-type gate of the first NMOS, the doping concentration of the P-well, the time constant of the first RC circuit, and the time constant of the second RC circuit.

[0017] Optionally, one of the voltage ports is grounded, and the other voltage port is connected to a positive voltage.

[0018] Optionally, the depths of the first N-well, the P-well, and the second N-well are all greater than the depths of the N-type source / drain region and the P-type doped region.

[0019] Optionally, the depths of the first N-well, the P-well, and the second N-well are all greater than the depth of the trench isolation structure.

[0020] In the NMOS transistor-triggered bidirectional silicon-controlled rectifier provided by the present invention, the first NMOS transistor includes an N-type gate and N-type source / drain regions located on both sides of the N-type gate, the N-type gate is located above the P-well, and the N-type source / drain regions on both sides of the N-type gate are respectively located at the junction of the first N-well and the P-well and at the junction of the second N-well and the P-well; two P-type doped regions are respectively located in the first N-well and the second N-well, and each P-type doped region is isolated from the corresponding N-type source / drain region by a trench isolation structure; the electrostatic pulse detection circuit has a control port and two voltage ports, each voltage port is electrically connected to the corresponding N-type source / drain region and the corresponding P-type doped region, and the two voltage ports are electrically connected to the corresponding N-type source / drain region and the corresponding P-type doped region. There is a voltage difference between the voltage ports, the control port is electrically connected to the N-type gate to output a control voltage to the N-type gate to control the on and off of the first NMOS tube. By controlling the conduction of the first NMOS tube, a channel current is formed in the first NMOS tube, and the channel current acts as a trigger current of the device, thereby triggering the device to work and reducing the trigger voltage of the device; and in the present invention, the N-type gate is connected to the electrostatic pulse detection circuit to control the first NMOS tube with the electrostatic pulse signal input from the voltage port, thereby avoiding the first NMOS tube being affected by radiation, etc., resulting in false triggering of the first NMOS tube or untimely triggering, thereby improving the applicability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Trigger bidirectional silicon controlled rectifier for NMOS tube;

[0022] Figure 2 The NMOS-triggered bidirectional silicon-controlled rectifier provided in the first embodiment of the present invention;

[0023] Figure 3 The NMOS tube-triggered bidirectional silicon-controlled rectifier provided in the second embodiment of the present invention;

[0024] Wherein, the accompanying drawings are marked as follows:

[0025] 10-substrate; 21-P-well; 22-first N-well; 23-second N-well; 31-first P-type doping region; 32-second P-type doping region; 41-first N-type doping region; 42-second N-type doping region; 50-trench isolation structure; 60-N-type gate; R1-first resistor; C1-first capacitor; R2-second resistor; C2-second capacitor; N1-second NMOS transistor; N2-third NMOS transistor; P1-first PMOS transistor; P2-second PMOS transistor; A, A1-first voltage port; K, K1-second voltage port; D, D1-control port. DETAILED DESCRIPTION

[0026] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0027] Example 1

[0028] Figure 2 The NMOS tube triggers the bidirectional silicon controlled rectifier provided in this embodiment. Please refer to Figure 2 This embodiment provides an NMOS transistor-triggered bidirectional silicon-controlled rectifier, including a substrate 10, a P-well 21, a first N-well 22, a second N-well 23, a first NMOS transistor, two P-type doped regions, an electrostatic pulse detection circuit, and a trench isolation structure 50. The substrate 10 is P-type. The first N-well 22, the P-well 21, and the second N-well 23 are arranged sequentially from left to right above the substrate 10, with the P-well 21 located between the first N-well 22 and the second N-well 23.

[0029] The first NMOS transistor includes an N-type gate 60 and N-type source / drain regions on either side of the N-type gate 60. The N-type gate 60 is located above the P-well 21, with a gate oxide layer (not shown) between the N-type gate 60 and the P-well 21. The N-type source / drain regions on either side of the N-type gate 60 are located at the junction of the first N-well 22 and the P-well 21, and at the junction of the second N-well 23 and the P-well 21, respectively. In this embodiment, the N-type source / drain regions on either side of the N-type gate 60 are the first N-type doping region 41 and the second N-type doping region 42, respectively. If the N-type source region is the first N-type doping region 41, the N-type drain region is the second N-type doping region 42; if the N-type source region is the second N-type doping region 42, the N-type drain region is the first N-type doping region 41. The first N-type doping region 41 is located at the junction of the first N-well 22 and the P-well 21, and the second N-type doping region 42 is located at the junction of the second N-well 23 and the P-well 21. Since the device provided in this embodiment is an NMOS-triggered bidirectional silicon-controlled rectifier, wherein the bidirectional silicon-controlled rectifier is symmetrical in structure, the positions of the N-type source region and the N-type drain region are not distinguished.

[0030] The two P-type doping regions are respectively located in the first N-well 22 and the second N-well 23, and each P-type doping region is isolated from the corresponding N-type source / drain region by a trench isolation structure 50; in this embodiment, the two P-type doping regions are respectively the first P-type doping region 31 and the second P-type doping region 32, the first P-type doping region 31 is located in the first N-well 22 and is located outside the first N-type doping region 41, and the second P-type doping region 32 is located in the second N-well 23 and is located outside the second N-type doping region 42; and the first N-type doping region 41 and the first P-type doping region 31 and the second N-type doping region 42 are located between the second P-type doping region 32 and are isolated by the trench isolation structure 50.

[0031] In this embodiment, trench isolation structures 50 are provided outside the first P-type doping region 31 and the second P-type doping region 32. That is, the first P-type doping region 31 and the second P-type doping region 32 are located between the two trench isolation structures 50. The depths of the P-well 21, the first N-well 22, and the second N-well 23 are all greater than the depths of the first N-type doping region 41, the second N-type doping region 42, the first P-type doping region 31, and the second P-type doping region 32. The trench isolation structure 50 between the first N-type doping region 41 and the first P-type doping region 31 is located in the first N-well 22, and the trench isolation structure 50 between the second N-type doping region 42 and the second P-type doping region 32 is located in the second N-well 23. The depths of both trench isolation structures 50 are less than the depths of the P-well 21, the first N-well 22, and the second N-well 23. The trench isolation structure 50 outside the first P-type doping region 31 is located in the first N-well 22, and the trench isolation structure 50 outside the second P-type doping region 32 is located in the second N-well 23, and the depths of the two trench isolation structures 50 are also smaller than the depths of the P-well 21, the first N-well 22 and the second N-well 23.

[0032] The electrostatic pulse detection circuit has a control port D1 and two voltage ports. Each voltage port is electrically connected to a corresponding N-type source / drain region and a corresponding P-type doped region, with a voltage difference between the two voltage ports. The control port D1 is electrically connected to the N-type gate 60 of the first NMOS transistor to output a control voltage to the N-type gate 60 to control the on / off state of the first NMOS transistor. In this embodiment, the two voltage ports are a first voltage port A1 and a second voltage port K1. The first voltage port A1 is electrically connected to the first N-type doped region 41 and the first P-type doped region 31, and the second voltage port K1 is electrically connected to the second N-type doped region 42 and the second P-type doped region 32. In this embodiment, the first voltage port A1 is grounded, and the second voltage port K1 is connected to a positive voltage. Alternatively, the first voltage port A1 is connected to a positive voltage, and the second voltage port K1 is grounded, but this is not limited to this. The connection between the first voltage port A1 and the second voltage port K1 depends on the actual situation.

[0033] In this embodiment, the electrostatic pulse detection circuit includes a first RC circuit, a second RC circuit, a second NMOS transistor N1, and a third NMOS transistor N2. The first RC circuit includes a first resistor R1 and a first capacitor C1 connected in series, and the second RC circuit includes a second resistor R2 and a second capacitor C2 connected in series. The gate of the second NMOS transistor N1 is connected between the second resistor R2 and the second capacitor C2, and the gate of the third NMOS transistor N2 is connected between the first resistor R1 and the first capacitor C1. The drain of the second NMOS transistor N1 and the drain of the third NMOS transistor N2 are connected to form a control port D1. The first resistor R1, the second capacitor C2, and the source of the second NMOS transistor N1 are connected to form a first voltage port A1. The first capacitor C1, the second resistor R2, and the source of the third NMOS transistor N2 are connected to form a second voltage port K1.

[0034] In this embodiment, the time constant of the first RC circuit and the time constant of the second RC circuit are required to be equal. The time constant of the first RC circuit is the product of the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1, and the time constant of the second RC circuit is the product of the resistance value of the second resistor R2 and the capacitance value of the second capacitor C2. In other words, the resistance values ​​of the first resistor R1 and the second resistor R2 are required to be equal, and the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are required to be equal. In this embodiment, the time constant of the first RC circuit and the time constant of the second RC circuit can both be 1nS to 10nS, the resistance values ​​of the first resistor R1 and the second resistor R2 can be 1kΩ to 10kΩ, and the capacitance values ​​of the first capacitor C1 and the second capacitor C2 can be 0.2pF to 2pF, but are not limited to this time constant range, resistance value range, and capacitance value range, and are determined according to actual conditions.

[0035] When the first voltage port A1 is connected to a positive voltage and the second voltage port K1 is grounded, an external electrostatic pulse signal is input through the first voltage port A1. The first RC circuit forms a capacitor charging circuit, and the potential of node T1 of the first RC circuit is low. That is, the potential of the gate of the third NMOS transistor N2 is low, and the third NMOS transistor N2 is in the off state. At this time, the second RC circuit forms a voltage coupling circuit, and the potential of node T2 of the second RC circuit is high. That is, the potential of the gate of the second NMOS transistor N1 is high, and the second NMOS transistor N1 is in the on state. Since the source of the second NMOS transistor N1 is connected to the positive voltage of the first voltage port A1, the high potential of the first voltage port A1 causes the drain of the second NMOS transistor N1 to also be high, thereby causing the N-type gate 60 of the first NMOS transistor to be high, turning on the first NMOS transistor. After the first NMOS tube is turned on, a channel current will be formed between the first N-type doping region 41 and the second N-type doping region 42. The channel current flows from the first N-type doping region 41 to the second N-type doping region 42. The channel current will act as a trigger current to reduce the trigger voltage of the bidirectional silicon-controlled rectifier triggered by the NMOS tube. At this time, the current path formed by the NMOS tube triggering the bidirectional silicon-controlled rectifier is input from the first voltage port A1 and then passes through the first N-type doping region 41, the P well 21, the second N well 23, the second P-type doping region 32 to the second voltage port K1 output, which also includes the channel current path flowing from the first N-type doping region 41 to the second N-type doping region 42 and then to the second voltage port K1 output. When the device is in a static voltage bias or normal operation, and there is no electrostatic pulse signal input, the T2 node is at a low potential, the T1 node is at a high potential, the gate potential of the second NMOS transistor N1 is at a low potential, the second NMOS transistor N1 is in a cut-off state, the gate potential of the third NMOS transistor N2 is at a high potential, the third NMOS transistor N2 is in a conducting state, and the second voltage port K1 is at a low potential, thereby causing the N-type gate 60 of the first NMOS transistor to be at a low potential, causing the first NMOS transistor to be in a cut-off state.

[0036] When the first voltage port A1 is grounded and the second voltage port K1 is connected to a positive voltage, an external electrostatic pulse signal is input from the second voltage port K1. The second RC circuit forms a capacitor charging circuit, and the potential of node T2 of the second RC circuit is low. That is, the potential of the gate of the second NMOS transistor N1 is low, and the second NMOS transistor N1 is in the off state. At this time, the first RC circuit forms a voltage coupling circuit, and the potential of node T1 of the first RC circuit is high. That is, the potential of the gate of the third NMOS transistor N2 is high, and the third NMOS transistor N2 is in the on state. Since the source of the third NMOS transistor N2 is connected to the positive voltage of the second voltage port K1, the high potential of the second voltage port K1 causes the drain of the third NMOS transistor N2 to also be high, thereby causing the N-type gate 60 of the first NMOS transistor to be high, turning on the first NMOS transistor. After the first NMOS tube is turned on, a channel current will be formed between the first N-type doping region 41 and the second N-type doping region 42. The channel current flows from the second N-type doping region 42 to the first N-type doping region 41. The channel current will act as a trigger current to reduce the trigger voltage of the bidirectional silicon-controlled rectifier triggered by the NMOS tube. At this time, the current path formed by the NMOS tube triggering the bidirectional silicon-controlled rectifier is input from the second voltage port K1 and then passes through the second N-type doping region 42, the P well 21, the first N well 22, the first P-type doping region 31 to the first voltage port A1 output, which also includes the channel current path flowing from the second N-type doping region 42 to the first N-type doping region 41 and then to the first voltage port A1 output. When the device is in a static voltage bias or normal operation, and there is no electrostatic pulse signal input, the T1 node is at a low potential, the T2 node is at a high potential, the gate potential of the third NMOS transistor N2 is at a low potential, the third NMOS transistor N2 is in a cut-off state, the gate potential of the second NMOS transistor N1 is at a high potential, the second NMOS transistor N1 is in a conducting state, and the first voltage port A1 is at a low potential, thereby causing the N-type gate 60 of the first NMOS transistor to be at a low potential, and the first NMOS transistor to be in a cut-off state.

[0037] In this embodiment, the control voltage output by the control port D1 to the N-type gate 60 of the first NMOS transistor can be obtained according to the length of the N-type gate of the first NMOS, the doping concentration of the P-well, the time constant of the first RC circuit and the time constant of the second RC circuit, wherein adjusting the time constant of the first RC circuit and the time constant of the second RC circuit can reduce this control voltage.

[0038] In this embodiment, the N-type gate 60 of the first NMOS transistor is connected to the second NMOS transistor N1 and the third NMOS transistor N2. Two RC circuits are connected in parallel between the first voltage port A1 and the second voltage port K1. The two RC circuits are used to control the operating states of the second NMOS transistor N1 and the third NMOS transistor N2, thereby controlling the on / off state of the first NMOS transistor by the input electrostatic pulse signal. The first NMOS transistor is used to trigger the bidirectional silicon-controlled rectifier, thereby avoiding the problem of the N-type gate 60 of the first NMOS transistor being directly connected to the power supply VDD, which would cause the potential of the N-type gate 60 of the first NMOS transistor to be susceptible to radiation. The NMOS-triggered bidirectional silicon-controlled rectifier proposed in this embodiment detects electrostatic pulses through the electrostatic pulse detection circuit to control the first NMOS transistor. The potential of the N-type gate 60 of the first NMOS transistor is affected by the input electrostatic pulse signal and directly responds to the input electrostatic pulse signal. This avoids the problem of unstable potential of the N-type gate 60, which could cause false triggering or untimely triggering of the first NMOS transistor, thereby improving the applicability of the device and making it suitable for high-radiation environments.

[0039] Example 2

[0040] Figure 3 The NMOS tube triggers the bidirectional silicon controlled rectifier provided in this embodiment. Please refer to Figure 3 The difference between this embodiment and the first embodiment is that the electrostatic pulse detection circuit of this embodiment includes a first PMOS transistor P1 and a second PMOS transistor P2 to replace the first NMOS transistor and the second NMOS transistor in the electrostatic pulse detection circuit of the first embodiment.

[0041] Specifically, the electrostatic pulse detection circuit includes a first RC circuit, a second RC circuit, a first PMOS transistor P1, and a second PMOS transistor P2. The first RC circuit includes a first resistor R1 and a first capacitor C1 connected in series, and the second RC circuit includes a second resistor R2 and a second capacitor C2 connected in series. The gate of the first PMOS transistor P1 is connected between the first resistor R1 and the first capacitor C1, the gate of the second PMOS transistor P2 is connected between the second resistor R2 and the second capacitor C2, and the drain of the first PMOS transistor P1 and the drain of the second PMOS transistor P2 are connected to form a control port D1. The first resistor R1, the second capacitor C2, and the source of the first PMOS transistor P1 are connected to form a first voltage port A1, and the first capacitor C1, the second resistor R2, and the source of the second PMOS transistor P2 are connected to form a second voltage port K1. The operating principle of the circuit is similar to that of the first embodiment, except that the gates of the first PMOS transistor P1 and the second PMOS transistor P2 are low-potential and conductive, which is opposite to the gates of the first NMOS transistor and the second NMOS transistor being high-potential and conductive.

[0042] When the first voltage port A1 is connected to a positive voltage and the second voltage port K1 is grounded, an external electrostatic pulse signal is input through the first voltage port A1. The first RC circuit forms a capacitor charging circuit, and the potential of node T1 of the first RC circuit is low, that is, the potential of the gate of the first PMOS transistor P1 is low, and the first PMOS transistor P1 is in the on state. At this time, the second RC circuit forms a voltage coupling circuit, and the potential of node T2 of the second RC circuit is high, that is, the potential of the gate of the second PMOS transistor P2 is high, and the second PMOS transistor P2 is in the off state. Because the source of the first PMOS transistor P1 is connected to the positive voltage of the first voltage port A1, the high potential of the first voltage port A1 causes the drain of the first PMOS transistor P1 to also be high, thereby causing the N-type gate 60 of the first NMOS transistor to be high, turning on the first NMOS transistor. The current path of the device after turning on is the same as that described in the first embodiment and will not be described here. When the device is in a static voltage bias or normal operation, and there is no electrostatic pulse signal input, the T2 node is at a low potential, the T1 node is at a high potential, the gate potential of the first PMOS transistor P1 is at a high potential, the first PMOS transistor P1 is in a cut-off state, the gate potential of the second PMOS transistor P2 is at a low potential, the second PMOS transistor P2 is in a conducting state, and the second voltage port K1 is at a low potential, thereby making the N-type gate 60 of the first NMOS transistor at a low potential, and making the first NMOS transistor in a cut-off state.

[0043] When the first voltage port A1 is grounded and the second voltage port K1 is connected to a positive voltage, an external electrostatic pulse signal is input through the first voltage port K1. The first RC circuit forms a voltage coupling circuit, and the T1 node of the first RC circuit is at a high potential, that is, the gate potential of the first PMOS transistor P1 is at a high potential, and the first PMOS transistor P1 is in a cutoff state. At this time, the second RC circuit forms a capacitor charging circuit, and the T2 node of the second RC circuit is at a low potential, that is, the gate potential of the second PMOS transistor P2 is at a low potential, and the second PMOS transistor P2 is in a conductive state. Because the source of the second PMOS transistor P2 is connected to the positive voltage of the second voltage port K1, the high potential of the second voltage port K1 causes the drain of the second PMOS transistor P2 to also be at a high potential, thereby causing the N-type gate 60 of the first NMOS transistor to be at a high potential, turning on the first NMOS transistor. The current path of the device after turning on is the same as that described in the first embodiment and will not be described again here. When the device is in a static voltage bias or normal operation, and there is no electrostatic pulse signal input, the T2 node is at a high potential, the T1 node is at a low potential, the gate potential of the second PMOS transistor P2 is at a high potential, and the second PMOS transistor P2 is in a cut-off state; the gate potential of the first PMOS transistor P1 is at a low potential, and the first PMOS transistor P1 is in a conducting state, and the first voltage port A1 is at a low potential, thereby making the N-type gate 60 of the first NMOS transistor at a low potential, and making the first NMOS transistor in a cut-off state.

[0044] In summary, in the NMOS tube-triggered bidirectional silicon-controlled rectifier provided by the present invention, the first NMOS tube includes an N-type gate and N-type source / drain regions located on both sides of the N-type gate, the N-type gate is located above the P-well, and the N-type source / drain regions on both sides of the N-type gate are respectively located at the junction of the first N-well and the P-well and at the junction of the second N-well and the P-well; the two P-type doped regions are respectively located in the first N-well and the second N-well, and each P-type doped region is isolated from the corresponding N-type source / drain region by a trench isolation structure; the electrostatic pulse detection circuit has a control port and two voltage ports, each voltage port is electrically connected to the corresponding N-type source / drain region and the corresponding P-type doped region, and the two A voltage difference exists between the two voltage ports, and the control port is electrically connected to the N-type gate to output a control voltage to the N-type gate to control the on / off of the first NMOS tube. By controlling the conduction of the first NMOS tube, a channel current is formed in the first NMOS tube, and the channel current acts as a trigger current of the device, thereby triggering the device to operate and reducing the trigger voltage of the device. In addition, in the present invention, the N-type gate is connected to the electrostatic pulse detection circuit to control the first NMOS tube with the electrostatic pulse signal input from the voltage port, thereby preventing the first NMOS tube from being affected by radiation, etc., resulting in false triggering or untimely triggering of the first NMOS tube, thereby improving the applicability of the device.

[0045] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. An NMOS tube triggered bidirectional silicon controlled rectifier, characterized in that: include: substrate; A first N-well, a P-well, and a second N-well are sequentially arranged from left to right above the substrate; a first NMOS transistor, comprising an N-type gate and N-type source / drain regions located on both sides of the N-type gate, wherein the N-type gate is located above the P-well, and the N-type source / drain regions on both sides of the N-type gate are located at the junction of the first N-well and the P-well and at the junction of the second N-well and the P-well, respectively; two P-type doped regions, respectively located in the first N-well and the second N-well, each of the P-type doped regions being isolated from the corresponding N-type source / drain region by a trench isolation structure, and the depths of the first N-well, the P-well, and the second N-well being greater than the depths of the N-type source / drain regions and the two P-type doped regions on both sides of the N-type gate; The electrostatic pulse detection circuit has a control port and two voltage ports. Each of the voltage ports is electrically connected to the corresponding N-type source / drain region and the corresponding P-type doped region, and a voltage difference exists between the two voltage ports. The control port is electrically connected to the N-type gate to output a control voltage to the N-type gate to control the on / off of the first NMOS transistor.

2. The NMOS-triggered bidirectional silicon-controlled rectifier according to claim 1, wherein: The electrostatic pulse detection circuit includes a first RC circuit, a second RC circuit, a second NMOS transistor and a third NMOS transistor, wherein the first RC circuit includes a first resistor and a first capacitor connected in series, and the second RC circuit includes a second resistor and a second capacitor connected in series; the gate of the second NMOS transistor is connected between the second resistor and the second capacitor, the gate of the third NMOS transistor is connected between the first resistor and the first capacitor, the drain of the second NMOS transistor and the drain of the third NMOS transistor are connected to form the control port; the first resistor, the second capacitor and the source of the second NMOS transistor are connected to form one voltage port; the first capacitor, the second resistor and the source of the third NMOS transistor are connected to form another voltage port.

3. The NMOS-triggered bidirectional silicon-controlled rectifier according to claim 1, wherein: The electrostatic pulse detection circuit includes a first RC circuit, a second RC circuit, a first PMOS transistor, and a second PMOS transistor, wherein the first RC circuit includes a first resistor and a first capacitor connected in series, and the second RC circuit includes a second resistor and a second capacitor connected in series; the gate of the first PMOS transistor is connected between the first resistor and the first capacitor, the gate of the second PMOS transistor is connected between the second resistor and the second capacitor, and the drain of the first PMOS transistor and the drain of the second PMOS transistor are connected to form the control port; the first resistor, the second capacitor, and the source of the first PMOS transistor are connected to form one voltage port, and the first capacitor, the second resistor, and the source of the second PMOS transistor are connected to form another voltage port.

4. The NMOS-triggered bidirectional silicon-controlled rectifier according to claim 2 or 3, characterized in that: The resistance values ​​of the first resistor and the second resistor are equal, and the capacitance values ​​of the first capacitor and the second capacitor are equal.

5. The NMOS-triggered bidirectional silicon-controlled rectifier according to claim 4, wherein: The time constant of the first RC circuit and the time constant of the second RC circuit are both 1 nS to 10 nS.

6. The NMOS-triggered bidirectional silicon-controlled rectifier according to claim 5, wherein: The resistance values ​​of the first resistor and the second resistor are 1KΩ to 10KΩ, and the capacitance values ​​of the first capacitor and the second capacitor are 0.2pF to 2pF.

7. The NMOS-triggered bidirectional silicon-controlled rectifier according to claim 2 or 3, characterized in that: The control voltage is obtained according to the length of the N-type gate of the first NMOS, the doping concentration of the P-well, the time constant of the first RC circuit, and the time constant of the second RC circuit.

8. The NMOS-triggered bidirectional silicon-controlled rectifier according to claim 1, wherein: One of the voltage ports is grounded, and the other voltage port is connected to a positive voltage.

9. The NMOS-triggered bidirectional silicon-controlled rectifier according to claim 1, wherein: The depths of the first N-well, the P-well, and the second N-well are all greater than the depth of the trench isolation structure.

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