Semiconductor structure and method of making same, integrated circuit, three-dimensional memory, and system

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof, an integrated circuit, a three-dimensional memory and a system, and relates to the technical field of semiconductor chips, aiming to reduce the process difficulty of forming a gate by etching a gate conductive layer. The semiconductor structure comprises a substrate and a high-voltage transistor arranged in a first region of the substrate, and the high-voltage transistor comprises a first source electrode, a first drain electrode, a first gate dielectric layer, a first gate electrode and a first protective layer. The first gate dielectric layer comprises a first part covering the first source electrode and the first drain electrode, and a second part arranged away from the first source electrode and the first drain electrode, and the thickness of the first part is less than the thickness of the second part; the first gate electrode is arranged on the side of the second part away from the substrate; and the first protective layer covers the surface of the first gate electrode away from the substrate, and the thickness of the first protective layer is less than the thickness of the second part. The above semiconductor structure is applied to a three-dimensional memory to realize data reading and writing operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and its fabrication method, an integrated circuit, a three-dimensional memory and system. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of process technology, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit. To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging memory cells three-dimensionally on a substrate.

[0003] In 3D NAND, peripheral circuits are used for logic operations and to control and detect the switching states of each memory cell string to achieve data storage and retrieval. These peripheral circuits typically employ symmetrical or asymmetrical double-diffused metal-oxide-semiconductor (MOS) field-effect transistors (FETs). Furthermore, to fully utilize the advantages of high speed from low-voltage transistors and high voltage withstand capability from high-voltage transistors, the peripheral circuits incorporate both low-voltage and high-voltage transistors.

[0004] However, in the peripheral circuit, the process window between the protective layers on the upper side of the gates of adjacent transistors is small. As a result, when etching the gate conductive layer with the protective layer as a mask to form the gate, the process is more difficult and the equipment requirements are higher. Summary of the Invention

[0005] The embodiments of this disclosure provide a semiconductor structure and its fabrication method, an integrated circuit, a three-dimensional memory and a system, which aim to reduce the process difficulty of etching the gate conductive layer to form the gate.

[0006] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0007] On one hand, a semiconductor structure is provided. The semiconductor structure includes a substrate and a high-voltage transistor. The substrate includes a first region. The high-voltage transistor is disposed in the first region and includes a first source, a first drain, a first gate dielectric layer, a first gate, and a first protective layer. The first source and the first drain are spaced apart and extend from a first surface of the substrate into the substrate; the first surface is one of two opposing main surfaces of the substrate. The first gate dielectric layer is disposed on the first surface of the substrate; the first gate dielectric layer includes a first portion covering the first source and the first drain, and a second portion offset from the first source and the first drain, the thickness of the first portion being less than the thickness of the second portion. The first gate is disposed on the side of the second portion away from the substrate. The first protective layer covers the surface of the first gate away from the substrate, the thickness of the first protective layer being less than the thickness of the second portion.

[0008] In the semiconductor structure provided by the above embodiments of this disclosure, the thickness of the first portion of the first gate dielectric layer is less than the thickness of the second portion of the first gate dielectric layer. That is, the thickness of the first gate dielectric layer above the first source and first drain of the high-voltage transistor is less than the thickness of the first gate dielectric layer below the first gate of the high-voltage transistor. Compared with related technologies, during the process of forming the first source and first drain by ion doping of the substrate, due to the reduction in the thickness of the first gate dielectric layer above the first source and first drain of the high-voltage transistor, the thickness of the first protective layer can be correspondingly reduced while ensuring that the first protective layer prevents ion implantation into the first gate. That is, the thickness of the first protective layer is less than the thickness of the second portion. The reduction in the thickness of the first protective layer, i.e., the reduction in the thickness of the protective film used to form the first protective layer, makes the process window between the multiple protective layers (including the first protective layer) formed by patterning the protective film larger, thereby reducing the process difficulty of etching the gate conductive layer to form the gate using the protective layer as a mask and reducing equipment requirements.

[0009] In some embodiments, the high-voltage transistor further includes a first gate sidewall that covers the side of the first gate.

[0010] In some embodiments, the outer boundary of the orthographic projection of the first gate sidewall onto the substrate coincides with the boundary of the orthographic projection of the second portion onto the substrate.

[0011] In some embodiments, the material of the first gate sidewall includes silicon nitride.

[0012] In some embodiments, the thickness of the first protective layer is 5 nm to 6 nm less than the thickness of the second portion.

[0013] In some embodiments, the material of the first protective layer includes silicon nitride; and / or, the material of the first gate dielectric layer includes silicon oxide.

[0014] In some embodiments, the substrate further includes a second region. The semiconductor device structure also includes a low-voltage transistor disposed in the second region. The low-voltage transistor includes a second source, a second drain, a second gate dielectric layer, a second gate, and a second protective layer. The second source and the second drain are spaced apart and extend from a first surface of the substrate into the substrate. The second gate dielectric layer is disposed on the first surface of the substrate, and the thickness of the second gate dielectric layer is equal to the thickness of the first portion. The second gate is disposed on the side of the second gate dielectric layer away from the substrate. The second protective layer covers the surface of the second gate away from the substrate.

[0015] In some embodiments, the low-voltage transistor further includes a second gate sidewall covering the side of the second gate.

[0016] On the other hand, a method for fabricating a semiconductor structure is provided, comprising:

[0017] An intermediate semiconductor structure is fabricated; the intermediate semiconductor structure includes a first region; the intermediate semiconductor structure includes a substrate, a gate insulating film disposed on a first surface of the substrate, a first gate disposed on the side of the gate insulating film away from the substrate, and a first protective layer covering the surface of the first gate away from the substrate. The first surface is one of two opposing main surfaces of the substrate; the first gate is located in the first region, and the thickness of the first protective layer is less than the thickness of the portion of the gate insulating film located below the first gate.

[0018] The portion of the gate insulating film located in the target region is etched to reduce the thickness of the portion of the gate insulating film located in the target region to the target thickness; the target region is the area in the first region that is not covered by the first gate.

[0019] In some embodiments, the portion of the gate insulating film located in the target region is etched using a chemical gas etching process.

[0020] In some embodiments, the fabrication of the intermediate semiconductor structure includes: forming a gate insulating film on a first surface of the substrate; forming a gate conductive layer on the side of the gate insulating film away from the substrate; forming a first protective layer on the side of the gate conductive layer away from the substrate; the orthogonal projection of the first protective layer on the substrate is the region corresponding to the first gate formed in a predetermined manner; and etching the gate conductive layer using the first protective layer as a mask to form the first gate.

[0021] In some embodiments, the intermediate semiconductor structure further includes a second region. During the formation of the first protective layer on the side of the gate conductive layer away from the substrate, a second protective layer is also formed. The orthogonal projection of the second protective layer onto the substrate corresponds to the region of a pre-formed second gate. During the etching of the gate conductive layer using the first protective layer as a mask to form the first gate, the second protective layer is also used as a mask to etch the gate conductive layer to form the second gate; the second gate is located in the second region.

[0022] In some embodiments, forming a gate insulating film on the first surface of the substrate includes: forming an initial gate insulating film on the first surface of the substrate; thinning the thickness of the portion of the initial gate insulating film located in the second region to form the gate insulating film.

[0023] In some embodiments, the target thickness is equal to the thickness of the portion of the gate insulating film covering the second region.

[0024] In some embodiments, between the fabrication of the intermediate semiconductor structure and the etching of the portion of the gate film located in the target region, the fabrication method further includes: forming a photoresist layer covering the second region.

[0025] In some embodiments, prior to forming the photoresist layer covering the second region, the fabrication method further includes: forming a first gate sidewall covering the side of the first gate and a second gate sidewall covering the side of the second gate.

[0026] In some embodiments, after etching the portion of the gate insulating film located in the target region, the method further includes: removing the photoresist layer. The substrate is ion-doped to form a first source and a first drain on both sides of the first gate in the target region, and a second source and a second drain on both sides of the second gate in the second region.

[0027] In another aspect, an integrated circuit is provided. The integrated circuit includes a semiconductor structure, which is the semiconductor structure described in some of the above embodiments or is fabricated by the method described in some of the above embodiments for fabricating a semiconductor structure.

[0028] In another aspect, a three-dimensional memory is provided. The three-dimensional memory includes an integrated circuit and a memory array device as described in some of the embodiments above, the memory array device being coupled to the integrated circuit.

[0029] In another aspect, a storage system is provided. The storage system includes a controller and a three-dimensional memory as described in some of the embodiments above, the controller being coupled to the three-dimensional memory to control the storage of data in the three-dimensional memory.

[0030] It is understood that the beneficial effects that the semiconductor structure fabrication method, integrated circuit, three-dimensional memory and storage system provided in the above embodiments of this disclosure can achieve can be referred to the beneficial effects of the semiconductor structure described above, and will not be repeated here. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0032] Figure 1 This is a block diagram of a storage system according to some embodiments;

[0033] Figure 2 A block diagram of a storage system according to some other embodiments;

[0034] Figure 3 This is a cross-sectional view of the device structure during the fabrication process of a semiconductor structure in related technologies;

[0035] Figure 4 A cross-sectional view of a three-dimensional memory according to some embodiments;

[0036] Figure 5 A top view of an integrated circuit (peripheral circuit) of a three-dimensional memory according to some embodiments;

[0037] Figure 6 for Figure 5 The external circuit shown is a cross-sectional view along section line AA'.

[0038] Figure 7 for Figure 5 The external circuit shown is a cross-sectional view along section line BB'.

[0039] Figure 8 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0040] Figure 9 for Figure 8 The diagram shows the preparation steps of the preparation method.

[0041] Figure 10 for Figure 8 The diagram shows the preparation steps of the preparation method.

[0042] Figure 11 for Figure 8 The preparation steps of the preparation method shown are illustrated in the diagram.

[0043] Figure 12 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0044] Figure 13 for Figure 12 The preparation steps of the preparation method shown are illustrated in the diagram.

[0045] Figure 14 for Figure 12 The preparation steps of the preparation method shown are illustrated in the diagram.

[0046] Figure 15 for Figure 12 The preparation steps of the preparation method shown are illustrated in the diagram.

[0047] Figure 16 for Figure 12 The preparation steps of the preparation method shown are illustrated in the diagram.

[0048] Figure 17 for Figure 12 The preparation steps of the preparation method shown are illustrated in the diagram.

[0049] Figure 18 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0050] Figure 19 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0051] Figure 20 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0052] Figure 21 for Figure 20 The preparation steps of the preparation method shown are illustrated in the diagram.

[0053] Figure 22 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0054] Figure 23 for Figure 22 The preparation steps of the preparation method shown are illustrated in the diagram.

[0055] Figure 24 for Figure 22 The preparation steps of the preparation method shown are illustrated in the diagram.

[0056] Figure 25 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0057] Figure 26This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0058] Figure 27 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments. Detailed Implementation

[0059] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0060] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0061] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0062] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0063] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0064] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0065] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0066] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0067] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0068] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0069] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0070] The term "three-dimensional memory" refers to a semiconductor device formed by strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicularly" means nominally perpendicular to the main surface of the substrate (i.e., the lateral surface).

[0071] Figure 3 This is a cross-sectional view of the device structure 100' during the fabrication process of a semiconductor structure in the related technology.

[0072] like Figure 3 As shown, the semiconductor structure 100' includes a substrate 110' and a plurality of transistors formed on the substrate 110', such as high voltage (HV) MOS, low voltage (LV) MOS and low voltage (LLV) MOS.

[0073] To meet the performance requirements of different transistors, the thickness of the gate dielectric layer may vary. For example, ... Figure 3 As shown, the thickness of the gate dielectric layer 120' of the HV MOS is greater than the thickness of the gate dielectric layer 121' of the LV MOS and LLV MOS.

[0074] To ensure that the ion doping process for forming the source and drain electrodes does not affect the gate, a protective layer is provided on top of the gate. In related technologies, such as... Figure 1 As shown, the protective layer 140' on the upper side of the gate 130' of the HV MOS is relatively thick, usually greater than or approximately equal to the thickness of the gate dielectric layer 120' of the HV MOS, to ensure that the subsequent ion doping process to form the source and drain electrodes will not affect the gate 130'.

[0075] In the process of forming the gate of a MOSFET, a protective layer 140' with the pattern of the gate to be formed is first etched. Then, the lower gate conductive layer is etched using the protective layer 140' as a mask to form the gate. However, during the etching process of the protective layer 140', the relatively large thickness of the protective layer 140' results in a small process window between the protective layers 140' of adjacent MOSFETs. Furthermore, because the side of the etched protective layer 140' is sloping, the opening at the end of the process window closer to the lower gate conductive layer is smaller than the opening at the end farther from the gate conductive layer. Therefore, etching the gate conductive layer using the protective layer 140' as a mask to form the gate 130' is technically challenging and requires sophisticated equipment.

[0076] Based on this, please see Figure 6 Some embodiments of this disclosure provide a semiconductor structure 100, which includes a substrate 110, a high-voltage transistor 120, and a low-voltage transistor 130. The low-voltage transistor 130 may also be a low-low voltage transistor, and this disclosure is not limited thereto.

[0077] It should be noted that the semiconductor structure 100 provided in this embodiment can be used to construct peripheral devices in a three-dimensional memory. Please refer to... Figure 4 , Figure 4 A cross-sectional structure of a three-dimensional memory 300 is shown, which includes a memory array device 400 and an integrated circuit 200 (i.e., the peripheral device mentioned above) that are electrically connected to each other. See also... Figure 5 , Figure 5 The top view of the integrated circuit 200 is shown, and it can be seen that the integrated circuit 200 includes at least one of the aforementioned semiconductor structures 100.

[0078] Figure 6 It shows Figure 5 The cross-sectional structure of integrated circuit 200 along section line AA'. See also Figure 6 The substrate 110 includes a first region HV, a second region LV, and an isolation region S. The isolation region S is configured to electrically isolate the first region HV and the second region LV from at least a portion of the transistors adjacent to them. Exemplarily, the isolation region S of the substrate 110 has an isolation groove extending from a first surface 111 of the substrate 110 into the substrate 110, thereby dividing the substrate 110 into the first region HV and the second region LV. The first surface 111 is one of two opposing main surfaces of the substrate 110. The isolation groove is filled with an insulating material to form an isolation structure 112, thereby electrically isolating the first region HV and the second region LV from the transistors adjacent to them. The substrate 110 may be made of at least one of silicon, silicon-germanium, germanium, and silicon-on-insulator thin films, but is not limited thereto.

[0079] It should be noted that there may be a gap between the boundary of isolation region S and the boundary of the first region HV and the boundary of the second region LV, or they may be directly adjacent. This disclosure does not limit this. The first region HV is a high-voltage region and is configured to house high-voltage devices, such as high-voltage transistor 120; the second region LV is a low-voltage region and is configured to house low-voltage devices, such as low-voltage transistor 130.

[0080] The high voltage transistor 120 is disposed in the first region HV. The high voltage transistor 120 includes a first source 121, a first drain 122, a first gate dielectric layer 123, a first gate 124 and a first protective layer 125. The first source 121 and the first drain 122 are disposed at intervals and extend from the first surface 111 of the substrate 110 into the substrate 110.

[0081] A first gate dielectric layer 123 is disposed on the first surface 111 of the substrate 110. The first gate dielectric layer 123 includes a first portion 1231 covering the first source 121 and the first drain 122, and a second portion 1232 offset from the first source 121 and the first drain 122. The thickness of the first portion 1231 is less than the thickness of the second portion 1232. This allows for a reduction in the thickness of the first gate dielectric layer 123 above the first source 121 and the first drain 122 while meeting the performance requirements of the high-voltage transistor 120. This facilitates ion penetration through the first portion 1231 of the first gate dielectric layer 123 into the substrate 110 to form the first source 121 and the first drain 122.

[0082] A first gate 124 is disposed on the side of the second portion 1232 of the first gate dielectric layer 123 away from the substrate 110; a first protective layer 125 covers the surface of the first gate 124 away from the substrate 110. The first protective layer 125 can serve as a mask for forming the first gate 124, and during the formation of the first source 121 and the first drain 122, it can protect the first gate 124 on the surface of the first gate 124 away from the substrate 110, preventing ion implantation into the first gate 124. The thickness of the first protective layer 125 is less than the thickness of the second portion 1232 of the first gate dielectric layer 123.

[0083] As can be seen from the above, in the semiconductor structure 100 provided by the above embodiments of this disclosure, the thickness of the first portion 1231 of the first gate dielectric layer 123 is less than the thickness of the second portion 1232 of the first gate dielectric layer 123. That is, the thickness of the first gate dielectric layer 123 below the first source 121 and the first drain 122 of the high voltage transistor 120 is less than the thickness of the first gate dielectric layer 123 above the first gate 124 of the high voltage transistor 120.

[0084] Compared with related technologies, during the process of forming the first source 121 and the first drain 122 by ion doping of the substrate 110, the thickness of the first gate dielectric layer 123 above the first source 121 and the first drain 122 of the high-voltage transistor 120 is reduced. Therefore, while ensuring that the first protective layer 125 prevents ion implantation into the first gate 124, the thickness of the first protective layer 125 can be correspondingly reduced. That is, the thickness of the first protective layer 125 is less than the thickness of the second portion 1232 of the first gate dielectric layer 123.

[0085] Figure 7 It shows Figure 5 The cross-sectional structure of integrated circuit 200 along section line BB'. See also... Figure 7 Since the thickness of the first protective layer 125 is less than the thickness of the second portion 1232 of the first gate dielectric layer 123, the thickness of the first protective layer 125 is reduced, that is, the thickness of the protective film used to form the first protective layer 125 is reduced, which makes the process window between the multiple protective layers (including the first protective layer 125) formed by patterning the protective film larger, thereby reducing the process difficulty of etching the gate conductive layer with the protective layer as a mask to form the gate (including the first gate 124) and reducing equipment requirements.

[0086] like Figure 6 As shown, the low-voltage transistor 130 is disposed in the second region LV. The low-voltage transistor 130 includes a second source 131, a second drain 132, a second gate dielectric layer 133, a second gate 134, and a second protective layer 135. The second source 131 and the second drain 132 are disposed at intervals and extend from the first surface 111 of the substrate 110 into the substrate 110.

[0087] The second gate dielectric layer 133 is disposed on the first surface 111 of the substrate 110. The thickness of the second gate dielectric layer 133 is approximately equal to the thickness of the first portion 1231 of the first gate dielectric layer 123. In this way, the second gate dielectric layer 133 can use the same material as the first gate dielectric layer 123 and be fabricated in the same process, thereby simplifying the process steps.

[0088] It should be noted that the materials of the first gate dielectric layer 123 and the second gate dielectric layer 133 include silicon oxide, but are not limited to it.

[0089] The second gate 134 is disposed on the side of the second gate dielectric layer 123 away from the substrate 110, and the second protective layer 135 covers the surface of the second gate 134 away from the substrate 110. The second protective layer 135 can serve as a mask for forming the second gate 134, and during the formation of the second source 131 and the second drain 132, it can protect the second gate 134 on the surface of the second gate 134 away from the substrate 110.

[0090] See Figure 6 In some embodiments, the thickness of the first protective layer 125 is 5 nm to 6 nm less than the thickness of the second portion 1232 of the first gate dielectric layer 123. For example, the thickness of the first protective layer 125 is any one of 5 nm, 5.2 nm, 5.4 nm, 5.6 nm, 5.8 nm, or 6 nm less than the thickness of the second portion 1232 of the first gate dielectric layer 123.

[0091] In addition, the thickness of the first protective layer 125 is greater than the thickness of the first portion 1231 of the first gate dielectric layer 123, so as to avoid the first protective layer 125 being too thin to effectively protect the first gate 124.

[0092] Similarly, the thickness of the second protective layer 135 is greater than the thickness of the second gate dielectric layer 133, so as to avoid the second protective layer 135 being too thin to effectively protect the second gate 134.

[0093] In some embodiments, the materials of the first protective layer 125 and the second protective layer 135 include silicon nitride, but are not limited thereto. Exemplarily, the first protective layer 125 and the second protective layer 135 are made of the same material and have approximately equal thicknesses, so that the first protective layer 125 and the second protective layer 135 can be made of the same material and fabricated in the same process, thereby simplifying the process steps.

[0094] During the formation of the first gate dielectric layer 123, and during the formation of the first source 121 and the first drain 122, in order to protect the first gate 124 from the sidewalls and prevent the first source 121 and the first drain 122 from becoming too close to the channel during the large-dose ion implantation into the substrate 110, thus causing the channel to be too short or even connected, see [see details]. Figure 6 In some embodiments, the high-voltage transistor 120 further includes a first gate sidewall 126, which covers the side of the first gate 124. The first gate sidewall 126 can be a single-layer structure or a multilayer structure. Exemplarily, the first gate sidewall 126 is a single-layer structure, and the material of the first gate sidewall 126 includes silicon nitride.

[0095] In some embodiments, the outer boundary of the orthographic projection of the first gate sidewall 126 onto the substrate 110 substantially coincides with the boundary of the orthographic projection of the second portion 1232 of the first gate dielectric layer 123 onto the substrate 110.

[0096] During the formation of the second gate dielectric layer 133, and during the formation of the second source 131 and the second drain 132, in order to protect the second gate 134 from the sidewalls and prevent the second source 131 and the second drain 132 from becoming too close to the channel during the large-dose ion implantation into the substrate 110, thus causing the channel to be too short or even connected, see [reference needed]. Figure 6 In some embodiments, the low-voltage transistor 120 further includes a second gate sidewall 136, which covers the side of the second gate 134. The second gate sidewall 136 can be a single-layer structure or a multilayer structure. Exemplarily, the second gate sidewall 136 is a single-layer structure, and the material of the second gate sidewall 136 includes silicon nitride.

[0097] like Figure 6 As shown, in some embodiments, the semiconductor structure 100 further includes a gate oxide layer 140, which is disposed on the side of the first protective layer 125 and the second protective layer 135 away from the substrate 110 to protect the first gate 123 and the second gate 124 and reduce contact resistance. The material of the gate oxide layer 140 includes silicon oxide, but is not limited to it.

[0098] For example, in addition to covering the first protective layer 125 and the second protective layer 135, the gate oxide layer 140 may also cover the first portion 1231 of the first gate dielectric layer 123 (i.e., the portion of the first gate dielectric layer 123 not covered by the first gate 124) and the portion of the second gate dielectric layer 133 not covered by the second gate 134. When the high-voltage transistor 120 further includes a first gate sidewall 126 and the low-voltage transistor 130 further includes a second gate sidewall 136, the gate oxide layer 140 may also cover the first gate sidewall 126 and the second gate sidewall 136.

[0099] like Figure 6 As shown, to reduce the drain field and improve hot electron degradation, in some embodiments, the high-voltage transistor 120 further includes a lightly doped drain region 127. The lightly doped drain region 127 extends from the first surface 111 of the substrate 110 into the substrate 110, and the first source 121 and the first drain 122 of the high-voltage transistor 120 are located within the lightly doped drain region 127. In this way, the lightly doped drain region 127 also withstands a portion of the voltage, which can prevent the hot electron degradation effect.

[0100] The lightly doped drain region 127 can be formed by ion implantation. For example, a mask layer is formed on the first surface 111 of the substrate 110, exposing the region for forming the lightly doped region 127. Ion implantation is performed in the exposed region to form the lightly doped region 127. The implanted ions can be arsenic ions.

[0101] like Figure 6 As shown, in some embodiments, the semiconductor structure 100 further includes a first well region 150 and a second well region 160. The first well region 150 is located in the first region HV and extends from the first surface 111 of the substrate 110 into the substrate 110. The first source 121 and the first drain 122 of the high-voltage transistor 120 are located within the first well region 150. If the high-voltage transistor 120 further includes a lightly doped region 127, the lightly doped region 127 is located within the first well region 150. The second well region 160 is located in the second region LV and extends from the first surface 111 of the substrate 110 into the substrate 110. The second source 131 and the second drain 132 are located within the second well region 160.

[0102] The first well region 150 and the second well region 160 can be formed by implanting impurity ions into the substrate 110. For example, a patterned mask layer is formed on the first surface 111 of the substrate 110, and the patterned mask layer exposes the predetermined formation areas of the first well region 150 and the second well region 160; impurity ions are implanted into the predetermined formation areas of the substrate 110 by an ion implantation process to form the first well region 150 and the second well region 160.

[0103] It should be noted that the doping type of the first well region 150 is different from that of the second well region 160. The first well region 150 is doped with N-type impurities, which include phosphorus ions or arsenic ions, but are not limited to these; the second well region 160 is doped with P-type impurities, which include boron ions or gallium ions, but are not limited to these.

[0104] like Figure 8 As shown, some embodiments of this disclosure also provide a semiconductor structure 100 (see...). Figure 6 The preparation methods of ) include S1 to S2.

[0105] S1: See Figure 8 and Figure 9 , Prepare intermediate semiconductor structure 101.

[0106] In the above steps, the intermediate semiconductor structure 101 includes a first region 120. The intermediate semiconductor structure includes a substrate 110, a gate insulating film 1230 disposed on a first surface 111 of the substrate 110, a first gate 124 disposed on the side of the gate insulating film 1230 away from the substrate 110, and a first protective layer 125 covering the surface of the first gate 124 away from the substrate 110. It should be noted that the first surface 111 is one of two opposing main surfaces of the substrate 110; the material of the gate insulating film 1230 includes silicon oxide, but is not limited to it; the first region HV is a high-voltage region, configured to house a high-voltage device, such as a high-voltage transistor 120.

[0107] The first gate 124 is located in the first region HV, and the thickness of the first protective layer 125 is less than the thickness of the portion of the gate insulating film 123 located below the first gate 124.

[0108] S2: See also Figure 8 and Figure 11 The portion of the gate insulating film 1230 located in the target region M is etched to reduce the thickness of the portion of the gate insulating film 1230 located in the target region M to the target thickness.

[0109] In the above steps, the target region M is the region in the first region HV that is not covered by the first gate 124.

[0110] Furthermore, the portion of the gate insulating film 1230 located in the target region M is etched using a chemical gas etching process. For example, a CATERAS (chemical gas etching) machine is used to etch the first region HV. Compared to plasma etching, chemical gas etching does not involve plasma, thus avoiding the problem of charged particles accumulating in the substrate 110 and the first gate 124, preventing plasma-induced damage (PID), and improving product yield.

[0111] See Figure 12 In some embodiments, S1 includes S11 to S14.

[0112] S11: See also Figure 12 and Figure 13 A gate insulating film 1230 is formed on the first surface 111 of the substrate 110.

[0113] S12: See also Figure 12 and Figure 15 A gate conductive layer 1241 is formed on the side of the gate insulating film 1230 away from the substrate 110.

[0114] In the above steps, the gate conductive layer 1241 can be formed by atomic layer deposition, physical vapor deposition, or chemical vapor deposition. For example, plasma chemical vapor deposition is used to form a polysilicon layer on the side of the gate insulating film 1230 away from the substrate 110, and the polysilicon layer is doped to form the gate conductive layer.

[0115] S13: See also Figure 12 and Figure 16 A first protective layer 125 is formed on the side of the gate conductive layer 1241 away from the substrate 110.

[0116] The orthographic projection of the first protective layer 125 onto the substrate 110 is the region corresponding to the pre-formed first gate 124.

[0117] S14: See also Figure 12 and Figure 17 Using the first protective layer 125 as a mask, the gate conductive layer 1241 is etched to form the first gate 124.

[0118] For example, an anisotropic plasma etching machine is used to etch the gate conductive layer 1241 to form the first gate 124.

[0119] See Figure 9 In some embodiments, the intermediate semiconductor structure 101 further includes a second region LV and an isolation region S. The second region LV is a low-voltage region configured to house low-voltage devices, such as low-voltage transistors 130; the isolation region S is configured to electrically isolate the first region HV and the second region LV from at least a portion of the transistors adjacent to them.

[0120] In this case, see Figure 16 In process S13, a second protective layer 135 is also formed. The orthogonal projection of the second protective layer 135 onto the substrate 110 is the region corresponding to the pre-formed second gate 134.

[0121] Based on this, see Figure 17 In process S14, the gate conductive layer 1241 is etched using the second protective layer 135 as a mask to form the second gate 134; the second gate 134 is located in the second region LV.

[0122] See Figure 18 In some embodiments, S11 includes S111 to S112.

[0123] S111: See also Figure 13 and Figure 18 An initial gate insulating film 1230 is formed on the first surface 111 of the substrate 110.

[0124] For example, such as Figure 13 As shown, the above steps include sequentially forming a first sub-gate insulating film 1233 and a second sub-gate insulating film 1234, both of which cover the first region HV and the second region LV, and together they form the initial gate insulating film 1230. The first sub-gate insulating film 1233 and the second sub-gate insulating film 1234 can be deposited by techniques such as chemical vapor deposition, physical vapor deposition, and plasma enhancement.

[0125] For example, an initial gate insulating film 1230 can be formed directly, the thickness of which is equal to the preset thickness of the gate dielectric layer 123 located below the gate of the high voltage transistor 120.

[0126] S112: See also Figure 13 , Figure 14 and Figure 18The thickness of the portion of the initial gate insulating film 1230 located in the second region LV is reduced to form the gate insulating film 1235.

[0127] For example, when the initial gate insulating film 1230 includes a first sub-gate insulating film 1233 and a second sub-gate insulating film 1234, this step includes: removing the portion of the second sub-gate insulating film 1234 located in the second region LV, and the remaining second sub-gate insulating film 1234 and the underlying first sub-gate insulating film 1233 forming a gate insulating film 1235. It can be seen that, for the initial gate insulating film 1230 as a whole, this is equivalent to thinning the thickness of the portion of the initial gate insulating film 1230 located in the second region LV, thereby obtaining the gate insulating film 1235. That is, the thickness of the portion of the gate insulating film 123 covering the first region HV is greater than the thickness of the portion covering the second region LV.

[0128] It should be noted that the target thickness in S2 above is approximately equal to the thickness of the portion of the gate insulating film 1230 covering the second region LV.

[0129] See Figure 19 In some embodiments, the preparation method described above further includes S3 between S1 and S2.

[0130] S3: See also Figure 10 and Figure 19 A photoresist layer 170 covering the second region LV is formed.

[0131] In the above steps, the photoresist layer 170 covers the second protective layer 135 and the portion of the gate insulating film 1230 covering the second region LV that is not covered by the second gate 124. In this way, when etching the target region M in S2, the photoresist layer 170 covers the second region LV, preventing the gate insulating film 1230 on the second region LV from being etched away, thereby avoiding damage to the substrate 110.

[0132] See Figure 20 In some embodiments, the preparation method described above further includes S4 before S3.

[0133] S4: See also Figure 20 and Figure 21 A first gate sidewall 126 is formed covering the side of the first gate 124, and a second gate sidewall 136 is formed covering the side of the second gate 134.

[0134] For example, silicon nitride is deposited on one side of the first surface 111 of the substrate 110 using chemical vapor deposition, and then the silicon nitride on the first surface 111 of the substrate 110 and the surface of the first gate 124 away from the substrate 110 is removed by dry etching, thereby forming the first gate sidewall 126 and the second gate sidewall 136.

[0135] It should be noted that after executing S4, see [link / reference]. Figure 23 and Figure 24 In S2, the target region M is the region in the first region HV that is not covered by the first gate 124 and its first gate sidewall 126.

[0136] See Figure 22 In some embodiments, after S2, the preparation method further includes S5 to S6.

[0137] S5: See also Figure 22 and Figure 23 Remove the photoresist layer 170 (see Figure 11 ).

[0138] S6: See also Figure 22 and Figure 24 The substrate 110 is ion-doped to form a first source 121 and a first drain 122 on both sides of the first gate 124 in the target region M, and a second source 131 and a second drain 132 on both sides of the second gate 134 in the second region LV. The ion doping method can be either ion implantation or ion diffusion.

[0139] In some embodiments, see Figure 6 The semiconductor structure 100 also includes an isolation structure 112. See [link / reference] Figure 25 Before S11, the above steps also include S15.

[0140] S15: An isolation structure 112 is formed on the substrate 110.

[0141] In the above steps, the isolation structure 112 can be formed by local silicon oxidation, or it can be a shallow trench isolation (STI) structure. Exemplarily, an isolation trench is formed on the first surface of the substrate 110 using photolithography and etching, and an insulating material is filled within the isolation trench. The insulating material may include at least one of silicon oxide, silicon oxynitride, ethoxysilane, low-temperature oxide, high-temperature oxide, and silicon nitride, but is not limited thereto.

[0142] In some embodiments, see Figure 6 The semiconductor structure 100 also includes a first well region 150 and a second well region 160. See [link / reference] Figure 26 Before S11, the above steps also include S16 to S17.

[0143] S16: A first well region 150 is formed in the first region HV on the substrate 110, and the first well region 150 extends from the first surface 111 of the substrate 110 into the substrate 110.

[0144] In the above steps, the first well region 150 can be formed by implanting impurity ions into the substrate 110. For example, a patterned mask layer is formed on the first surface 111 of the substrate 110, and the patterned mask layer exposes a predetermined formation area of ​​the first well region 150; impurity ions are implanted into the predetermined formation area of ​​the substrate 110 by an ion implantation process to form the first well region 150.

[0145] It should be noted that the first well region 150 is doped with N-type, that is, impurity ions, including phosphorus ions or arsenic ions, are implanted into the predetermined formation region of the substrate 110 through ion implantation process, but are not limited to these.

[0146] S17: A second well region 160 is formed in the second region LV on the substrate 110, and the second well region 160 extends from the first surface 111 of the substrate 110 into the substrate 110.

[0147] In the above steps, the second well region 160 can be formed by implanting impurity ions into the substrate 110. For example, a patterned mask layer is formed on the first surface 111 of the substrate 110, and the patterned mask layer exposes a predetermined formation area of ​​the second well region 160; impurity ions are implanted into the predetermined formation area of ​​the substrate 110 by an ion implantation process to form the second well region 160.

[0148] It should be noted that the doping type of the second well region 160 is P-type, that is, impurity ions, including boron ions or gallium ions, are implanted into the predetermined formation region of the substrate 110 through an ion implantation process, but are not limited to these.

[0149] It should be noted that the execution order of S16 and S17 is not limited; S16 can be executed first and then S17, or S17 can be executed first and then S16.

[0150] In some embodiments, see Figure 6 The semiconductor structure 100 also includes a lightly doped region 127. See [link / reference] Figure 27 Before S5, the above steps also include S7.

[0151] S7: Ion doping is performed on the substrate 110 to form lightly doped regions 127 on both sides of the first gate 124 in the target region M.

[0152] In the above steps, the lightly doped drain region 127 can be formed by ion implantation. Exemplarily, a mask layer is formed on the first surface 111 of the substrate 110, exposing the region for forming the lightly doped region 127. Ion implantation is performed in the exposed region to form the lightly doped region 127. It should be noted that the implanted ions can be arsenic ions.

[0153] See Figure 5Some embodiments of this disclosure also provide an integrated circuit 200, which includes a semiconductor structure 100. The semiconductor structure 100 is the semiconductor structure 100 of the above embodiments or is fabricated by the methods described above for fabricating the semiconductor structure 100. The integrated circuit 200 may, for example, be a three-dimensional memory 300 (see...). Figure 4 The array 410 (see) is used to control and detect each memory cell string array. Figure 4 ( ) is a peripheral device that enables data storage and retrieval by controlling the switching state of the device.

[0154] The peripheral device may include, for example, a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, and a series of other circuits 210 (see [link to relevant documentation]). Figure 4 The peripheral device includes a series of circuits 210 (see...). Figure 4 At least one of them includes the aforementioned semiconductor structure 100.

[0155] Please see Figure 4 Some embodiments of this disclosure also provide a three-dimensional memory 300, which includes an integrated circuit 200 and a memory array device 400 as described in some embodiments above. The memory array device 400 is electrically connected to the integrated circuit 200 to enable the integrated circuit 200 to support the functions of the memory array device 400, such as reading, writing and erasing data in the memory cells.

[0156] See Figure 4 In some embodiments, the memory array device 400 includes a memory cell string array 410 and an array interconnect layer 420 disposed on the side of the memory cell string array 410 near the integrated circuit 200, with the memory cell string array 410 electrically connected to the array interconnect layer 420. The integrated circuit 200 includes a series of circuits 210, such as page buffers, and a peripheral interconnect layer 220 disposed on the side of the series of circuits 210 near the memory array device 400, with the series of circuits 210 electrically connected to the peripheral interconnect layer 220. The memory array device 400 and the integrated circuit 200 are electrically connected through the array interconnect layer 420 and the peripheral interconnect layer 220, thereby enabling the memory cell string array 410 to be electrically connected to the series of circuits 210.

[0157] Figure 1 This is a block diagram of a storage system 10 according to some embodiments. Figure 2 This is a block diagram of a storage system 10 according to some other embodiments. See also... Figure 1 and Figure 2Some embodiments of this disclosure also provide a storage system 10. The storage system 10 includes a controller 500 and a three-dimensional memory 300 as described in some of the embodiments above, the controller 500 being coupled to the three-dimensional memory 300 to control the three-dimensional memory 300 to store data.

[0158] The storage system 10 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 10 can be applied to and packaged into different types of electronic products, such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0159] In some embodiments, see Figure 1 The storage system 10 includes a controller 500 and a three-dimensional memory 300, and the storage system 10 can be integrated into a memory card.

[0160] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0161] In other embodiments, see Figure 2 The storage system 10 includes a controller 500 and multiple three-dimensional storage devices 300, and the storage system 10 is integrated into a solid state drive (SSD).

[0162] In some embodiments of the storage system 10, the controller 500 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0163] In other embodiments, the controller 500 is configured to operate in a high duty cycle environment using SSDs or eMMCs, which are used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0164] In some embodiments, the controller 500 may be configured to manage data stored in the 3D memory 300 and to communicate with external devices (e.g., a host). In some embodiments, the controller 500 may also be configured to control the operation of the 3D memory 300, such as read, erase, and program operations. In some embodiments, the controller 500 may also be configured to manage various functions relating to data stored or to be stored in the 3D memory 300, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the controller 500 is also configured to process error correction codes relating to data read from or written to the 3D memory 300.

[0165] Of course, controller 500 can also perform any other suitable functions, such as formatting the three-dimensional memory 300. For example, controller 500 can communicate with external devices (e.g., a host) through at least one of various interface protocols.

[0166] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0167] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, including the first region; A high-voltage transistor, disposed in the first region, includes: A first source and a first drain, spaced apart, extend from a first surface of the substrate into the substrate; the first surface is one of two opposing main surfaces of the substrate. A first gate dielectric layer is disposed on a first surface of the substrate; the first gate dielectric layer includes a first portion covering the first source and the first drain, and a second portion offset from the first source and the first drain, wherein the thickness of the first portion is less than the thickness of the second portion; A first gate is disposed on the side of the second portion away from the substrate; A first protective layer covers the surface of the first gate away from the substrate, and the thickness of the first protective layer is less than the thickness of the second portion; the thickness of the first protective layer is greater than the thickness of the first portion.

2. The semiconductor structure according to claim 1, characterized in that, The high-voltage transistor also includes: The first gate sidewall covers the side of the first gate.

3. The semiconductor structure according to claim 2, characterized in that, The outer boundary of the orthographic projection of the first gate sidewall onto the substrate coincides with the boundary of the orthographic projection of the second portion onto the substrate.

4. The semiconductor structure according to claim 2, characterized in that, The material of the first gate sidewall includes silicon nitride.

5. The semiconductor structure according to claim 1, characterized in that, The thickness of the first protective layer is 5nm to 6nm less than the thickness of the second part.

6. The semiconductor structure according to claim 1, characterized in that, The material of the first protective layer includes silicon nitride; and / or, the material of the first gate dielectric layer includes silicon oxide.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that, The substrate further includes a second region; the semiconductor structure further includes: A low-voltage transistor, disposed in the second region, includes: A second source and a second drain, spaced apart, extend from the first surface of the substrate into the substrate; A second gate dielectric layer is disposed on the first surface of the substrate, and the thickness of the second gate dielectric layer is equal to the thickness of the first portion; The second gate is disposed on the side of the second gate dielectric layer away from the substrate; A second protective layer covers the surface of the second gate away from the substrate.

8. The semiconductor structure according to claim 7, characterized in that, The low-voltage transistor also includes: The second gate sidewall covers the side of the second gate.

9. A method for fabricating a semiconductor structure, characterized in that, include: Preparation of intermediate semiconductor structures; The intermediate semiconductor structure includes a first region; the intermediate semiconductor structure includes: a substrate, a gate insulating film disposed on a first surface of the substrate, a first gate disposed on the side of the gate insulating film away from the substrate, and a first protective layer covering the surface of the first gate away from the substrate; the first surface is one of two opposing main surfaces of the substrate; the first gate is located in the first region, and the thickness of the first protective layer is less than the thickness of the portion of the gate insulating film located below the first gate; The portion of the gate insulating film located in the target region is etched to reduce the thickness of the portion of the gate insulating film located in the target region to a target thickness; the target region is the region in the first region not covered by the first gate; the thickness of the first protective layer is greater than the target thickness.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The portion of the gate insulating film located in the target region is etched using a chemical gas etching process.

11. The method for preparing a semiconductor structure according to claim 9, characterized in that, The preparation of the intermediate semiconductor structure includes: A gate insulating film is formed on the first surface of the substrate; A gate conductive layer is formed on the side of the gate insulating film away from the substrate; A first protective layer is formed on the side of the gate conductive layer away from the substrate; the orthographic projection of the first protective layer on the substrate is the region corresponding to the first gate formed in a predetermined manner; Using the first protective layer as a mask, the gate conductive layer is etched to form the first gate.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, The intermediate semiconductor structure further includes a second region. During the process of forming the first protective layer on the side of the gate conductive layer away from the substrate, a second protective layer is also formed. The orthographic projection of the second protective layer on the substrate is the region corresponding to the pre-formed second gate. During the process of etching the gate conductive layer using the first protective layer as a mask to form the first gate, the second protective layer is also used as a mask to etch the gate conductive layer to form the second gate; the second gate is located in the second region.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, The formation of the gate insulating film on the first surface of the substrate includes: An initial gate insulating film is formed on the first surface of the substrate; The thickness of the portion of the initial gate insulating film located in the second region is reduced to form the gate insulating film.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, The target thickness is equal to the thickness of the portion of the gate insulating film that covers the second region.

15. The method for preparing a semiconductor structure according to any one of claims 12 to 14, characterized in that, Between the fabrication of the intermediate semiconductor structure and the etching of the portion of the gate insulating film located in the target region, the method further includes: A photoresist layer covering the second region is formed.

16. The method for preparing a semiconductor structure according to claim 15, characterized in that, Before forming the photoresist layer covering the second region, the method further includes: A first gate sidewall is formed that covers the side of the first gate, and a second gate sidewall is formed that covers the side of the second gate.

17. The method for preparing a semiconductor structure according to claim 15, characterized in that, After etching the portion of the gate insulating film located in the target region, the method further includes: Remove the photoresist layer; The substrate is ion-doped to form a first source and a first drain on both sides of the first gate in the target region, and a second source and a second drain on both sides of the second gate in the second region.

18. An integrated circuit, characterized in that, Includes a semiconductor structure, wherein the semiconductor structure is the semiconductor structure as described in any one of claims 1 to 8 or is prepared by the method for preparing the semiconductor structure as described in any one of claims 9 to 17.

19. A three-dimensional memory, characterized in that, include: The integrated circuit as described in claim 18; A storage array device coupled to the integrated circuit.

20. A storage system, characterized in that, It includes a controller and a three-dimensional memory as described in claim 19, the controller being coupled to the three-dimensional memory to control the three-dimensional memory to store data.

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