Nanosheet gated diode

Abstract

One or more gated nanosheet diodes are disposed on a substrate and made from a nanosheet structure. A first (second) source / drain (S / D) is disposed on the substrate. The first (second) S / D has a first (second) S / D doping concentration of a first (second) S / D doping type. One or more p-n junctions form one or more respective diodes. Each of the p-n junctions has a first side and a second side. The first (second) side of the p-n junction is electrically and physically connected to the first (second) S / D and has a same type of doping, respectively. A gate stack made from a gate dielectric layer and a gate metal interfaces and surrounds each of the p-n junctions.

Description

Technical Field

[0001] This invention relates to an improved semiconductor diode. More specifically, this invention relates to one or more gating diodes and a method for manufacturing gating diodes from nanosheets. Background Technology

[0002] Nanosheets are thin semiconductor layers. Nanosheets are laminated together to form nanosheet stacks.

[0003] Nanosheet technology is being pursued as a viable option for fabricating small devices targeting 5 nanometers (nm). Nanosheet stacks are used as precursor structures for fabricating devices like field-effect transistors (FETs).

[0004] Diodes are semiconductor devices widely used in many circuit applications, including digital circuits, analog circuits, logic and control circuits, and electrostatic discharge circuits.

[0005] There is a need for efficient nanosheet gating diode structures and methods for fabricating gating diodes using nanotechnology. Furthermore, there is a need for methods and structures that integrate gating diodes along with other components (like FETs) within nanosheet structures. Summary of the Invention

[0006] Embodiments of the present invention include one or more gating diode structures and methods for fabricating gating diodes from nanosheet structures and integrating gating diodes in nanosheet structures.

[0007] The gating diode includes a substrate. A first source / drain (S / D) is disposed on the substrate. The first S / D has a first S / D doping concentration of a first S / D doping type. A second source / drain (S / D) is disposed on the substrate. The second S / D has a second S / D doping concentration of a second S / D doping type.

[0008] One or more pn junctions each form a diode. Each pn junction has a first side and a second side. The first side has a first-side junction doping concentration and a first-side junction doping type. The first-side junction doping type is the same as the first S / D doping type, and the first side of the pn junction is electrically and physically connected to the first S / D. The second side has a second-side junction doping concentration and a second-side junction doping type. The second-side junction doping type is the same as the second S / D doping type, and the second side of the pn junction is electrically and physically connected to the second S / D.

[0009] A gate dielectric layer interface is provided and surrounds each of the pn junctions, and a gate metal layer surrounds the gate dielectric layer. The gate metal and the gate dielectric layer form a gate stack surrounding each pn junction. Attached Figure Description

[0010] Various embodiments of the present invention will now be described in more detail with reference to the accompanying drawings, which are now briefly described. The drawings illustrate various apparatuses, structures, and related method steps of the present invention.

[0011] Figure 1 A cross-sectional view of an intermediate layered structure (e.g., a stack of nanosheets).

[0012] Figure 2 It is set in Figure 1 A cross-sectional view of a pair of dummy gates and a pair of gate spacers on the intermediate structure.

[0013] Figure 3 It is a cross-sectional view of an intermediate layered nanosheet structure, in which multiple regions are removed to form a stacked body.

[0014] Figure 4 It is a cross-sectional view of the intermediate structure having internal spacers formed on each of the stacked bodies of the pair.

[0015] Figure 5 This is a cross-sectional view of the intermediate structure after the deposition of a pair of masks, where each mask covers half of the stack.

[0016] Figure 6 This is a cross-sectional view of the intermediate structure after selective etching of the sides of one or more channel layers.

[0017] Figure 7 This is a cross-sectional view of the intermediate structure after the epitaxial growth of the first source / drain (S / D) electrode, including the channel epitaxy.

[0018] Figure 8 This is a cross-sectional view of the intermediate structure after the mask has been filled into the deposition opening area.

[0019] Figure 9 This is a cross-sectional view of the intermediate structure after the epitaxial growth of one or more second source and drain electrodes.

[0020] Figure 10 This is a cross-sectional view of the intermediate structure after the region filler mask has been removed and interlayer dielectric (ILD) filler has been deposited.

[0021] Figure 11 This is a cross-sectional view of an embodiment of one or more nanosheet gating diodes after one or more gate stacks have been formed.

[0022] Figure 12 It is a flowchart of the method steps for manufacturing a nanosheet gating diode. Detailed Implementation

[0023] It should be understood that embodiments of the present invention are not limited to the illustrative methods, apparatuses, structures, systems and devices disclosed herein, but are more broadly applicable to other alternative and broader methods, apparatuses, structures, systems and devices, which will become apparent to those skilled in the art in the context of the present invention.

[0024] Furthermore, it should be understood that the various layers, structures, and / or regions shown in the accompanying drawings are not drawn to scale, and one or more layers, structures, and / or regions of commonly used types may not be explicitly shown in a given drawing. This does not mean that layers, structures, and / or regions not explicitly shown are omitted from the actual device.

[0025] Furthermore, when the explanation does not necessarily focus on such omitted elements, certain elements may be omitted from the view for clarity and / or simplicity. Additionally, the same or similar reference numerals used throughout the figures are used to denote the same or similar features, elements, or structures, and therefore, detailed descriptions of the same or similar features, elements, or structures may not be repeated for each figure.

[0026] The semiconductor devices, structures, and methods disclosed in embodiments of the present invention can be used in applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cellular phones and smartphones), solid-state media storage devices, expert and artificial intelligence systems, functional circuits, neural networks, etc. Systems and hardware comprising semiconductor devices and structures are contemplated embodiments of the present invention.

[0027] As used herein, “height” refers to the vertical dimension of an element (e.g., layer, groove, hole, opening, etc.) in a cross-sectional or elevation view measured from the bottom surface of the element to the top surface and / or relative to the surface on which the element is located.

[0028] Conversely, "depth" refers to the vertical dimension of a component (e.g., layer, trench, hole, opening, etc.) in a cross-sectional or elevation view measured from the top surface to the bottom surface of the component. Where indicated, terms such as "thickness," "thickness," "thin," or derivatives thereof may be used instead of "height."

[0029] As used herein, “lateral,” “lateral side,” “side,” and “lateral surface” refer to the side surface of an element (e.g., a layer, an opening, etc.), such as the left or right side surface in the accompanying drawings.

[0030] As used herein, “width” or “length” refers to the dimension of an element (e.g., layer, trench, hole, opening, etc.) measured from the side surface of the element to the opposite surface in the accompanying drawings. Where indicated, terms such as “thickness,” “thickness,” “thin,” or derivatives thereof may be used instead of “width” or “length.”

[0031] As used herein, terms such as “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall refer to the disclosed structures and methods as oriented as shown in the accompanying drawings. For example, as used herein, “vertical” means a direction perpendicular to the top surface of the substrate in an elevation view, and “horizontal” means a direction parallel to the top surface of the substrate in an elevation view.

[0032] As used herein, unless otherwise specified, terms such as “on,” “cover,” “on top,” “on top of,” “positioned on,” or “positioned on top of” mean that the first element is present on the second element, wherein an intermediate element may be present between the first and second elements. As used herein, unless otherwise specified, the term “direct” as used in conjunction with the terms “on,” “above,” “on top,” “on top of,” “positioned on,” “positioned on,” “set on,” or the terms “contact” or “direct contact” means that the first and second elements are connected without any intermediate element (such as an intermediate conductive, insulating, or semiconductor layer) between the first and second elements.

[0033] It should be understood that these terms may be affected by the orientation of the device being described. For example, while the meaning of these descriptions may change if the device is rotated upside down, the descriptions remain valid because they describe the relative relationships between the features of the invention.

[0034] The accompanying drawings illustrate a series of intermediate structures and different method steps leading to one or more nanosheet-gated diodes. In one non-limiting exemplary embodiment, for example, the epitaxial growth of the first source / drain is made of an n-type material. A first portion of the epitaxial growth of the first source / drain is channel epitaxy, wherein the n-type material is epitaxially grown into etched spaces in one or more recessed channels containing a semiconductor material of the opposite type (p-type material).

[0035] Various implementations of a “fully enclosed” gate are disclosed. For example, a fully enclosed gate may be a gate that is in direct contact (boundary) with the top, bottom, front, and rear surfaces of one or more channels (and pn junctions) in which each (i.e., diode) forms a pn junction. In embodiments, the gate is a uniform structure that surrounds (“fully encloses”) the entirety of each individual parallel channel / pn junction and all pn junctions are simultaneously subjected to the same gate voltage.

[0036] Now refer to the attached diagram.

[0037] Figure 1 This is a cross-sectional view of the intermediate layer structure 100. The initial structure 100 is a layer of nanosheets disposed on a substrate 105. Each nanosheet (120, 130, 122, 132, 124, and 134, typically 140) is either a channel layer (130, 132, and 134, typically 150) or a fully enclosed dummy gate layer (120, 122, and 124, typically 160). The channel layer 150 and the fully enclosed dummy gate layer 160 alternate, one disposed on top of the other, to form the layer of nanosheets 140.

[0038] Substrate 105 may be made of a single element (e.g., silicon or germanium); primarily a single element (e.g., a doped material), such as doped silicon; or a compound semiconductor, such as gallium arsenide (GaAs); or a semiconductor alloy, such as silicon-germanium (SiGe). Non-limiting examples of the substrate 105 material include one or more semiconductor materials, such as silicon (Si), silicon-germanium (SiGe), Si:C (carbon-doped silicon), germanium (Ge), carbon-doped silicon-germanium (SiGe:C), Si alloys, Ge alloys, 11I-V materials (e.g., GaAs, indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide (InP), aluminum arsenide (AlAs), etc.), 11-V materials (e.g., cadmium selenide (CdSe), cadmium sulfide (CdS), or any combination thereof) or other similar semiconductors. Furthermore, multilayer semiconductor materials may constitute substrate 105. In some embodiments, substrate 105 comprises both semiconductor materials and dielectric materials. In silicon-on-insulator (SOI) implementation, a buried oxide layer (BOX, such as SiO2) is buried in the substrate 105.

[0039] The channel layer 150 is formed of semiconductor material.

[0040] The channel layer 150 has the same type of doping as the second S / D 950 (described below); however, the doping level or concentration of the channel layer 150 (typically 155) is lower than that of the second S / D. (See the more detailed description of the second S / D 950 below.)

[0041] If the second S / D 950 and the channel layer 150 are p-type doped, the dopant can be selected from the non-limited group of boron (B), gallium (Ga), indium (In), and thallium (Tl). If the second S / D and the channel layer 150 are n-type doped, the dopant can be selected from the non-limited group of phosphorus (P), arsenic (As), and antimony (Sb).

[0042] In some embodiments, the channel layer 150 has a thickness 135 ranging from 5 to 12 nanometers (nm).

[0043] Variations in the doping level / concentration of channel layer 150. For example, for p-type doping, channel layer 150 can be doped, for example, with boron (B) at a concentration of 1 x 10⁻⁶. 17 cm -3 and 1x10 19 cm -3 Between. For n-type doping, the channel layer 150 can be doped with phosphorus (P) at a concentration of 1 x 10⁻⁶. 19 cm -3 and 4x10 20 cm -3 Other doping levels / concentrations of 155 and channel layer thicknesses of 135 are possible.

[0044] In a non-limiting example, the channel layer 150 consists of a 1x10 17 cm -3 and 1x10 19 cm -3 Silicon is made of p-type doped silicon with boron (B) concentrations between these ranges.

[0045] The fully enclosed dummy gate layer 160 is made of a sacrificial material that can be removed by a process that does not affect other materials of structure 100, such as the material used to fabricate substrate 105 and channel layer 150. In some embodiments, the fully enclosed dummy gate layer 160 is made of silicon germanium (SiGe).

[0046] The thickness 125 of the fully enclosed dummy gate layer 160 is between 6 nm and 20 nm, with a thickness of 8 nm to 10 nm being preferred. Other thicknesses are possible.

[0047] In some embodiments, nanosheets 140 are epitaxially grown on top of each other. The terms “epitaxygical growth and / or deposition” and “epitaxygical growth and / or deposition” refer to growing a semiconductor material on a deposition surface of a semiconductor material, wherein the grown semiconductor material has the same crystal properties as the semiconductor material on the deposition surface.

[0048] In epitaxial deposition, the chemical reactants supplied by the source gas are controlled, and system parameters are set so that the deposited atoms reach the deposition surface of the semiconductor substrate with sufficient energy to move on the surface and orient themselves to the crystalline arrangement of atoms on the deposition surface. Therefore, each semiconductor layer of the epitaxial semiconductor material stack has the same crystallization properties as the deposition surface on which it is formed.

[0049] Examples of various epitaxial growth processing apparatuses that can be used in this invention include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The temperatures used for epitaxial deposition are typically in the range of 550°C to 900°C.

[0050] In some embodiments, the gas source for epitaxial growth may include a mixture of a silicon-containing gas source and / or a germanium-containing gas source. Examples of silicon gas sources include silane, disilane, propane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. Examples of germanium gas sources include germanane, digerane, or combinations thereof. In some embodiments, the epitaxial SiGe alloy may be formed from a source gas containing compounds containing silicon and germanium. Carrier gases such as hydrogen, helium, and argon may be used. During the epitaxial growth of the layer, a suitable type of dopant may be added to the precursor gas or gas mixture.

[0051] In some embodiments of the channel layer 150 material, no dopant or no dopant is added in the precursor gas or gas mixture. In other embodiments, the channel layer 150 is doped with dopant in the gas mixture, but with a lower doping concentration than the second S / D 950, as described below.

[0052] In a preferred embodiment, layer 140 is grown using an integrated epitaxial process. In this integrated epitaxial process, the structure is continuously epitaxially grown as the type of gas source and the type and / or concentration of the dopant change at different times and time intervals to produce different layers with different dopant types and concentrations. Temperature adjustments may also be made for one or more layers during epitaxial growth.

[0053] Nanosheets 140 are grown on top of each other as described below to complete structure 100. The grown channel layers 150 may be in-situ doped, meaning that dopants are incorporated into the epitaxial layers during the growth / deposition of each epitaxial channel layer 150.

[0054] In some embodiments, the source gas is modified to create a fully enclosed dummy gate layer 160. Typically, the fully enclosed dummy gate layer 160 is undoped. Doping of the fully enclosed dummy gate layer 160 is not critical because these layers 160 are sacrificed.

[0055] In some embodiments, two or three channel layers 150 are formed. More channel layers 150 may be formed.

[0056] Creating structure 100 by epitaxially growing nanolayer 140 allows for precise control over the thickness and doping level of nanolayer 140. Furthermore, layer alignment is not required during the growth of nanolayer 140.

[0057] Figure 2 It is a cross-sectional view 200 of a pair of (210A, 210B) virtual gates 210 and a pair of (220A, 220B) gate spacers 220 disposed on the intermediate structure 100.

[0058] The dummy gate 210 and gate spacer 220 are formed using well-known methods. For example, the dummy gate material 210 is deposited using a mask. After mask removal, the gate spacer material 220 is conformally deposited and directional etch-back is performed. The dummy gate 210 is made of a sacrificial material that is chemically selectively different from the gate spacer 220 material.

[0059] The dummy gate 210 material may include, for example, amorphous silicon (α-Si) or polycrystalline silicon (polysilicon). In some embodiments, for example, the dummy gate material is the same material as the material that completely surrounds the dummy gate layer 160. The dummy gate 210 material may be deposited by a deposition process, including but not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), and plasma-enhanced chemical vapor deposition (PECVD). The dummy gate 210 has a thickness of about 10 nm to about 100 nm or 20 nm to 50 nm. Other thicknesses are possible.

[0060] The gate spacer 220 material can be deposited using known techniques such as PVD, CVD, or atomic layer deposition (ALD), and can be made of materials such as silicon nitride (SiN), boron silicon nitride (SiBN), silicon boron carbon nitride (SiBCN), silicon oxycarbon nitride (SiOCN), dielectric oxynitride, or dielectric oxides such as silicon oxide (SiOx). The thickness of the gate spacer 220 can be between 3 nm and 15 nm, but other thicknesses are also possible. In some embodiments, the gate spacer 220 is SiN.

[0061] Figure 3 This is a cross-sectional view of the intermediate structure 300 of a pair of stacks 360, in which regions (310, 315, 320) have been removed to allow for the growth of the mask and source / drain regions, as described below. For example, the region between these stacks 360, 315, and adjacent to these stacks (310, 320) will have no material above the substrate 105.

[0062] In some embodiments, the gate spacer 220 is used as a mask in a directional reactive ion etching (RIE) process, which etches away the nanolayer 140 in regions 310, 315, and 320 while leaving pairs (360A, 360B) of stacked nanolayers 140 beneath each gate spacer in the gate spacer 220. In some embodiments, the RIE etching is a series of different RIEs required based on the chemistry of the removed layer 140. The RIE stops when it reaches surface 305 of the substrate 105, using known techniques such as endpoint detection, i.e., monitoring when the last layer of material of the removed layer 120 is detected to have stopped.

[0063] Each pair of stacks has one or more channels 730, each channel 730 having a channel top 710 and a channel bottom 720. The channels 730 are distinct from channel layers 150, which include the material inside the respective channel 730. Each channel 730 also has a channel width 325.

[0064] Figure 4 This is a cross-sectional view of an intermediate structure 400 with internal spacers 450, resulting in a pair of spacer stacks 460 (460A, 460B). The internal spacers 450 are formed at the ends (typically 455) of each fully enclosed dummy gate layer 160 and protect the fully enclosed dummy gate layer 160 in some subsequent processing steps.

[0065] The formation of the internal spacer 450 begins with a partial etch-back of the fully enclosed dummy gate layer 160. The etch chemical selectively removes material such as SiGe from the fully enclosed dummy gate layer 160 without affecting the material in the channel layer 150 or the gate spacer 220. For example, structure 300 is exposed to known chemicals (like gaseous HCl) for a certain period of time. Other available methods exist, such as those developed by TEL (Tokyo Electron Ltd).

[0066] The time length of the distance 451 required to recess the end 455 of the fully enclosed dummy gate layer 160 is empirically determined.

[0067] After recessing the end 455, internal spacer 450 material is conformally deposited. Known processes (e.g., masked directional etching) redefine the sides of the spacer stack 460 and remove the spacer material from the surface 305 of the substrate 105.

[0068] The material and deposition technique for the internal spacer 450 can be the same as those used to form the gate spacer 220. In some embodiments, the internal spacer 450 is made of silicon nitride (SiN). The thickness 451 of the internal spacer 450 is between 3 nm and 8 nm. Other thicknesses are possible.

[0069] Figure 5 It is a cross-sectional view of the intermediate structure 500 after the deposition of a pair of (550A, 550B) half-masks 550, wherein each half-mask 550 masks half of the spacer stack 460.

[0070] In some embodiments, the semi-mask 550 is made of a material that does not support epitaxial growth (such as an oxide, including silicon dioxide (SiO2)). The material of the semi-mask 550 is chemiselective of the material constituting the channel layer 150.

[0071] Figure 6 This is a cross-sectional view of the intermediate structure 600 after the selective etching step.

[0072] Because the semi-mask 550 exposes region 315, the channel layer end (typically 655) of the channel layer 150 is also exposed. An etching process step, such as appropriate timed wet or dry etching, is performed that selectively etches back / recesses the material 150 in the 650 channel 730 while having little or no effect on the gate spacers 220 and internal spacers 450, or on the material masked by the gate spacers 220 and internal spacers 450 (e.g., the end 455 of the dummy layer 160).

[0073] Continue etching until enough channel layer 150 material is removed to recess approximately half 625 of the width 325 of each channel 730, leaving the exposed ends 655 of the channel layer 150 recessed into the channel 730, approximately half 625 of the width 325 of the channel 730.

[0074] Silicon can be selectively etched using an ammonium hydroxide (NH4OH) solution at above room temperature. Other methods are available from TEL (Tokyo Electron Ltd).

[0075] The remaining channel layer 150 material in the channel 730 becomes the second side 680 of the pn junction with exposed channel layer ends 655.

[0076] Figure 7 This is a cross-sectional view of the intermediate structure 700 after the first source / drain (S / D) 725 has been epitaxially grown using the epitaxial growth and doping methods described above.

[0077] Because the exposed channel layer end 655 and the dummy gate material 160 are made of semiconductor material, the first S / D 725 material will be epitaxially grown on the bottom (typically 720), top (typically 710), and exposed channel layer end 655 (semiconductor surface) of the exposed region 650 within the channel 730. This channel epitaxy is the first portion of the first S / D epitaxial growth 725.

[0078] In some embodiments, during channel epitaxy, for example, at a doping level 781 (first pn junction doping level 781) maintained at a lower level 781, the exposed recesses 650 of the channel layer 150 are filled with epitaxial growth material 750 (in the first portion of the epitaxial growth of the first S / D 725 - channel epitaxy).

[0079] As epitaxial growth continues 728, in the second portion of the epitaxial growth of the first S / D 725, epitaxial growth continues to fill the first S / D region 725 (e.g., further filling the previous void space 315). In this second portion of the continued epitaxial growth of the first S / D 725, the doping level 726 increases to a higher level 726, for example, a first source / drain doping level 726.

[0080] After a period of time sufficient to fill the voids / exposed recesses 650 in the 750 channel 730 to form a first side junction 780 having a first side junction doping level / concentration 781 and a first side junction doping type 782, a higher first S / D doping concentration 726 is switched on. Thus, a pn junction 790 is formed by timing channel epitaxial growth at a lower doping concentration 781, which forms a first side junction 780 in contact with a second side 680 of the pn junction 790 in the channel (typically 730).

[0081] In other words, after the void / exposed region 650 is filled 750, the doping level increases, thereby forming a first side junction 780 made of material 750 having a first side junction doping level / concentration 781 and a first side junction doping type 782. After filling the void / exposed region 650, the first S / D 725 continues epitaxial growth 728 (the second part of the first S / D epitaxial growth) with a higher first S / D doping concentration 726 and a first S / D doping type 727. Therefore, the first S / D doping type 727 and the first side junction doping type 782 are the same. In some embodiments, the material used for the first S / D 725 and the material filling 750 in the exposed recess 650 in the channel 730 is the same first S / D material having the same doping type (727, 782) but different doping concentrations (726, 781). Other materials with different compositions but with sufficiently matched lattice structures are envisioned. In other words, in some embodiments, the first S / D material changes from one first S / D material to another first S / D material, wherein the one first S / D material and the other first S / D material are different materials but have matching lattice structures.

[0082] In some embodiments, the time it takes for the doping level to increase from a lower first side junction doping level / concentration 781 to a higher first S / D doping level / concentration 726 is determined empirically through experiments.

[0083] Therefore, a pn junction or diode, typically 790, is now formed at the end 655 of each previously exposed channel layer. The pn junction / diode 790 has a first side typically 780 and a second side typically 680.

[0084] The fill portion 750 of the channel 730 forms the first side 780 of the pn junction / diode 790, which is physically and electrically connected to the first S / D 725. The first side 780 of the pn junction / diode 790 is made of the same material as the first S / D. The doping type 782 of the first side junction is the same as the doping type 727 of the first S / D, but the doping concentration 781 of the first side junction is lower than the doping concentration 726 of the first S / D.

[0085] The second side 680 of the pn junction / diode 790 is the doped semiconductor material that originally constitutes the channel layer 150, having the same doping type (second side junction doping type 682) and concentration (second side junction doping concentration 681 / 155) as the original channel layer 150.

[0086] In some embodiments, the filled 750 exposed recess / void 650 channel 730 (i.e., the first side 780 of the pn junction 790) is 1x10 19 cm -3 With 4x10 20 cm -3 The first side junction is doped at a doping level / concentration of 781, while the first S / D 725 is doped at 8x10. 20 cm -3 With 2x10 21 cm -3 The first S / D doping concentration 726 is used for doping. The pn junction / diode 790 is formed in the channel 730 because the doping type 782 of the first side junction 780 is opposite to that of the second side junction 680.

[0087] In a non-limiting example, the material / doping of the filler 750 (i.e., the first side 780 of the pn junction 790) constituting the first S / D 725 and the exposed recess 650 of the channel 730 is, for example, n-type doped silicon 782, for example, phosphorus (P) doped. The second side of the junction / diode 680 is made of p-type doped silicon 682 doped with boron (B). The doping concentration (with boron, B) of the second-side junction is 681 at 1 x 10⁻⁶. 17 cm -3 and 1x10 19 cm -3 Between. The first side junction 780 is n-type doped 782 silicon (with phosphorus, P), having a 1x10 19 cm -3 With 4x1020 cm -3 The first side junction has a doping concentration of 781. Other doping levels are envisioned. The doping types (782, 682) and concentrations (781, 681) of the first side 780 and the second side 680 can be in opposite positions in the channel 730.

[0088] Figure 8 This is a cross-sectional view of the intermediate structure 800 after the half-mask 550 is removed and the opening area is filled with the mask 850.

[0089] The removal of the (550A, 550B) half-mask 550 is performed by appropriate wet or dry etching. Wet or dry etching removes the material constituting the half-mask 550 but has little effect on the gate spacer 220 and the internal spacer 450.

[0090] Removing the half-mask 550 again exposes the top 825 pairs (825A, 825B) of the gate spacers 220 (220A, 220B) and the outer regions (310, 320). The outer edge (typically 810) of each pair (810A, 810B) of the channel layer (typically 150) (now the second side of the junction / diode 680) is also exposed.

[0091] For example, a fill mask 850 is deposited using a photolithography process to fill any voids above the first source / drain 725. In some embodiments, the fill mask 850 overlaps with some of the top 825s of the top 825 pairs (825A, 825B) of the gate spacers 220. In some embodiments, chemical mechanical polishing (CMP) (not shown) is performed to flush the top of the structure 800.

[0092] The fill mask 120 is a protective material that protects the first source / drain 725 during the epitaxial growth of the second source / drain in the next step. The dielectric material of the fill mask 120 includes, but is not limited to, any of the following: silicon oxide (SiOx), silicon nitride (SiN), silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), and silicon oxynitride (SiON), and is deposited by known techniques such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0093] Figure 9 This is a cross-sectional view of an intermediate structure 900 following one or more epitaxial growths (e.g., a pair of (950A, 950B) second source / drain electrodes 950).

[0094] The second S / D 950 pair (950A, 950B) is epitaxially grown as described above. During epitaxial growth, each second source drain (950A, 950B) becomes electrically and physically connected to the outer edge (810A, 810B) of the channel layer 150 (now the second side 680 of the pn junction / diode 790), respectively.

[0095] In some embodiments, a left second S / D 950A and a right second S / D 950B are present. The left second S / D 950A is electrically connected to the left device stack ( Figure 11 The second side 680 of the pn junction / diode 790 in the 1160A) and the right second S / D950B are electrically connected to the right device stack ( Figure 11 All second sides 680 of the pn junction / diode 790 in 1160B).

[0096] The second source / drain 950 will have the same second S / D doping type 952 as the channel layer 150 / second pn junction side 680. However, in some embodiments, the second S / D doping concentration 951 of the second source / drain 950 will be higher than the doping concentration of the second side 680 of the pn junction / diode 790. For example, the second S / D doping concentration / level 951 of the second source / drain 950 is between 8 x 10⁻⁶. 20 cm -3 With 2x10 21 cm -3 Between the levels.

[0097] In some embodiments, the second source / drain 950 is doped with, for example, a p-type dopant, boron (B).

[0098] Figure 10 This is a cross-sectional view of the intermediate structure 1000 after the removal of the region-fill mask 850 and the deposition of interlayer dielectric (ILD) filler 1050.

[0099] The filler mask 850 is removed by performing known selective wet and / or dry etching techniques.

[0100] The ILD filler 1050 may be formed from a low-k dielectric material (k < 4.0), including but not limited to silicon oxide, spin-coated glass, flowable oxide, high-density plasma oxide, borophosphosilicate glass (BPSG), or any combination thereof. The ILD 1050 may be deposited using other deposition processes, including but not limited to CVD, PVD, PECVD, ALD, evaporation, chemical solution deposition, or similar processes.

[0101] ILD 1050 covers structure 1000. However, in some embodiments, ILD 1050 does not cover access from the front and / or back (off- and on-) sides of the fully enclosed dummy gate layer (120, 122, 124, typically 160).

[0102] In some embodiments, structure 1000 is planarized using known methods such as CMP. In some embodiments, in addition to smoothing the top surface of structure 1000, CMP removes (not shown) the top portion 825 of the gate spacer 220 and exposes the dummy gate 210 material. Line 1015 shows the level at which CMP would stop in this case.

[0103] Figure 11 This is a cross-sectional view of an embodiment 1100 of a nanosheet gating diode 1100 after the dummy gate 210 and the material surrounding the dummy gate 160 have been removed and one or more gate stacks (1125, 1150) have been formed.

[0104] The materials of the dummy gate 210 and the all-enclosed dummy gate 160 are removed by release etching. When the dummy gate 210 and the all-enclosed dummy gate layer 160 are made of the same material, such as SiGe, only one release etching is required. When the dummy gate 210 and the all-enclosed dummy gate 160 are made of different materials, multiple release etchings may be required.

[0105] In some embodiments, the dummy gate 210 and the all-enclosed dummy gate 160 are made of SiGe. Under these conditions, the SiGe in the dummy gate 210 and the all-enclosed dummy gate 160 material (SiGe) between the channel 730 and the inner spacer 450 can be selectively removed or stripped by dry etching or exposure to ammonium hydroxide (NH4OH) or hydrofluoric acid (HF) solution at above room temperature.

[0106] For example, the etched material can be accessed from the top of structure 1100, and from horizontal 1015. The etched material can be accessed from the exposed sides of the front and back sides (not shown) of structure 1100, which fully surround the material in the dummy gate 160.

[0107] The release etching leaves a gap (not shown) between the internal spacer 450 and the channel 730, and removes the dummy gate 210 material at the gap. The top 710 and bottom 720 of the channel 730, as well as the front and back (not shown) and the various pn junctions (typically 790) formed in the channel 730 are also exposed.

[0108] Gate stacks (1125, 1150) are formed in the void region between the internal spacers 450 and the channel 730, wherein the dummy gate 210 material is removed. The gate stacks (1125, 1150) have a gate dielectric layer 1125 that is in contact with and surrounds the surface of the channel 730 and the corresponding pn junction 790 within the channel 730 (and also on the surfaces of the remaining gate spacers and internal spacers (220, 450) material). The metal gate 1150 fills the remaining portion of the space.

[0109] Note that there are two device stacks 1160, a first or left device stack 1160A and a second or right device stack 1160B.

[0110] The gate dielectric layer 1125 may be made of a dielectric material having a dielectric constant greater than 3.9, more preferably greater than 7.0, and even more preferably greater than 10.0. Non-limiting examples of suitable materials for the gate dielectric material 1125 include oxides, nitrides, oxynitrides, or any combination thereof. Examples of high-k materials (having a dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. High-k materials may also include dopants such as lanthanum and aluminum.

[0111] The gate dielectric material 1125 layer can be formed by a suitable deposition process, such as CVD, PECVD, ALD, PVD, evaporation, chemical solution deposition, or other similar processes. The thickness of the gate dielectric material 1125 can vary depending on the deposition process and the composition and amount of the high-k dielectric material used.

[0112] The gate metal layer 1150 includes, but is not limited to, titanium nitride (TiN), tantalum nitride (TaN), or ruthenium (Ru), titanium aluminum nitride (TiAlN), titanium aluminum carbonitride (TiAlCN), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), tantalum aluminum carbonitride (TaAlCN), or lanthanum-doped (La) TiN or TaN. These gate metals 1050 are deposited using, for example, deposition techniques, including but not limited to, CVD, PECVD, PVD, ALD, LSMCD, radio frequency chemical vapor deposition (RFCVD), pulsed laser deposition (PLD), liquid source atomized chemical deposition (LSMCD), and / or sputtering.

[0113] In some embodiments, an external electrical contact 1175 is formed with the first source / drain 725. One or more openings / trenches are created through the ILD 1150 using photolithography or laser technology to expose the first source / drain 725. A silicide layer 725 is then formed on the exposed surface of the first source / drain. A conductive material 1175 is deposited to fill the openings / trenches formed to the external electrical contact 1175 of the first source / drain 725.

[0114] In other embodiments, external electrical contacts (e.g., 1120) may also be formed to the gate working metal 1150 and / or the second source / drain 950 (e.g., 1115). As previously described, openings / trenches may be fabricated to contact the corresponding contacts, i.e., the gate metal (1150) and / or the second source / drain 950, if needed. A silicide layer is formed on the exposed surface of the semiconductor material. A conductive material 1120 is then deposited to fill the openings / trenches.

[0115] In this manner, external connections 1115 are manufactured to each of the second S / D 950. External connection 1115A is manufactured to the second S / D 950A, and external connection 1115B is manufactured to the second S / D 950B.

[0116] The conductive materials (1120, 1175, 1115) can be conductive metals, such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), cobalt (Co), or any combination thereof. The conductive materials (1120, 1175) can be deposited using suitable deposition processes, such as CVD, PECVD, PVD, electroplating, thermal or electron beam evaporation, or sputtering.

[0117] A typical known silicide formation process involves depositing a metal (such as Ni) on a semiconductor surface, followed by annealing, for example, holding it between 410 degrees Celsius and 425 degrees Celsius for about 15 minutes, and then removing the unreacted metal.

[0118] CMP can be performed to flatten the surface of device 1100.

[0119] In embodiments where the gate stacks (1125, 1150) completely surround the channel 730 and pn junction 790 (upper 710 and lower 720, as well as front and rear portions) for pairs (1125A, 1150A, 1125B, 1150B), all portions of the gate stacks (1125, 1150) are at substantially the same voltage potential because the gate metal (1150A, 1150B) in each of the device stacks 1160 (1160A, 1160B) is connected to a common connection 1150. Therefore, the substantially identical voltage applied to the respective gate connections (1150A, 1150B) causes an electric field in all channels 730 and pn junctions 790 within each (1160A, 1160B) of the device stack 1160.

[0120] In some embodiments, each of the plurality of diodes 790 in each (1160A, 1160B) device stack 1160 is connected in parallel. The diodes 790 connected in parallel in each (1160A, 1160B) device stack 1160 may further be connected in parallel.

[0121] In this embodiment, the current flowing through the entire gating diode device 1100 (e.g., the current flowing through the first source / drain 725 and the second source / drain 950) is approximately multiplied by the number of diode paths. In other words, the current capacity of the gating diode 1100 increases with the number of diodes 790 connected in parallel.

[0122] Stacking diodes 790 along a vertical direction (perpendicular to substrate 105) enables the realization of high current capacity diodes (diode junctions) in a reduced region on substrate 105.

[0123] The voltage / signal applied to the gate stack 1125 / 1150 surrounding the diode 790 modulates the current-voltage characteristics of the diode 790, and thus modulates the current-voltage characteristics of the gating diode device 1100. In one embodiment, the breakdown voltage of the gating diode device 1100 is a function of the voltage applied to the gate stack 1125 / 1150.

[0124] Figure 12 This is a flowchart of process 1200, which includes the steps of manufacturing a nanosheet gating diode (e.g., 1100).

[0125] The method begins at step 1305: forming alternating nanolayers 140, depositing pairs of dummy gates 210 (210A, 210B) and pairs of gate spacers 220 (220A, 220B), and removing materials (310, 315 and 320) to prepare for the formation of internal spacers 450.

[0126] In step 1210, an internal spacer 450 is formed on the exposed end 455 of the remaining portion of the dummy gate layer 160. The channel layer 150 is etched to expose the channel layer end 655 and the void 650 in the channel 730. A first source / drain (S / D) 725 is epitaxially grown (the first portion of the first S / D growth), and a pn junction / diode 790 is formed with a first side junction doping level / concentration 781 and a first side junction doping type 782. After the first side 780 of the pn junction 790 is formed (the second portion of the first S / D growth), the doping level of the first source / drain (S / D) 726 is increased to the first S / D doping level 726.

[0127] In step 1215, the first source / drain 725 is masked with an opening region filling mask 850, and second S / D 950s (left 950A and right 950B) are grown. The second S / D 950 has a second S / D type doping 952, the same doping type (682, 150) as the second side 680 of the pn junction 790. The doping level / concentration 951 of the second S / D 950 is increased to a higher doping concentration 681 / 155 than that of the second side 680.

[0128] In step 1220, as described above, a gate stack (1125, 1150) is formed.

[0129] In step 1225, external connections (1115, 1120, 1175) are made for the selection diode 790.

[0130] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. For example, semiconductor devices, structures, and methods disclosed according to embodiments of the invention can be used in applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cellular phones and smartphones), solid-state media storage devices, expert and artificial intelligence systems, functional circuits, etc. Systems and hardware incorporating semiconductor devices are contemplated embodiments of the invention.

[0131] The terminology used herein is chosen to explain the principles of the embodiments and their practical application or technical improvements over those found in the market, or otherwise enable others skilled in the art to understand the embodiments disclosed herein. Apparatus, components, elements, features, devices, systems, structures, techniques, and methods described using different terms perform substantially the same functions, operate in substantially the same manner, have substantially the same purpose, and / or perform similar steps as embodiments of the invention.

Claims

1. A gated nanosheet diode, comprising: Substrate; A first source / drain S / D is disposed on the substrate, the first S / D having a first S / D doping concentration, and the first S / D doping concentration having a first S / D doping type; A second S / D is disposed on the substrate. The second S / D has a second S / D doping concentration and a second S / D doping type, which is opposite to the first S / D doping type. Forming a pn junction for a diode; The first side of the pn junction has a first side junction doping concentration, the first side junction doping concentration has a first side junction doping type, the first side junction doping type is the same as the first S / D doping type, and the first side of the pn junction is electrically connected and physically connected to the first S / D, and the first side junction doping concentration is lower than the first S / D doping concentration; The second side of the pn junction has a second side junction doping concentration with a second side junction doping type, the second side junction doping type being the same as the second S / D doping type, and the second side of the pn junction being electrically and physically connected to the second S / D, the second side junction doping concentration being lower than the second S / D doping concentration; A gate dielectric layer that is adjacent to and surrounds the pn junction; as well as A gate metal surrounding the gate dielectric layer, the gate metal and the gate dielectric layer forming a gate stack surrounding the pn junction.

2. The gated nanosheet diode according to claim 1, wherein, The first side junction doping type and the first S / D doping type are n-type doped.

3. The gated nanosheet diode according to claim 2, wherein, The n-type dopant is one of the following: phosphorus, arsenic, and antimony.

4. The gated nanosheet diode according to claim 2, wherein, The first side junction doping concentration is 1x10⁻⁶. 19 cm -3 With 4x10 20 cm -3 Between and the first S / D doping concentration is 8x10 20 cm -3 With 2x10 21 cm -3 between.

5. The gated nanosheet diode according to claim 1, wherein, The second side junction doping type and the second S / D doping type are p-type dopants.

6. The gated nanosheet diode according to claim 5, wherein, The p-type dopant is one of the following: boron, gallium, indium, and thallium.

7. The gated nanosheet diode according to claim 2, wherein, The second side junction doping concentration is 1x10 17 cm -3 With 1x10 19 cm -3 Between and the second S / D doping concentration 8x10 20 cm -3 With 2x10 21 cm -3 between.

8. The gated nanosheet diode according to claim 1, wherein, The first side junction doping type and the first S / D doping type are p-type doped.

9. The gated nanosheet diode according to claim 8, wherein, The first side junction doping concentration is 1x10⁻⁶. 17 cm -3 With 1x10 19 cm -3 Between and the first S / D doping concentration is 8x10 20 cm -3 With 2x10 21 cm -3 between.

10. The gated nanosheet diode according to claim 1, wherein, The second side junction doping type and the second S / D doping type are n-type dopants.

11. The gated nanosheet diode according to claim 10, wherein, The second side junction doping concentration is 1x10 19 cm -3 With 4x10 20 cm -3 Between and the second S / D doping concentration is 8x10 20 cm -3 With 2x10 21 cm -3 between.

12. A gating nanosheet diode, comprising: Substrate; A first source / drain S / D is disposed on the substrate, the first S / D having a first S / D doping concentration, and the first S / D doping concentration having a first S / D doping type; Two or more second S / Ds are disposed on the substrate, the second S / Ds having a second S / D doping concentration with a second S / D doping type, one of the second S / Ds being a right second S / D and one of the second S / Ds being a left second S / D, the second S / D doping type being opposite to the first S / D doping type; One or more pn junctions, each pn junction forming a diode in a separate channel, each diode and the channel being surrounded by a gate stack having a gate dielectric layer that interfaces with and surrounds each pn junction and a gate metal layer that surrounds the gate dielectric layer; Two or more device stacks are formed by one or more of the diodes stacked on top of each other, with the left device stack located between the left second S / D and the first S / D, and the right device stack located between the right second S / D and the first S / D; Each of the pn junctions has a first side, the first side having a first side junction doping concentration, the first side junction doping concentration having a first side junction doping type, the first side junction doping type being the same as the first S / D doping type, and the first side of the pn junction being electrically and physically connected to the first S / D, the first side junction doping concentration being lower than the first S / D doping concentration; The second side of the pn junction has a second side junction doping concentration with a second side junction doping type that is the same as the second S / D doping type. The second side of the pn junction in the left device stack is electrically and physically connected to the left second S / D, and the second side of the pn junction in the right device stack is electrically and physically connected to the right second S / D. The second side junction doping concentration is lower than the second S / D doping concentration. In this configuration, a plurality of diodes are formed on the first side of the pn junction in the left and right device stacks that are electrically connected to the first S / D.

13. The gated nanosheet diode according to claim 12, wherein, The gate metal surrounding the gate dielectric layer is electrically connected to each of the diodes.

14. The gated nanosheet diode according to claim 12, wherein, The current capacity of the selected nanosheet diode increases with the number of diodes.

15. A method for manufacturing a gated nanosheet diode, comprising the following steps: An intermediate layered structure is formed by multiple nanolayers, wherein the nanolayers are one or more channel layers and one or more dummy gate layers, the channel layers and the dummy gate layers are arranged alternately to form the intermediate layered structure, and the channel layers are semiconductor materials having a second side junction doping concentration and a second side junction doping type. Two dummy gates are deposited on the intermediate layered structure, each covered by a free gate spacer layer; Using the gate spacer layer as a mask, a pair of stacks is created from the intermediate layered structure by removing the nanolayers located between and next to the stacks; An internal spacer is formed on each of one or more exposed ends of the dummy gate layer; A portion of each of the trench layers is removed to expose the trench layer ends of each trench layer within the trench, which are now second side junctions; Epitaxial growth is a channel epitaxy as the first part of the first S / D epitaxial growth, the channel epitaxy grows a first side junction in the channel and creates a pn junction / diode at the exposed channel layer, at the exposed channel layer, the first side junction contacts the second side junction, the first side junction has a first side junction doping concentration and a first side junction doping type opposite to the second side junction doping type; Continue the first S / D epitaxial growth to grow a first S / D with a first S / D doping concentration and a first S / D doping type, wherein the first side junction doping type is the same as the first S / D doping type and the first S / D doping concentration is higher than the first side junction doping concentration; Epitaxial growth of a second S / D having a second S / D doping concentration and a second S / D doping type, the second S / D being electrically contacted with the second side junction, the second S / D doping type being the same as the second side junction doping type and the second S / D doping concentration being higher than the second side junction doping concentration, the second S / D doping type being opposite to the first S / D doping type; as well as A gate stack is formed around one or more of the pn junctions / diodes.

16. The method according to claim 15, wherein, After forming the pn junction / diode, the doping concentration of the first side junction is increased to the first S / D doping concentration.

17. The method according to claim 16, wherein, The channel epitaxy is performed by timed epitaxial growth.

18. The method according to claim 15, wherein, The portion of each of the removed trench layers exposes the end of the trench layer at half the width of the trench layer.

19. The method according to claim 15, wherein, The first S / D doping concentration and the second S / D doping concentration are at 8x10 20 cm -3 With 2x10 21 cm -3 between.

20. The method of claim 15, wherein, The gate stack has a gate dielectric layer that is connected to and surrounds each of the pn junctions and a gate metal that surrounds the gate dielectric layer, and the gate metal is one or more of the following: titanium nitride, tantalum nitride or ruthenium, titanium aluminum nitride, titanium aluminum carbonitride, titanium carbide, titanium aluminum carbide, tantalum aluminum carbonitride, tantalum aluminum carbonitride or lanthanum-doped titanium nitride, tantalum nitride.

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