Trench gate insulated gate bipolar transistor and manufacturing method therefor

Abstract

The present application relates to a trench gate insulated gate bipolar transistor (IGBT) and a manufacturing method therefor. The trench gate IGBT comprises: a collector region; a drift region; a body region; an emitter region; a trench gate structure, comprising a gate dielectric layer located on an inner surface of a first trench, and a gate electrode located in the first trench and surrounded by the gate dielectric layer; a target trench structure, comprising an insulating dielectric layer located on a side wall of a second trench, and doped polysilicon located in the second trench and surrounded by the insulating dielectric layer from a side surface, wherein the doped polysilicon is P-type doped polysilicon; a first P-type doped region which is located in the drift region below the second trench, surrounds the bottom of the second trench, and is electrically connected to the doped polysilicon; and a target metal interconnect, which is located above the body region and is configured to be connected to an emitter potential, and is electrically connected to the doped polysilicon, the emitter region, and the body region by means of a target contact hole and an emitter contact hole below. The present invention can shorten the time of a tail current, thereby shortening the turn-off time of the IGBT.

Description

Trench gate insulated gate bipolar transistor and its manufacturing method Cross-references to related applications

[0001] This patent application claims priority to Chinese Patent Application No. 202411850939.7, filed on December 16, 2024, entitled "Trench Gate Insulated Gate Bipolar Transistor and Method for Manufacturing the Same Thereof," the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor manufacturing technology, and in particular to a trench gate insulated gate bipolar transistor (TGBMT), and also to a method for manufacturing a trench gate insulated gate bipolar transistor. Background Technology

[0003] An Insulated Gate Bipolar Transistor (IGBT) is a composite, fully controllable, voltage-driven power semiconductor device composed of a bipolar junction transistor (BJT) and an insulated gate field-effect transistor (MOSFET). It combines the operating mechanisms of both MOSFETs and bipolar transistors, possessing the advantages of both, making it an improved power device. Compared to bipolar transistors, IGBTs are voltage-controlled devices with high gain at high currents; compared to MOSFETs, IGBTs can withstand higher voltages and have lower on-state voltage at high currents, thus offering higher voltage and current handling capabilities, making them suitable for high-voltage, high-current applications.

[0004] Traditional IGBT devices struggle to balance low on-state voltage drop with high turn-off speed. Summary of the Invention

[0005] Therefore, it is necessary to provide a trench gate insulated gate bipolar transistor that can balance low on-state voltage drop and high turn-off speed.

[0006] A trench-gate insulated-gate bipolar transistor (TG-BMT) includes: a collector region; a drift region located on the collector region; a body region located on the drift region; an emitter region located in the body region, wherein the conductivity type of the emitter region is opposite to that of the body region; a trench gate structure extending from the body region to the drift region, including a gate dielectric layer located on the inner surface of a first trench, and a gate located in the first trench and surrounded by the gate dielectric layer; and a target trench structure extending from the body region to the drift region, including a second trench... The second trench includes an insulating dielectric layer on its sidewalls and a doped polysilicon located in the second trench and surrounded from the side by the insulating dielectric layer, wherein the doped polysilicon is P-type doped polysilicon; a first P-type doped region located in the drift region below the second trench and surrounding the bottom of the second trench, and electrically connected to the doped polysilicon; and a target metal interconnect located above the body region for connecting to the emitter potential, wherein the target metal interconnect is electrically connected to the doped polysilicon, the emitter region, and the body region through a contact hole below.

[0007] In the trench gate insulated gate bipolar transistor described above, at the instant the IGBT is turned off from the on state, the holes in the drift region are rapidly drawn away by the emitter along the first P-type doped region-doped polysilicon-contact hole-target metal connection line, thus shortening the tail current time and thereby reducing the IGBT turn-off time.

[0008] In one embodiment, the first P-type doped region forms an ohmic contact with the doped polysilicon.

[0009] In one embodiment, a second P-type doped region is further included within a drift region located below the first trench and surrounding the bottom of the first trench.

[0010] In one embodiment, the gate material is N-type doped polycrystalline silicon.

[0011] In one embodiment, the drift region and the emitter region have a first conductivity type, and the collector region and the body region have a second conductivity type, wherein the first conductivity type and the second conductivity type are opposite conductivity types.

[0012] In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0013] In one embodiment, the first trench and the second trench have the same depth.

[0014] In one embodiment, the junction depths of the first P-type doped region and the second P-type doped region are equal.

[0015] In one embodiment, a buffer layer is also included between the collector region and the drift region.

[0016] In one embodiment, the buffer layer and the drift region have a first conductivity type, and the collector region has a second conductivity type, wherein the first conductivity type and the second conductivity type are opposite conductivity types; the doping concentration of the buffer layer is greater than the doping concentration of the drift region.

[0017] In one embodiment, the depth of the trench grid structure is less than the depth of the target trench structure.

[0018] In one embodiment, the target trench structure and the trench grid structure are distributed adjacently and alternately.

[0019] In one embodiment, the gate dielectric layer and the insulating dielectric layer are made of silicon oxide.

[0020] In one embodiment, an interlayer dielectric layer is further included above the body region, the emitter region, the trench gate structure and the target trench structure and below the target metal interconnect, and the contact hole penetrates the interlayer dielectric layer.

[0021] A method for manufacturing a trench-gate insulated-gate bipolar transistor includes: obtaining a substrate having a drift region; forming a trench gate structure, a target trench structure, and a first P-type doped region in the drift region; the trench gate structure includes a gate dielectric layer formed on the inner surface of the first trench, and a gate electrode formed in the first trench and surrounded by the gate dielectric layer; the target trench structure includes an insulating dielectric layer formed on the sidewall of a second trench, and doped polysilicon formed in the second trench and surrounded from the side by the insulating dielectric layer, wherein the doped polysilicon is P-type doped polysilicon; the first P-type doped region is formed in the drift region below the second trench and surrounds the second trench. At the bottom, the first P-type doped region is electrically connected to the doped polysilicon; the drift region is doped to form a body region located on the upper side of the trench gate structure and the upper side of the target trench structure; the body region is doped to form an emitter region; the conductivity type of the emitter region is opposite to that of the emitter region; a contact hole is formed on the doped polysilicon, and the contact hole is filled with a conductive material electrically connected to the doped polysilicon, the emitter region, and the body region; a target metal interconnect is formed on the contact hole; the target metal interconnect is electrically connected to the doped polysilicon, the emitter region, and the body region through the contact hole; a collector region is formed at the bottom of the substrate.

[0022] In the above-mentioned trench gate insulated gate bipolar transistor manufacturing method, when the formed IGBT is turned off from the on state, the holes in the drift region are rapidly drawn away by the emitter along the first P-type doped region-doped polysilicon-target contact hole-target metal connection line, thus shortening the tail current time and thereby reducing the IGBT turn-off time. Attached Figure Description

[0023] Figure 1 is a schematic diagram of the structure of a trench gate insulated gate bipolar transistor in one embodiment of this application.

[0024] Figure 2 is a flowchart of a method for manufacturing a trench gate insulated gate bipolar transistor according to an embodiment of this application.

[0025] Figures 3a to 3j are schematic cross-sectional views of the IGBT during the manufacturing of a trench gate insulated gate bipolar transistor using the method shown in Figure 2, according to one embodiment of this application.

[0026] Figure 4 is a flowchart of the sub-steps of step S220 in one embodiment of this application.

[0027] Figure 5 is a schematic diagram of the structure of a trench gate insulated gate bipolar transistor in another embodiment of this application. Detailed Implementation

[0028] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0030] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0031] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0033] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0034] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0035] The reason why IGBT devices cannot simultaneously achieve low on-state voltage drop and high turn-off speed is that if IGBT devices need to have low on-state voltage drop, the drift region needs to have a high hole concentration. However, this will result in more holes that are difficult to be quickly removed when the IGBT device turns off from the on state, and the tail current time is longer, so the IGBT device turns off slowly.

[0036] Figure 1 is a schematic diagram of a trench-gate insulated-gate bipolar transistor (TG-BPT) according to an embodiment of this application, including a collector region 110, a drift region 130, a body region 152, an emitter region 154, a trench gate structure, a target trench structure, a first P-type doped region 132, and a target metal interconnect 172. The trench gate structure includes a gate dielectric layer 141 located on the inner surface of the first trench (not shown in Figure 1), and a gate electrode 142 located in the first trench and surrounded by the gate dielectric layer. The trench gate structure extends downward from the body region 152 into the drift region 130. The target trench structure includes an insulating dielectric layer 143 located on the sidewall of the second trench (not shown in Figure 1), and a doped polysilicon 144 located in the second trench and surrounded laterally by the insulating dielectric layer 143, wherein the doped polysilicon 144 is P-type doped polysilicon. The target trench structure extends downward from the body region 152 into the drift region 130. Drift region 130 is located on collector region 110. In the embodiment shown in FIG1, a buffer layer 120 is also provided between collector region 110 and drift region 130. Body region 152 is located on drift region 130. Emitter region 154 is located in body region 152. The conductivity type of emitter region 154 is opposite to that of body region 152. First P-type doped region 132 is located in drift region 130 below second trench and surrounds the bottom of second trench, and is electrically connected to doped polysilicon 144. Target metal interconnect 172 is located above body region 152 and is used to connect to the potential of emitter E. Target metal interconnect 172 is electrically connected to doped polysilicon 144, emitter region 154 and body region 152 through contact holes below. The contact hole can be a large hole that simultaneously contacts the doped polysilicon 144, the emitter region 154, and the body region 152, or it can include a target contact hole 163 and an emitter contact hole 161. The target contact hole 163 (which is filled with conductive material) is electrically connected to the doped polysilicon 144, and the target metal wire 172 is also electrically connected to the emitter region 154 and the body region 152 through the emitter contact hole 161 below (which is filled with conductive material).

[0037] In the trench gate insulated gate bipolar transistor described above, at the instant the IGBT is turned off from the on state, the holes in the drift region 130 are rapidly drawn away by the emitter E along the first P-type doped region 132-doped polysilicon-144-contact hole-target metal connection 172, thus shortening the tail current time and thereby reducing the IGBT turn-off time.

[0038] In one embodiment of this application, the first P-type doped region 132 forms an ohmic contact with the P-type doped polysilicon 144 to reduce resistance and increase hole extraction speed.

[0039] In one embodiment of this application, the target trench structure and the trench gate structure are distributed adjacently and alternately.

[0040] In one embodiment of this application, the trench gate insulated gate bipolar transistor (IGBT) further includes a second P-type doped region 134 located within a drift region 130 below the first trench and surrounding the bottom of the first trench. During reverse breakdown, the IGBT withstands high voltage by widening the depletion layer of the adjacent first P-type doped region 132 and second P-type doped region 134 to form a pinch-off, thereby reducing the gate electric field at the bottom of the trench gate structure and improving device reliability and robustness. When the IGBT is in the on-state, the device voltage drop is low, and the adjacent first P-type doped region 132 and second P-type doped region 134 are essentially not depleted, allowing current to flow through the trench gate structure. When the IGBT transitions from on to off, holes in the drift region 130 can be quickly extracted through the first P-type doped region 132 connected to the second trench, significantly reducing the IGBT's turn-off tail current, improving device switching speed, and reducing IGBT turn-off losses. In summary, the trench gate insulated gate bipolar transistor (IGBT) of this application achieves high withstand voltage by introducing a first P-type doped region 132 and a second P-type doped region 134 at the bottom of the trench gate structure and the target trench structure. This significantly reduces the P-body channel length of the trench gate channel, thereby greatly reducing the switching capacitance and on-state voltage drop of the IGBT, solving the problem of electric field concentration at the bottom of the trench, and improving device reliability. Simultaneously, when the IGBT transitions from turn-on to turn-off, holes can be quickly extracted through the first P-type doped region 132, thereby increasing the device switching speed and reducing IGBT turn-off losses.

[0041] In one embodiment of this application, the gate 142 is made of N-type doped polysilicon. The gate dielectric layer 141 and the insulating dielectric layer 143 can be made of silicon oxide, such as silicon dioxide.

[0042] In one embodiment of this application, the depths of the first trench and the second trench are equal. In one embodiment of this application, the junction depths of the first P-type doped region 132 and the second P-type doped region 134 are equal.

[0043] In one embodiment of this application, the drift region 130 and the emitter region 154 have a first conductivity type, and the collector region 110 and the body region 152 have a second conductivity type. In the embodiment shown in FIG. 1, the first conductivity type is N-type, and the second conductivity type is P-type. In one embodiment of this application, the buffer layer 120 has a first conductivity type. Further, the doping concentration of the buffer layer 120 is greater than the doping concentration of the drift region 130.

[0044] In one embodiment of this application, the trench gate insulated gate bipolar transistor further includes an interlayer dielectric (ILD) layer 162 located above the body region 152, the emitter region 154, the trench gate structure, and the target trench structure, and below the target metal interconnect 172. The target contact hole 163 and the emitter contact hole 161 penetrate the interlayer dielectric layer 162. The interlayer dielectric can be a silicon oxide layer, such as a doped or undoped silicon oxide material layer formed using thermal chemical vapor deposition (TCVD) or high-density plasma chemical vapor deposition (HDPCVD) processes. Specifically, it can be undoped silicon glass (USG), silicon phosphosilicate glass (PSG), or borosilicate phosphosilicate glass (BPSG). Alternatively, the interlayer dielectric can also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS), or boron-doped tetraethoxysilane (BTEOS), etc.

[0045] Figure 5 is a schematic diagram of a trench gate insulated gate bipolar transistor (TGBT) according to another embodiment of this application. The main difference between this embodiment and the one shown in Figure 1 is that the second P-type doped region 134 is not provided, and the depth of the first trench (not shown in Figure 5) is shallower. Therefore, the trench gate structure (including the gate dielectric layer 141 and the gate 142) is shallower than the target trench structure. In the embodiment shown in Figure 5, because the gate 142 extends shallower into the drift region 130, the Cgc (gate-collector capacitance) can be significantly reduced compared to the embodiment shown in Figure 1, thus improving the switching characteristics of the device.

[0046] This application provides a method for manufacturing a trench-gate insulated-gate bipolar transistor, which can be used to manufacture the trench-gate insulated-gate bipolar transistor described in any of the foregoing embodiments. Figure 2 is a flowchart of a method for manufacturing a trench-gate insulated-gate bipolar transistor according to an embodiment of this application, including the following steps:

[0047] S210, Obtain a substrate with a drift region.

[0048] In one embodiment of this application, an epitaxial layer is formed on a wafer substrate as a drift region 130. In another embodiment of this application, the substrate is an N+ substrate, and the epitaxial layer is an N-type epitaxial layer (N EPI). The substrate is not shown in Figure 3a.

[0049] S220 forms a trench gate structure, a target trench structure, and a first P-type doped region in the drift region.

[0050] Referring to Figure 3g, the trench gate structure includes a gate dielectric layer 141 formed on the inner surface of a first trench 131 (not shown in Figure 3g), and a gate 142 formed in the first trench 131 and surrounded by the gate dielectric layer 141. The target trench structure includes an insulating dielectric layer 143 formed on the sidewalls of a second trench 133 (not shown in Figure 3g), and doped polysilicon 144 formed in the second trench 133 and surrounded by the insulating dielectric layer 143. The doped polysilicon 144 is P-type doped polysilicon. A first P-type doped region 132 is formed in a drift region 130 below the second trench 133 and surrounds the bottom of the second trench 133. The first P-type doped region 132 is electrically connected to the doped polysilicon 144.

[0051] In one embodiment of this application, a trench gate structure can be formed first, followed by the formation of the target trench structure and the first P-type doped region 132. Referring to Figure 4, in one embodiment of this application, step S220 specifically includes the following steps:

[0052] S221, photolithography and etching are used to form the first trench.

[0053] Referring to Figure 3b, photolithography is performed on the front side of the epitaxial layer (i.e., the drift region 130), and deep trench etching is performed downwards to form the first trench 131.

[0054] S222, a gate dielectric layer is formed on the inner surface of the first trench.

[0055] In one embodiment of this application, the gate dielectric layer 141 is made of silicon oxide, such as silicon dioxide. In another embodiment of this application, prior to step S222, a step is included to form a second P-type doped region 134 within the drift region 130 below the first trench 131, as shown in FIG. 3c. The second P-type doped region 134 can be formed by ion implantation, using the etching mask (e.g., photoresist) from step S221 as an implantation barrier layer.

[0056] S223, a gate is formed in the first trench.

[0057] Referring to Figure 3d, gate material is filled into the first trench 131. In one embodiment of this application, the gate material is N-type doped polysilicon. In one embodiment of this application, N-type doped polysilicon is deposited on the front side of the wafer to fill the first trench 131, and then excess polysilicon is removed by etch-back and / or polishing (CMP).

[0058] S224, photolithography and etching are used to form the second trench.

[0059] Referring to Figure 3e, photolithography is performed on the front side of the epitaxial layer (i.e., the drift region 130), and deep trench etching is performed downwards to form the second trench 133.

[0060] S225, a second P-type doped region is formed in the drift region below the second trench.

[0061] The second P-type doped region 134 can be formed by ion implantation, using the etching mask (e.g., photoresist) during step S224 as an implantation barrier layer.

[0062] S226, an insulating dielectric layer is formed on the sidewall of the second trench.

[0063] In one embodiment of this application, the insulating dielectric layer 143 is made of silicon oxide, such as silicon dioxide. In one embodiment of this application, silicon dioxide is deposited into the second trench 133, and then the silicon dioxide at the bottom of the second trench 133 is etched away to obtain the insulating dielectric layer 143. The structure after step S226 is shown in FIG3f.

[0064] S227, fill the second trench with doped polysilicon.

[0065] See Figure 3g. In one embodiment of this application, P-type doped polysilicon is deposited on the front side of the wafer to fill the second trench 133, and then excess polysilicon is removed by etch-back and / or polishing (CMP).

[0066] At this point, step S220 is complete. In another embodiment of this application, the target trench structure and the first P-type doped region 132 may be formed first, and then the trench gate structure (and the second P-type doped region 134) may be formed.

[0067] S230 is used to dope the drift region to form the bulk region.

[0068] In one embodiment of this application, ion implantation of a second conductivity type is performed on the top of the epitaxial layer to form a body region 152 on the upper side of the trench gate structure and the upper side of the target trench structure. In one embodiment of this application, the first conductivity type is N-type, the second conductivity type is P-type, and the body region 152 is a P-type body region.

[0069] S240 is used to dope the bulk region to form the emitter region.

[0070] In one embodiment of this application, ion implantation of a first conductivity type is performed on the top of the body region 152 to form an emitter region 154, see FIG3h. In one embodiment of this application, the emitter region 154 is an N+ region.

[0071] S250 forms a contact hole.

[0072] In one embodiment of this application, a target contact hole 163 is formed on the doped polysilicon 144 and an emitter contact hole 161 is formed on the body region 152. The target contact hole 163 is filled with a conductive material electrically connected to the doped polysilicon 144, and the emitter contact hole 161 is filled with a conductive material electrically connected to the emitter region 154 and the body region 152. In another embodiment of this application, an interlayer dielectric layer 162 is deposited on the body region 152, and then the target contact hole 163 and the emitter contact hole 161 are formed by photolithography and etching, as shown in FIG3i.

[0073] S260, forming the target metal connection on the contact hole.

[0074] Referring to Figure 3j, a metal layer is formed on the interlayer dielectric layer 162, and a pad for the emitter E is formed. The metal layer includes a target metal interconnect 172, which is electrically connected to the doped polysilicon 144, the emitter region 154, and the body region 152 through a contact hole. The contact hole can be a large hole that simultaneously contacts the doped polysilicon 144, the emitter region 154, and the body region 152, or it can include a target contact hole 163 and an emitter contact hole 161. The target contact hole 163 is electrically connected to the doped polysilicon 144, and the emitter contact hole 161 is electrically connected to the emitter region 154 and the body region 152.

[0075] S270 forms a collector region at the bottom of the substrate.

[0076] In one embodiment of this application, after back-side thinning of the substrate, ions of a second conductivity type are implanted into the back-side of the substrate to form a collector region 110. Then, a back-side metal is formed as the collector electrode C, as shown in FIG1. ​​In one embodiment of this application, an N+ substrate serves as a buffer layer 120, and the collector region 110 is a P++ region.

[0077] In the above-described method for manufacturing trench gate insulated gate bipolar transistors, the holes in the drift region are rapidly drawn away by the emitter along the first P-type doped region-doped polysilicon-target contact hole-target metal connection line at the instant the IGBT is turned off from the on state. Therefore, the tail current time can be shortened, thereby reducing the IGBT's turn-off time.

[0078] The manufacturing method of the trench gate insulated gate bipolar transistor in this application is based on the same inventive concept as the trench gate insulated gate bipolar transistor. For details not specifically described in the manufacturing method of the trench gate insulated gate bipolar transistor, please refer to the above introduction of the trench gate insulated gate bipolar transistor.

[0079] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0080] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0081] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A trench-gate insulated-gate bipolar transistor, characterized in that, include: Collection area; The drift region is located on the current collector region; The body region is located on the drift region; An emission region is located within the body region, and the conductivity type of the emission region is opposite to that of the body region. A trench gate structure extending from the body region into the drift region includes a gate dielectric layer located on the inner surface of a first trench, and a gate located in the first trench and surrounded by the gate dielectric layer. The target trench structure extends from the body region to the drift region and includes an insulating dielectric layer located on the sidewall of the second trench, and a doped polysilicon located in the second trench and surrounded from the side by the insulating dielectric layer, wherein the doped polysilicon is P-type doped polysilicon. The first P-type doped region is located in the drift region below the second trench and surrounds the bottom of the second trench, and is electrically connected to the doped polysilicon. The target metal interconnect, located above the body region, is used to connect to the emitter potential. The target metal interconnect is electrically connected to the doped polysilicon, the emitter region, and the body region through the contact hole below.

2. The trench gate insulated gate bipolar transistor according to claim 1, characterized in that, The first P-type doped region forms an ohmic contact with the doped polysilicon.

3. The trench gate insulated gate bipolar transistor according to claim 1, characterized in that, It also includes a second P-type doped region located in the drift region below the first trench and surrounding the bottom of the first trench.

4. The trench gate insulated gate bipolar transistor according to claim 1, characterized in that, The gate material is N-type doped polycrystalline silicon.

5. The trench gate insulated gate bipolar transistor according to claim 1, characterized in that, The drift region and the emitter region have a first conductivity type, and the collector region and the body region have a second conductivity type, wherein the first conductivity type and the second conductivity type are opposite conductivity types.

6. The trench gate insulated gate bipolar transistor according to claim 5, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type.

7. The trench gate insulated gate bipolar transistor according to claim 3, characterized in that, The first trench and the second trench have the same depth.

8. The trench gate insulated gate bipolar transistor according to claim 3, characterized in that, The junction depths of the first P-type doped region and the second P-type doped region are equal.

9. The trench gate insulated gate bipolar transistor according to claim 1, characterized in that, It also includes a buffer layer located between the collector region and the drift region.

10. The trench gate insulated gate bipolar transistor according to claim 9, characterized in that, The buffer layer and the drift region have a first conductivity type, and the collector region has a second conductivity type. The first conductivity type and the second conductivity type are opposite conductivity types. The doping concentration of the buffer layer is greater than the doping concentration of the drift region.

11. The trench gate insulated gate bipolar transistor according to claim 1, characterized in that, The depth of the trench grid structure is less than the depth of the target trench structure.

12. The trench gate insulated gate bipolar transistor according to claim 1, characterized in that, The target trench structure and the trench grid structure are distributed adjacently and alternately.

13. The trench gate insulated gate bipolar transistor according to claim 1, characterized in that, The gate dielectric layer and the insulating dielectric layer are made of silicon oxide.

14. The trench gate insulated gate bipolar transistor according to claim 1, characterized in that, It also includes an interlayer dielectric layer located above the body region, the emitter region, the trench gate structure and the target trench structure, and below the target metal interconnect, wherein the contact hole penetrates the interlayer dielectric layer.

15. A method for manufacturing a trench gate insulated gate bipolar transistor, comprising: Obtain a substrate with a drift region; A trench gate structure, a target trench structure, and a first P-type doped region are formed in the drift region; The trench gate structure includes a gate dielectric layer formed on the inner surface of a first trench, and a gate formed in the first trench and surrounded by the gate dielectric layer; the target trench structure includes an insulating dielectric layer formed on the sidewall of a second trench, and doped polysilicon formed in the second trench and surrounded from the side by the insulating dielectric layer, wherein the doped polysilicon is P-type doped polysilicon. The first P-type doped region is formed in the drift region below the second trench and surrounds the bottom of the second trench. The first P-type doped region is electrically connected to the doped polysilicon. The drift region is doped to form a bulk region located on the upper side of the trench gate structure and the upper side of the target trench structure; The body region is doped to form an emitter region within the body region; the conductivity type of the emitter region is opposite to that of the emitter region. A contact hole is formed on the doped polysilicon, and the contact hole is filled with a conductive material that is electrically connected to the doped polysilicon, the emitter region and the body region; A target metal interconnect is formed on the contact hole; the target metal interconnect is electrically connected to the doped polysilicon, the emitter region and the body region through the contact hole; A current collector region is formed at the bottom of the substrate.

Images