Semiconductor storage device

Abstract

An embodiment provides a semiconductor memory device that operates at high speed. The semiconductor memory device of the embodiment includes a memory cell array and a peripheral circuit. The peripheral circuit is connected to the memory cell array and inputs and outputs user data as an instruction set including instruction data and address data is input. The peripheral circuit includes an instruction register, an address register, and a queue register. The instruction register includes an n-bit first register column capable of storing n-bit data constituting the instruction data. The address register includes an n-bit second register column capable of storing n-bit data constituting the address data. The queue register includes a plurality of third register columns capable of storing at least n + 1-bit data. The third register column can store n-bit data constituting the instruction data and n-bit data constituting the address data.

Description

[0001] [Related Application]

[0002] This application claims priority based on Japanese Patent Application No. 2020-111767 (filing date: June 29, 2020). This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Art

[0004] A semiconductor memory device is known, which includes: a memory cell array including a plurality of memory cells; and a peripheral circuit connected to the memory cell array, which outputs user data in response to an instruction set including instruction data and address data. Summary of the Invention

[0005] An embodiment provides a semiconductor memory device that operates at high speed.

[0006] A semiconductor memory device according to one embodiment includes: a memory cell array including a plurality of memory cells; and a peripheral circuit connected to the memory cell array, which inputs and outputs user data in response to an instruction set including instruction data and address data. The peripheral circuit includes an instruction register, an address register, and a queue register. The instruction register includes an n-bit first register column capable of storing n (n is a natural number) bits of data constituting the instruction data. The address register includes an n-bit second register column capable of storing n bits of data constituting the address data. The queue register includes a plurality of third register columns capable of storing at least n + 1 bits of data, and the third register columns can store n bits of data constituting the instruction data and n bits of data constituting the address data.

[0007] A semiconductor memory device according to one embodiment includes: a memory cell array including a plurality of memory cells; and a peripheral circuit connected to the memory cell array, which inputs and outputs user data in response to an instruction set including instruction data and address data. The peripheral circuit includes a queue register capable of storing the input instruction set, and is configured to execute an internal operation corresponding to the instruction set stored in the queue register without erasing the instruction set stored in the queue register in response to the input of the first instruction data.

[0008] A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells; and a peripheral circuit connected to the memory cell array, which inputs and outputs user data in response to an instruction set including instruction data and address data. The peripheral circuit includes a queue register capable of storing the instruction set input during a busy period in which a first internal operation is being executed, and is configured to automatically execute a second internal operation corresponding to the instruction set stored in the queue register after the first internal operation is executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 6 is a schematic block diagram showing the configuration of the memory system 10 according to the first embodiment.

[0010] Figure 2 FIG. 10 is a schematic side view showing a configuration example of the memory system 10.

[0011] Figure 3 FIG. 14 is a schematic top view showing the configuration example.

[0012] Figure 4 FIG. 18 is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment.

[0013] Figure 5 FIG. 22 is a schematic circuit diagram showing a partial configuration of the memory die MD.

[0014] Figure 6 FIG. 26 is a schematic block diagram showing a partial configuration of the memory die MD.

[0015] Figure 7 FIG. 30 is a schematic block diagram showing a partial configuration of the memory die MD.

[0016] Figure 8 FIG. 34 is a timing chart for explaining the operation of the memory die MD.

[0017] Figure 9 FIG. 38 is a timing chart for explaining the operation of the memory die MD.

[0018] Figure 10 FIG. 42 is a timing chart for explaining the operation of the memory die MD.

[0019] Figure 11 FIG. 46 is a timing chart for explaining the operation of the memory die MD.

[0020] Figure 12 FIG. 50 is a timing chart for explaining the operation of the memory die MD.

[0021] Figure 13 FIG. 54 is a timing chart for explaining the operation of the memory die MD.

[0022] Figure 14 It is a timing diagram for explaining the operation of the memory die MD.

[0023] Figure 15 It is a timing diagram for explaining the operation of the memory die of the second embodiment.

[0024] Figure 16 It is a timing diagram for explaining the operation of the memory die of the third embodiment.

[0025] Figure 17 It is a timing diagram for explaining the operation of the memory die of the third embodiment.

[0026] Figure 18 It is a timing diagram for explaining the operation of the memory die of the fourth embodiment.

[0027] Figure 19 It is a schematic block diagram showing the configuration of the memory die MD' of the fifth embodiment.

[0028] Figure 20 It is a timing diagram for explaining the operation of the memory die MD' of the fifth embodiment.

[0029] Figure 21 It is a schematic block diagram showing the configuration of the memory die MD'' of the sixth embodiment.

[0030] Figure 22 It is a timing diagram for explaining the operation of the memory die MD'' of the sixth embodiment.

[0031] Figure 23 It is a schematic block diagram showing a partial configuration of the memory die of the seventh embodiment.

[0032] Figure 24 It is a timing diagram for explaining the operation of the memory die of the seventh embodiment.

[0033] Figure 25 It is a timing diagram for explaining the operation of the memory die of the seventh embodiment.

[0034] Figure 26 It is a schematic block diagram showing a partial configuration of the memory die of the eighth embodiment.

[0035] Figure 27 It is a timing diagram for explaining the operation of the memory die of the eighth embodiment. Detailed Embodiments

[0036] Next, the semiconductor memory device according to the embodiment will be described in detail with reference to the drawings. In addition, the following embodiments are merely examples and are not intended to limit the present invention.

[0037] In addition, when referring to a "semiconductor memory device" in this specification, it sometimes refers to a memory die (memory chip), and sometimes refers to a memory system including a controller die such as a memory card, an SSD (Solid State Drive), etc. Furthermore, it sometimes also refers to a configuration including a host such as a smartphone, a tablet terminal, or a personal computer.

[0038] In addition, when it is mentioned in this specification that a first configuration is "electrically connected" to a second configuration, it may be that the first configuration is directly connected to the second configuration, or it may be that the first configuration is connected to the second configuration via wiring, semiconductor components, transistors, etc. For example, in the case of connecting three transistors in series, even if the second transistor is in the off state, the first transistor is "electrically connected" to the third transistor.

[0039] In addition, when it is mentioned in this specification that a first configuration is "connected between" a second configuration and a third configuration, it sometimes means that the first configuration, the second configuration, and the third configuration are connected in series, and the second configuration is connected to the third configuration via the first configuration.

[0040] In addition, when it is mentioned in this specification that a circuit or the like makes two wirings or the like "conductive", it sometimes means that, for example, the circuit or the like includes transistors or the like, the transistors or the like are provided on the current path between the two wirings, and the transistors or the like are in the on state.

[0041] [First Embodiment]

[0042] [Memory System 10]

[0043] Figure 1 It is a schematic block diagram showing the configuration of the memory system 10 according to the first embodiment.

[0044] The memory system 10 reads, writes, erases, etc. user data according to signals sent from the host 20. The memory system 10 is, for example, a memory card, an SSD, or other systems capable of storing user data. The memory system 10 includes a plurality of memory dies (memory chips) MD for storing user data, and a controller die (controller chip) CD connected to the plurality of memory dies MD and the host 20. The controller die CD includes, for example, a processor, a RAM (Random Access Memory), etc., and performs processing such as conversion between logical addresses and physical addresses, bit error detection / correction, garbage collection (compression), wear leveling, etc.

[0045] Figure 2 It is a schematic side view showing a configuration example of the memory system 10 according to this embodiment. Figure 3 It is a schematic top view showing the configuration example. For ease of explanation,Figure 2 and Figure 3 a part of the structure is omitted.

[0046] As Figure 2 shown, the memory system 10 of the present embodiment includes a mounting substrate MSB, a plurality of memory dies MD stacked on the mounting substrate MSB, and a controller die CD stacked on the memory die MD. Pad electrodes P are provided in the end regions in the Y direction on the upper surface of the mounting substrate MSB, and other partial regions are bonded to the lower surface of the memory die MD via an adhesive or the like. Pad electrodes P are provided in the end regions in the Y direction on the upper surface of the memory die MD, and other regions are bonded to the lower surface of other memory dies MD or the controller die CD via an adhesive or the like. Pad electrodes P are provided in the end regions in the Y direction on the upper surface of the controller die CD.

[0047] As Figure 3 shown, the mounting substrate MSB, the plurality of memory dies MD, and the controller die CD each include a plurality of pad electrodes P arranged in the X direction. The plurality of pad electrodes P provided in the mounting substrate MSB, the plurality of memory dies MD, and the controller die CD are connected to each other via bonding wires B.

[0048] In addition,[[]] Figure 2 and Figure 3 the structures shown are only examples, and the specific structures can be adjusted appropriately. For example, in the examples shown in Figure 2 and Figure 3 the controller die CD is stacked on the plurality of memory dies MD, and these structures are connected by bonding wires B. In this structure, the plurality of memory dies MD and the controller die CD are included in one package. However, the controller die CD may also be included in a package different from the memory die MD. In addition, the plurality of memory dies MD and the controller die CD may also be connected to each other via through electrodes or the like instead of the bonding wires B.

[0049] [Structure of Memory Die MD]

[0050] Figure 4 is a schematic block diagram showing the structure of the memory die MD of the first embodiment. Figure 5 is a schematic circuit diagram showing a partial structure of the memory die MD. Figure 6 and Figure 7 are schematic block diagrams showing a partial structure of the memory die MD.

[0051] In addition,[[]] Figure 4Multiple control terminals and the like are shown. The multiple control terminals have the following three cases, that is, being represented as control terminals corresponding to active-high signals (positive logic signals), being represented as control terminals corresponding to active-low signals (negative logic signals), and being represented as control terminals corresponding to both active-high signals and active-low signals. Figure 4 In, the symbol of the control terminal corresponding to the active-low signal includes an over line. In this specification, the symbol of the control terminal corresponding to the active-low signal includes a slash (" / "). In addition, Figure 4 Taking the description of as an example, the specific aspect can be adjusted appropriately. For example, some or all of the active-high signals can be set as active-low signals, or some or all of the active-low signals can be set as active-high signals.

[0052] As Figure 4 shown, the memory die MD includes a memory cell array MCA for storing data and a peripheral circuit PC connected to the memory cell array MCA. The peripheral circuit PC includes a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, a cache memory CM, and a sequencer SQC. In addition, the peripheral circuit PC includes an input / output control circuit I / O and a logic circuit CTR. In addition, the peripheral circuit PC includes an address register ADR, an instruction register CMR, a queue register QR connected to the address register ADR and the instruction register CMR, and a queue register control circuit QRC ( Figure 7 ).

[0053] [Configuration of Memory Cell Array MCA]

[0054] As Figure 5 shown, the memory cell array MCA includes a plurality of memory blocks BLK. The plurality of memory blocks BLK each include a plurality of string components SU. The plurality of string components SU each include a plurality of memory strings MS. One ends of the plurality of memory strings MS are respectively connected to the peripheral circuit PC via bit lines BL. In addition, the other ends of the plurality of memory strings MS are respectively connected to the peripheral circuit PC via a common source line SL.

[0055] The memory string MS includes a drain-side selection transistor STD connected in series between the bit line BL and the source line SL, a plurality of memory cells MC (memory transistors), a source-side selection transistor STS, and a source-side selection transistor STSb. Hereinafter, the drain-side selection transistor STD, the source-side selection transistor STS, and the source-side selection transistor STSb may sometimes be simply referred to as selection transistors (STD, STS, STSb).

[0056] The memory cell MC is a field-effect transistor having a semiconductor layer that functions as a channel region, a gate insulating film including a charge storage film, and a gate electrode. The threshold voltage of the memory cell MC varies according to the amount of charge in the charge storage film. The memory cell MC stores 1 bit or multiple bits of data. Further, word lines WL are respectively connected to the gate electrodes of a plurality of memory cells MC corresponding to one memory string MS. These word lines WL are commonly connected to all the memory strings MS in one memory block BLK.

[0057] The selection transistors (STD, STS, STSb) are field-effect transistors having a semiconductor layer that functions as a channel region, a gate insulating film, and a gate electrode. Selection gate lines (SGD, SGS, SGSb) are respectively connected to the gate electrodes of the selection transistors (STD, STS, STSb). The drain-side selection gate line SGD is provided corresponding to the string component SU and is commonly connected to all the memory strings MS in one string component SU. The source-side selection gate line SGS is commonly connected to all the memory strings MS in a plurality of string components SU. The source-side selection gate line SGSb is commonly connected to all the memory strings MS in a plurality of string components SU.

[0058] [Configuration of the voltage generation circuit VG]

[0059] For example, as Figure 5 shown, the voltage generation circuit VG ( Figure 4 ) is connected to a plurality of voltage supply lines 31. The voltage generation circuit VG includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit 32. These step-down circuit and step-up circuit are respectively connected to the supply power voltage V CC and the ground voltage V SS ( Figure 4 ). These voltage supply lines are connected to, for example, the pad electrodes P described with reference to Figure 2 , Figure 3 . The voltage generation circuit VG generates, for example, a plurality of operation voltages to be applied to the bit line BL, the source line SL, the word line WL, and the selection gate lines (SGD, SGS, SGSb) during a read operation, a write operation, and an erase operation of the memory cell array MCA according to a control signal from the sequencer SQC, and outputs them to the plurality of voltage supply lines 31 at the same time. The operation voltages output from the voltage supply lines 31 are appropriately adjusted according to the control signal from the sequencer SQC.

[0060] [Configuration of the row decoder RD]

[0061] For example, as Figure 5 shown, the row decoder RD ( Figure 4 ) has address data D ADDAn address decoder 22 that performs decoding, and a block selection circuit 23 and a voltage selection circuit 24 that transmit an operation voltage to the memory cell array MCA according to an output signal of the address decoder 22.

[0062] The address decoder 22 includes a plurality of block selection lines BLKSEL and a plurality of voltage selection lines 33. For example, the address decoder 22 sequentially refers to the row address RA of the address register ADR( Figure 4 ) according to a control signal from the sequencer SQC, decodes the row address RA, turns on specific block selection transistors 35 and voltage selection transistors 37 corresponding to the row address RA, and turns off the other block selection transistors 35 and voltage selection transistors 37. For example, the voltages of the specific block selection lines BLKSEL and the voltage selection lines 33 are set to the "H" state, and the other voltages are set to the "L" state. In addition, when P-channel transistors are used instead of N-channel transistors, opposite voltages are applied to these wirings.

[0063] In addition, in the illustrated example, in the address decoder 22, one block selection line BLKSEL is provided for one memory block BLK. However, this configuration can be appropriately changed. For example, one block selection line BLKSEL can be provided for two or more memory blocks BLK.

[0064] The block selection circuit 23 includes a plurality of block selection units 34 corresponding to the memory blocks BLK. The plurality of block selection units 34 each include a plurality of block selection transistors 35 corresponding to the word lines WL and the selection gate lines (SGD, SGS, SGSb). The block selection transistors 35 are, for example, field effect type withstand voltage transistors. The drain electrodes of the block selection transistors 35 are electrically connected to the corresponding word lines WL or selection gate lines (SGD, SGS, SGSb) respectively. The source electrodes are electrically connected to the voltage supply line 31 via the wirings CG and the voltage selection circuit 24 respectively. The gate electrodes are commonly connected to the corresponding block selection lines BLKSEL.

[0065] In addition, the block selection circuit 23 further includes a plurality of transistors (not shown). The plurality of transistors are field effect type withstand voltage transistors connected between the selection gate lines (SGD, SGS, SGSb) and the voltage supply line that supplies the ground voltage V SS . The plurality of transistors supply the ground voltage V SS to the selection gate lines (SGD, SGS, SGSb) included in the unselected memory blocks BLK. In addition, the plurality of word lines WL included in the unselected memory blocks BLK become floating states.

[0066] The voltage selection circuit 24 includes a plurality of voltage selection units 36 corresponding to the word lines WL and the selection gate lines (SGD, SGS, SGSb). Each of the plurality of voltage selection units 36 includes a plurality of voltage selection transistors 37. The voltage selection transistor 37 is, for example, a field effect type withstand voltage transistor. The drain terminals of the voltage selection transistors 37 are electrically connected to the corresponding word line WL or selection gate line (SGD, SGS, SGSb) via the wiring CG and the block selection circuit 23, respectively. The source terminals are electrically connected to the corresponding voltage supply line 31, respectively. The gate electrodes are connected to the corresponding voltage selection line 33, respectively.

[0067] [Configuration of the Sense Amplifier Module SAM]

[0068] The sense amplifier module SAM includes, for example, a plurality of sense amplifier units SAU ( Figure 6 ) corresponding to a plurality of bit lines BL. Each sense amplifier unit SAU includes a sense amplifier SA connected to the bit line BL, a wiring LBUS connected to the sense amplifier SA, and a plurality of latch circuits DL connected to the wiring LBUS. The sense amplifier SA includes a sensing circuit connected to the bit line BL, a voltage transfer circuit connected to the bit line BL, and a latch circuit connected to the sensing circuit and the voltage transfer circuit. The sensing circuit includes a sensing transistor that becomes conductive or non-conductive according to the voltage or current of the bit line BL and releases the charge in the wiring LBUS according to this state. The voltage transfer circuit conducts the bit line BL to either one of the two voltage supply lines according to the data latched in the latch circuit in the sense amplifier SA. The wiring LBUS in the sense amplifier unit SAU is connected to the wiring dbus constituting the bus DBUS via a switching transistor DSW.

[0069] [Configuration of the Cache Memory CM]

[0070] The cache memory CM includes a plurality of latch circuits XDL ( Figure 6 ) connected to the latch circuits in the sense amplifier module SAM via a plurality of wirings dbus constituting the bus DBUS. User data written into the memory cell MC or user data read from the memory cell MC is stored in the latch circuit XDL, for example. The data DAT contained in the plurality of latch circuits XDL is sequentially transmitted to the sense amplifier module SAM or the input / output control circuit I / O.

[0071] In addition, a decoding circuit and a switching circuit (not shown) are connected to the cache memory CM. The decoding circuit decodes the column address CA stored in the address register ADR ( Figure 4 ). The switching circuit conducts the latch circuit XDL corresponding to the column address CA to the bus DB ( Figure 4 ) according to the output signal of the decoding circuit.

[0072] [Configuration of Sequencer SQC]

[0073] Sequencer SQC( Figure 4 ) outputs the internal control number to the row decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG according to the instruction data D stored in the instruction register CMR. In addition, the sequencer SQC appropriately outputs the status data D representing the state of the memory die MD CMD to the status register STR. ST

[0074] In addition, the sequencer SQC generates a ready / busy signal and outputs it to the terminal RY / / BY. During the period when the signal at the terminal RY / / BY is in the "L" state (busy period), access to the memory die MD is basically prohibited. In addition, during the period when the signal at the terminal RY / / BY is in the "H" state (ready period), access to the memory die MD is permitted. In addition, the signal at the terminal RY / / BY is realized, for example, by referring to Figure 2 Figure 3 the pad electrode P described. Sometimes the signal output from the terminal RY / / BY is called the ready / busy signal RY / / BY.

[0075] [Configuration of Input / Output Control Circuit I / O]

[0076] The input / output control circuit I / O includes data signal input / output terminals DQ0 to DQ7, trigger signal input / output terminals DQS, / DQS, input circuits such as comparators connected to the data signal input / output terminals DQ0 to DQ7, and output circuits such as an OCD (OffChip Driver) circuit. In addition, the input / output circuit I / O includes a shift register and a buffer circuit connected to the input circuit and the output circuit. The input circuit, the output circuit, the shift register, and the buffer circuit are respectively connected to the terminals for supplying the power supply voltage V CCQ and the ground voltage V SS . The data signal input / output terminals DQ0 to DQ7, the trigger signal input / output terminals DQS, / DQS, and the terminals for supplying the power supply voltage V CCQ are realized, for example, by referring to Figure 2 Figure 3 the pad electrode P described.

[0077] According to the internal control signal from the logic circuit CTR, the data input via the data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, the address register ADR, or the instruction register CMR. Additionally, according to the internal control signal from the logic circuit CTR, the data output via the data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or the status register STR to the buffer circuit.

[0078] [Configuration of Logic Circuit CTR]

[0079] Logic circuit CTR( Figure 4 ) receives external control signals from the controller die CD via the external control terminals / CEn, CLE, ALE, / WE, RE, / RE, and correspondingly outputs internal control signals to the input / output control circuit I / O. In addition, the external control terminals / CEn, CLE, ALE, / WE, RE, / RE are implemented, for example, by referring to Figure 2 , Figure 3 the pad electrodes P described.

[0080] The external control terminal / CEn is used when selecting the memory die MD. The input / output control circuit I / O of the memory die MD to which “L” is input to the external control terminal / CEn performs the operation of inputting and outputting data via the data signal input / output terminals DQ0 to DQ7. The input / output control circuit I / O of the memory die MD to which “H” is input to the external control terminal / CEn does not perform the operation of inputting and outputting data via the data signal input / output terminals DQ0 to DQ7. Sometimes the signal input to the external control terminal / CEn is called the chip enable signal / CEn.

[0081] Additionally, the external control terminal CLE is used when using the instruction register CMR. When “H” is input to the external control terminal CLE, the data input via the data signal input / output terminals DQ0 to DQ7 is stored as instruction data D CMD in the buffer memory within the input / output control circuit I / O and is transferred to the instruction register CMR. Sometimes the signal input to the external control terminal CLE is called the instruction latch enable signal CLE.

[0082] Additionally, the external control terminal ALE is used when using the address register ADR. When “H” is input to the external control terminal ALE, the data input via the data signal input / output terminals DQ0 to DQ7 is stored as address data D ADD in the buffer memory within the input / output control circuit I / O and is transferred to the address register ADR. Sometimes the signal input to the external control terminal ALE is called the address latch enable signal ALE.

[0083] In addition, when "L" is input to the two external control terminals CLE and ALE, the data DAT input via the data signal input / output terminals DQ0 to DQ7 is stored as user data in the buffer memory within the input / output control circuit I / O, and is transmitted to the cache memory CM via the bus DB.

[0084] The external control terminal / WE is used when inputting data via the data signal input / output terminals DQ0 to DQ7. The data input via the data signal input / output terminals DQ0 to DQ7 is taken into the shift register within the input / output control circuit I / O at the time when the voltage of the external control terminal / WE rises (switching the input signal). Sometimes the signal input to the external control terminal / WE is called the write enable signal / WE.

[0085] The trigger signal input / output terminals DQS and / DQS are used when inputting data via the data signal input / output terminals DQ0 to DQ7. The data input via the data signal input / output terminals DQ0 to DQ7 is taken into the shift register within the input / output control circuit I / O at the time when the voltage of the trigger signal input / output terminal DQS rises (switching the input signal) and the voltage of the trigger signal input / output terminal / DQS drops (switching the input signal), and at the time when the voltage of the trigger signal input / output terminal DQS drops (switching the input signal) and the voltage of the trigger signal input / output terminal / DQS rises (switching the input signal). Sometimes the signals input to the trigger signal input / output terminals DQS and / DQS are called the data strobe signals DQS and / DQS.

[0086] In addition, when inputting data, the external control terminal / WE can be used, or the trigger signal input / output terminals DQS and / DQS can be used.

[0087] The external control terminals RE and / RE are used when outputting data via the data signal input / output terminals DQ0 to DQ7. The data output from the data signal input / output terminals DQ0 to DQ7 is switched at the time when the voltage of the external control terminal RE drops (switching the input signal) and the voltage of the external control terminal / RE rises (switching the input signal), and at the time when the voltage of the external control terminal RE rises (switching the input signal) and the voltage of the external control terminal / RE drops (switching the input signal). Sometimes the signals input to the external control terminals RE and / RE are called the read enable signals RE and / RE.

[0088] [Configuration of the address register ADR]

[0089] As Figure 7As shown, the address register ADR is connected to the input / output control circuit I / O via path S101, and stores the address data D input from the input / output control circuit I / O ADD . The address register ADR includes, for example, a register circuit group RG101, RG102 including six groups of 8-bit register columns. The 8-bit register column includes an 8-bit register circuit Register[7:0]. The 8-bit register circuit Register[7:0] may also include, for example, eight latch circuits that use a pair of CMOS (Complementary Metal Oxide Semiconductor) inverters to store 1-bit data. The register circuit group RG101 stores the address data D corresponding to the internal operation being executed, for example, when performing internal operations such as read operations, write operations, or erase operations ADD . The register circuit group RG102 can be used, for example, in the following situations, that is, when temporarily suspending a write operation or an erase operation and performing a read operation, it temporarily stores the address data D corresponding to the write operation or the erase operation ADD .

[0090] [Configuration of Instruction Register CMR]

[0091] The instruction register CMR is connected to the input / output control circuit I / O via path S102, and stores the instruction data D input from the input / output control circuit I / O CMD . The instruction register CMR includes, for example, a register circuit group RG103 including one group of 8-bit register columns. The 8-bit register column includes an 8-bit register circuit Register[7:0]. The 8-bit register circuit Register[7:0] may also include, for example, eight latch circuits that use a pair of CMOS inverters to store 1-bit data. When the instruction data D is stored in the instruction register CMR CMD , a control signal is sent to the sequencer SQC via path S108, or a control signal is sent to the queue register control circuit QRC via path S107

[0092] [Configuration of Queue Register QR]

[0093] The queue register QR is connected to the address register ADR via paths S103 and S104, and is connected to the instruction register CMR via paths S105 and S106, so as to perform two-way data input / output with the address register ADR and the instruction register CMR

[0094] Paths S103 and S105 are paths for transmitting data from the address register ADR and the instruction register CMR to the queue register QR

[0095] The paths S104 and S106 are the paths for transferring data from the queue register QR to the address register ADR and the instruction register CMR.

[0096] In addition, the configurations of the paths S103, S104, S105, and S106 can be adjusted appropriately. For example, the paths S103, S104, S105, and S106 may also include eight wirings and switching circuits such as MOS transistors. The eight wirings transfer data, and the MOS transistors become conductive in response to the Q setting operation described later and become non-conductive in response to the Q end operation described later. In addition, the paths S103 and S104 may also include switching circuits such as MOS transistors that become conductive when transferring address data and become non-conductive when transferring instruction data. In addition, the paths S105 and S106 may also include switching circuits such as MOS transistors that become non-conductive when transferring address data and become conductive when transferring instruction data. In addition, the paths S103 and S104 may be implemented by a common configuration. In addition, the paths S105 and S106 may be implemented by a common configuration.

[0097] The queue register QR includes, for example, a register circuit group RG104 including a register column of 10 sets in total of 9 bits. The 9-bit register column includes an 8-bit register circuit Register[7:0] for storing address / instruction data and a 1-bit register circuit ADDnCMD for address / instruction determination. The 8-bit register circuit Register[7:0] may include, for example, eight latch circuits that use a pair of CMOS inverters to store 1-bit data. The 1-bit register circuit ADDnCMD may include, for example, one latch circuit that uses a pair of CMOS inverters to store 1-bit data.

[0098] The 8-bit register circuit Register[7:0] for storing address / instruction data stores 8-bit data constituting the address data D ADD or the instruction data D CMD The 1-bit register circuit ADDnCMD for address / instruction determination stores 1-bit data indicating whether the data stored in the 8-bit register circuit Register[7:0] for storing address / instruction data is address data or instruction data. For example, when the data stored in the 8-bit register circuit Register[7:0] for storing address / instruction data is the instruction data D CMD "H" is stored, and when the stored data is the address data D ADD "L" is stored.

[0099] In addition, when no address data or instruction data is stored in the register column, for example, the same data as the instruction data C999 described later is stored in the 8-bit register circuit Register[7:0] of the register column, and "H" is stored in the 1-bit register circuit ADDnCMD of the register column.

[0100] The operation of storing data in the queue register QR is a FIFO (First In First Out) operation, and the data input first is output first. The specific configuration of the queue register QR can be adjusted appropriately. For example, the queue register QR can also be configured as a shift register, that is, the data is updated corresponding to the rising edge of the signal line QueCLK. In this case, for example, corresponding to the rising edge of the signal line QueCLK, the data stored in the first register column to the ninth register column is transferred to the second register column to the tenth register column. In addition, when the path S103 or the path S105 is open, the data stored in the address register ADR or the instruction register CMR is transferred to the first register column. In addition, when neither the path S103 nor the path S105 is open, the data stored in the tenth register column is transferred to the first register column. In addition, when the path S104 or the path S106 is open, the data stored in the tenth register column is transferred to the address register ADR or the instruction register CMR. However, even when the path S104 or the path S106 is open, if the data stored in the tenth register column is the instruction data C999, this data will not be transferred to the address register ADR or the instruction register CMR.

[0101] In addition, a circuit can be provided at least at one place between the queue register QR and the instruction register CMR and between the queue register QR and the address register ADR. The circuit stores "H" or "L" in the 1-bit register circuit ADDnCMD according to whether the data input to the queue register QR is instruction data D CMD or address data D ADD . Such a circuit can be realized, for example, by connecting the signal line of at least one of the switch circuits included in the control path S103 and the switch circuits included in the path S105 to the 1-bit register circuit ADDnCMD, or can include a CMOS inverter or the like. The input terminal of the CMOS inverter is connected to such a signal line, and the output terminal is connected to the 1-bit register circuit ADDnCMD. In addition, for example, the queue register control circuit QRC can also obtain the signal levels of the external control terminal CLE and / or the external control terminal ALE from the logic circuit CTR, and store "H" or "L" in the 1-bit register circuit ADDnCMD according to these signal levels.

[0102] Alternatively, a circuit may be provided between the queue register QR, the instruction register CMR, and the address register ADR. The circuit connects the 8-bit register circuit Register[7:0] in the queue register QR to the 8-bit register circuit Register[7:0] in the instruction register CMR or the address register ADR according to whether the data output from the queue register QR is instruction data D CMD or address data D ADD . Such a circuit can be implemented, for example, by connecting the signal lines of the switch circuits included in the control path S104 and the signal lines of the switch circuits included in the control path S106 to the 1-bit register circuit ADDnCMD, or by including a CMOS inverter or the like. The output terminal of the CMOS inverter is connected to such a signal line, and the input terminal is connected to the 1-bit register circuit ADDnCMD.

[0103] [Configuration of Queue Register Control Circuit QRC]

[0104] The queue register control circuit QRC is connected to the instruction register CMR via the path S107. The queue register control circuit QRC is configured to be able to perform a Q setting action, a Q end action, a Q execution action, and a Q reset action based on the instruction data input from the instruction register CMR.

[0105] The Q setting action is an action that allows data transfer from the instruction register CMR and the address register ADR to the queue register QR by opening the paths S103 and S105 through the path S201.

[0106] The Q end action is an action that prohibits data transfer from the instruction register CMR and the address register ADR to the queue register QR by blocking the paths S103 and S105 through the path S202.

[0107] The Q execution action is an action that opens the paths S104 and S106 through the path S203 and sequentially transfers all the data stored in the queue register QR to the instruction register CMR and the address register ADR.

[0108] The Q reset action is an action that erases all the data stored in the queue register QR. In the case of performing the Q reset action, the instruction data C999 is stored in all the 8-bit register circuits Register[7:0] in the queue register QR. In addition, "H" is stored in all the 1-bit register circuits ADDnCMD in the queue register QR.

[0109] In addition, the configurations of paths S201 and S202 can be appropriately adjusted. For example, paths S201 and S202 may also have a shared wiring line that is connected to the switching circuits included in paths S103 and S105, and becomes a state in which the switching circuits are turned on (in the "H" state when the switching circuits are composed of NMOS transistors) as the Q setting operation is executed, and becomes a state in which the switching circuits are not turned on (in the "L" state when the switching circuits are composed of NMOS transistors) as the Q end operation is executed. Additionally, for example, paths S201 and S202 may also have a flip-flop circuit, an RS (reset set) flip-flop circuit, or other circuits whose output terminals are connected to such a wiring line and whose output signals are inverted as a rectangular wave is input.

[0110] In addition, the configuration of path S203 can be appropriately adjusted. For example, path S203 may also have a shared wiring line that is connected to the switching circuits included in paths S104 and S106, and becomes a state in which the switching circuits are turned on (in the "H" state when the switching circuits are composed of NMOS transistors) as the Q execution operation starts, and becomes a state in which the switching circuits are not turned on (in the "L" state when the switching circuits are composed of NMOS transistors) as the Q execution operation ends. Additionally, for example, path S203 may also have a flip-flop circuit, an RS flip-flop circuit, or other circuits whose output terminals are connected to such a wiring line and whose output signals are inverted as a rectangular wave is input.

[0111] In addition, in the case where the switching circuits included in paths S103 and S104 are implemented by a common configuration, and in the case where the switching circuits included in paths S105 and S106 are implemented by a common configuration, part or all of the configurations included in paths S201 and S202 and part or all of the configurations included in path S203 may also be implemented by a common configuration.

[0112] In addition, Figure 7 the queue register control circuit QRC is shown as an independent circuit, but the queue register control circuit QRC may also be configured as part of the sequencer SQC.

[0113] [Read operation]

[0114] Next, with reference to Figure 8 the read operation of the semiconductor memory device of the present embodiment will be described.

[0115] At time point t101, the controller die CD inputs the instruction data C101 as the instruction data D CMD to the memory die MD. The instruction data C101 is an instruction indicating the start of inputting the instruction set CmdOP0 corresponding to the read operation.

[0116] When inputting the data as instruction data D CMD the voltages of the data signal input / output terminals DQ0 to DQ7 are set to "H" or "L" according to each bit of the input data, and in a state where "H" is input to the external control terminal CLE and "L" is input to the external control terminal ALE, the external control terminal / WE is raised from "L" to "H". In addition, at this time, the signals of the trigger signal input / output terminals DQS and / DQS can also be switched (triggered) instead of raising the signal of the external control terminal / WE.

[0117] At time points t102, t103, t104, t105, t106, the controller die CD inputs the address data A101, A102, A103, A104, A105 as address data D ADD to the memory die MD.

[0118] When inputting the data as address data D ADD the voltages of the data signal input / output terminals DQ0 to DQ7 are set to "H" or "L" according to each bit of the input data, and in a state where "L" is input to the external control terminal CLE and "H" is input to the external control terminal ALE, the external control terminal / WE is raised from "L" to "H". In addition, at this time, the signals of the trigger signal input / output terminals DQS and / DQS can also be switched (triggered) instead of raising the signal of the external control terminal / WE.

[0119] The address data A101 to A105 include, for example, a column address CA ( Figure 4 ) and a row address RA ( Figure 4 ). The row address RA includes, for example, a block address for specifying a memory block BLK ( Figure 5 ), a page address for specifying a string component SU and a word line WL, a memory plane address for specifying a memory cell array MCA, and a chip address for specifying a memory die MD.

[0120] At time point t107, the controller die CD inputs the instruction data C102 as instruction data D CMD to the memory die MD. The instruction data C102 is an instruction indicating that the input of the instruction set corresponding to the read operation has ended.

[0121] At time point t108, the signal of the terminal RY / / BY changes from the "H" state to the "L" state, prohibiting access to the memory die MD, and a read operation commanded by the instruction set CmdOP0 is executed in the memory die MD. Thus, the data stored in the memory cell array MCA ( Figure 4 ) is read out to the cache memory CM ( Figure 4)。

[0122] At time t109, the read operation in the memory die MD ends, and the signal of the terminal RY / / BY changes from the "L" state to the "H" state, allowing access to the memory die MD.

[0123] [Write operation]

[0124] Next, with reference to Figure 9 the write operation of the semiconductor memory device according to this embodiment will be described.

[0125] At time t111, the controller die CD inputs the instruction data C111 as the instruction data D CMD to the memory die MD. The instruction data C111 is an instruction indicating the start of input of an instruction set corresponding to the write operation.

[0126] At times t112, t113, t114, t115, t116, the controller die CD inputs the address data A111, A112, A113, A114, A115 as the address data D ADD to the memory die MD.

[0127] The address data A111 to A115 include, for example, a column address CA ( Figure 4 ) and a row address RA ( Figure 4 ). The row address RA includes, for example, a block address for specifying a memory block BLK ( Figure 5 ), a page address for specifying a string component SU and a word line WL, a memory plane address for specifying a memory cell array MCA, and a chip address for specifying a memory die MD.

[0128] Before the time from time t117 to time t120, the controller die CD inputs the data D111, D112, D113... as the data DAT to the memory die MD. The data D111, D112, D113... are user data stored in the memory cell array MCA through the write operation.

[0129] When inputting data as the data DAT, the voltages of the data signal input / output terminals DQ0 to DQ7 are set to "H" or "L" according to each bit of the input data, and in a state where "L" is input to the external control terminal CLE and "L" is input to the external control terminal ALE, the external control terminal / WE is raised from "L" to "H". In addition, at this time, the signals of the trigger signal input / output terminals DQS, / DQS may be switched (triggered) instead of raising the signal of the external control terminal / WE.

[0130] At time t120, the controller die CD inputs the instruction data C112 as the instruction data DCMD Input to memory die MD. Instruction data C112 is an instruction indicating that the input of the instruction set CmdOP1 corresponding to the write operation has ended.

[0131] At time point t121, the signal of terminal RY / / BY changes from the "H" state to the "L" state, prohibiting access to memory die MD, and a write operation commanded by instruction set CmdOP1 is executed in memory die MD. Thus, the data D111, D112, D113... input before the time point from t117 to t120 is stored in the memory cell array MCA( Figure 4 ).

[0132] At time point t122, the write operation in memory die MD ends, and the signal of terminal RY / / BY changes from the "L" state to the "H" state, allowing access to memory die MD.

[0133] At time point t123, controller die CD inputs instruction data C113 as instruction data D CMD to memory die MD. Instruction data C113 is an instruction corresponding to the status read operation. The status read operation is an operation to output status data D ST ( Figure 4 ) from memory die MD.

[0134] [Erase operation]

[0135] Next, the erase operation of the semiconductor memory device of the present embodiment will be described with reference to Figure 10 .

[0136] At time point t131, controller die CD inputs instruction data C121 as instruction data D CMD to memory die MD. Instruction data C121 is an instruction indicating the start of input of the instruction set corresponding to the erase operation.

[0137] At time points t132, t133, and t134, controller die CD inputs address data A121, A122, and A123 as address data D ADD to memory die MD.

[0138] The address data A121 to A123 includes, for example, a row address RA( Figure 4 ). The row address RA includes, for example, a block address specifying a memory block BLK( Figure 5 ), a memory plane address specifying a memory plane of the memory cell array MCA, and a chip address specifying a memory die MD.

[0139] At time point t135, controller die CD inputs instruction data C122 as instruction data DCMD Input to memory die MD. Instruction data C122 is an instruction indicating the end of the input of an instruction set corresponding to an erase operation.

[0140] At time point t136, the signal of terminal RY / / BY changes from the "H" state to the "L" state, prohibiting access to memory die MD, and an erase operation commanded by instruction set CmdOP2 is executed in memory die MD. Thereby, the data stored in a specific memory block BLK ( Figure 4 ) of the memory cell array MCA ( Figure 5 ) is erased.

[0141] At time point t137, the erase operation in memory die MD ends, and the signal of terminal RY / / BY changes from the "L" state to the "H" state, allowing access to memory die MD.

[0142] At time point t138, controller die CD inputs instruction data C113 as instruction data D CMD to memory die MD.

[0143] [Operation using queue register QR]

[0144] Next, an operation example of using queue register QR of the semiconductor memory device of the present embodiment will be described. Figure 11 FIGS. Figure 11 are a timing chart for explaining such an operation example and a schematic diagram showing data stored inside queue register QR when executing such an operation.

[0145] In the Figure 11 example, during the ready period (RY / / BY = "H"), instruction data C811 indicating a Q set operation and instruction data C812 indicating a Q end operation are input. Thereby, instruction set CmdOP0 described with reference to Figure 8 is stored in queue register QR. Next, instruction data C813 indicating a Q execution operation is input. Thereby, instruction set CmdOP0 stored in queue register QR is transferred to instruction register CMR and address register ADR, and a read operation (internal operation OP0) is executed. When instruction data C816 indicating a Q reset operation is input, instruction set CmdOP0 stored in queue register QR is erased.

[0146] Hereinafter, the operation will be described according to the Figure 11 timing chart in FIGS.

[0147] At time point t140, the signal of terminal RY / / BY is in the "H" state. Additionally, at time point t140, instruction data C999 is stored in the 8-bit register circuit Register[7:0] corresponding to all register columns in the queue register QR, and "H" is stored in the 1-bit register circuit ADDnCMD corresponding to all register columns.

[0148] At time point t141, the controller die CD inputs the instruction data C811 indicating the Q setting operation as instruction data D CMD into the memory die MD. The instruction data C811 is input into the register circuit group RG103 ( Figure 7 ) within the instruction register CMR through path S102.

[0149] When the instruction data C811 is input to the instruction register CMR, the queue register control circuit QRC is controlled through path S107. The queue register control circuit QRC performs the Q setting operation via path S201, opening paths S103 and S105 ( Figure 7 ).

[0150] At time point t142, the controller die CD inputs the instruction data C101 as instruction data D CMD into the memory die MD. Here, at time point t142, paths S103 and S105 are already open. If the instruction data C101 is input in this state, a pulse signal is input to the signal line QueCLK of the semiconductor memory device once. Subsequently, the instruction data C101 input to the instruction register CMR is transmitted through path S105 to the 8-bit register circuit Register[7:0] corresponding to the first register column in the queue register QR. Additionally, at this time, since the instruction data C101 is instruction data D CMD , "H" is stored in the 1-bit register circuit ADDnCMD for address / instruction determination.

[0151] At time point t143, the controller die CD inputs a part of the address data A101 as address data D ADD into the memory die MD. Here, at time point t142, paths S103 and S105 are already open. If the address data A101 is input in this state, a pulse signal is input to the signal line QueCLK of the semiconductor memory device once. Subsequently, the address data A101 input to the address register ADR is transmitted through path S103 to the 8-bit register circuit Register[7:0] corresponding to the first register column in the queue register QR. Additionally, at this time, since the address data A101 is address data D ADD, so the "L" is stored in the 1-bit register ADDnCMD for address / instruction determination. In addition, the instruction data C101 and "H" stored in the first register column are transferred to the second register column.

[0152] At time point t144, the controller die CD inputs the address data A102 as part of the address data D ADD to the memory die MD. Subsequently, the address data A102 and "L" are stored in the first register column within the queue register QR, the address data A101 and "L" are stored in the second register column, and the instruction data C101 and "H" are stored in the third register column.

[0153] At time point t145, the controller die CD inputs the address data A103 as part of the address data D ADD to the memory die MD. Subsequently, the address data A103 and "L" are stored in the first register column within the queue register QR, the address data A102 and "L" are stored in the second register column, the address data A101 and "L" are stored in the third register column, and the instruction data C101 and "H" are stored in the fourth register column.

[0154] At time point t146, the controller die CD inputs the instruction data C102 as the instruction data D CMD to the memory die MD. Subsequently, the instruction data C112 and "H" are stored in the first register column within the queue register QR, the address data A113 and "L" are stored in the second register column, the address data A112 and "L" are stored in the third register column, the address data A111 and "L" are stored in the fourth register column, and the instruction data C111 and "H" are stored in the fifth register column.

[0155] At time point t147, the controller die CD inputs the instruction data C812 indicating the end action of Q as the instruction data D CMD to the memory die MD.

[0156] When the instruction data C812 is input to the instruction register CMR, the queue register control circuit QRC is controlled through the path S107. The queue register control circuit QRC performs the Q end action via the path S202 and blocks the paths S103 and S105 ( Figure 7 ).

[0157] At time point t148, the controller die CD inputs the instruction data C813 indicating the execution action of Q as the instruction data D CMD to the memory die MD. The instruction data C813 is input to the register circuit group RG103 within the instruction register CMR through the path S102 (Figure 7 )。

[0158] When instruction data C813 is input to the instruction register CMR, the queue register control circuit QRC is controlled through path S107. The queue register control circuit QRC opens paths S104 and S106 via path S203. In addition, a pulse signal is input 10 times to the signal line QueCLK of the semiconductor memory device. When a pulse signal is input once, the data stored in the 10th register column of the queue register QR is transferred to the instruction register CMR or the address register ADR, and the 1st register column of the queue register QR. However, the instruction data C999 in the data stored in the queue register QR is not transferred to the instruction register CMR. In addition, when a pulse signal is input once, the data stored in the 1st to 9th register columns of the queue register QR is transferred to the 2nd to 10th register columns of the queue register QR. Therefore, when a pulse signal is input 10 times in the illustrated example, the instruction data C101 stored in the 5th register column to the instruction data C102 stored in the 1st register column are sequentially transferred to the instruction register CMR and the address register ADR, and at time point t149, a read operation (internal operation OP0) is executed.

[0159] In addition, for example, by inputting instruction data C113 ( Figure 9 ) a status read operation is executed, whereby it is possible to determine whether data is stored in the queue register QR. For example Figure 11 as illustrated, at time point t150 after the completion of the read operation (internal operation OP0), the controller die CD inputs the instruction data C816 indicating a Q reset operation as instruction data D CMD to the memory die MD. If the instruction data C816 is input, then the instruction data C999 is stored in all 8-bit register circuits Register[7:0] in the queue register QR, and "H" is stored in all 1-bit register circuits ADDnCMD in the queue register QR.

[0160] In addition, the data stored in the queue register QR is saved within the queue register QR before the Q reset operation is executed. Therefore, for example Figure 12 as illustrated, at time point t149 after time point t148, if the instruction data C813 is input again, then the read operation (internal operation OP0) is executed again.

[0161] In addition, even at the time point after the input of instruction data C811 and before the input of instruction data 812, if instruction data C999 is input to the semiconductor memory device, the instruction data C999 will not be transmitted to the queue register QR, and the sequencer SQC will execute the operation corresponding to the instruction data C999. For example, in Figure 13 the example, at such a time point t151, the instruction data C999 indicating an internal reset operation is input as instruction data D CMD . In addition, the instruction data C999 is not transmitted to the queue register QR, but is stored in the register circuit group RG103 in the instruction register CMR. Then, the internal reset operation is performed using the sequencer SQC. Thus, for example, even when an internal reset operation must be performed during the process of storing the instruction set in the queue register QR, the internal reset operation can be immediately executed using the sequencer SQC, so that the reliability of the operation of the memory die MD can be improved.

[0162] In addition, Figures 11 - 13 shows an example of storing the instruction set CmdOP0 corresponding to the read and write operations in the queue register QR. However, it is also possible to store a part of the instruction set CmdOP1 corresponding to the write operation, or a part or all of other instruction sets such as the instruction set CmdOP2 corresponding to the erase operation in the queue register QR.

[0163] For example, in Figure 14 the example, the instruction data C811 indicating the Q setting operation is input at the time point t151, the instruction set CmdOP1 is input from the time point t152 to the time point t153, and the instruction data C812 indicating the Q end operation is input at the time point t154. Here, in the present embodiment, only the instruction data C111 and C112 corresponding to the instruction data, and the address data A111 to A115 corresponding to the address data in the instruction set CmdOP1( Figure 9 ) are stored in the queue register QR, and the data DAT1 (data D111, D112, D113...) is not stored in the queue register QR.

[0164] In addition, for example, in Figure 14 the example, the instruction data C814 indicating the start of data input is input at the time point t155, the data DAT1 (data D111, D112...) included in the instruction set CmdOP1 is input at the time points from t156 to before t158, and the instruction data C815 indicating the end of data input is input at the time point t158. Here, in the present embodiment, the data D111, D112... input at the time points from t156 to before t158 are stored in the cache memory CM( Figure 4 ).

[0165] In addition, for example, in Figure 14 In the example of Figure 14 , instruction data C813 indicating that Q executes an action is input at time point t159. Subsequently, a write operation (internal operation OP1) starts at time point t160.

[0166] [Effect]

[0167] In the semiconductor memory device according to the present embodiment, by previously storing an instruction set in the queue register QR, the same internal operation can be executed multiple times as long as an instruction for Q to execute an operation is input. Therefore, for example, in the case of executing the same internal operation multiple times, etc., the time required to input the instruction set to the memory die MD can be significantly reduced. As a result, the operation of the semiconductor memory device can be speeded up.

[0168] [Second Embodiment]

[0169] Next, refer to Figure 15 The semiconductor memory device according to the second embodiment will be described. Figure 15 It is a timing chart for explaining the operation of the semiconductor memory device according to the present embodiment, and a schematic diagram showing data stored inside the queue register QR when executing this operation.

[0170] The semiconductor memory device according to the second embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, the queue register control circuit QRC according to the first embodiment is configured to execute operations such as Q setting operations based on instruction data input from the instruction register CMR. On the other hand, the queue register control circuit according to the second embodiment is configured to automatically execute operations such as Q setting operations according to the state of the semiconductor memory device.

[0171] In addition, the semiconductor memory device according to the present embodiment can also be configured, for example, to be able to select two operation modes through, for example, the set_feature function. One is to make the automatic execution of operations such as Q setting operations effective, and the other is to make the automatic execution of operations such as Q setting operations ineffective. In the case where the automatic execution of operations such as Q setting operations is made effective, for example, a set_feature instruction set modeset for setting the operation mode is input to the memory die MD, and "QueueBusyMode" is made effective.

[0172] When "QueueBusyMode" becomes effective, if the signal (ready / busy signal) of the terminal RY / / BY is in the "H" state, the input instruction set will be transmitted to the sequencer SQC via the instruction register CMR and the address register ADR, and the sequencer SQC will execute the first internal operation corresponding to the input instruction. At this time, the input instruction set is not transmitted to the queue register QR.

[0173] In the semiconductor memory device of the present embodiment, when the first internal operation is started, the signal of the terminal RY / / BY falls from the "H" state to the "L" state. Additionally, thereby, the Q setting operation can be executed.

[0174] When "QueueBusyMode" is valid, if the signal (ready-busy signal) of the terminal RY / / BY is in the "L" state, the input instruction set is transmitted to the queue register QR via the instruction register CMR and the address register ADR, and stored in the queue register QR.

[0175] After the completion of the first internal operation executed during the input of the instruction set, the Q end operation and the Q execution operation are automatically executed, and the second internal operation corresponding to the instruction set stored in the queue register QR is started. Additionally, the Q reset operation can be automatically executed after the execution of the Q execution operation and during the execution of the second internal operation. Further, during the execution of the second internal operation, the signal of the terminal RY / / BY is in the "L" state.

[0176] After the completion of the second internal operation, the signal of the terminal RY / / BY rises from the "L" state to the "H" state.

[0177] Hereinafter, the operation will be described according to Figure 15 the timing diagram in

[0178] At time t211, the controller die CD inputs the set_feature instruction set modeset as the instruction data D CMD to the memory die MD and makes "QueueBusyMode" valid.

[0179] At time t212, the controller die CD inputs the instruction data C121 as the instruction data D CMD to the memory die MD. Here, at time t212, the signal of the terminal RY / / BY is in the "H" state. Therefore, the instruction data C121 is not transmitted to the queue register QR but stored in the instruction register CMR.

[0180] At times t213, t214, and t215, the controller die CD inputs the address data A121, A122, A123 as the address data D ADD to the memory die MD. Here, at times t213, 214, 215, the signal of the terminal RY / / BY is in the "H" state. Therefore, the address data A121, A122, A123 are not transmitted to the queue register QR but stored in the address register ADR.

[0181] At time t216, the controller die CD inputs the instruction data C122 as instruction data D CMD into the memory die MD. Here, at time t216, the signal of the terminal RY / / BY is in the "H" state. Therefore, the instruction data C122 is not transmitted to the queue register QR but stored in the instruction register CMR.

[0182] At time t217, the internal operation OP2 starts to be executed according to the instruction set CmdOP2. In addition, the signal of the terminal RY / / BY then changes to the "L" state.

[0183] At time t218, the controller die CD inputs the instruction data C121 as instruction data D CMD into the memory die MD. Here, at time t218, the signal of the terminal RY / / BY is in the "L" state. Therefore, with the input of the instruction data C121, the instruction data C221 and "H" are stored in the first register column in the queue register QR.

[0184] At times t219, t220, and t221, the controller die CD inputs the address data A121', A122', A123' as address data D ADD into the memory die MD. The address data A121', A122', A123' can also be data specifying an address different from the address data A121, A122, A123 input at times t213 to t215, for example. Here, at times t219, 220, 221, the signal of the terminal RY / / BY is in the "L" state. Therefore, with the input of the address data A121', A122', A123', the address data A123' and "L" are stored in the first register column in the queue register QR, the address data A122' and "L" are stored in the second register column, the address data A121' and "L" are stored in the third register column, and the instruction data C121 and "H" are stored in the fourth register column.

[0185] At time t222, the controller die CD inputs the instruction data C122 as instruction data D CMD into the memory die MD. Here, at time t222, the signal of the terminal RY / / BY is in the "L" state. Therefore, with the input of the instruction data C122, the instruction data C122 and "H" are stored in the first register column in the queue register QR, the address data A123' and "L" are stored in the second register column, the address data A122' and "L" are stored in the third register column, the address data A121' and "L" are stored in the fourth register column, and the instruction data C121 and "H" are stored in the fifth register column.

[0186] At time t223, the execution of the internal operation OP2 is completed. In addition, the Q end operation and the Q execution operation are automatically executed, and the execution of the internal operation OP2' corresponding to the instruction set CmdOP2' stored in the queue register QR is started.

[0187] In addition, Figure 15 In the example of, the Q execution operation is executed at the time when the execution of the internal operation OP2 is completed, but the time when the Q execution operation is executed may also be the time just before the execution of the internal operation OP2 is completed. Such a time may also be a specific time within a period (hereinafter referred to as "recovery period") when the execution of the internal operation OP2 is substantially completed and the wiring voltage in the memory cell array MCA returns to the voltage when the internal operation is not executed, etc.

[0188] [Effect]

[0189] In the semiconductor memory device of the present embodiment, data is stored in the queue register QR according to the signal of the terminal RY / / BY, so there is no need to input the instruction data C811 and C812. In addition, at the time of the Q execution operation, there is no need to input the instruction data C813. Therefore, an instruction set can be input to the queue register QR by inputting the same number of instructions as in the past. Therefore, the operation of the semiconductor memory device can be speeded up.

[0190] In addition, according to the semiconductor memory device of the present embodiment, an instruction set can be input when the signal of the terminal RY / / BY is in the "L" state. Therefore, compared with the case where the instruction set is input after waiting for the signal of the terminal RY / / BY to rise to the "H" state, the operation of the semiconductor memory device can be speeded up.

[0191] [Third Embodiment]

[0192] Next, refer to Figure 16 The semiconductor memory device of the third embodiment will be described. Figure 16 is a timing chart for explaining the operation of the semiconductor memory device of the present embodiment.

[0193] The semiconductor memory device of the third embodiment is basically configured in the same manner as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the first embodiment is configured such that an instruction set can be input to the queue register QR only during the ready period. On the other hand, the semiconductor memory device of the third embodiment is configured such that an instruction set can be input to the queue register QR even during the busy period.

[0194] Hereinafter, the operation will be described according to the Figure 16 timing chart in.

[0195] Figure 16 The operation illustrated is the same as that of before time t217.Figure 15 The illustrated actions are executed in the same manner.

[0196] At time point t311, command data C811 indicating the Q setting action is input. At time points t312 to t316, instruction set CmdOP2' is input. At time point t317, command data C812 indicating the end of the Q action is input.

[0197] At time point t318, the execution of internal action OP2 is completed. Additionally, the signal of terminal RY / / BY will rise from the "L" state to the "H" state accordingly.

[0198] At time point t319, controller die CD inputs the command data C813 indicating the Q execution action as command data D CMD to memory die MD.

[0199] At time point t320, the execution of internal action OP2' starts. Additionally, as the execution of internal action OP2' starts, the signal of terminal RY / / BY drops from the "H" state to the "L" state.

[0200] Furthermore, in this embodiment, when instruction set CmdOP1 indicating a write action is input to queue register QR, similar to the example of Figure 14 data DAT1 corresponding to the write action needs to be additionally input.

[0201] For example, in the example of Figure 17 at time points t331 to t332, instruction set CmdOP1 is input, and at time point t333, the write action (internal action OP1) starts. Additionally, the signal of terminal RY / / BY drops from the "H" state to the "L" state accordingly.

[0202] Moreover, for example, in the example of Figure 17 at time point t334, command data C811 indicating the Q setting action is input. At time points t335 to t336, instruction set CmdOP1' is input. At time point t337, command data C812 indicating the end of the Q action is input. Here, in this embodiment, only command data C111 and C112 corresponding to the command data, and address data A111 to A115 corresponding to the address data in instruction set CmdOP1' are stored in queue register QR, and data DAT2 (data D111, D112, D113...) is not stored in queue register QR.

[0203] Moreover, for example, in the example of Figure 17In the example, the write operation (internal operation OP1) is completed at time point t338, and the signal of terminal RY / / BY rises from the "L" state to the "H" state. Additionally, at time point t339, command data C113 indicating a status read operation is input.

[0204] Additionally, for example, in Figure 17 the example, at time point t340, command data C814 indicating the start of data input is input, and data DAT2 (data D111, D112,...) included in command set CmdOP1' is input at a time point before time points t341 to t343. At time point t343, command data C815 indicating the completion of data input is input.

[0205] Additionally, for example, in Figure 17 the example, at time point t344, command data C813 indicating the execution of a Q operation is input. Subsequently, at time point t345, the write operation (internal operation OP1') starts. Additionally, the signal of terminal RY / / BY subsequently falls from the "H" state to the "L" state.

[0206] [Effect]

[0207] According to the semiconductor memory device of the present embodiment, it is possible to input a command set when the signal of terminal RY / / BY is in the "L" state. Therefore, compared with the case where the command set is input after waiting for the signal of terminal RY / / BY to rise to the "H" state, the operation of the semiconductor memory device can be speeded up.

[0208] [Fourth Embodiment]

[0209] Next, with reference to Figure 18 the semiconductor memory device of the fourth embodiment will be described. Figure 18 is a timing chart for explaining the operation of the semiconductor memory device of the present embodiment.

[0210] The semiconductor memory device of the fourth embodiment is basically configured in the same manner as the semiconductor memory device of the third embodiment. However, the semiconductor memory device of the third embodiment is configured to execute the second internal operation by inputting command data C813 during the ready period after the completion of the first internal operation. On the other hand, the semiconductor memory device of the fourth embodiment is configured to automatically execute the second internal operation after the completion of the first internal operation by inputting command data C842 during the busy period while the first internal operation is being executed.

[0211] Hereinafter, the operation will be described according to the Figure 18 timing chart in.

[0212] Figure 18 The operation exemplified in is the same as that in Figure 13The illustrated operations are similarly performed.

[0213] At time point t401, the controller die CD substitutes instruction data C842 for instruction data C812 as instruction data D CMD and inputs it to the memory die MD. Instruction data C842 is an instruction that indicates an internal operation corresponding to the instruction data being currently input is automatically executed upon completion of the currently executing internal operation.

[0214] At time point t402, the execution of internal operation OP2 is completed. In addition, the Q execution operation is performed accordingly, and the execution of internal operation OP2' is started.

[0215] In addition, Figure 18 in the example of [], the Q execution operation is performed at the time point when the execution of internal operation OP2 is completed, but the time point for performing the Q execution operation may also be a time point immediately before the execution of internal operation OP2 is completed. Such a time point may also be a specific time point during a recovery period or the like.

[0216] [Effect]

[0217] According to the semiconductor memory device of the present embodiment, after the completion of the currently executing internal operation, the operation corresponding to the instruction set stored in the queue register QR can be executed without inputting the instruction data C813 corresponding to the Q execution operation. Therefore, compared with the third embodiment, the operation of the semiconductor memory device can be made faster.

[0218] In addition, for example, by adopting a form in which operations such as Figure 16 illustrated can be executed by instruction discrimination and operations such as Figure 18 illustrated, the operability of the semiconductor memory device can be improved.

[0219] [Fifth Embodiment]

[0220] Next, a semiconductor memory device according to the fifth embodiment will be described with reference to Figure 19 . Figure 19 is a schematic block diagram showing the configuration of the memory die MD' of the present embodiment.

[0221] The semiconductor memory device of the fifth embodiment is basically configured in the same manner as the semiconductor memory device of the first embodiment. However, as Figure 19 shown, the input / output circuit I / O of the fifth embodiment further includes a data signal input terminal X1 in addition to the data signal input / output terminals DQ0 to DQ7 and the trigger signal input / output terminals DQS, / DQS. The data signal input terminal X1 is, for example, by referring to Figure 2 , Figure 3It is implemented by the described pad electrode P. In the fifth embodiment, the data signal input terminal X1 is used when inputting an instruction set to the queue register QR.

[0222] The data signal input terminal X1 is a terminal different from the data signal input / output terminals DQ0 to DQ7, and can accept input during both the ready period and the busy period. The 8-bit data input via the data signal input / output terminals DQ0 to DQ7 is input in parallel from the controller die CD to the memory die MD'. That is, if the signals of the external control terminal / WE or the trigger signal input / output terminals DQS, / DQS are switched once, 8-bit data is input simultaneously. On the other hand, the 8-bit data input via the data signal input terminal X1 is input serially from the controller die CD to the memory die MD. That is, each time the signals of the external control terminal / WE or the trigger signal input / output terminals DQS, / DQS are switched, 1-bit data is input sequentially.

[0223] Figure 20 It is a timing diagram for explaining the operation of the semiconductor memory device of this embodiment.

[0224] Hereinafter, the operation will be described according to Figure 20 the timing diagram in.

[0225] Figure 20 The operation illustrated is executed in the same manner as Figure 15 the operation illustrated before time point t217.

[0226] At time points t501 to t502, the 8-bit data constituting the instruction data C811 is sequentially input in 1-bit units via the data signal input terminal X1.

[0227] Before the time point between time points t503 and t504, the 5×8-bit data constituting the instruction set CmdOP2' and the 1×8-bit data constituting the instruction data C812 are sequentially input in 1-bit units via the data signal input terminal X1. In addition, Figure 20 in the example of, the instruction data C113 indicating a status read operation is input at time point t503.

[0228] At time point t504, the execution of the internal operation OP2 is completed. In addition, as the internal operation OP2 is completed, the signal of the terminal RY / / BY rises from the "L" state to the "H" state.

[0229] At time point t505, the controller die CD inputs the instruction data C813 instructing Q to execute an operation as instruction data D CMD to the memory die MD.

[0230] At time point t506, the internal operation OP2' starts to be executed. Additionally, as the internal operation OP2' starts to be executed, the signal of the terminal RY / / BY drops from the "H" state to the "L" state.

[0231] In addition, in Figure 20 's example, it is assumed that instruction data C811, instruction set CmdOP2', and instruction data C812 are input via the data signal input terminal X1. However, instruction data C842 can be input instead of instruction data C812. Additionally, in this case, the time point when the Q execution operation is performed can be the time point when the execution of the internal operation OP2 is completed, or the time point immediately before the execution of the internal operation OP2 is completed.

[0232] In addition, in Figure 20 's shown example, an example of inputting the instruction set CmdOP2' using instruction data C811, etc. is shown. However, for example, instruction data D CMD input via the data signal input terminal X1 and address data D ADD can also be automatically transferred to the queue register QR.

[0233] [Effect]

[0234] According to the semiconductor memory device of the present embodiment, the instruction set stored in the queue register QR is input via the data signal input terminal X1. Therefore, other operations such as the status read operation can be executed in parallel with the instruction set stored in the queue register QR. Therefore, compared with the first embodiment, the operation of the semiconductor memory device can be made faster.

[0235] [Sixth Embodiment]

[0236] Next, with reference to Figure 21 the semiconductor memory device of the sixth embodiment will be described. Figure 21 is a schematic block diagram showing the configuration of the memory die MD" of the present embodiment.

[0237] The semiconductor memory device of the sixth embodiment is basically configured in the same manner as the semiconductor memory device of the first embodiment. However, as Figure 21 shown, the memory die MD" of the sixth embodiment includes the same as that with reference to Figure 4Two memory cell arrays MCA1 and MCA2 corresponding to the memory cell array MCA described above, two sense amplifier modules SAM1 and SAM2 corresponding to the sense amplifier module SAM, and two cache memories CM1 and CM2 corresponding to the cache memory CM. For example, the memory plane addresses in the two memory cell arrays MCA1 and MCA2 are different from each other. The sense amplifier modules SAM1 and SAM2 are respectively connected to the memory cell arrays MCA1 and MCA2. The cache memories CM1 and CM2 are respectively connected to the sense amplifier modules SAM1 and SAM2. In addition, the input / output circuit I / O of the present embodiment is respectively connected to the cache memories CM1 and CM2.

[0238] Figure 22 It is a timing chart for explaining the operation of the semiconductor memory device according to the embodiment, and a schematic diagram showing the data stored in the cache memories CM1 and CM2 during the execution of the operation.

[0239] As described with reference to Figure 17 In the semiconductor memory device of the third embodiment, when an instruction set CmdOP1' indicating a write operation is input to the queue register QR, only the instruction data C111 and C112 corresponding to the instruction data and the address data A111 to A115 corresponding to the address data in the instruction set CmdOP1' are stored in the queue register QR, and the data DAT2 (data D111, D112, D113...) is not stored in the queue register QR.

[0240] On the other hand, in the semiconductor memory device of the sixth embodiment, when an instruction set CmdOP1' indicating a write operation is input to the queue register QR, it is determined whether the memory plane address included in the instruction set CmdOP1' is the same as the memory plane address corresponding to the currently executing internal operation OP1. If the memory plane addresses are the same, then as described with reference to Figure 17 After the internal operation OP1 is executed, the data DAT2 is additionally input. If the memory plane addresses are different, then as Figure 22 Illustrated, the data DAT2 is stored in the cache memory CM1 or the cache memory CM2 corresponding to the instruction set CmdOP1'.

[0241] Hereinafter, the operation will be described according to the timing chart in Figure 22 The operation illustrated in is the same as the operation illustrated in until time point t339. However, different from

[0242] Figure 22 The operation illustrated in is the same as the operation illustrated in until time point t339. However, different from Figure 17 The operation illustrated in Figure 17Different from the illustrated operations, the data DAT2 input during the period from time point t335 to time point t336 is stored in the cache memory CM2.

[0243] At time point t601, after the internal operation OP1 is completed, instead of inputting the data DAT2, the instruction data C813 indicating to execute the operation of Q is input as the instruction data D CMD .

[0244] At time point t602, the execution of the internal operation OP1' is started. In addition, the signal of the terminal RY / / BY drops from the "H" state to the "L" state accordingly.

[0245] In addition, Figure 22 In, an example in which the instruction set CmdOP1' indicating the write operation is input during the execution of the write operation is described. However, for example, when the instruction set CmdOP1' indicating the write operation is input during the execution of the read operation or the erase operation, such an operation can also be executed. In addition, there is a case where the cache memories CM1 and CM2 are not used in the erase operation. In the case where the instruction set CmdOP1' indicating the write operation is input during the execution of the erase operation, even if the memory plane addresses match, an operation Figure 22 the same as the illustrated operation can be executed.

[0246] In addition, in Figure 22 the illustrated example, an example in which the instruction data C812 indicating the end of the operation of Q is input after the execution of the instruction set CmdOP1' is assumed. However, the instruction data C842 can be input instead of the instruction data C812. In addition, in this case, the time point when Q executes the operation can be the time point when the execution of the internal operation OP1 is completed, or the time point immediately before the execution of the internal operation OP1 is completed.

[0247] In addition, in Figure 22 the illustrated example, an example in which the instruction set CmdOP1' is input using the instruction data C811, etc. is shown. However, for example, in the operation mode described with reference to Figure 15 the operation described with reference to Figure 22 can also be executed. In addition, even in the case where the instruction set CmdOP1' is input using the data signal input terminal X1 as described with reference to Figure 19 the operation described with reference to Figure 22 can also be executed.

[0248] [7th Embodiment]

[0249] Next, a semiconductor memory device according to the 7th embodiment will be described with reference to Figure 23 . Figure 23It is a schematic block diagram showing the configuration of the semiconductor memory device of the present embodiment.

[0250] The semiconductor memory device of the 7th embodiment is basically configured in the same manner as the semiconductor memory device of the 1st embodiment. However, as Figure 23 shown, the semiconductor memory device of the 7th embodiment includes a queue register QR' and queue register control circuits QRCa and QRCb in place of the queue register QR and queue register control circuit QRC with reference to Figure 7 .

[0251] The queue register QR' is connected to the address register ADR via paths S103' and S104', and is connected to the instruction register CMR via paths S105' and S106', thereby performing two-way data input / output with the address register ADR and the instruction register CMR.

[0252] Paths S103', S104', S105', and S106 are basically configured in the same manner as paths S103, S104, S105, and S106 ( Figure 7 ). However, paths S103', S104', S105', and S106 may not include a switching circuit or the like.

[0253] The queue register QR' includes two register circuit groups RG104a and RG104b instead of the one register circuit group RG104 described with reference to Figure 7 . These two register circuit groups RG104a and RG104b are each configured in the same manner as the register circuit group RG104 described with reference to Figure 7 .

[0254] In addition, the queue register QR' includes a switching circuit SWa provided between the register circuit group RG104a and paths S103', S104', S105', and S106'. In addition, the queue register QR' includes a switching circuit SWb provided between the register circuit group RG104b and paths S103', S104', S105', and S106'. The switching circuits SWa and SWb may, for example, also include a configuration corresponding to the switching circuit included in paths S103, S104, S105, and S106 ( Figure 7 ).

[0255] The queue register control circuits QRCa and QRCb are each with reference to Figure 7The described queue register control circuit QRC is configured in the same manner. The queue register control circuits QRCa and QRCb are respectively connected to the instruction register CMR via paths S107a and S107b. In addition, the queue register control circuit QRCa is connected to the register circuit group RG104a and the switch circuit SWa via the path S204a. In addition, the queue register control circuit QRCb is connected to the register circuit group RG104b and the switch circuit SWb via the path S204b. The paths S204a and S204b respectively include configurations corresponding to the paths S201, S202, and S203 described with reference to Figure 7 The paths described.

[0256] Figure 24 and Figure 25 are timing diagrams for explaining the operation of the semiconductor memory device of the present embodiment.

[0257] The semiconductor memory device of the seventh embodiment operates basically in the same manner as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the seventh embodiment can independently execute the Q setting operation, Q end operation, Q execution operation, and Q reset operation for the register circuit group RG104a, and the Q setting operation, Q end operation, Q execution operation, and Q reset operation for the register circuit group RG104b.

[0258] For example, as Figure 24 shown, the semiconductor memory device of the seventh embodiment can execute the Q setting operation for the register circuit group RG104a by inputting the instruction data C8a1, can execute the Q end operation for the register circuit group RG104a by inputting the instruction data C8a2, can execute the Q execution operation for the register circuit group RG104a by inputting the instruction data C8a3, and can execute the Q reset operation for the register circuit group RG104a by inputting the instruction data C8a4.

[0259] In addition, in the Figure 24 example, the instruction data C8a1 is input at the time point t7a1, the instruction set CmdOP0 is input from the time point t7a2 to the time point t7a6, and the instruction data C8a2 is input at the time point t7a7. As a result, the instruction set CmdOP0 is stored in the register circuit group RG104a. In addition, in the Figure 24 example, the instruction data C8a3 is input at the time point t7a8, and thus the read operation (internal operation OP0) is started. In addition, in the Figure 24 example, the instruction data C8a4 is input at the time point t7a9, and thus the instruction set CmdOP0 stored in the register circuit group RG104a is erased.

[0260] In addition, for example, as Figure 25As shown, the semiconductor memory device according to the seventh embodiment can execute the Q setting operation for the register circuit group RG104b by inputting the instruction data C8b1, can execute the Q end operation for the register circuit group RG104b by inputting the instruction data C8b2, can execute the Q execution operation for the register circuit group RG104b by inputting the instruction data C8b3, and can execute the Q reset operation for the register circuit group RG104b by inputting the instruction data C8b4.

[0261] In addition, in Figure 25 's example, the instruction data C8b1 is input at the time point t7b1, the instruction set CmdOP0 is input from the time point t7b2 to the time point t7b6, and the instruction data C8b2 is input at the time point t7b7. As a result, the instruction set CmdOP0 is stored in the register circuit group RG104b. In addition, in Figure 25 's example, the instruction data C8b3 is input at the time point t7b8, and thus the read operation (internal operation OP0) is started. In addition, in Figure 25 's example, the instruction data C8b4 is input at the time point t7b9, and thus the instruction set CmdOP0 stored in the register circuit group RG104b is erased.

[0262] As described above, Figure 24 The actions exemplified can be executed independently of Figure 25 The actions exemplified. Therefore, for example, it is also possible to execute at least one of the actions corresponding to the time points t7b1 to t7b7, the action corresponding to the time point t7b8, and the action corresponding to the time point t7b9 of Figure 24 between the time points t7a7 and t7a8, or between the time points t7a8 and t7a9 of Figure 25 .

[0263] In addition, in Figure 24 and Figure 25 's examples, examples of inputting the instruction set CmdOP0 using the instruction data C8a1, C8b1, etc. are shown. However, for example, it is also possible to execute the actions as described with reference to Figure 15 in the action mode as described with reference to Figure 24 and Figure 25 . In addition, even when the instruction set CmdOP0 is input using the data signal input terminal X1 as described with reference to Figure 19 , it is also possible to execute the actions as shown in Figure 24 and Figure 25 .

[0264] In addition, in Figure 24 and Figure 25In the example shown, examples of the input instruction data C8a3 and C8b3 when performing the Q execution operation on the register banks RG104a and RG104b are shown. However, for example, it is also possible to automatically perform the Q execution operation on the register banks RG104a and RG104b by, for example, an operation mode as described with reference to Figure 15 and an instruction corresponding to the instruction data C842 described with reference to Figure 18 .

[0265] In this case, for example, the first instruction set input during the busy period can also be input to the register bank RG104a. In addition, when the second instruction set has been input before starting the execution of the first internal operation corresponding to the first instruction set, the second instruction set can also be input to the register bank RG104b. In addition, it is also possible to execute the first internal operation corresponding to the first instruction set at the point in time when the internal operation that was in progress when the first instruction set was input has been completed or just before completion. Furthermore, it is also possible to execute the second internal operation corresponding to the second instruction set at the point in time when the first internal operation has been completed or just before completion. In addition, for example, when the third instruction set is further input after the first internal operation has started, the third instruction set can also be input to the register bank RG104a. In addition, it is also possible to execute the third internal operation corresponding to the third instruction set at the point in time when the second internal operation has been completed or just before completion.

[0266] In addition, when performing a write operation in the semiconductor memory device of the present embodiment, it is also possible to execute, for example, the operations described with reference to Figure 21 and Figure 22 .

[0267] [Eighth Embodiment]

[0268] Next, the semiconductor memory device of the eighth embodiment will be described with reference to Figure 26 . Figure 26 is a schematic block diagram showing the configuration of the semiconductor memory device of the present embodiment.

[0269] The semiconductor memory device of the eighth embodiment is basically configured in the same manner as the semiconductor memory device of the first embodiment. However, as Figure 26 shows, the semiconductor memory device of the eighth embodiment includes a queue register QR” instead of the queue register QR with reference to Figure 7 . In addition, the semiconductor memory device of the eighth embodiment includes a queue register selection circuit QRS.

[0270] The queue register QR” is connected to the address register ADR via paths S103' and S104', and is connected to the instruction register CMR via paths S105' and S106', thereby performing bidirectional input / output of data with the address register ADR and the instruction register CMR.

[0271] The queue register QR” includes m (m is a natural number of 2 or more) register circuit groups RG104 1 ~RG104 m instead of the single register circuit group RG104 described in the reference Figure 7 . The m register circuit groups RG104 1 ~RG104 m are each configured in the same manner as the register circuit group RG104 described in the reference Figure 7 .

[0272] In addition, the queue register QR” includes m switch circuits SW 1 ~RG104 m provided between the register circuit groups RG104 and the paths S103', S104', S105', S106'. 1A ~SW mA . The switch circuits SW 1A ~SW mA may, for example, include a configuration corresponding to the switch circuits included in the paths S103, S104, S105, S106 ( Figure 7 ).

[0273] In addition, the queue register QR” includes m switch circuits SW 1 ~RG104 m provided between the register circuit groups RG104 and the path S204. 1B ~SW mB . The switch circuits SW 1B ~SW mB may, for example, include a configuration corresponding to the switch circuits included in the paths S201, S202, S203 described in the reference Figure 7 .

[0274] The queue register selection circuit QRS is connected to the m switch circuits SW 1B ~SW mB via path S205. Path S205 may, for example, include m wires. The queue register selection circuit QRS may, for example, include MOS transistors or the like connected to the m wires.

[0275] Figure 27 is a timing diagram for explaining the operation of the semiconductor memory device of the present embodiment.

[0276] The semiconductor memory device according to the eighth embodiment operates substantially in the same manner as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the eighth embodiment can perform a Q setting operation, a Q end operation, a Q execution operation, and a Q reset operation independently for m register circuit groups RG104 1 ~RG104 m independently.

[0277] For example, as Figure 27 shown, the semiconductor memory device according to the eighth embodiment can perform a Q setting operation on the k-th register circuit group RG104 by inputting instruction data C811 and instruction data C8k1 (k is an integer from 1 to m), and can perform a Q end operation on the k-th register circuit group RG104 by inputting instruction data C812 and instruction data C8k1 k and can perform a Q execution operation on the k-th register circuit group RG104 by inputting instruction data C813 and instruction data C8k1 k and can perform a Q reset operation on the k-th register circuit group RG104 by inputting instruction data C814 and instruction data C8k1 k . k

[0278] The instruction data C8k1 is an instruction specifying which one of the m register circuit groups RG104 1 ~RG104 m to access.

[0279] In addition, in the Figure 27 example, instruction data C811 is input at time point t801, instruction data C8k1 is input at time point t802, an instruction set CmdOP0 is input from time point t803 to time point t807, instruction data C812 is input at time point t808, and instruction data C8k1 is input at time point t809. As a result, the instruction set CmdOP0 is stored in the register circuit group RG104 k . Also, in the Figure 27 example, instruction data C813 is input at time point t810, instruction data C8k1 is input at time point t811, and thus a read operation (internal operation OP0) is started. Also, in the Figure 27 example, instruction data C814 is input at time point t812, instruction data C8k1 is input at time point t813, and thus the instruction set CmdOP0 stored in the register circuit group RG104 k is erased.

[0280] In addition, in the Figure 27In the example shown, at time point t809, instruction data C8k1 was also input when the Q end operation was executed. However, for example, the input of instruction data C8k1 may be omitted when the Q end operation is executed. Additionally, in Figure 27 the example shown, at time point t813, instruction data C8k1 was also input when the Q reset operation was executed. However, for example, the input of instruction data C8k1 may be omitted when the Q reset operation is executed, and the Q reset operation is performed on all register circuit groups RG104 k

[0281] Additionally, in the semiconductor memory device of the eighth embodiment, the number of register circuit groups RG104 that can operate may be specified by setting an operation mode or the like. In this case, for example, m register circuit groups RG104 1 ~RG104 m may all operate, or only one of the register circuit groups may operate, or all register circuit groups may be made inoperative.

[0282] Additionally, in Figure 27 the example shown, an example of inputting an instruction set CmdOP0 using instruction data C811 or the like is shown. However, for example, the semiconductor memory device of the present embodiment may also operate in an operation mode described, for example, with reference to Figure 15 In addition, in the semiconductor memory device of the present embodiment, an instruction set CmdOP0' may be input using, for example, a data signal input terminal X1 described with reference to Figure 19

[0283] Additionally, in Figure 27 the example shown, an example of inputting instruction data C813 and instruction data C8k1 when performing a Q execution operation on register circuit groups RG104 1 ~RG104 m is shown. However, for example, the Q execution operation on register circuit groups RG104 Figure 15 ~RG104 Figure 18 may be automatically executed by an operation mode described with reference to 1 ~RG104 m and an instruction corresponding to instruction data C842 described with reference to

[0284] Additionally, when a write operation is performed in the semiconductor memory device of the present embodiment, operations described, for example, with reference to Figure 21 and Figure 22 may also be executed.

[0285] [Other Embodiments]

[0286] The above embodiments are merely illustrative, and the specific forms may be appropriately changed.​​

[0287] For example, in Figure 2 , 3 an example is shown in which a plurality of memory dies MD and a controller die CD are stacked on a mounting substrate MSB, and the pad electrodes P of the mounting substrate MSB, the plurality of memory dies MD, and the controller die CD are connected via bonding wires B. However, the memory dies MD may also be stacked in a specific area on the mounting substrate MSB, and the controller die CD may be arranged in other areas on the mounting substrate MSB. In addition, instead of stacking all the memory dies MD in one place, the plurality of stacked memory dies MD may be dispersed and stacked in multiple places. In addition, all the memory dies MD may be directly provided on the mounting substrate MSB. In addition, the pad electrodes P of the mounting substrate MSB and the plurality of memory dies MD may also be connected not through the bonding wires B but through other electrodes or wirings, etc. For example, they may be connected through electrodes such as so-called TSV (Through Silicon Via) electrodes that penetrate the substrates of the memory dies MD, etc.

[0288] In addition, for example, in the above example, the memory cell array MCA is configured as a so-called flash memory and includes memory transistors having a charge storage film in the gate insulating film. However, this configuration is merely an illustration, and various configurations may be applied to the memory cell array. For example, the memory cell array may also be a phase change memory including a chalcogenide film such as GeSbTe, and the crystalline state of the chalcogenide film changes according to the write operation. In addition, the memory cell array may also be an MRAM (Magnetoresistive Random Access Memory) including a pair of ferromagnetic films arranged opposite to each other and a tunnel insulating film provided between these ferromagnetic films, and the magnetization direction of the ferromagnetic films changes according to the write operation. In addition, the memory cell array may also be a ReRAM (Resistive Random Access Memory) including a pair of electrodes and a metal oxide, etc. provided between these electrodes, and the electrodes are electrically connected to each other via a filament conductive channel such as an oxygen defect according to the write operation. In addition, the memory cell array may also be a DRAM (Dynamic Random Access Memory) including a capacitor and a transistor, and the capacitor is charged and discharged during the write operation and the read operation. In addition, the memory cell array may also have other configurations.

[0289] In addition, for example, in the above example, the number of bits of the register columns included in the instruction register CMR and the register columns included in the address register is 8 bits, and the number of bits of the multiple register columns included in the queue register QR is 9 bits. That is, the number of bits of the register columns included in the queue register QR is 1 bit more than the number of bits of the register columns included in the instruction register CMR and the register columns included in the address register. However, the number of bits of the register columns included in the queue register QR may also be 2 bits or more more than the number of bits of the register columns included in the instruction register CMR and the register columns included in the address register.

[0290] In addition, for example, in the above example, an example in which an instruction set, user data, etc. are input and output via the 8-bit data signal input / output terminals DQ0 to DQ7 has been described. However, the number of data signal input / output terminals can be appropriately changed.

[0291] Similarly, in the fifth embodiment described with reference to Figure 19 and Figure 20 in addition to the data signal input / output terminals DQ0 to DQ7, the input / output circuit I / O is provided with a data signal input terminal X1 corresponding to 1-bit data. In addition, an instruction set is input to the queue register QR via the data signal input terminal X1 corresponding to 1-bit data. However, for example, in addition to the data signal input / output terminals DQ0 to DQ7, the input / output circuit I / O may also be provided with data signal input terminals corresponding to data of 2 bits or more. In addition, an instruction set may be input to the queue register QR via the data signal input terminals corresponding to data of 2 bits or more.

[0292] [Other]

[0293] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their variations are included in the scope or gist of the invention, and are included in the invention described in the claims and its equivalents.

[0294] [Description of Symbols]

[0295] MC: Memory Cell

[0296] MCA: Memory Cell Array

[0297] PC: Peripheral Circuit

[0298] ADR: Address Register

[0299] CMR: Instruction Register

[0300] QR: Queue Register.

Claims

1. A semiconductor memory device includes: A memory cell array including a plurality of memory cells; and A peripheral circuit connected to the memory cell array, which inputs and outputs user data as an instruction set including instruction data and address data is input. The peripheral circuit Includes: An instruction register having an n-bit first register column capable of storing n (n is a natural number) bits of data constituting the instruction data; An address register having an n-bit second register column capable of storing n bits of data constituting the address data; and A queue register: Having a plurality of third register columns capable of storing at least n + 1 bits of data, The third register column: capable of storing n bits of data constituting the instruction data and n bits of data constituting the address data, and capable of storing 1 bit of data indicating whether the stored n bits of data are the address data or the instruction data.

2. The semiconductor memory device according to claim 1, wherein The third register column includes: A first register circuit connected to the first register column and the second register column, capable of storing n bits of data; and A second register circuit capable of storing at least 1 bit of data.

3. The semiconductor memory device according to claim 2 includes: A first switch circuit connected between the first register circuit and the first register column; and A second switch circuit connected between the first register circuit and the second register column; When transferring the data stored in the first register circuit to the first register column or the second register column, When the first information is stored in the second register circuit, the first switch circuit is turned on and the second switch circuit is turned off, When the second information is stored in the second register circuit, the first switch circuit is turned off and the second switch circuit is turned on.

4. The semiconductor memory device according to claim 3 includes: A third switch circuit connected between the first register circuit and the first register column; and A fourth switch circuit connected between the first register circuit and the second register column; When n bits of data are input to the first register circuit, When the third switch circuit is turned on and the fourth switch circuit is turned off, the first information is input to the second register circuit, When the third switch circuit is turned off and the fourth switch circuit is turned on, the second information is input to the second register circuit.

5. The semiconductor memory device according to claim 4, wherein The third switch circuit also functions as the first switch circuit, The fourth switch circuit also functions as the second switch circuit.

6. The semiconductor memory device according to claim 1 is configured to With the input of the first instruction data, be able to execute internal operations corresponding to the instruction set stored in the queue register without erasing the instruction set stored in the queue register.

7. The semiconductor memory device according to claim 1, configured to be able to save an instruction set input during the execution of the first internal operation in the queue register, and configured to be able to automatically execute a second internal operation corresponding to the instruction set saved in the queue register after the execution of the first internal operation.

8. The semiconductor memory device according to any one of claims 1 to 7, wherein the instruction set input during the period from inputting the second instruction data to inputting the third instruction data is input to the queue register.

9. The semiconductor memory device according to any one of claims 1 to 7, wherein the instruction set input during the execution of the first internal operation is automatically input to the queue register.

10. The semiconductor memory device according to any one of claims 1 to 7, comprising: n first data input terminals capable of being used to input the instruction set, and a second data input terminal capable of being used to input the instruction set, and configured to be able to input an instruction set to the queue register via the second data input terminal.

11. The semiconductor memory device according to any one of claims 1 to 7, wherein the instruction set saved in the queue register is erased as the fourth instruction data is input.

12. The semiconductor memory device according to any one of claims 1 to 7, comprising: a first memory cell array and a second memory cell array; a first cache memory connected to the first memory cell array; and a second cache memory connected to the second memory cell array; and when an instruction set including address data corresponding to the second memory cell array is input during the execution of the first internal operation on the first memory cell array and the input instruction set includes the user data, the user data included in the instruction set is input to the second cache memory.

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