Semiconductor structure and method of manufacturing the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2021-08-31
- Publication Date
- 2026-05-29
Smart Images
Figure CN113939905B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] In the back-end of line (BEOL) process of semiconductor manufacturing, the trenches of the upper metal lines are usually over-etched to ensure that the upper metal lines are electrically connected to the corresponding lower metal lines.
[0003] However, as the critical dimension (CD) in semiconductor processes becomes smaller and smaller, the size of metal lines and the distance between adjacent metal lines in the same layer also become smaller and smaller. During the etching of trenches for upper metal lines, the position of the trenches and the corresponding lower metal lines are prone to deviation. This will cause the air gap between adjacent lower metal lines to be destroyed, thereby affecting the reliability of the semiconductor structure.
[0004] Technical issues
[0005] This invention provides a semiconductor structure and its fabrication method, which effectively solves the problem that when the position of the trench and the corresponding lower metal line deviates during the etching of the trench of the upper metal line, the air gap between adjacent lower metal lines is destroyed, thereby affecting the reliability of the semiconductor structure.
[0006] Technical solutions
[0007] In one aspect, the present invention provides a semiconductor structure, the semiconductor structure comprising:
[0008] Base;
[0009] A first metal layer is disposed on the substrate and includes a plurality of first metal lines arranged at intervals.
[0010] A hollow dielectric layer is disposed on the substrate and located between the first metal lines; and,
[0011] A medium landing layer is disposed between the first metal layer and the hollow medium layer, and between a portion of the substrate and the hollow medium layer.
[0012] More preferably, the semiconductor structure further includes an interlayer dielectric layer, which covers the first metal layer, the hollow dielectric layer, and the dielectric landing layer, and the interlayer dielectric layer is made of the same material as the hollow dielectric layer.
[0013] More preferably, the interlayer medium layer is made of a different material than the medium landing layer.
[0014] More preferably, the medium landing layer includes a first medium landing layer and a second medium landing layer, the second medium landing layer being located above the first medium landing layer. In the environment of etching the interlayer medium layer, the interlayer medium layer and the first medium landing layer have a first etching selectivity ratio, the interlayer medium layer and the second medium landing layer have a second etching selectivity ratio, and the first etching selectivity ratio is less than the second etching selectivity ratio.
[0015] More preferably, the semiconductor structure further includes a second metal layer, the second metal layer including a plurality of second metal vias, the plurality of second metal vias passing through the interlayer dielectric layer and the dielectric landing layer and connected to the corresponding first metal line.
[0016] More preferably, the hollow medium layer has a first step coverage rate, the medium landing layer has a second step coverage rate, and the first step coverage rate is less than the second step coverage rate.
[0017] More preferably, the first metal wire has a first end in contact with the substrate and a second end in contact with the medium landing layer, the first end having a first cross-sectional area and the second end having a second cross-sectional area, the first cross-sectional area being smaller than the second cross-sectional area.
[0018] On the other hand, the present invention also provides a method for preparing a semiconductor structure, the method comprising:
[0019] Provide a base;
[0020] A first metal layer is formed on the substrate, the first metal layer comprising a plurality of first metal lines arranged at intervals;
[0021] A medium landing layer is formed on the first metal layer and a portion of the substrate;
[0022] A hollow dielectric layer is formed on the dielectric landing layer, and the hollow dielectric layer is located between the first metal lines.
[0023] Further preferably, after the step of forming a hollow dielectric layer on the dielectric landing layer, and the hollow dielectric layer being located between the first metal lines, the method further includes:
[0024] An interlayer medium layer is formed on the hollow medium layer and part of the medium landing layer;
[0025] The interlayer medium layer and the hollow medium layer are made of the same material. The hollow medium layer has a first step coverage rate, and the medium landing layer has a second step coverage rate. The first step coverage rate is less than the second step coverage rate.
[0026] More preferably, the dielectric landing layer includes a first dielectric landing layer and a second dielectric landing layer, and the step of forming the dielectric landing layer on the first metal layer and a portion of the substrate specifically includes:
[0027] A first dielectric landing layer and a second dielectric landing layer are sequentially formed on the first metal layer and a portion of the substrate;
[0028] In the environment of etching the interlayer dielectric layer, the interlayer dielectric layer and the first dielectric landing layer have a first etching selectivity ratio, and the interlayer dielectric layer and the second dielectric landing layer have a second etching selectivity ratio, wherein the first etching selectivity ratio is less than the second etching selectivity ratio.
[0029] More preferably, after the step of forming an interlayer dielectric layer on the hollow dielectric layer and a portion of the dielectric landing layer, the method further includes:
[0030] The interlayer dielectric layer and the dielectric landing layer are etched to form multiple trenches, and the multiple trenches expose a portion of the first metal layer;
[0031] Metal material is deposited in the plurality of trenches to form a second metal layer including a plurality of second metal through holes.
[0032] Beneficial effects
[0033] This invention provides a semiconductor structure comprising: a substrate; a first metal layer disposed on the substrate, the first metal layer including a plurality of first metal lines arranged at intervals; a hollow dielectric layer disposed on the substrate, the hollow dielectric layer being located between the first metal lines; and a dielectric landing layer disposed between the first metal layer and the hollow dielectric layer, and also between a portion of the substrate and the hollow dielectric layer. The semiconductor structure provided by this invention effectively protects the hollow dielectric layer located between the first metal lines of the first metal layer by providing a dielectric landing layer between the first metal layer and the hollow dielectric layer, thereby improving the reliability of the semiconductor structure. Attached Figure Description
[0034] To more clearly illustrate the technical solutions of the present invention, the drawings used in the description of the various embodiments made according to the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0035] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure provided in the first embodiment of the present invention.
[0036] Figure 2 This is a schematic flowchart of a method for fabricating a semiconductor structure according to a first embodiment of the present invention.
[0037] Figures 3a to 3d This is a schematic diagram of the process flow of the semiconductor structure fabrication method provided in the first embodiment of the present invention.
[0038] Figure 4 This is a cross-sectional schematic diagram of a semiconductor structure provided in the second embodiment of the present invention.
[0039] Figure 5 This is a schematic flowchart of a method for fabricating a semiconductor structure according to a second embodiment of the present invention.
[0040] Figures 6a to 6e This is a schematic diagram of the process flow of the semiconductor structure fabrication method provided by the second embodiment of the present invention.
[0041] Embodiments of the present invention
[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0043] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0044] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0045] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0046] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.
[0047] This invention addresses the problem in existing semiconductor processes where, during the etching of trenches for upper metal lines, a positional deviation between the trenches and the corresponding lower metal lines can disrupt the air gaps between adjacent lower metal lines, thereby affecting the reliability of the semiconductor structure. Embodiments based on this invention are used to solve this problem.
[0048] Please see Figure 1 , Figure 1 A schematic diagram of the semiconductor structure 100 provided according to the first embodiment of the present invention is shown. The components of the first embodiment of the present invention and their relative positions can be seen intuitively from the figure.
[0049] like Figure 1 As shown, the semiconductor structure 100 includes a substrate 110, a first metal layer 120, a hollow dielectric layer 130, and a dielectric landing layer 140.
[0050] The substrate 110 includes a substrate 111 and a dielectric layer 112 located on the substrate 111. The material of the substrate 111 can be single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC), or silicon-on-insulator (SOI), germanium-on-insulator (GOI), or other materials, such as gallium arsenide and other III-V compounds.
[0051] A first metal layer 120 is disposed on a substrate 110 and includes a plurality of first metal lines 121, which are arranged at intervals. An exemplary material for the first metal lines 121 is tungsten (W).
[0052] A hollow dielectric layer 130 is disposed on the substrate 110 and located between adjacent first metal lines 121. It should be noted that the hollow dielectric layer 130 can also be referred to as an air gap. Since the dielectric constant of air is much lower than that of oxide, a hollow dielectric layer 130 is usually used instead of filling the spaces between the first metal lines 121 with oxide, thereby improving the RC delay (R: resistance; C: capacitance) between the metal lines.
[0053] A dielectric landing layer 140 is disposed between the first metal layer 120 and the hollow dielectric layer 130, and also between a portion of the substrate 110 and the hollow dielectric layer 130. It should be noted that the dielectric landing layer 140 serves as a protective layer for the hollow dielectric layer 130 between adjacent first metal lines 121. When etching the metal via trench above the first metal layer 120, alignment misalignment occurs, causing only a portion of the metal via trench corresponding to the first metal line 121 to fall above the first metal line 121. For example… Figure 1 The second metal via 161' shown in this embodiment can ensure that another part of the second metal via 161' falls on the dielectric landing layer 140 located between adjacent first metal lines 121 without damaging the hollow dielectric layer 130 located between adjacent first metal lines 121, thereby ensuring the reliability of the semiconductor structure 100.
[0054] It should be noted that in this embodiment, the hollow dielectric layer 130 has a first step coverage rate, and the dielectric landing layer 140 has a second step coverage rate, wherein the first step coverage rate is less than the second step coverage rate. That is, because the dielectric landing layer 140 has a better step coverage rate, it is easier to deposit on the top and sides of the first metal line 121, which is beneficial for protecting the hollow dielectric layer 130; while because the hollow dielectric layer 130 has a poorer step coverage rate, the material of the hollow dielectric layer 130 is less likely to be deposited between adjacent first metal lines 121, which is beneficial for forming the hollow structure (i.e., air gap) of the hollow dielectric layer 130.
[0055] Furthermore, in a possible variation according to the present invention, the first metal wire has a first end in contact with the substrate and a second end in contact with the dielectric landing layer. The first end has a first cross-sectional area, and the second end has a second cross-sectional area, wherein the first cross-sectional area is smaller than the second cross-sectional area. That is, in this variation, the first metal wire has a structure that is wider at the top and narrower at the bottom. Such a structure makes it difficult for the material of the hollow dielectric layer 130 to flow between adjacent first metal wires 121 when forming the hollow dielectric layer 130, thereby facilitating the formation of the hollow structure (i.e., air gap) of the hollow dielectric layer 130.
[0056] For further information, please refer to [link / reference]. Figure 1 In this embodiment, the semiconductor structure 100 further includes an interlayer dielectric layer 150 and a second metal layer 160.
[0057] The interlayer dielectric layer 150 covers the first metal layer 120, the hollow dielectric layer 130, and the dielectric landing layer 140. In this embodiment, the interlayer dielectric layer 150 and the hollow dielectric layer 130 are made of the same material. It should be noted that in other variations of this invention, the interlayer dielectric layer may be made of other materials with better step coverage.
[0058] The second metal layer 160 includes a plurality of second metal vias 161, which pass through the interlayer dielectric layer 150 and the dielectric landing layer 140 and are connected to the corresponding first metal lines 121.
[0059] It should be noted that in this embodiment, the materials of the interlayer dielectric layer 150 and the dielectric landing layer 140 are different. Therefore, under the same etching conditions, the etching speed of the interlayer dielectric layer 150 is faster than that of the dielectric landing layer 140. That is, the etching selectivity ratio of the interlayer dielectric layer 150 to the dielectric landing layer 140 is greater than 1. For example, in a possible variation of the present invention, the first metal line has the structure described above, which is wider at the top and narrower at the bottom (that is, the first metal line is an inverted trapezoid, and the hollow dielectric layer between adjacent first metal lines is a regular trapezoid that is narrower at the top and wider at the bottom). When the trench of the second metal via is over-etched to ensure that the second metal via is connected to the corresponding first metal line, and the alignment of the second metal via and the corresponding first metal line is deviated, since the environment of etching the interlayer dielectric layer is being etched, the etching rate will slow down when the etching solution etches to the dielectric landing layer. This prevents the trench of the second metal via from sinking too much into the dielectric landing layer. Furthermore, due to the inverted trapezoidal structure of the first metal line, the trench of the second metal via will not come into contact with the hollow dielectric layer between the first metal lines, thereby achieving the purpose of protecting the hollow dielectric layer.
[0060] Specifically, the materials of the dielectric landing layer 140 include, but are not limited to, silicon nitride (SiN), silicon carbonitride (SiCN), silicon (Si), and other carbon-containing substances.
[0061] Please see Figure 2 as well as Figures 3a to 3d , Figure 2 This is a schematic flowchart of the method for fabricating the semiconductor structure 100 provided in the first embodiment of the present invention. Figures 3a to 3d This is a schematic diagram of the process flow for fabricating the semiconductor structure 100 provided in the first embodiment of the present invention, as shown below. Figure 2 As shown, the method for fabricating the semiconductor structure 100 includes:
[0062] Substrate provision step S101: Provide substrate 110;
[0063] First metal layer formation step S102: A first metal layer 120 is formed on the substrate 110. The first metal layer 120 includes a plurality of first metal lines 121, which are arranged at intervals.
[0064] Medium landing layer formation step S103: A medium landing layer 140 is formed on the first metal layer 120 and a portion of the substrate 110;
[0065] Hollow dielectric layer formation step S104: A hollow dielectric layer 130 is formed on the dielectric landing layer 140, and the hollow dielectric layer 130 is located between the first metal lines 121;
[0066] Interlayer medium layer formation step S105: An interlayer medium layer 150 is formed on the hollow medium layer 130 and part of the medium landing layer 140;
[0067] Trench etching step S106: Etching the interlayer dielectric layer 150 and the dielectric landing layer 140 to form multiple trenches, with the multiple trenches exposing portions of the first metal layer 120;
[0068] Second metal layer formation step S107: Deposit metal material in multiple trenches to form a second metal layer 160 including multiple second metal vias 161.
[0069] This invention provides a semiconductor structure 100, comprising: a substrate 110; a first metal layer 120 disposed on the substrate 110, the first metal layer 120 including a plurality of first metal lines 121 arranged at intervals; a hollow dielectric layer 130 disposed on the substrate 110, the hollow dielectric layer 130 being located between the first metal lines 121; and a dielectric landing layer 140 disposed between the first metal layer 120 and the hollow dielectric layer 130, and also between a portion of the substrate 110 and the hollow dielectric layer 130. The semiconductor structure 100 provided by this invention effectively protects the hollow dielectric layer 130 located between the first metal lines 121 of the first metal layer 120 by disposing of the dielectric landing layer 140 between the first metal layer 120 and the hollow dielectric layer 130, thereby improving the reliability of the semiconductor structure 100.
[0070] Please see Figure 4 , Figure 4 A schematic diagram of the semiconductor structure 200 provided according to the second embodiment of the present invention is shown. The components of the second embodiment of the present invention and their relative positions can be seen intuitively from the figure.
[0071] like Figure 4As shown, the second embodiment has a structure that is largely the same as the first embodiment. Specifically, the substrate 210 (including a substrate 211 and a dielectric layer 212) in the second embodiment has the same function and location as the substrate 110 (including a substrate 111 and a dielectric layer 112) in the first embodiment; the first metal layer 220 (including multiple first metal lines 221) in the second embodiment has the same function and location as the first metal layer 120 (including multiple first metal lines 121) in the first embodiment; the hollow dielectric layer 230 in the second embodiment has the same function and location as the hollow dielectric layer 130 in the first embodiment; the dielectric landing layer 240 in the second embodiment has the same function as the dielectric landing layer 140 in the first embodiment; the interlayer dielectric layer 250 in the second embodiment has the same function and location as the interlayer dielectric layer 150 in the first embodiment; and the second metal layer 260 in the second embodiment has the same function and location as the second metal layer 160 in the first embodiment.
[0072] The difference lies in that, in this embodiment, the dielectric landing layer 240 includes a first dielectric landing layer 241 and a second dielectric landing layer 242, with the second dielectric landing layer 242 located above the first dielectric landing layer 241. Under the environment of etching the interlayer dielectric layer 250, the interlayer dielectric layer 250 and the first dielectric landing layer 241 have a first etching selectivity ratio, and the interlayer dielectric layer 250 and the second dielectric landing layer 242 have a second etching selectivity ratio, wherein the first etching selectivity ratio is less than the second etching selectivity ratio. That is, under the same etching conditions, the etching rate of the interlayer dielectric layer 150 is faster than the etching rate of the first dielectric landing layer 241, and the etching rate of the first dielectric landing layer 241 is faster than the etching rate of the second dielectric landing layer 242.
[0073] It is readily understood that, since the dielectric landing layer 240 is a multi-layered structure in this embodiment, it can more effectively protect the hollow dielectric layer 230. Further, for example, in a possible variation of the present invention, the first metal line has the structure described above as wider at the top and narrower at the bottom (i.e., the first metal line is an inverted trapezoid, and the hollow dielectric layer between adjacent first metal lines is a regular trapezoid with a narrow top and a wide bottom). When the trench of the second metal via is over-etched to ensure connection between the second metal via and the corresponding first metal line, and the alignment of the second metal via and the corresponding first metal line deviates, since this is in the environment of etching the interlayer dielectric layer, the etching rate slows down when the etching solution etches to the dielectric landing layer. This prevents the trench of the second metal via from sinking excessively into the dielectric landing layer. Furthermore, due to the inverted trapezoidal structure of the first metal line, the trench of the second metal via will not come into contact with the hollow dielectric layer between the first metal lines, thereby achieving the purpose of protecting the hollow dielectric layer. Furthermore, in this embodiment, the etching rate of the trench in the second metal via is gradually reduced, and there will be no sudden change in the etching rate. Moreover, the etching rate of the trench in the second metal via can be reduced to a greater extent.
[0074] Please see Figure 5 as well as Figures 6a to 6e , Figure 5 This is a schematic flowchart of the method for fabricating the semiconductor structure 200 provided in the second embodiment of the present invention. Figures 6a to 6e This is a schematic diagram of the process flow for fabricating the semiconductor structure 200 provided in the second embodiment of the present invention, as shown below. Figure 5 As shown, the method for fabricating the semiconductor structure 200 includes:
[0075] Substrate provision step S201: Provide substrate 210;
[0076] First metal layer formation step S202: A first metal layer 220 is formed on the substrate 210. The first metal layer 220 includes a plurality of first metal lines 221, which are arranged at intervals.
[0077] Medium landing layer formation step S203: A first medium landing layer 241 and a second medium landing layer 242 are sequentially formed on the first metal layer 220 and a portion of the substrate 210;
[0078] Hollow dielectric layer formation step S204: A hollow dielectric layer 230 is formed on the second dielectric landing layer 242, and the hollow dielectric layer 230 is located between the first metal lines 221;
[0079] Interlayer medium layer formation step S205: An interlayer medium layer 250 is formed on the hollow medium layer 230 and part of the medium landing layer 240;
[0080] Trench etching step S206: Etching the interlayer dielectric layer 250 and the dielectric landing layer 240 to form multiple trenches, with the multiple trenches exposing portions of the first metal layer 220;
[0081] Second metal layer formation step S207: Deposit metal material in multiple trenches to form a second metal layer 260 including multiple second metal vias 261.
[0082] This invention provides a semiconductor structure 200, comprising: a substrate 210; a first metal layer 220 disposed on the substrate 210, the first metal layer 220 including a plurality of first metal lines 221 arranged at intervals; a hollow dielectric layer 230 disposed on the substrate 210, the hollow dielectric layer 230 being located between the first metal lines 221; and a dielectric landing layer 240 disposed between the first metal layer 220 and the hollow dielectric layer 230, and between a portion of the substrate 210 and the hollow dielectric layer 230. The dielectric landing layer 240 includes a first dielectric landing layer 241 and a second dielectric landing layer 242 made of different materials. The semiconductor structure 200 provided by this invention, by disposing of the dielectric landing layer 240 between the first metal layer 220 and the hollow dielectric layer 230, effectively protects the hollow dielectric layer 230 located between the first metal lines 221 of the first metal layer 220, thereby improving the reliability of the semiconductor structure 200.
[0083] In addition to the embodiments described above, the present invention may have other implementations. All technical solutions formed by equivalent substitutions or equivalent replacements fall within the protection scope claimed by the present invention.
[0084] In summary, although the preferred embodiments of the present invention have been disclosed above, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.
Claims
1. A semiconductor structure, wherein, The semiconductor structure includes: Base; A first metal layer is disposed on the substrate and includes a plurality of first metal lines arranged at intervals. A hollow dielectric layer is disposed on the substrate and located between the first metal lines; and, A medium landing layer is disposed between the first metal layer and the hollow dielectric layer, and between a portion of the substrate and the hollow dielectric layer; An interlayer dielectric layer covers the first metal layer, the hollow dielectric layer, and the dielectric landing layer, and the interlayer dielectric layer is made of the same material as the hollow dielectric layer; The medium landing layer includes a first medium landing layer and a second medium landing layer. The second medium landing layer is located above the first medium landing layer. In the environment of etching the interlayer medium layer, the interlayer medium layer and the first medium landing layer have a first etching selectivity ratio, and the interlayer medium layer and the second medium landing layer have a second etching selectivity ratio. The first etching selectivity ratio is less than the second etching selectivity ratio.
2. The semiconductor structure according to claim 1, wherein, The interlayer medium layer is made of a different material than the medium landing layer.
3. The semiconductor structure according to claim 1, wherein, The semiconductor structure further includes a second metal layer, which includes a plurality of second metal vias that pass through the interlayer dielectric layer and the dielectric landing layer and are connected to the corresponding first metal lines.
4. The semiconductor structure according to claim 1, wherein, The hollow medium layer has a first step coverage rate, and the medium landing layer has a second step coverage rate, wherein the first step coverage rate is less than the second step coverage rate.
5. The semiconductor structure according to claim 1, wherein, The first metal wire has a first end in contact with the substrate and a second end in contact with the medium landing layer. The first end has a first cross-sectional area, and the second end has a second cross-sectional area. The first cross-sectional area is smaller than the second cross-sectional area.
6. A method for fabricating a semiconductor structure, wherein, The preparation method includes: Provide a base; A first metal layer is formed on the substrate, the first metal layer comprising a plurality of first metal lines arranged at intervals; A medium landing layer is formed on the first metal layer and a portion of the substrate; A hollow dielectric layer is formed on the dielectric landing layer, and the hollow dielectric layer is located between the first metal lines; An interlayer medium layer is formed on the hollow medium layer and part of the medium landing layer; the interlayer medium layer is made of the same material as the hollow medium layer. The dielectric landing layer includes a first dielectric landing layer and a second dielectric landing layer. The step of forming the dielectric landing layer on the first metal layer and a portion of the substrate specifically includes: A first dielectric landing layer and a second dielectric landing layer are sequentially formed on the first metal layer and a portion of the substrate; wherein, in an environment where the interlayer dielectric layer is etched, the interlayer dielectric layer and the first dielectric landing layer have a first etching selectivity ratio, the interlayer dielectric layer and the second dielectric landing layer have a second etching selectivity ratio, and the first etching selectivity ratio is less than the second etching selectivity ratio.
7. The preparation method according to claim 6, wherein, The hollow medium layer has a first step coverage rate, and the medium landing layer has a second step coverage rate, wherein the first step coverage rate is less than the second step coverage rate.
8. The preparation method according to claim 6, wherein, Following the step of forming an interlayer medium layer on the hollow medium layer and a portion of the medium landing layer, the method further includes: The interlayer dielectric layer and the dielectric landing layer are etched to form multiple trenches, and the multiple trenches expose a portion of the first metal layer; Metal material is deposited in the plurality of trenches to form a second metal layer including a plurality of second metal through holes.