A semiconductor structure
By setting flow channels in the peripheral area of the semiconductor wafer and adding flow grooves or turbulence pillars in the transition area, the problem of uneven coating caused by turbulent photoresist flow is solved, and a more uniform coating effect is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WUHAN CHUXING TECH CO LTD
- Filing Date
- 2024-12-19
- Publication Date
- 2026-06-23
AI Technical Summary
In the spin coating process, the turbulence caused by the height difference at the edges of the die during photoresist flow leads to poor coating uniformity and radial stripe defects.
By setting flow channels in the peripheral area of the semiconductor wafer and/or adding flow channels or turbulence pillars in the transition and dicing areas, the photoresist can be diverted through the flow channels and turbulence pillars, reducing the degree of turbulence and improving the uniformity of photoresist coating.
By designing flow channels and turbulence pillars, the disturbance of photoresist flowing through the corners is reduced, resulting in smoother flow and more uniform coating, and reducing radial stripe defects.
Smart Images
Figure CN122269767A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure. Background Technology
[0002] In the spin coating process, as the photoresist flows outward from the center of the wafer, when it encounters the edges of the die on the semiconductor wafer, the flow is disturbed due to the height difference, generating strong turbulence. Especially in the diagonal direction of the die, a turbulent characteristic similar to the fluid being "split" by the edge of the die is generated. Obvious radial stripes can be seen from a macroscopic perspective. The essence is that the strong turbulence generated when the photoresist flows through the edge of the die leads to poor coating uniformity. Summary of the Invention
[0003] This invention discloses a semiconductor structure for reducing the disturbance encountered by photoresist when it flows through the corners of the effective area, making the flow smoother and the coating more uniform, thereby reducing radial stripe defects.
[0004] To achieve the above objectives, the present invention provides the following technical solution:
[0005] A semiconductor structure includes: an effective region and a peripheral region surrounding the effective region;
[0006] The effective area includes multiple first corner areas; the peripheral area includes multiple peripheral corner areas, and one of the peripheral corner areas partially encloses the outside of one of the first corner areas.
[0007] At least one flow channel is formed in each of the peripheral corner areas of the peripheral region, and the flow channel extends along the direction from the peripheral region to the effective region.
[0008] In spin coating, as photoresist flows outward from the center of a semiconductor wafer, it first contacts the peripheral region outside the effective region, and then contacts the effective region surrounded by this peripheral region. This peripheral region has peripheral corner regions that correspond one-to-one with the first corner regions within the effective region. In other words, when the photoresist flows through these corresponding peripheral corner regions and first corner regions, it first encounters the peripheral corner regions of the peripheral region before encountering the first corner regions of the effective region. Based on this, the peripheral region forms flow channels in all or all peripheral corner regions. As the photoresist flows through the peripheral region, these channels divert the photoresist, thereby reducing turbulence and improving coating uniformity.
[0009] In some embodiments, there are multiple flow channels, and the multiple flow channels are arranged at intervals around the effective area.
[0010] In some embodiments, the peripheral region includes a cutting channel region and a transition region, the transition region surrounding the outside of the effective region, the cutting channel region surrounding the outside of the transition region, and the flow channel being formed in the cutting channel region and / or the transition region.
[0011] In some embodiments, the transition region includes a plurality of second corner regions, the second corner regions partially enclosing the outside of the first corner region, and the outer contour of the second corner region is arc-shaped.
[0012] In some embodiments, the flow guiding channel is formed in the transition region;
[0013] The semiconductor structure includes a substrate and an auxiliary stack formed on the substrate; the auxiliary stack includes at least one film layer;
[0014] The orthographic projection of the auxiliary layer onto the substrate is located within the transition region;
[0015] At least one of the membrane layers is formed with a flow channel having a flow channel extending along the direction from the transition region to the effective region.
[0016] In some embodiments, the outer contour of the orthographic projection of the auxiliary stack on the substrate is located inside the outer contour of the transition region;
[0017] The auxiliary stack includes multiple film layers, including a first film layer and a second film layer. The first film layer is located on the side of the second film layer closer to the substrate. The outer contour of the orthographic projection of the second film layer on the substrate is located inside the outer contour of the orthographic projection of the first film layer on the substrate.
[0018] In some embodiments, the semiconductor structure includes a substrate and a plurality of turbulence pillars formed on the substrate;
[0019] The orthographic projections of the plurality of turbulence-disrupting columns on the substrate are located inside the peripheral region and are arranged around the effective region;
[0020] There is a gap between two adjacent turbulence columns to form the flow channel.
[0021] In some embodiments, the plurality of turbulence columns include a plurality of flow guide groups, one of the flow guide groups being disposed outside a first corner region;
[0022] Each of the flow guide groups includes a plurality of spaced-apart turbulence columns.
[0023] In some embodiments, the plurality of spoilers include at least one annular assembly, each annular assembly including a plurality of spoilers spaced apart around the effective area.
[0024] In some embodiments, the orthographic projection of the turbulence column onto the substrate includes any one of a rectangle, square, circle, ellipse, and irregular polygon. Attached Figure Description
[0025] Figure 1 This is a schematic diagram of the structure of a semiconductor wafer;
[0026] Figure 2 A schematic diagram of a semiconductor structure provided in an embodiment of the present invention;
[0027] Figure 3 for Figure 2 A structural diagram of one of the outer corner regions;
[0028] Figure 4 This is a schematic diagram of another semiconductor wafer structure provided in an embodiment of the present invention;
[0029] Figure 5 This is a schematic diagram of the structure of a bare die provided in an embodiment of the present invention;
[0030] Figure 6 This is an AA section view of the bare film;
[0031] Figure 7 This is a schematic diagram of another bare die and dicing area provided in an embodiment of the present invention;
[0032] Figure 8 This is a schematic diagram of another bare die and dicing area provided in an embodiment of the present invention;
[0033] Figure 9 This is a schematic diagram of another bare die and dicing area provided in an embodiment of the present invention;
[0034] Figure 10 This is a schematic diagram of another bare die and dicing area provided in an embodiment of the present invention;
[0035] Figure 11 This is a schematic diagram of another bare die and dicing area provided in an embodiment of the present invention;
[0036] Figure 12 This is a schematic diagram of another bare die and dicing area provided in an embodiment of the present invention;
[0037] Figure 13 This is a schematic diagram of a flow guide groove in the transition area provided in an embodiment of the present invention;
[0038] Figure 14 Another AA cross-sectional view of a bare wafer provided in an embodiment of the present invention;
[0039] Figure 15 This is a schematic diagram of another type of guide channel in the transition area provided in an embodiment of the present invention;
[0040] Figure 16 This is a schematic diagram of another type of guide channel in the transition area provided in an embodiment of the present invention;
[0041] Figure 17 This is a schematic diagram of another bare die structure provided in an embodiment of the present invention;
[0042] Figure 18 This is a schematic diagram of another bare die structure provided in an embodiment of the present invention;
[0043] Figure 19 for Figure 18 Mid-BB cross-section;
[0044] Figure 20 This is a schematic diagram of another bare die and dicing area provided in an embodiment of the present invention;
[0045] Figure 21 This is a schematic diagram of another bare die and dicing area provided in an embodiment of the present invention;
[0046] Figure 22 This is a schematic diagram of another bare die and dicing area provided in an embodiment of the present invention;
[0047] Figure 23 for Figure 22 C-section diagram;
[0048] Figure 24 A process flow diagram for preparing a turbulence column is provided in an embodiment of the present invention;
[0049] Figure 25 A flowchart illustrating the fabrication process of another turbulence-disrupting column provided in an embodiment of the present invention;
[0050] Figure 26 A flowchart illustrating the fabrication process of another turbulence-disrupting column provided in an embodiment of the present invention;
[0051] Figure 27 A flowchart illustrating the fabrication process of another turbulence-disrupting column provided in an embodiment of the present invention;
[0052] Icons: 100 - Effective area; 200 - Peripheral area; 300 - Flow channel; 101 - First corner area; 210 - Transition area; 220 - Cutting channel area; 201 - Peripheral corner area; 211 - Second corner area; 1 - Substrate; 2 - Bare wafer; 3 - Auxiliary stack; 3a - Flow channel; 31 - Membrane layer; 31a - First membrane layer; 31b - Second membrane layer; 4 - Turbulence column. Detailed Implementation
[0053] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention. In the description of the embodiments of this application, unless otherwise stated, " / " means "or", for example, A / B can mean A or B; "and / or" in the text is only a description of the relationship between related objects, indicating that there can be three relationships, for example, A and / or B can mean: A alone, A and B at the same time, and B alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.
[0054] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature, and in the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.
[0055] This invention provides a semiconductor structure fabricated on a semiconductor wafer. The fabrication process includes a spin coating process, and a schematic diagram of the photoresist flow during the spin coating process is shown below. Figure 1 As shown, Figure 1 Arrows are used to indicate the flow direction of photoresist on the semiconductor wafer. For example... Figure 2 and Figure 3 As shown, the semiconductor structure provided in this embodiment of the invention includes: an effective region 100 and a peripheral region 200 surrounding the effective region 100;
[0056] The effective area 100 includes multiple first corner areas 101; the peripheral area 200 includes multiple peripheral corner areas 201, and one peripheral corner area 201 partially encloses the outside of one first corner area 101.
[0057] At least one flow channel 300 is formed in each peripheral corner area 201 of the peripheral area 200, and the flow channel 300 extends along the direction from the peripheral area 200 to the effective area 100.
[0058] In the spin coating process, as the photoresist flows outward from the center of the semiconductor wafer, it first contacts the peripheral region 200 outside the effective region 100, and then contacts the effective region 100 surrounded by the peripheral region 200. The peripheral region 200 has peripheral corner regions 201 that correspond one-to-one with the first corner regions 101 in the effective region 100. That is, when the photoresist flows through the corresponding peripheral corner regions 201 and the first corner regions 101, it first encounters the peripheral corner regions 201 of the peripheral region 200 and then the first corner regions 101 of the effective region 100. Based on this, the peripheral region 200 forms a flow channel 300 in all or all of the peripheral corner regions 201. When the photoresist flows through the peripheral region 200, the flow channel 300 diverts the photoresist, thereby reducing the turbulence generated by the photoresist and improving coating uniformity.
[0059] In one embodiment, such as Figure 4 As shown, the semiconductor structure includes a substrate 1 and a die 2 formed on the substrate 1, wherein the orthographic projection of the die 2 onto the substrate 1 is rectangular. Figure 5 As shown, the bare die 2 includes an effective area 100; in the spin coating process, the flow direction of the photoresist is as follows: Figure 1 As indicated by the middle arrow, when the photoresist flows outward from the center of the semiconductor wafer, its flow is disturbed when it encounters the corners of die 2 due to height differences, especially in the diagonal direction of die 2. Figure 2 and Figure 3 The semiconductor structure provided in this embodiment provides a flow channel 300 in the peripheral region 200 outside the effective region 100. The flow channel 300 can divert the photoresist, reduce disturbance effects, and thus avoid strong turbulence in the photoresist. The semiconductor structure provided in this embodiment can reduce the disturbance encountered by the photoresist when flowing through the corners of the effective region 100, making the flow smoother and the coating more uniform, thereby reducing radial stripe defects.
[0060] In some embodiments, the peripheral region 200 includes a cutting channel region 220 and a transition region 210; the transition region 210 surrounds the outer side of the effective region 100.
[0061] The cutting channel region 220 is located between two adjacent transition regions 210;
[0062] A flow channel 300 is formed within the transition area 210 and / or the cutting channel area 220.
[0063] like Figure 5 and Figure 6 As shown, die 2 includes an effective region 100 and a transition region 210, with the transition region 210 surrounding the effective region 100. A cross-sectional view of die 2 is shown below. Figure 6As shown, the height of the portion of the die 2 located in the transition region 210 is higher than the height of the portion located in the effective region 100. In other words, there is a height difference between the transition region 210 and the effective region 100 in the die 2. A dicing channel region 220 is provided between two adjacent dies 2 so that subsequent processes can dicing and separating the semiconductor wafer into multiple independent dies 2. Therefore, the region located outside the effective region 100 of the die 2 is the transition region 210 and the dicing channel region 220, forming the peripheral region 200 as referred to in this application. The current channel 300 can be located in the transition region 210 of the peripheral region 200, or in the dicing channel region 220 of the peripheral region 200, or simultaneously in both the transition region 210 and the dicing channel region 220.
[0064] In some embodiments, such as Figure 6 As shown, the transition region 210 includes multiple second corner regions 211, each of which partially encloses the outer side of the first corner region 101, and the outer contour of the second corner region 211 is arc-shaped.
[0065] In one embodiment, such as Figure 6 As shown, and in combination Figure 2 The bare die 2 includes an effective region 100 and a transition region 210, with the transition region 210 surrounding the effective region 100. The effective region 100 includes four first corner regions 101; each transition region 210 includes four second corner regions 211, with one second corner region 211 partially enclosing one of the first corner regions 101. The outer contours of the first corner regions 101 are right angles, and the outer contours of the second corner regions 211 are arc-shaped.
[0066] In one embodiment, such as Figure 7 As shown, the semiconductor structure includes an effective region 100, a transition region 210, and a dicing region 220. The transition region 210 surrounds the effective region 100, and the dicing region 220 surrounds the transition region 210. In the spin coating process, as the photoresist flows outward from the center of the semiconductor wafer, it first contacts the dicing region 220, then the transition region 210 surrounded by the dicing region 220, and finally the effective region 100 surrounded by the transition region 210. A flow channel 300 is formed in the transition region 210 to guide the photoresist flowing from the dicing region 220 to the transition region 210, thereby reducing the turbulence of the photoresist flowing from the transition region 210 to the effective region 100 and improving the coating uniformity within the effective region 100.
[0067] In one embodiment, such as Figure 8As shown, the semiconductor structure includes an effective region 100, a transition region 210, and a dicing region 220. The transition region 210 surrounds the effective region 100, and the dicing region 220 surrounds the transition region 210. In the spin coating process, as the photoresist flows outward from the center of the semiconductor wafer, it first contacts the dicing region 220, then the transition region 210 surrounded by the dicing region 220, and finally the effective region 100 surrounded by the transition region 210. A flow channel 300 is formed in the dicing region 220 to guide the photoresist flowing through the dicing region 220, thereby reducing the turbulence of the photoresist flowing from the dicing region 220 through the transition region 210 to the effective region 100 and improving the coating uniformity within the effective region 100.
[0068] In one embodiment, such as Figure 9 As shown, the semiconductor structure includes an effective region 100, a transition region 210, and a dicing region 220. The transition region 210 surrounds the effective region 100, and the dicing region 220 surrounds the transition region 210. In the spin coating process, as the photoresist flows outward from the center of the semiconductor wafer, it first contacts the dicing region 220, then the transition region 210 surrounded by the dicing region 220, and finally the effective region 100 surrounded by the transition region 210. A flow channel 300 is formed in the dicing region 220 and the transition region 210, which can guide the photoresist flowing through the dicing region 220 and further guide the photoresist flowing from the dicing region 220 to the transition region 210, thereby further reducing the turbulence of the photoresist flowing from the dicing region 220 to the effective region 100 through the transition region 210 and further improving the coating uniformity within the effective region 100.
[0069] like Figures 7-9 As shown, and in combination Figure 2 and Figure 5 The flow channel 300 is deployed in areas corresponding to each first corner region 101 of the effective area 100. The flow channel 300 is used to reduce the strong turbulence generated at all first corner regions 101.
[0070] In some embodiments, such as Figures 10-12 As shown, there are multiple flow channels 300, and the multiple flow channels 300 are arranged at intervals around the effective area 100.
[0071] In one embodiment, such as Figure 10 As shown, the flow channel 300 is formed in the transition region 210 of the bare die 2, and is consistent with... Figure 7The difference is that the distribution area of the flow channel 300 is the same as that of the transition area 210, that is, the flow channel 300 is distributed around the effective area 100, thereby further reducing the turbulence of the photoresist flowing into the effective area 100 and further improving the uniformity of the coating in the effective area 100.
[0072] In one embodiment, such as Figure 11 As shown, the flow channel 300 is formed in the cutting channel region 220 of the bare die 2, and is consistent with... Figure 8 The difference is that the distribution area of the flow channel 300 is the same as that of the cutting channel area 220, that is, the flow channel 300 is distributed around the effective area 100, thereby further reducing the turbulence of the photoresist flowing into the effective area 100 and further improving the uniformity of the coating in the effective area 100.
[0073] In one embodiment, such as Figure 12 As shown, the flow channel 300 is formed throughout the entire peripheral area 200, and is consistent with... Figure 9 The difference is that the distribution area of the flow channel 300 is the same as that of the outer area 200, that is, the flow channel 300 is distributed around the effective area 100, thereby further reducing the turbulence of the photoresist flowing into the effective area 100 and further improving the uniformity of the coating in the effective area 100.
[0074] In some embodiments, the cutting channel region 220 and the transition region 210 are evenly provided with guide channels 300, and the guide channels 300 in the cutting channel region 220 are correspondingly connected to the guide channels 300 in the transition region 210. In other embodiments, the cutting channel region 220 and the transition region 210 are evenly provided with guide channels 300, but the guide channels 300 in the cutting channel region 220 are not connected to the guide channels 300 in the transition region 210.
[0075] In some embodiments, a current-guiding channel 300 is formed within the transition region 210 of the semiconductor structure, such as... Figures 13 to 15 As shown, the semiconductor structure includes a substrate 1 and an auxiliary stack 3 formed on the substrate 1; the auxiliary stack 3 includes at least one film layer 31;
[0076] The orthographic projection of the auxiliary stack 3 onto the substrate 1 is located inside the transition region 210;
[0077] At least one membrane layer 31 is formed with a flow channel 3a, which has a flow channel 300 extending in the direction from the transition region 210 to the effective region 100.
[0078] In one embodiment, such as Figure 13 As shown, the semiconductor structure includes a substrate 1 and an auxiliary stack 3 formed on the substrate 1. The orthographic projection of the auxiliary stack 3 onto the substrate 1 is located within the transition region 210. For ease of display, Figure 13 Only the cross-sectional structure of the transition region 210 is shown. The auxiliary stack 3 is a film layer 31, which has a flow channel 3a. The internal space of the flow channel 3a is a flow channel 300 extending along the direction from the transition region 210 to the effective region 100.
[0079] In one embodiment, such as Figure 14 As shown, the semiconductor structure includes a substrate 1 and an auxiliary stack 3 formed on the substrate 1. The orthographic projection of the auxiliary stack 3 onto the substrate 1 is located inside the transition region 210. For ease of display, Figure 14 Only the cross-sectional structure of the transition region 210 is shown. The auxiliary stack 3 consists of two membrane layers 31, each membrane layer 31 having a flow channel 3a. The flow channels 3a in the two membrane layers 31 are connected to form a flow channel 300 extending along the direction from the transition region 210 to the effective region 100.
[0080] In one embodiment, such as Figure 15 As shown, the semiconductor structure includes a substrate 1 and an auxiliary stack 3 formed on the substrate 1. The orthographic projection of the auxiliary stack 3 onto the substrate 1 is located inside the transition region 210. For ease of display, Figure 15 Only the cross-sectional structure of the transition region 210 is shown. The auxiliary stack 3 consists of two membrane layers 31, each membrane layer 31 having a flow channel 3a. The flow channels 3a in the two membrane layers 31 are not interconnected, and the internal space of each flow channel 3a is a flow channel 300 extending along the direction from the transition region 210 to the effective region 100.
[0081] Of course, the auxiliary stack 3 can also be a multilayer membrane structure. The flow channels 3a in each membrane layer 31 can be connected or not connected. The shape and size of the flow channels 3a in each membrane layer 31 can be the same or different, which will not be elaborated here.
[0082] It should be noted that the flow channel 3a can be formed by patterning on each membrane layer 31.
[0083] In some embodiments, the outer contour of the orthographic projection of the auxiliary stack 3 onto the substrate 1 is located inside the outer contour of the transition region 210.
[0084] The auxiliary stack 3 includes multiple film layers 31, such as Figures 14 to 16 As shown, the multilayer film 31 includes a first film layer 31a and a second film layer 31b. The first film layer 31a is located on the side of the second film layer 31b closer to the substrate 1. The outer contour O2 of the orthographic projection of the second film layer 31b on the substrate 1 is located inside the outer contour O1 of the orthographic projection of the first film layer 31a on the substrate.
[0085] All the film layers 31 on the substrate 1 form a stepped structure with the substrate 1, and the stepped structure rises sequentially from the transition region 210 to the effective region 100. In the spin coating process, the photoresist rises sequentially along the stepped structure, which helps to reduce the generation of photoresist turbulence.
[0086] It should be noted that the first film layer 31a and the second film layer 31b can be any two film layers in a multilayer film.
[0087] In some embodiments, the semiconductor structure includes a substrate 1 and a plurality of turbulence pillars 4 formed on the substrate 1;
[0088] The orthographic projections of multiple turbulence columns 4 on the base 1 are located inside the peripheral region 200 and are arranged around the effective region 100;
[0089] There is a gap between two adjacent turbulence columns 4 to form a flow channel 300.
[0090] In some embodiments, such as Figure 17 and Figure 18 As shown, all the spoiler columns 4 are located in the transition region 210, and the guide channel 300 formed between two adjacent spoiler columns 4 is also located within the transition region 210. Figure 19 As shown, the turbulence column 4 is formed on the substrate 1 and is a columnar structure.
[0091] In one embodiment, such as Figure 20 As shown, all the turbulence columns 4 are located in the cutting channel area 220, and the flow guiding channel 300 formed between two adjacent turbulence columns 4 is also located in the cutting channel area 220.
[0092] In one embodiment, such as Figure 21 As shown, of all the spoiler columns 4, a portion of the spoiler columns 4 are located within the transition region 210, while the remaining portion are located within the cutting channel region 220. In other words, the guide channel 300 is simultaneously located in both the cutting channel region 220 and the transition region 210.
[0093] In some embodiments, the plurality of turbulence columns 4 include a plurality of flow guide groups, one flow guide group being disposed outside a first corner region 101;
[0094] Each flow guide group includes multiple spaced-apart turbulence columns 4.
[0095] In one embodiment, such as Figure 17 As shown, the effective area 100 has four first corner areas 101. Correspondingly, a flow guide group is arranged around each first corner area 101. Each flow guide group has multiple flow deflectors 4, and a flow guide channel 300 is formed between two adjacent flow deflectors 4. That is to say, the flow deflectors 4 on the base 1 are divided into four flow guide groups.
[0096] In some embodiments, the plurality of spoiler columns 4 include at least one annular assembly, each annular assembly including a plurality of spoiler columns 4 arranged at intervals around the effective region 100.
[0097] In one embodiment, such as Figure 18 As shown, all the turbulence pillars 4 are located within the transition region 210. A ring-shaped assembly is formed within the transition region 210. The ring-shaped assembly includes multiple turbulence pillars 4, and all the turbulence pillars 4 are arranged at intervals around the effective region 100, so that the turbulence is dispersed and weakened when the photoresist flows through the region.
[0098] In one embodiment, such as Figure 20 As shown, all the turbulence pillars 4 are located within the dicing channel region 220. A ring-shaped assembly is formed within the dicing channel region 220. The ring-shaped assembly includes multiple turbulence pillars 4, and all the turbulence pillars 4 are arranged at intervals around the effective region 100, so that the turbulence is dispersed and weakened when the photoresist flows through the region.
[0099] In one embodiment, such as Figure 21 As shown, all the turbulence pillars 4 include two annular components, and each annular component includes multiple turbulence pillars 4. The first annular component is located in the dicing region 220, and the second annular component is located in the transition region 210, so that the turbulence is dispersed and weakened when the photoresist flows through these two regions.
[0100] In one embodiment, such as Figure 22 As shown, all the turbulence-dispersing pillars 4 comprise two annular components, both located in the transition region 210, which disperses and weakens the turbulence as the photoresist flows through this region. Each annular component includes multiple turbulence-dispersing pillars 4. Figure 23 As shown, the turbulence columns 4 in both annular components are formed on the substrate 1.
[0101] In some embodiments, the orthographic projection of the turbulence column 4 onto the base 1 is any one of a rectangle, square, circle, ellipse, and irregular polygon.
[0102] In one embodiment, such as Figure 17 and Figure 18 As shown, the orthographic projection of the turbulence column 4 onto the base 1 is rectangular. In one embodiment, as... Figure 20 and Figure 21 As shown, the orthographic projection of the turbulence column 4 onto the base 1 is a circle.
[0103] Of course, the orthographic projection of the turbulence column onto the base can also be other shapes, which will not be elaborated here.
[0104] It should be noted that there are multiple ways to form a turbulence column. The following are examples of several specific implementation methods.
[0105] In one embodiment, such as Figure 24 As shown, a film layer is deposited on the substrate; a photoresist layer is coated on the film layer; the photoresist is exposed, developed, and etched to form a mask layer. The mask layer is then used as a mask to etch the film layer to form turbulence pillars.
[0106] In one embodiment, such as Figure 25 As shown, a layer of photoresist is coated on the substrate, and the photoresist is exposed, developed, and etched into turbulence pillars.
[0107] In one embodiment, such as Figure 26 As shown, a layer of photoresist is coated on the substrate, and the photoresist is exposed, developed and etched into a groove structure. A film layer is deposited on the photoresist layer and the film layer fills the groove structure. The film layer above the photoresist is removed. The removal of the photoresist layer causes the film layer filling the groove structure to form a turbulence pillar.
[0108] In one embodiment, such as Figure 27 As shown, a first layer of photoresist is coated on the substrate, and the first layer of photoresist is exposed, developed, and etched into a groove structure. A film layer is deposited on the first layer of photoresist and the film layer fills the groove structure. A second layer of photoresist is coated on the film layer. The second layer of photoresist is exposed, developed, and then removed. The film layer is etched, and the first layer of photoresist is removed to form a turbulence pillar.
[0109] In a semiconductor structure provided by this invention, in order to ensure the uniformity of photoresist coating in the effective area, a flow channel or a flow-dispersing column is added in the transition area and / or a flow-dispersing column is added in the dicing area. That is, some special structures are added at the corners of the transition area and / or the edge of the dicing area or at the edge of the transition area to guide and disperse turbulence, thereby reducing the disturbance encountered by the photoresist when it flows through the corners of the die, making the flow more stable and the coating more uniform, thereby reducing radial stripe defects.
[0110] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the invention. Therefore, if these modifications and variations fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.
Claims
1. A semiconductor structure, characterized in that, include: The effective area and the surrounding area enclosing the effective area; The effective area includes multiple first corner areas; the peripheral area includes multiple peripheral corner areas, and one of the peripheral corner areas partially encloses the outside of one of the first corner areas. At least one flow channel is formed in each of the peripheral corner areas of the peripheral region, and the flow channel extends along the direction from the peripheral region to the effective region.
2. The semiconductor structure according to claim 1, characterized in that, There are multiple flow channels, and the multiple flow channels are arranged at intervals around the effective area.
3. The semiconductor structure according to claim 1, characterized in that, The peripheral area includes a cutting channel area and a transition area. The transition area surrounds the outside of the effective area, and the cutting channel area surrounds the outside of the transition area. The flow guiding channel is formed in the cutting channel area and / or the transition area.
4. The semiconductor structure according to claim 3, characterized in that, The transition region includes multiple second corner regions, each of which partially encloses the outer side of the first corner region, and the outer contour of the second corner region is arc-shaped.
5. The semiconductor structure according to claim 3, characterized in that, The flow guiding channel is formed within the transition area; The semiconductor structure includes a substrate and an auxiliary stack formed on the substrate; the auxiliary stack includes at least one film layer; The orthographic projection of the auxiliary layer onto the substrate is located within the transition region; At least one of the membrane layers is formed with a flow channel having a flow channel extending along the direction from the transition region to the effective region.
6. The semiconductor structure according to claim 5, characterized in that, The outer contour of the auxiliary layer's orthographic projection onto the substrate is located inside the outer contour of the transition region; The auxiliary stack includes multiple film layers, including a first film layer and a second film layer. The first film layer is located on the side of the second film layer closer to the substrate. The outer contour of the orthographic projection of the second film layer on the substrate is located inside the outer contour of the orthographic projection of the first film layer on the substrate.
7. The semiconductor structure according to any one of claims 1-6, characterized in that, The semiconductor structure includes a substrate and a plurality of turbulence pillars formed on the substrate; The orthographic projections of the plurality of turbulence-disrupting columns on the substrate are located inside the peripheral region and are arranged around the effective region; There is a gap between two adjacent turbulence columns to form the flow channel.
8. The semiconductor structure according to claim 7, characterized in that, The plurality of turbulence columns include a plurality of flow guide groups, and one of the flow guide groups is disposed outside a first corner region; Each of the flow guide groups includes a plurality of spaced-apart turbulence columns.
9. The semiconductor structure according to claim 7, characterized in that, The plurality of baffles include at least one layer of annular components, each of which includes a plurality of baffles arranged at intervals around the effective area.
10. The semiconductor structure according to claim 7, characterized in that, The orthographic projection of the turbulence column onto the substrate includes any one of the following: rectangle, square, circle, ellipse, and irregular polygon.