Memory system and method of operating the same

Abstract

The present disclosure relates to a memory system. The memory system includes: a memory device; and a controller adapted to control the memory device and including a buffer memory, wherein the controller performs error history recording in the buffer memory in response to a record start command from a host, stops the error history recording in response to a record stop command from the host, and provides the recorded error history to the host in response to an output command from the host.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0089028, filed on Jul. 17, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments are directed to a memory system including a memory device. Background Art

[0004] The computer environment paradigm has shifted to ubiquitous computing, which enables the use of computing systems anywhere, anytime. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and laptop computers has increased rapidly. These portable electronic devices typically use a memory system having one or more memory devices to store data. The memory system can be used as a primary memory device or an auxiliary memory device of the portable electronic device.

[0005] Because the memory system has no moving parts, the memory system provides advantages such as excellent stability and durability, high information access speed, and low power consumption. Examples of memory systems having such advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces, and solid-state drives (SSDs). Summary of the invention

[0006] Various embodiments relate to a memory system and an operating method thereof, the memory system being capable of recording an error history in response to a request from a host to facilitate error analysis and debugging.

[0007] According to an embodiment, a memory system includes: a memory device; and a controller adapted to control the memory device and including a buffer memory, wherein the controller performs error history recording in the buffer memory in response to a record start command from a host, stops the error history recording in response to a record stop command from the host, and provides the recorded error history to the host in response to an output command from the host.

[0008] According to an embodiment, an operating method of a memory system includes: in response to a record start command from a host, performing error history recording in a buffer memory included in the memory system; in response to a record stop command from the host, stopping the error history recording; and in response to an output command from the host, providing the recorded error history to the host.

[0009] According to an embodiment, a system includes: a host; and a memory system including a memory device and a controller, the controller including a memory, wherein the controller is configured to: receive a first error history command from the host; trigger an error history recording in response to the first error history command so that errors occurring in the system are recorded in the memory, wherein each error recorded in the memory is associated with command information of one or more commands of the memory device and at least one of status information of the memory system when the corresponding error occurs; receive a second error history command from the host; and provide the error history to the host in response to the second error history command. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A data processing system according to an embodiment is shown.

[0011] Figure 2 A read buffer command included in a small computer system interface (SCSI) command set is shown.

[0012] Figure 3 Shows various modes of read buffer commands.

[0013] Figure 4 Shows various actions of the error history command.

[0014] Figure 5 Commands according to an embodiment are shown.

[0015] Figure 6 A transaction between a host and a memory system according to an embodiment is shown.

[0016] Figure 7 An error history directory that may be stored in a history buffer area according to an embodiment is shown. DETAILED DESCRIPTION

[0017] The various embodiments are described in more detail below with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art. Throughout the disclosure, the same figure numerals refer to the same parts in the various figures and embodiments of the present disclosure. Moreover, throughout the specification, references to "embodiment", "another embodiment" and the like are not necessarily directed only to one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment.

[0018] Figure 1 is a block diagram illustrating a data processing system 100 according to an embodiment of the present invention.

[0019] Reference Figure 1, data processing system 100 may include a host 102 operably coupled to a memory system 110 .

[0020] The host 102 may include any of various portable electronic devices such as a mobile phone, an MP3 player, and a laptop computer, or any of various non-portable electronic devices such as a desktop computer, a game console, a television (TV), and a projector.

[0021] The host 102 may include at least one operating system (OS), which may manage and control all functions and operations of the host 102 and provide operations between the host 102 and a user using the data processing system 100 or the memory system 110. The OS may support functions and operations corresponding to the user's purpose and usage. For example, the OS may be divided into a general-purpose OS and a mobile OS according to the mobility of the host 102. The general-purpose OS may be divided into a personal OS and an enterprise OS according to the user's environment.

[0022] The memory system 110 may operate in response to a request of the host 102 to store data of the host 102. A non-limiting example of the memory system 110 includes a universal flash storage (UFS) device.

[0023] The memory system 110 may be implemented by any of various types of memory devices. Examples of such memory devices include, but are not limited to, volatile memory devices such as dynamic random access memory (DRAM) and static RAM (SRAM), and non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric RAM (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM or ReRAM), and flash memory. The flash memory may have a three-dimensional (3D) stacked structure.

[0024] The memory system 110 may include a controller 130 and a memory device 150. The memory device 150 may store data of the host 102, and the controller 130 may control the data to be stored in the memory device 150.

[0025] The controller 130 and the memory device 150 may be integrated into a single semiconductor device. For example, the controller 130 and the memory device 150 may be integrated into one semiconductor device to constitute a solid state drive (SSD). When the memory system 110 is used as an SSD, the operating speed of the host 102 connected to the memory system 110 may be increased. In another embodiment, the controller 130 and the memory device 150 may be integrated into one semiconductor device to constitute a memory card such as a Personal Computer Memory Card International Association (PCMCIA) card, a Compact Flash (CF) card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC) including a Reduced Size MMC (RS-MMC) and a Micro MMC, a Secure Digital (SD) card including a Mini SD card, a Micro SD card, and an SDHC card, or a Universal Flash (UFS) device.

[0026] Non-limiting application examples of the memory system 110 include a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional television, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device constituting a data center, a device capable of transmitting / receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, a radio frequency identification (RFID) device, or one of various components constituting a computing system.

[0027] The memory device 150 may be a nonvolatile memory device, and the stored data may be retained even if power is not supplied. The memory device 150 may store data provided from the host 102 through a programming operation, and provide the stored data to the host 102 through a read operation. The memory device 150 may include a plurality of memory blocks, each of which may include a plurality of pages, and each of the pages may include a plurality of memory cells coupled to a word line. In an embodiment, the memory device 150 may be a flash memory. The flash memory may have a three-dimensional (3D) stacked structure.

[0028] The controller 130 may control the memory device 150 in response to a request from the host 102. For example, the controller 130 may provide data read from the memory device 150 to the host 102, and store data provided from the host 102 in the memory device 150. For this operation, the controller 130 may control a read operation, a program operation, and an erase operation of the memory device 150.

[0029] The controller 130 may include a host interface (I / F) 132 , a processor 134 , a memory I / F 142 , and a buffer memory 144 , all of which are operably coupled via an internal bus.

[0030] Host I / F 132 may be configured to process commands and data from host 102. Host I / F 132 may communicate with host 102 through one or more of various interface protocols such as Small Computer System Interface (SCSI), Serial Attached SCSI (SAS).

[0031] The host I / F 132 may be driven by firmware referred to as a host interface layer (HIL) to exchange data with the host 102 .

[0032] The memory I / F 142 may be used as a memory / storage interface for interfacing the controller 130 and the memory device 150 so that the controller 130 controls the memory device 150 in response to a request from the host 102. When the memory device 150 is a flash memory or, specifically, a NAND flash memory, the memory I / F 142 may generate a control signal for the memory device 150 under the control of the processor 134, and process data to be provided to the memory device 150. The memory I / F 142 may be used as an interface (e.g., a NAND flash memory interface) for processing commands and data between the controller 130 and the memory device 150. Specifically, the memory I / F 142 may support data transfer between the controller 130 and the memory device 150.

[0033] The memory I / F 142 may be driven by firmware referred to as a flash interface layer (FIL) to exchange data with the memory device 150 .

[0034] The processor 134 may control the overall operation of the memory system 110. The processor 134 may drive firmware to control the overall operation of the memory system 110. The firmware may be referred to as a flash translation layer (FTL). Also, the processor 134 may be implemented as a microprocessor or a central processing unit (CPU).

[0035] The processor 134 may drive the FTL and perform a foreground operation corresponding to a request received from the host 102. For example, the processor 134 may control a write operation of the memory device 150 in response to a write request from the host 102, and control a read operation of the memory device 150 in response to a read request from the host 102.

[0036] Also, the controller 130 may perform background operations on the memory device 150. Examples of the background operations include a garbage collection (GC) operation, a wear leveling (WL) operation, a map clearing operation, and a bad block management operation.

[0037] Buffer memory 144 may buffer data received from host 102, or may buffer data to be provided from memory system 110 to host 102. The data to be provided to host 102 may include error history. In an embodiment, buffer memory 144 may include history buffer area 146, that is, an area in buffer memory 144 that may buffer error history.

[0038] The buffer memory 144 may be implemented as a volatile memory. For example, the buffer memory 144 may be implemented as a static random access memory (SRAM) or a dynamic random access memory (DRAM). The buffer memory 144 may be provided inside or outside the controller 130. Figure 1 In the illustrated embodiment, the buffer memory 144 is disposed inside the controller 130. In another embodiment, the buffer memory 144 may be implemented as an external volatile memory device having a memory interface for exchanging data between the buffer memory 144 and the controller 130.

[0039] The host 102 may obtain data related to an error caused due to any of various reasons during the operation of the memory system 110 , and may perform debugging based on the data.

[0040] For example, when an error is detected in the memory system 110, the processor 134 may record an error event including state information of the memory system 110 into the history buffer area 146, the state information indicating the time when the error occurred. In an embodiment, the state information may include information related to the register value of the controller 130 when the error occurred. In some embodiments, the state information may include another piece of information, such as command information. The multiple error events recorded in the history buffer area 146 together constitute the error history of the memory system 110.

[0041] The memory system 110 using the SCSI command set may support an error history command. The host 102 may obtain data related to errors by providing the error history command to the memory system 110. In particular, the specifications UFS 3.0 and UFS 3.1 stipulate that the memory system 110 shall support the error history command.

[0042] The memory system 110 may provide the recorded error history to the host 102 in response to an error history command from the host 102. The host 102 may identify the cause of the error based on the error history, and may perform debugging.

[0043] If the processor 134 records only status information indicating the time when an error occurred as an error history, the host 102 can only identify the cause of the error occurring in the memory system 110 based on the error history, which may not always be accurate or up-to-date.

[0044] For example, even when the memory system 110 performs an operation in response to one command, the state of the memory system 110 may change. Therefore, the state information recorded in the history buffer area 146 may be different according to the time when the processor 134 detects an error. In addition, the internal operation information in the memory system 110 before the error is detected may not be recorded in the history buffer area 146. Therefore, although the host 102 obtains the error history from the memory system 110, it is generally difficult for the host 102 to check the internal operation of the memory system 110 and to perform debugging.

[0045] Therefore, a method is needed to enable the host 102 to obtain desired information within a desired time window, where the desired information is not limited to the status information indicating the time when an error occurred.

[0046] For example, it may be desirable for host 102 to be able to obtain command information provided from controller 130 to memory device 150 in addition to status information indicating when an error occurred.

[0047] According to an embodiment, the host 102 may control the processor 134 to start command information recording in the history buffer area 146 of the buffer memory 144 by providing a first command to the memory system 110, and may control the processor 134 to stop the command information recording by providing a second command to the memory system 110. The processor 134 may record command information within a time window determined by receiving the first and second commands from the host 102. The host 102 may obtain the command information recorded in the history buffer area 146 by providing a third command to the memory system 110.

[0048] The command information may be an error history different from the error history of the state information. That is, in an embodiment, the error history may include a state type information error history and a command type information error history.

[0049] The first to third commands may be implemented based on the SCSI command set. If the first to third commands are implemented based on the SCSI command set, the complexity of such implementation of the controller 130 may be reduced compared to the case where the first to third commands are implemented as vendor-specific commands.

[0050] In the following, reference is made to Figures 2 to 4 Describes the SCSI command set. Figure 5 Commands implemented based on a SCSI command set according to some embodiments are described.

[0051] Figure 2 A first table 200 is shown which describes the read buffer commands included in the SCSI command set.

[0052] Reference Figure 2 , a first table 200 shows a command descriptor block (CDB) of a read buffer command. The read buffer command may be configured to have 10 bytes of data and may include data such as: an operation code "3ch", a mode, a buffer identifier (ID), a buffer offset, an allocation length, and a control code "00h".

[0053] The memory system 110 may provide a set number of data bytes from a set offset within the buffer memory 144 to a buffer of the host 102 in response to a read buffer command from the host 102 .

[0054] The host 102 may specify a data mode or an error history mode of the memory system 110 by setting a mode value of a read buffer command provided to the memory system 110 .

[0055] Figure 3 A second table 300 is shown describing various modes of read buffer commands.

[0056] Reference Figure 3 , the second table 300 indicates the mode values ​​of the read buffer command. Mode values ​​"00h" and "03h-1Bh" may not be used for the UFS memory system. Mode value "01h" may indicate a vendor-specific mode. Mode value "02h" may specify a data mode. Mode value "1Ch" may indicate an error history mode. "1Dh-1Fh" may be a reserved mode value that is not currently used to specify any (multiple) modes.

[0057] A read buffer command having a mode value set to '1Ch' may be represented as an error history command.

[0058] Figure 4 A third table 400 is shown describing various actions of the error history command.

[0059] Reference Figure 4 , the host 102 can set Figure 2 The action to be performed by the memory system 110 and the data to be returned by the memory system 110 are specified by the buffer ID value of the error history command in the error history command.

[0060] For example, a buffer ID value of "00h" may indicate that an error history directory buffered in the buffer memory 144 should be returned. The error history directory may include multiple directory entries. Each of the directory entries may include an error history. "10h-EFh" may indicate that only the error history of a selected directory entry in the error history directory should be returned.

[0061] Buffer ID values ​​"01h-03h" and "FEh-FFh" may not be used in a UFS memory system. Buffer ID values ​​"04h-0Fh" and "F0h-FDh" may be reserved values ​​that currently do not specify any action. Figure 4 The dashed lines shown indicate the reserved buffer ID values.

[0062] According to an embodiment, the memory system 110 may support a record start command, a record stop command, and an output command, wherein the record start command uses the reserved buffer ID value of the error history command to control the processor 134 to start command information recording in the buffer memory 144, the record stop command controls the processor 134 to stop the command information recording, and the output command controls the processor 134 to output the command information recorded in the buffer memory 144.

[0063] Figure 5 A fourth table 500 is shown describing commands according to an embodiment.

[0064] In some embodiments, Figure 5 As shown, the memory system 110 may support command descriptors for a record start command, a record stop command, and an output command. The memory system 110 may further support a clear command. Figure 5 The command descriptor for the clear command is also shown.

[0065] according to Figure 5 In the example shown, the host 102 may provide the memory system 110 with an error history command that sets the buffer ID to "04h" and the buffer offset to "0x10" as a record start command. Figure 2 and Figure 3 As stated, Figure 5The illustrated "READ_BUFFER(10), Mode=1Ch" indicates an error history command. The buffer offset "0x10" may specify the history buffer area 146. In some embodiments, the value of the buffer offset may be different.

[0066] Processor 134 may record command information in response to a record start command into history buffer area 146. For example, after receiving a record start command, processor 134 may record commands generated by processor 134 and provided to memory device 150 to create a command history.

[0067] The host 102 may provide an error history command setting the buffer ID to “05h” and the buffer offset to “0x10” as a record stop command to the memory system 110. The processor 134 may stop command information recording in response to the record stop command.

[0068] The host 102 can actively determine the time window in which the command information will be recorded by providing a record start command and a record stop command. Further, the host 102 can obtain the command information recorded in the time window by providing an output command.

[0069] The host 102 may provide an error history command with the buffer ID set to "F0h" and the buffer offset set to "0x10" as an output command to the memory system 110. The processor 134 may provide the host 102 with command information buffered in the history buffer area 146 in response to the output command.

[0070] The host 102 may provide an error history command setting the buffer ID to “F1h” and the buffer offset to “0x10” as a clear command to the memory system 110. The processor 134 may clear the command information buffered in the history buffer area 146 in response to the clear command.

[0071] As an example, the fourth table 500 shows the buffer IDs of the record start command, the record stop command, the output command, and the clear command as "04h", "05h", "F0h", and "F1h", respectively, but the present invention is not limited to those specific contents. For example, any one or all of the buffer IDs of the record start command, the record stop command, the output command, and the clear command can be specified by the reserved (multiple) buffer ID values.

[0072] Figure 6 A transaction between a host 102 and a memory system 110 is shown according to an embodiment.

[0073] Reference Figure 6 In operation S602 , the host 102 may provide a recording start command to the memory system 110 .

[0074] For example, when an error is detected in the memory system 110 during testing of the memory system 110, the host 102 can confirm the cause of the error by reproducing the occurrence of the error and can perform debugging. In order to obtain command information before and after the error occurs, the host 102 can provide a record start command before the error occurs.

[0075] In operation S604 , the memory system 110 may record all commands (or all pieces of command information) into the history buffer area 146 before receiving a record stop command from the host 102 .

[0076] For example, each time the controller 130 provides a command to the memory device 150 , the memory system 110 may store command information of the command in the history buffer area 146 .

[0077] While the memory system 110 records the command information, an error may be detected in the memory system 110. In some embodiments, separately from the command information recorded in operation S604, the memory system 110 may also record status information indicating when the error occurred.

[0078] The command information and status information may be included in the error history directory stored in the history buffer area 146. Figure 7 An error history directory according to an embodiment is described.

[0079] In operation S606, the host 102 may provide a record stop command to the memory system 110 to stop command information recording. The memory system 110 may stop command information recording in response to the record stop command.

[0080] In operation S608 , the host 102 may provide an output command to the memory system 110 to obtain the command information (command history) recorded in operation S604 .

[0081] In operation S610 , the memory system 110 may provide the host 102 with a command history (history data) buffered in the history buffer area 146 in response to an output command.

[0082] In operation S612 , the host 102 may perform debugging based on the command information received from the memory system 110 .

[0083] Figure 7 is a diagram illustrating an error history directory 700 that may be stored in the history buffer area 146 according to some embodiments.

[0084] Reference Figure 7 , the error history directory 700 may include multiple directory entries. Figure 7 Not shown, but error history directory 700 may also include a header.

[0085] Each of the plurality of directory entries may include an error history. In an embodiment, the error history may include any one of status information and command information. Figure 7 In the example shown, the error history type of each directory entry may depend on whether each error history indicates status information or command information.

[0086] When the set conditions are met, the processor 134 may perform error history recording. When an error event occurs, the processor 134 may add the error event to the error history directory 700.

[0087] Figure 7 Operation S604 in FIG. Figure 6 The following operation is described: a record start command is provided by the host 102, and command information in a time window before a record stop command is provided is recorded by the processor 134.

[0088] During the time window, whenever a command is provided to the memory device 150, the processor 134 may add an error event including associated command information to the error history directory 700. Each error event added is associated with status information and / or command information.

[0089] Even when an error occurs within the time window, the processor 134 may add state information indicating the time when the error occurred to the error history directory 700 .

[0090] According to an embodiment, the memory system 110 may support a record start command, a record stop command, and an output command so that the host 102 can obtain expected information in an expected time window, which is not limited to the state information indicating the time when the error occurred. The memory system 110 may support the record start command, the record stop command, and the output command using the reserved buffer ID value of the error history command. As an example, the expected information may be command information provided from the controller 130 to the memory device 150, but the present invention is not limited thereto.

[0091] The host 102 can use the record start command, the record stop command and the output command to obtain the command information in the expected time window. The host 102 can obtain the command information before and after the error occurs, generally can check the internal operation before and after the error occurs, can easily analyze the cause of the error, and can perform debugging.

[0092] The present disclosure may provide a memory system and an operating method thereof, the memory system being capable of recording error events in response to a request from a host to generate an error history for facilitating error analysis and debugging.

[0093] While various embodiments have been shown and described, it will be apparent to those skilled in the art in light of this disclosure that various changes and modifications can be made without departing from the spirit and scope of the disclosure as defined in the following claims.

Claims

1. A memory system, comprising: Memory device; as well as a controller that controls the memory device and includes a buffer memory, wherein the controller performs error history recording in the buffer memory in response to a record start command from the host, stops the error history recording in response to a record stop command from the host, and provides the recorded error history to the host in response to an output command from the host, wherein the record start command, the record stop command and the output command are included in an error history command which is a small computer system interface command, i.e., a SCSI command, and When an error is detected in the memory system during testing of the memory system, the host confirms the cause of the error by reproducing the occurrence of the error and performs debugging, and the host provides the recording start command before the error occurs so as to obtain command information before and after the error occurs. 2 . The memory system according to claim 1 , wherein the controller clears the error history from the buffer memory in response to a clear command from the host.

3. The memory system of claim 2, wherein: The clear command is included in the SCSI command, and Each of the record start command, the record stop command, the output command, and the clear command is specified based on the value of a buffer identifier, ie, a buffer ID, of the error history command. 4 . The memory system of claim 3 , wherein the error history command is designated as a specific mode value of a read buffer command which is the SCSI command.

5. The memory system of claim 3, wherein: Each of the record start command, the record stop command, the output command, and the clear command further includes a value of a buffer offset of the error history command, and The buffer offset value specifies the location where the error history directory is stored. 6 . The memory system according to claim 1 , wherein each time the controller provides a command to the memory device, the controller performs recording the error history by storing command information of the command in the buffer memory. 7 . The memory system of claim 6 , wherein the controller further stores status information in the buffer memory, the status information indicating when an error occurs in the memory system. 8 . The memory system of claim 7 , wherein the status information includes information about a register value of the controller when the error occurs.

9. The memory system of claim 7, wherein: The buffer memory stores an error history directory, the error history directory including a plurality of directory entries, and Each of the plurality of directory entries includes one of the command information and the status information.

10. A method for operating a memory system, comprising: performing error history recording in a buffer memory included in the memory system in response to a record start command from a host; In response to a recording stop command from the host, stopping the error history recording; and providing the recorded error history to the host in response to an output command from the host, wherein the record start command, the record stop command and the output command are included in an error history command which is a small computer system interface command, i.e., a SCSI command, and When an error is detected in the memory system during testing of the memory system, the host confirms the cause of the error by reproducing the occurrence of the error and performs debugging, and the host provides the recording start command before the error occurs so as to obtain command information before and after the error occurs.

11. The operating method according to claim 10, further comprising clearing the error history from the buffer memory in response to a clear command from the host.

12. The operating method according to claim 11, wherein: The clear command is included in the SCSI command, and each of the record start command, the record stop command, the output command, and the clear command is specified based on a value of a buffer identifier, ie, a buffer ID, of the error history command.

13. The operating method according to claim 12, wherein the error history command is designated as a specific mode value of a read buffer command which is the SCSI command.

14. The operating method according to claim 12, wherein: Each of the record start command, the record stop command, the output command, and the clear command further includes a value of a buffer offset of the error history command, and The buffer offset value specifies the location where the error history directory is stored.

15. The operating method according to claim 10, wherein recording the error history comprises: Whenever a controller of the memory system provides a command to a memory device of the memory system, command information of the command is stored in the buffer memory.

16. The operating method according to claim 15, further comprising: Status information is stored in the buffer memory, the status information indicating when an error occurred in the memory system. 17 . The operating method according to claim 16 , wherein the status information includes information on a register value of the controller when the error occurs.

18. The operating method according to claim 16, wherein: The buffer memory stores an error history directory, the error history directory including a plurality of directory entries, and Each of the plurality of directory entries includes one of the command information and the status information.

19. A system comprising: Host; as well as A memory system comprising a memory device and a controller, wherein the controller comprises a memory, The controller: receiving a first error history command from the host; triggering an error history record in response to the first error history command so that errors occurring in the memory system are recorded in the memory, wherein each error recorded in the memory is associated with at least one of command information about one or more commands of the memory device and state information of the memory system when the corresponding error occurs; receiving a second error history command from the host; and providing the error history to the host in response to the second error history command, When an error is detected in the memory system during testing of the memory system, the host confirms the cause of the error by reproducing the occurrence of the error and performs debugging, and the host triggers the first error history command before the error occurs to obtain command information before and after the error occurs.

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