Semiconductor package structure and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor package structure and a manufacturing method thereof. The semiconductor package structure includes a first chip, a second chip, a bridge circuit, and a reinforcing structure. The bridge circuit is disposed between the first chip and the second chip. The reinforcing structure is disposed on the bridge circuit and includes a top support and a lateral support. When the reinforcing structure is subjected to stress, a stress component perpendicular to the reinforcing structure can be counteracted by the material strength of the reinforcing structure itself. A stress component parallel to the reinforcing structure can be counteracted by the lateral support, thereby preventing the bridge circuit from being subjected to structural stress and preventing the bridge circuit from being broken.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a semiconductor package structure and a manufacturing method thereof. BACKGROUND

[0002] The existing package structure, such as a FOCoS (Fan Out Chip on Substrate) package structure, has different degrees of deformation of each material due to the difference in the coefficient of thermal expansion of each material when the temperature changes, which causes the package structure to warp and generate stress inside. Due to the fact that the overall structure cannot directly release stress during the thermal cycle process, the underfill material between the ASIC (Application Specific Integrated Circuit) chip and the HBM (High Bandwidth Memory) chip at the stress concentration point produces cracks due to insufficient tensile strength, and the cracks can extend downward to damage the redistribution layer. SUMMARY

[0003] The present disclosure provides a semiconductor package structure and a manufacturing method thereof.

[0004] In a first aspect, the present disclosure provides a semiconductor package structure, comprising:

[0005] a first chip;

[0006] a second chip, disposed adjacent to the first chip;

[0007] a redistribution layer, comprising a bridge circuit and a reinforcing structure above the bridge circuit, the bridge circuit being located below a gap between the first chip and the second chip, and the reinforcing structure having an edge lateral support extending to the redistribution layer.

[0008] In some optional embodiments, the semiconductor package structure further comprises a solder layer above the reinforcing structure, the solder layer being electrically connected to the first chip and the second chip, respectively.

[0009] In some optional embodiments, the edge lateral support comprises at least two through holes.

[0010] In some optional embodiments, the edge lateral support comprises two through holes, and the two through holes are respectively located on opposite sides of the bridge circuit; and

[0011] the reinforcing structure further comprises a top support between the two through holes, a center line of the top support being out-of-plane and not out-of-plane perpendicular to a center line of the bridge circuit.

[0012] In some optional embodiments, the bridge line has opposite first and second sides; and

[0013] The edge lateral support includes four through holes, and two of the four through holes are located on the first side, and the other two of the four through holes are located on the second side.

[0014] In some optional embodiments, the reinforcing structure further includes a top support located between the four through holes, and the top support presents a cross shape and / or a surrounding shape.

[0015] In some optional embodiments, the reinforcing structure further includes a top support covering the four through holes, and the top support presents a rectangular shape.

[0016] In some optional embodiments, the bridge line has opposite first and second sides, a third side adjacent to the first side, and a fourth side opposite to the third side; and

[0017] The edge lateral support includes six through holes, and two of the six through holes are located on the first side, two of the remaining four through holes are located on the second side, and the other two of the remaining two through holes are located on the third side and the fourth side, respectively; and

[0018] The reinforcing structure further includes a first top support located between the through hole on the first side and the through hole on the second side, and a second top support located between the through hole on the third side and the through hole on the fourth side, and the first top support presents a cross shape and / or a surrounding shape.

[0019] In some optional embodiments, the semiconductor package structure further includes:

[0020] A substrate, and the redistribution layer is disposed on the substrate and electrically connected to the substrate.

[0021] In some optional embodiments, the semiconductor package structure further includes:

[0022] A mold encapsulation layer covering the first chip and the second chip.

[0023] In a second aspect, the present disclosure provides a manufacturing method of a semiconductor package structure, comprising:

[0024] Providing a substrate;

[0025] Forming a bottom redistribution layer on the substrate, and the bottom redistribution layer includes a bridge line located in a gap between a preset first chip area and a preset second chip area;

[0026] forming a top redistribution layer on the bottom redistribution layer and a reinforcement structure above the bridge line, the reinforcement structure having edge lateral supports extending to edges of the redistribution layer and a top support between the edge lateral supports.

[0027] In some optional embodiments, the method further comprises:

[0028] forming a solder layer electrically connected to the top redistribution layer and the reinforcement structure.

[0029] In some optional embodiments, the method further comprises:

[0030] forming a first chip and a second chip on the solder layer and electrically connected to the solder layer.

[0031] In some optional embodiments, the method further comprises:

[0032] forming a mold encapsulation layer encapsulating the first chip and the second chip.

[0033] The present disclosure provides a semiconductor package structure and a manufacturing method thereof, by providing a reinforcement structure on a bridge line under a gap between a first chip and a second chip, wherein the reinforcement structure comprises edge lateral supports surrounding the bridge line and a top support above the bridge line. When the reinforcement structure is under stress, the stress components perpendicular to the reinforcement structure can be counteracted by the material strength of the reinforcement structure itself. The stress components parallel to the reinforcement structure can be provided with sufficient stress resistance by the edge lateral supports fixing the top support, thereby avoiding the impact of the bridge line under structural stress and preventing the bridge line from breaking. BRIEF DESCRIPTION OF DRAWINGS

[0034] Other features, objects, and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments thereof as taken in conjunction with the accompanying drawings:

[0035] Figure 1 is a first structural diagram of a semiconductor package structure according to the present disclosure;

[0036] Figure 2 is a perspective structural diagram of a reinforcement structure according to the present disclosure;

[0037] Figures 3-9 is a first structural diagram to a seventh structural diagram of a reinforcement structure according to the present disclosure;

[0038] Figure 10 is a second structural diagram of a semiconductor package structure according to the present disclosure;

[0039] Figures 11-16 is a structural schematic diagram in a manufacturing process of a semiconductor package structure according to the present disclosure.

[0040] Symbol explanation:

[0041] 1 - first chip, 2 - second chip, 3 - redistribution layer, 31 - bridge line, 32 - reinforcing structure, 321 - edge lateral support, 322 - top support, 33 - solder layer, 34 - bottom redistribution layer, 35 - top redistribution layer, 4 - substrate, 5 - mold layer, 6 - bottom filler, 7 - preset first chip area, 8 - preset second chip area, 9 - photoresist layer. DETAILED DESCRIPTION

[0042] The specific embodiments of the present application will be described below with reference to the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems solved by the present application and the technical effects produced by the present application through the content described in the specification. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, in order to facilitate description, only the parts related to the application are shown in the drawings.

[0043] It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the specification are only used to cooperate with the content described in the specification for understanding and reading by those skilled in the art, and are not used to limit the implementation conditions of the present application, so they do not have technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be produced by the present application, should still fall within the scope of the technical content disclosed by the present application. At the same time, the terms such as "upper", "first", "second" and "one" used in the specification are only for the convenience of clear description, and are not used to limit the scope of the application that can be implemented, and the change or adjustment of the relative relationship without substantial change of the technical content is also considered as the implementation scope of the present application.

[0044] In addition, the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0045] Figure 1 A first structural schematic diagram of a semiconductor package structure according to the present disclosure is shown. As shown in FIG. 1, the semiconductor package structure includes a first chip 1, a second chip 2, a substrate 4, a mold layer 5, a bottom filler 6, a first chip area 7, a second chip area 8, a photoresist layer 9, a redistribution layer 3, a bridge line 31, a reinforcing structure 32, an edge lateral support 321, a top support 322, a solder layer 33, a bottom redistribution layer 34 and a top redistribution layer 35. Figure 1As shown, the semiconductor package structure includes a first chip 1, a second chip 2, a redistribution layer 3, a solder layer 33, a substrate 4, an underfill 6, and a mold layer 5. The first chip 1 can be arranged adjacent to the second chip 2. The redistribution layer 3 can include a bridge line 31 and a reinforcement structure 32. The bridge line 31 can be located below the gap between the first chip 1 and the second chip 2. The reinforcement structure 32 can be located above the bridge line 31. The solder layer 33 can be located above the reinforcement structure 32. The solder layer 33 can be in contact with the first chip 1 and the second chip 2, and can serve as a reinforcement. In some scenarios, the solder layer 33 can also be electrically connected to the first chip 1 and the second chip 2, respectively. The redistribution layer 3 can be arranged on the substrate 4 and electrically connected to the substrate 4. The underfill 6 can be filled in the bottom of the first chip 1 and the bottom of the second chip 2, and can serve as a reinforcement. The mold layer 5 can cover the first chip 1 and the second chip 2.

[0046] In this embodiment, the first chip 1 can be an ASIC chip, for example. The second chip 2 can be an HBM chip, for example. The underfill 6 can be a capillary underfill (CUF), a molded underfill (MUF), or a non-conductive paste (NCP), for example.

[0047] Figure 2 A perspective view of the reinforcement structure 32 is shown. When the reinforcement structure 32 is cut along the AA' direction, an AA' cross-sectional plane as shown in (a) of FIG. 11 can be obtained. When the solder layer 33 is arranged on the surface of the reinforcement structure 32, an AA' cross-sectional plane as shown in (b) of FIG. 11 can be obtained. Figure 2 Figure 2 Figure 2 As can be seen from FIG. 11, the entire reinforcement structure 32 can have edge lateral support members 321 and top support members 322. The edge lateral support members 321 can extend to the edges of the redistribution layer 3 and surround the bridge line 31. The edge lateral support members 321 can include at least two through holes. The top support members 322 can be located between the edge lateral support members 321 and above the bridge line 31. When the reinforcement structure 32 is subjected to stress, the stress components perpendicular to the reinforcement structure 32 can be counteracted by the material strength of the reinforcement structure 32 itself. The stress components parallel to the reinforcement structure 32 can be counteracted by the edge lateral support members 321, which can provide sufficient stress resistance to avoid the impact of structural stress on the bridge line 31.

[0048] Figure 3 ​​is a first structural schematic diagram of a reinforcing structure 32 according to the present disclosure. From a top view, the edge lateral support 321 can include two through holes. The two through holes can be located at opposite sides of the bridge line 31 respectively. The top support 322 can be located between the two through holes. The two through holes can be located between opposite corners of the bridge line 31. The center line BB’ of the top support 322 can be out of plane with the center line CC’ of the bridge line 31, and non-perpendicular, out of plane means that the angle between the center line of the top support 322 and the center line of the bridge line 31 is not a right angle. In other words, when the center lines of the top support 322 and the bridge line 31 are projected to the lower surface of the top support 322 respectively, the two center lines are in a non-perpendicular and non-parallel state. In other words, in space, the reinforcing structure 32 can withstand stress in different directions, because the structural strength of the top support 322 and the edge lateral support 321 themselves can provide sufficient stress resistance.

[0049] Figure 4 A second structural schematic diagram of a reinforcing structure according to the present disclosure is shown. From a top view, the edge lateral support 321 can include four through holes. The top support 322 located between the four through holes can present a cross shape.

[0050] Figure 5 A third structural schematic diagram of a reinforcing structure according to the present disclosure is shown. From a top view, the edge lateral support 321 can include two through holes. The top support 322 located between the two through holes can present a cross shape. Figure 4 The reinforcing structure shown, Figure 5 The reinforcing structure 32 shown also includes a top support 322 that presents a surrounding shape.

[0051] Figure 6 A fourth structural schematic diagram of a reinforcing structure according to the present disclosure is shown. From a top view, the two top supports 322 in the reinforcing structure shown Figure 4 and Figure 5 The two top supports 322 in the reinforcing structure shown are of the same size, Figure 6 The two top supports 322 in the reinforcing structure 32 shown are of different sizes.

[0052] Figure 7 A fifth structural schematic diagram of a reinforcing structure according to the present disclosure is shown. From a top view, the edge lateral support 321 can include four through holes. The top support 322 located between the four through holes can present a rectangular shape.

[0053] Figure 8A sixth structural schematic diagram of the reinforcing structure according to the present disclosure is shown. From a top view, the edge lateral support 321 can include six via holes. The top support 322 is located between the six via holes.

[0054] Figure 9 A seventh structural schematic diagram of the reinforcing structure according to the present disclosure is shown. From a top view, the edge lateral support 321 can include four via holes. As shown in (a) of FIG. 6, Figure 9 As shown in (b) of FIG. 6, the top support 322 can be a transverse structure. As shown in (c) of FIG. 6, the top support 322 can include a longitudinal structure and a transverse structure. Figure 9 As shown in (b) of FIG. 6, the top support 322 can be a transverse structure. As shown in (c) of FIG. 6, the top support 322 can include a longitudinal structure and a transverse structure. Figure 9 As shown in (b) of FIG. 6, the top support 322 can be a transverse structure. As shown in (c) of FIG. 6, the top support 322 can include a longitudinal structure and a transverse structure.

[0055] Figure 10 A second structural schematic diagram of the semiconductor package structure according to the present disclosure is shown. From a top view, in the case of including multiple chips, the chips can be distributed in multiple regions, and the reinforcing structure 32 in each region can be in different angular directions, for example, can include reinforcing structures 32 in 90-degree directions, and can also include reinforcing structures 32 in 45-degree directions. Figures 11-16 A structural schematic diagram in the manufacturing process of the semiconductor package structure according to the present disclosure is shown. The figures have been simplified for better understanding of aspects of the present disclosure.

[0056] As shown in FIG. 4, a bottom redistribution layer 34 is formed on the substrate 4. The bottom redistribution layer 34 can include a bridge line 31 located in the gap between the preset first chip region 7 and the preset second chip region 8. Figure 11 As shown in FIG. 5, a photoresist layer 9 is formed on the bottom redistribution layer 34.

[0057] Figure 12 As shown in FIG. 6, the photoresist layer 9 is patterned, and the photoresist layer 9 above the bridge line 31 can define the position of the edge lateral support in advance.

[0058] As shown in FIG. 6, the photoresist layer 9 is patterned, and the photoresist layer 9 above the bridge line 31 can define the position of the edge lateral support in advance. Figure 13 As shown in FIG. 7, a top redistribution layer 35 is formed on the bottom redistribution layer 34, and the edge lateral support is formed in the patterned photoresist layer 9. The top support is formed between the edge lateral supports, and the edge lateral support and the top support together form the reinforcing structure 32. The edge lateral support can be, for example, a via hole.

[0059] Figure 14 As shown in FIG. 7, a top redistribution layer 35 is formed on the bottom redistribution layer 34, and the edge lateral support is formed in the patterned photoresist layer 9. The top support is formed between the edge lateral supports, and the edge lateral support and the top support together form the reinforcing structure 32. The edge lateral support can be, for example, a via hole.

[0060] As shown in FIG. 8, a solder layer 33 connected to the top redistribution layer 35 and the reinforcing structure 32 is formed. Figure 15 As shown in FIG. 8, a solder layer 33 connected to the top redistribution layer 35 and the reinforcing structure 32 is formed.

[0061] Figure 16 ​​​As shown, the first chip 1 and the second chip 2 are formed on the welding layer 33 in contact with the welding layer 33. The bottom of the first chip 1 and the bottom of the second chip 2 are filled with the bottom filler 6. The mold encapsulation layer 5 encapsulating the first chip 1 and the second chip 2 is formed.

[0062] The manufacturing method of the semiconductor package structure in the embodiment can achieve the technical effects of the semiconductor package structure described above, which will not be repeated here.

[0063] Although the disclosure has been described and illustrated with reference to specific embodiments, the descriptions and illustrations have been made by way of example only. It is understood that variations in form and detail can be made without departing from the true spirit and scope of the disclosure as defined by the following claims. The drawings can not be to scale. There can be differences in the exact device implementation, which is due to, e.g., manufacturing variations, etc. Other embodiments of the disclosure can exist that are not specifically illustrated. The specification and drawings are to be regarded as illustrative in nature and not as restrictive. Modifications can be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the method disclosed herein has been described with reference to particular operations performed in a particular order, it will be understood that these operations can be combined, sub-divided, or re-ordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of operations are not a limitation of the disclosure.

Claims

1. A semiconductor package structure, comprising: a first chip; a second chip disposed adjacent to the first chip; a redistribution layer comprising a bridge line and a reinforcement structure above the bridge line, the bridge line is below a gap between the first chip and the second chip, the reinforcement structure has edge lateral supports and top supports, the edge lateral supports extend to edges of the redistribution layer and surround the bridge line, the top supports are between the edge lateral supports and above the bridge line; an underfill material filling bottoms of the first chip and the second chip and contacting the redistribution layer and the reinforcement structure.

2. The semiconductor package structure of claim 1, wherein, The semiconductor package structure further comprises a solder layer above the reinforcement structure, the solder layer is electrically connected to the first chip and the second chip respectively.

3. The semiconductor package structure of claim 1, wherein, The edge lateral supports comprise at least two vias.

4. The semiconductor package structure of claim 3, wherein, The edge lateral supports comprise two vias, and the two vias are respectively located on opposite sides of the bridge line; and A center line of the top supports is out of plane with a center line of the bridge line and is not out of plane perpendicular.

5. The semiconductor package structure of claim 3, wherein, The bridge line has opposite first and second sides; and The edge lateral supports comprise four vias, and two of the four vias are located on the first side, and the other two of the four vias are located on the second side.

6. The semiconductor package structure of claim 5, wherein, The top supports are located between the four vias, and the top supports present a cross shape and / or a surrounding shape.

7. The semiconductor package structure of claim 5, wherein, The top supports cover between the four vias, and the top supports present a rectangular shape.

8. The semiconductor package structure of claim 1, wherein, The semiconductor package structure further comprises: a mold encapsulation layer covering the first chip and the second chip. 9.A method for manufacturing a semiconductor package structure, comprising: providing a substrate; forming a bottom redistribution layer on the substrate, the bottom redistribution layer comprises a bridge line below a gap between a preset first chip region and a preset second chip region; forming a top redistribution layer and a reinforcement structure above the bridge line on the bottom redistribution layer, the reinforcement structure has edge lateral supports extending to edges of the redistribution layer and surrounding the bridge line, and top supports between the edge lateral supports and above the bridge line; forming a solder layer electrically connected to the top redistribution layer and the reinforcement structure; forming a first chip and a second chip on the solder layer and in contact with the solder layer, and filling an underfill material in bottoms of the first chip and the second chip, the underfill material contacts the redistribution layer and the reinforcement structure.

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