Semiconductor package structure

Abstract

The semiconductor package structure provided by the present disclosure integrates discrete components in advance to form a stacked passive component integration body. The stacked passive component integration body can provide a signal transmission path in the Z-axis direction, thereby shortening the internal signal transmission path between the discrete components and reducing the signal transmission loss between the discrete components. In addition, when the stacked passive component integration body is embedded in the substrate and then subjected to dielectric material compression, the generation of voids can be avoided, thereby improving productivity and yield.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor package structure. BACKGROUND

[0002] Figures 1-3 A method of integrating passive elements is shown, first referring to Figure 1 , a substrate 1 with cavities 101 is provided, then referring to Figure 2 , a plurality of passive elements 2 are embedded into the cavities 101 respectively by using a pick-and-place device, and finally referring to Figure 3 , a dielectric material 3 is compressed, followed by laser forming through holes and electroplating forming a circuit layer 4.

[0003] However, by using the above method, the planar placement method for integrating embedded passive elements results in an increase in the size in the X-Y plane. In addition, the connection path between the passive elements 2 is long, resulting in a large signal loss. When the passive elements 2 are picked and placed multiple times, the spacing between the passive elements 2 is inconsistent due to the pick-and-place process error, and when the spacing is small, the dielectric material 3 is not easy to compress, and voids are easily generated in the dielectric material 3. SUMMARY

[0004] The present disclosure provides a semiconductor package structure.

[0005] In a first aspect, the present disclosure provides a semiconductor package structure, comprising: a stacked passive element integration body having a plurality of passive elements stacked from bottom to top, the stacked passive element integration body providing a signal transmission path in a first direction.

[0006] In some optional embodiments, a first conductive layer is provided between the passive elements adjacent in the first direction in the stacked passive element integration body to realize electrical connection in the first direction.

[0007] In some optional embodiments, the passive element has a pair of end electrodes, and the first conductive layer is provided on the end electrodes.

[0008] In some optional embodiments, a non-conductive layer is provided between the passive elements adjacent in the first direction in the stacked passive element integration body.

[0009] In some optional embodiments, the passive element has a pair of end electrodes, and the non-conductive layer is provided on the end electrodes.

[0010] In some optional embodiments, an insulating layer is provided between the passive elements adjacent in the first direction in the stacked passive element integration body.

[0011] In some embodiments, the passive element integrated body further comprises:

[0012] In some embodiments, the passive element integrated body further comprises:

[0013] In some embodiments, the passive element integrated body further comprises:

[0014] In some embodiments, the passive element integrated body further comprises:

[0015] In some embodiments, the passive element integrated body further comprises:

[0016] In some embodiments, the passive element integrated body further comprises:

[0017] In some embodiments, the passive element integrated body further comprises:

[0018] In some embodiments, the first direction is Z direction, the second direction is X direction and the third direction is Y direction.

[0019] In some embodiments, the passive element integrated body further comprises:

[0020] In some embodiments, the passive element integrated body further comprises:

[0021] In some embodiments, the semiconductor package structure further comprises:

[0022] In some embodiments, the semiconductor package structure further comprises:

[0023] In some embodiments, the semiconductor package structure further comprises:

[0024] In some embodiments, the semiconductor package structure further comprises:

[0025] In some optional embodiments, the semiconductor package structure further comprises:

[0026] a power management chip, the stacked passive element integrated body is arranged on the power management chip, and the stacked passive element is electrically connected with the power management chip.

[0027] In some optional embodiments, the semiconductor package structure further comprises:

[0028] a second mold sealing layer, covering the power management chip.

[0029] In some optional embodiments, the semiconductor package structure further comprises:

[0030] a redistribution layer, arranged between the second mold sealing layer and the stacked passive element integrated body, and electrically connected with the stacked passive element integrated body and the power management chip respectively.

[0031] The semiconductor package structure provided by the present disclosure integrates passive elements in advance to form a stacked passive element integrated body, which can provide a signal transmission path in the Z-axis direction, thereby shortening the internal signal transmission path between passive elements and reducing the signal transmission loss between passive elements. In addition, when the stacked passive element integrated body is embedded in the substrate and then subjected to dielectric material compression, the generation of voids can be avoided, thereby improving production capacity and yield. BRIEF DESCRIPTION OF DRAWINGS

[0032] Other features, objects, and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments made with reference to the following drawings:

[0033] Figures 1-3 is a structural schematic diagram in the manufacturing process of the integrated passive element;

[0034] Figures 4-7 is a first structural schematic diagram to a fourth structural schematic diagram of the semiconductor package structure according to the present disclosure;

[0035] Figures 8 to 15 is a structural schematic diagram in the manufacturing process of the semiconductor package structure according to the present disclosure.

[0036] SYMBOL DESCRIPTION:

[0037] 1 - substrate, 101 - cavity, 2 - passive element, 21 - terminal electrode, 3 - compression material, 4 - circuit layer, 5 - stacked passive element integrated body, 6 - first conductive layer, 7 - non-conductive layer, 8 - insulating layer, 9 - second conductive layer, 10 - first mold sealing layer, 11 - dielectric material, 12 - power management chip, 13 - second mold sealing layer, 14 - redistribution layer, 15 - adhesive layer, 16 - carrier. DETAILED DESCRIPTION

[0038] The specific embodiments of the present disclosure will be described below with reference to the drawings and examples, and those skilled in the art can easily understand the technical problems solved by the present disclosure and the technical effects generated by the content recorded in the specification. It should be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, only the parts related to the application are shown in the drawings for ease of description.

[0039] It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the specification are only used to cooperate with the content recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the implementation conditions of the present disclosure, so they do not have technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be generated by the present disclosure, should still fall within the scope of the technical content disclosed by the present disclosure. At the same time, the terms such as "upper", "first", "second" and "one" used in the specification are only for the convenience of clear understanding of the description, and are not used to limit the scope of the present disclosure, and the change or adjustment of the relative relationship without substantial change of the technical content is also considered as the implementation of the present disclosure.

[0040] It should also be noted that the embodiments of the present disclosure correspond to the longitudinal cross-section in the front view direction, the transverse cross-section in the right view direction, and the horizontal cross-section in the upper view direction.

[0041] It should be readily understood that the meaning of "on", "above" and "on top of" in the present disclosure should be interpreted in the broadest sense, so that "on" not only means "directly on" but also means "on" including intermediate components or layers between them.

[0042] Furthermore, spatial relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. Spatial relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0043] In addition, the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict, which will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0044] Figure 4 is a first structural schematic diagram of a semiconductor package structure according to the present disclosure. As shown in Figure 4 The semiconductor package structure includes a stacked passive element integrated body 5. The stacked passive element integrated body 5 can have a plurality of passive elements 2 stacked from bottom to top. The stacked passive element integrated body 5 can provide a signal transmission path in a first direction. The stacked passive element integrated body 5 can include a first mold layer 10. The first mold layer 10 can cover the plurality of passive elements 2 and fill the gaps between the passive elements 2.

[0045] In this embodiment, the passive element 2 can be a discrete component, such as a resistor, capacitor, or inductor. The first direction can be the Z-axis direction. The first direction can be a direction perpendicular to the upper surface of any passive element 2. A first conductive layer 6 can be provided between adjacent passive elements 2 along the first direction in the stacked passive element assembly 5 to achieve electrical connection in the first direction. Specifically, the passive element 2 can have a pair of end electrodes, and the first conductive layer 6 can be disposed on the end electrodes. The first conductive layer 6 can be made of a conductive material of metal or metal alloy, such as gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof. The first conductive layer 6 can be made of conductive adhesive, such as silver-based conductive adhesive, gold-based conductive adhesive, or copper-based conductive adhesive. Conductive adhesive is an adhesive that has a certain conductivity after curing or drying. Conductive adhesive has conductivity and bonding strength. The passive elements 2 along the first direction can be connected by conductive adhesive, forming an electrical path between the passive elements 2. The resistance between passive elements 2 can be reduced by conductive adhesive. In addition, compared to the reliability issues of using solder to connect passive components in some cases (solder has a low melting point, and repeated thermal processing may cause the solder to melt, resulting in reliability issues), this disclosure uses a conductive material to achieve electrical connection of the passive component 2 along the first direction, which still has good connection characteristics and reliability after repeated thermal processing.

[0046] In this embodiment, an insulating layer 8 may be provided between adjacent passive components 2 along the first direction in the stacked passive component assembly 5. From a top view, an insulating layer 8 may be provided between adjacent passive components 2 along the second direction in the stacked passive component assembly 5 (e.g., Figure 10 (As shown in Figure (a)). In the stacked passive component assembly 5, an insulating layer 8 can be provided between adjacent passive components 2 along a third direction. The first direction, the second direction, and the third direction can be perpendicular to each other. The first direction can be the Z direction, the second direction can be the X direction, and the third direction can be the Y direction. The insulating layer 8 can be provided between adjacent passive components 2 in each direction, which can enhance the bonding strength between the passive components 2 and effectively prevent short circuits when connected by electroplating later.

[0047] In this embodiment, from a top view, a second conductive layer 9 may be provided between adjacent passive components 2 along the second direction in the stacked passive component assembly 5 (e.g., ...). Figure 14 (As shown in Figure (b)). In the stacked passive component assembly 5, a second conductive layer 9 may be provided between adjacent passive components 2 along the third direction (e.g., Figure 14 (As shown in Figure (b)). This allows for the formation of signal transmission paths in various directions, fulfilling the electrical connection requirements in each direction.

[0048] In this embodiment, the stacked passive component integration 5 can include a plurality of stacked layers along the first direction. Each stacked layer can include a plurality of passive components 2. Each passive component 2 in each stacked layer can be arranged at equal intervals (as shown in FIG. 1(a)) or at unequal intervals (as shown in FIG. 1(b)) from a top view. Figure 8 In this embodiment, the stacked passive component integration 5 can include a plurality of stacked layers along the first direction. Each stacked layer can include a plurality of passive components 2. Each passive component 2 in each stacked layer can be arranged at equal intervals (as shown in FIG. 1(a)) or at unequal intervals (as shown in FIG. 1(b)) from a top view. Figure 8 In this embodiment, the stacked passive component integration 5 can include a plurality of stacked groups. Each stacked group can include a plurality of passive components 2. The intervals between the passive components 2 in each stacked group are different from the intervals between the stacked groups (as shown in FIG. 1(b)). Figure 8 In this embodiment, the stacked passive component integration 5 can include a plurality of stacked groups. Each stacked group can include a plurality of passive components 2. The intervals between the passive components 2 in each stacked group are different from the intervals between the stacked groups (as shown in FIG. 1(b)).

[0049] In an actual application scenario, the stacked layers along the first direction in the stacked passive component integration 5 can be a first capacitor layer, an inductor layer, and a second capacitor layer in sequence. The first capacitor layer / second capacitor layer can include a plurality of capacitors. The inductor layer can include a plurality of inductors.

[0050] Figure 5 is a second structural diagram of a semiconductor package structure according to the present disclosure. According to the electrical connection requirement between the adjacent passive components 2 along the first direction in the stacked passive component integration 5, a first conductive layer 6 or a non-conductive layer 7 is arranged between the adjacent passive components 2. As shown in FIG. 2(a), when no electrical connection is required, a non-conductive layer 7 can be arranged between the adjacent passive components 2 along the first direction in the stacked passive component integration 5. As shown in FIG. 2(b), when electrical connection is required, a first conductive layer 6 can be arranged between the adjacent passive components 2 along the first direction in the stacked passive component integration 5. Figure 5 is a second structural diagram of a semiconductor package structure according to the present disclosure. According to the electrical connection requirement between the adjacent passive components 2 along the first direction in the stacked passive component integration 5, a first conductive layer 6 or a non-conductive layer 7 is arranged between the adjacent passive components 2. As shown in FIG. 2(a), when no electrical connection is required, a non-conductive layer 7 can be arranged between the adjacent passive components 2 along the first direction in the stacked passive component integration 5. As shown in FIG. 2(b), when electrical connection is required, a first conductive layer 6 can be arranged between the adjacent passive components 2 along the first direction in the stacked passive component integration 5. Figure 5 is a second structural diagram of a semiconductor package structure according to the present disclosure. According to the electrical connection requirement between the adjacent passive components 2 along the first direction in the stacked passive component integration 5, a first conductive layer 6 or a non-conductive layer 7 is arranged between the adjacent passive components 2. As shown in FIG. 2(a), when no electrical connection is required, a non-conductive layer 7 can be arranged between the adjacent passive components 2 along the first direction in the stacked passive component integration 5. As shown in FIG. 2(b), when electrical connection is required, a first conductive layer 6 can be arranged between the adjacent passive components 2 along the first direction in the stacked passive component integration 5.

[0051] Figure 6 is a third structural diagram of a semiconductor package structure according to the present disclosure. Figure 6 As shown in FIG. 3, the semiconductor package structure can include a substrate 1, a stacked passive component integration 5, and a dielectric material 11. The substrate 1 can have a cavity 101. The stacked passive component integration 5 can be arranged in the cavity 101. The dielectric material 11 can be filled between the stacked passive component integration 5 and the cavity 101.

[0052] In this embodiment, the substrate 1 can be a Printed Circuit Board (PCB) for example. The first mold encapsulation layer 10 in the stacked passive component integrated body 5 can encapsulate the plurality of passive components and fill the gaps between the passive components 2, and the insulating layer 8 in the stacked passive component integrated body 5 can fill the gaps between the passive components 2, so that when the stacked passive component integrated body 5 is placed in the cavity 101 of the substrate 1 in the subsequent process, and the dielectric material 11 is pressed, the generation of voids can be avoided, and the process yield can be increased. In this way, the pressing of the dielectric material can be facilitated in some cases where the spacing between the passive components 2 is small, and voids are less likely to occur in the dielectric material.

[0053] Figure 7 is a fourth structure diagram of a semiconductor package structure according to the present disclosure. Figure 7 The semiconductor package structure shown can include a stacked passive component integrated body 5, a power management chip 12, a redistribution layer 14, and a second mold encapsulation layer 13. The second mold encapsulation layer 13 can encapsulate the power management chip 12. The second mold encapsulation layer 13 can be substantially separated from the first mold encapsulation layer 10. The stacked passive component integrated body 5 can be disposed on the power management chip 12 / second mold encapsulation layer 13. The redistribution layer 14 can be disposed between the second mold encapsulation layer 13 and the stacked passive component integrated body 5, and electrically connected to the stacked passive component integrated body 5 and the power management chip 12, respectively. The stacked passive component integrated body 5 can be electrically connected to the power management chip 12 through the redistribution layer 14. Here, the redistribution layer 14 and the power management chip 12 can be used as a base, and the stacked passive component integrated body 5 can be disposed thereon, so as to shorten the electrical path between the power management chip 12 and the stacked passive component integrated body 5.

[0054] Please refer to Figures 8 to 15 , Figures 8 to 15 shows a structure diagram in the manufacturing process of a semiconductor package structure according to the present disclosure.

[0055] In the first step, as shown in Figure 8 , the passive components 2 are picked up and placed on a carrier 16 provided with an adhesive layer 15 to form a first stacked layer.

[0056] From a top view, as shown in Figure 8 (a) of the figure, the passive components 2 in the first stacked layer can be arranged at equal intervals. As shown in Figure 8As shown in FIG. B, the passive elements 2 in the first stack layer can be arranged at different intervals. Specifically, the passive elements 2 in the first stack layer can be distributed at different positions, for example, can be distributed to present a first group A, a second group B, and a third group C, and the interval between the passive elements 2 in each group can be different from the interval between the groups.

[0057] In the second step, as shown in FIG. 2, a first conductive layer 6 is arranged on the passive elements 2 in the first stack layer (in the Z-axis direction). Figure 9 Figure 9 As shown in FIG. A and FIG. B, the semiconductor package structure is viewed from the top. Figure 9

[0058] In the third step, as shown in FIG. 3, an insulating layer 8 is arranged on the passive elements 2 in the first stack layer (in the Z-axis direction). Here, the order between the second step and the third step can also be changed, that is, the insulating layer 8 can be arranged first and then the first conductive layer 6 is arranged. Figure 10 As shown in FIG. A, the insulating layer 8 can be arranged between the passive elements 2 adjacent in the Y-axis direction, which can strengthen the bonding strength between the passive elements 2, and can effectively prevent short circuit when the connection is made by electroplating later.

[0059] Figure 10 In the fourth step, as shown in FIG. 4, the passive elements 2 are placed on the first stack layer to form a second stack layer.

[0060] In the fifth step, as shown in FIG. 5, the first conductive layer 6 is arranged on the passive elements 2 in the second stack layer. The insulating layer 8 is arranged on the passive elements 2 in the second stack layer. Figure 11 Figure 11 As shown in FIG. A and FIG. B, the semiconductor package structure is viewed from the top. Figure 11

[0061] In the sixth step, as shown in FIG. 6, the passive elements 2 are placed on the second stack layer to form a third stack layer. Figure 12A Figure 12A As shown in FIG. A and FIG. B, the semiconductor package structure is viewed from the top. Figure 12A In the fifth step, as shown in FIG. 5, the first conductive layer 6 and / or the non-conductive layer 7 are arranged on the passive elements 2 in the second stack layer. The insulating layer 8 is arranged on the passive elements 2 in the second stack layer. Figure 12B

[0062] In the seventh step, as shown in FIG. 7, the passive elements 2 are placed on the third stack layer to form a fourth stack layer. Figure 13 Figure 13 As shown in FIG. A and FIG. B, the semiconductor package structure is viewed from the top. Figure 13

[0063] In the eighth step, as shown in FIG. 8, the passive elements 2 are placed on the fourth stack layer to form a fifth stack layer. Figure 14 ​​​​​​​​​As shown, the second conductive layer 9 is formed along the X-axis direction, the Y-axis direction and the Z-axis direction.

[0064] As shown in the plan view, Figure 14 As shown in the plan view, Figure 14 As shown in the plan view, Figure 14 As shown in the plan view of (b) of FIG. 1, the second conductive layer 9 is formed between the passive elements 2 within each group, but not formed between the groups. This can be achieved by selective plating. Specifically, the distance between the groups can be made sufficiently large (the distance between the groups is larger than the distance between the passive elements 2 within each group), so that the adjacent passive elements 2 are electrically connected by selective plating, and the adjacent passive elements 2 that are sufficiently far apart are not electrically connected. Thus, the second conductive layer 9 is formed only between the passive elements 2 within each group, but not formed between the groups. The selective plating can be achieved by controlling the distance between the adjacent passive elements 2, by controlling the process parameters (such as current density / time / temperature, etc.), or by pre-setting the insulating material to block the plating. In this way, various internal connection lines can be formed in the stacked passive element integrated body 5 to achieve different electrical requirements.

[0065] In addition, the passive elements 2 within each group can be electrically connected to each other in the X-Y plane. The passive elements 2 within each group can also not be electrically connected to each other in the X-Y plane, for example, one passive element 2 can be electrically connected to the passive element 2 on the opposite side, but not electrically connected to the adjacent passive element 2. The first conductive layer 6 can be provided between the adjacent passive elements 2 in the Z-axis direction within each group to electrically connect them, or the non-conductive layer 7 can be provided to isolate them.

[0066] As shown in the plan view, Figure 15 As shown in the plan view, the first mold layer 10 is formed to cover the passive elements 2, and then the first mold layer 10 is thinned to expose the upper surface of the passive elements 2 in the third stacked layer, obtaining the stacked passive element integrated body 5. Here, the thinning can be grinding or chemical mechanical polishing (CMP) process. The thinning of the first mold layer 10 exposes the end electrodes of the passive elements 2, which can be used as the connection for the upper and lower conduction of the stacked passive element integrated body 5. Figure 15 As shown in the plan view, Figure 15 As shown in the plan view,

[0067] The semiconductor package structure provided by the present disclosure integrates the passive elements 2 in advance to form a stacked passive element integration body 5, which can provide a signal transmission path in the Z-axis direction, thereby shortening the internal signal transmission path between the passive elements 2 and reducing the signal transmission loss between the passive elements 2. In addition, when the dielectric material 11 is pressed after the stacked passive element integration body 5 is embedded in the substrate 1, the generation of voids can be avoided, and the yield and yield can be improved.

[0068] Although the present disclosure has been described and illustrated with reference to specific embodiments, the description and illustrations have been made by way of example only. It is understood that various changes in the details can be made by persons of ordinary skill in the art without departing from the true spirit and scope of the present disclosure. The drawings are not necessarily to scale. There can be differences between the technology in the disclosure and the actual equipment due to variables in the manufacturing process, etc. There can be other embodiments of the present disclosure that are not specifically illustrated. The specification and drawings should be considered illustrative only and not restrictive. Modifications can be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed in the present disclosure have been described with reference to specific operations performed in a specific order, it should be understood that these operations can be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, the order and grouping of operations do not limit the present disclosure unless specifically indicated in the present disclosure.

Claims

1. A semiconductor package structure, comprising: a stacked passive component integrated body having a plurality of passive components stacked from bottom to top, the stacked passive component integrated body providing a signal transmission path in a first direction; the stacked passive component integrated body comprising a plurality of stacked groups, each of the stacked groups comprising a plurality of passive components, a pitch between the passive components in each of the stacked groups being different from a pitch between the stacked groups; a second conductive layer being provided between passive components adjacent in a second direction or a third direction in the stacked passive component integrated body, the second conductive layer being formed between the passive components in each of the stacked groups but not formed between the stacked groups; in each of the stacked groups, one passive component is electrically connected with a diagonally-adjacent passive component in an X-Y plane, and is not electrically connected with an adjacent passive component.

2. The semiconductor package structure of claim 1, wherein, a first conductive layer being provided between passive components adjacent in the first direction in the stacked passive component integrated body to achieve electrical connection in the first direction.

3. The semiconductor package structure of claim 2, wherein, an insulating layer being provided between passive components adjacent in the first direction or the second direction or the third direction in the stacked passive component integrated body.

4. The semiconductor package structure of claim 1, wherein, the stacked passive component integrated body further comprising: a first mold encapsulation layer encapsulating the plurality of passive components and filling gaps between the passive components.

5. The semiconductor package structure of claim 4, wherein, the semiconductor package structure further comprising: a substrate having a cavity, the stacked passive component integrated body being disposed in the cavity; a dielectric material filling between the stacked passive component integrated body and the cavity.

6. The semiconductor package structure of claim 5, wherein, the semiconductor package structure further comprising: a power management chip, the stacked passive component integrated body being disposed on the power management chip, the stacked passive component integrated body being electrically connected with the power management chip.

7. The semiconductor package structure of claim 6, wherein, the semiconductor package structure further comprising: a redistribution layer being disposed between the power management chip and the stacked passive component integrated body, and being electrically connected with the stacked passive component integrated body and the power management chip respectively.

8. The semiconductor package structure of claim 7, wherein, the semiconductor package structure further comprising: a second mold encapsulation layer encapsulating the power management chip and being substantially separated from the first mold encapsulation layer.

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