Display substrate, method for preparing same, and display device

Abstract

A display substrate, a method for manufacturing the same, and a display device. In a plane perpendicular to the display substrate, the display substrate includes a polysilicon transistor layer, a first interlayer insulating layer, a first hydrogen barrier layer, a second buffer layer, and an oxide transistor layer sequentially disposed on a substrate, wherein: the polysilicon transistor layer includes active layers and gate electrodes of a plurality of polysilicon transistors, and the oxide transistor layer includes active layers and gate electrodes of a plurality of oxide transistors; the hydrogen element content in the first interlayer insulating layer is greater than the hydrogen element content in the first hydrogen barrier layer, or the atomic ratio of silicon element to oxygen element in the first hydrogen barrier layer is greater than the atomic ratio of silicon element to oxygen element in the second buffer layer. The present disclosure reduces the influence of hydrogen elements in the polysilicon transistor layer on the oxide transistor layer, and ensures the stability of polysilicon transistor and oxide transistor devices.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to, but are not limited to, the field of display technologies, and in particular, to a display substrate, a method for manufacturing the same, and a display device. Background Art

[0002] An organic light emitting diode (OLED) is an active light emitting display device, which has the advantages of light emission, ultra-thin, wide viewing angle, high brightness, high contrast ratio, low power consumption, extremely high response speed, etc. According to different driving methods, OLEDs can be divided into two types: passive matrix driving (PM) type and active matrix driving (AM) type. Among them, AMOLED is a current-driven device, and an independent thin film transistor (TFT) is used to control each sub-pixel, and each sub-pixel can be continuously and independently driven to emit light. Summary of the Invention

[0003] Embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device, which can improve the display effect.

[0004] Embodiments of the present disclosure provide a display substrate. In a plane perpendicular to the display substrate, the display substrate includes a polysilicon transistor layer, a first interlayer insulating layer, a first hydrogen barrier layer, a second buffer layer, and an oxide transistor layer, which are sequentially disposed on a substrate, where: the polysilicon transistor layer includes active layers and gate electrodes of a plurality of polysilicon transistors, and the oxide transistor layer includes active layers and gate electrodes of a plurality of oxide transistors; the hydrogen element content of the first interlayer insulating layer is greater than the hydrogen element content of the first hydrogen barrier layer, or the atomic ratio of silicon element and oxygen element of the first hydrogen barrier layer is greater than the atomic ratio of silicon element and oxygen element of the second buffer layer.

[0005] In an exemplary embodiment, the first hydrogen barrier layer includes a second interlayer insulating layer, where the atomic ratio of silicon element and nitrogen element of the first interlayer insulating layer is greater than the atomic ratio of silicon element and nitrogen element of the second interlayer insulating layer and less than twice the atomic ratio of silicon element and nitrogen element of the second interlayer insulating layer.

[0006] In an exemplary embodiment, the atomic ratio of silicon element and nitrogen element of the second interlayer insulating layer is between 0.7 and 0.8.

[0007] In an exemplary embodiment, the Si-H bond content of the second interlayer insulating layer is 2 to 5 times that of the first interlayer insulating layer.

[0008] In an exemplary embodiment, the content of silicon-hydrogen (Si-H) bonds in the second interlayer insulating layer is 1% to 3%, and the refractive index is between 1.8 and 1.9.

[0009] In an exemplary embodiment, the stress of the second interlayer insulating layer is controlled between -200 Mpa and 400 Mpa, and the content of nitrogen-hydrogen bonds is 5% to 10%.

[0010] In an exemplary embodiment, the first hydrogen-blocking layer includes a first buffer layer, wherein the atomic ratio of silicon element to oxygen element in the first buffer layer is less than twice the atomic ratio of silicon element to oxygen element in the second buffer layer.

[0011] In an exemplary embodiment, the atomic ratio of silicon element to oxygen element in the first buffer layer is between 1.1 and 1.2.

[0012] In an exemplary embodiment, the first hydrogen-blocking layer includes a second interlayer insulating layer and a first buffer layer disposed on the second interlayer insulating layer, wherein the atomic ratio of silicon element to nitrogen element in the first interlayer insulating layer is greater than the atomic ratio of silicon element to nitrogen element in the second interlayer insulating layer and less than twice the atomic ratio of silicon element to nitrogen element in the second interlayer insulating layer; the atomic ratio of silicon element to oxygen element in the first buffer layer is less than twice the atomic ratio of silicon element to oxygen element in the second buffer layer.

[0013] In an exemplary embodiment, the display substrate further includes a fourth conductive layer on the oxide transistor layer and a second hydrogen-blocking layer covering the fourth conductive layer, wherein: the fourth conductive layer includes the first and second poles of a plurality of polysilicon transistors and the first and second poles of a plurality of oxide transistors; the second hydrogen-blocking layer includes a first passivation layer and a second passivation layer disposed on the first passivation layer, the hydrogen element content of the first passivation layer is lower than that of the second passivation layer, and the atomic ratio of silicon element to oxygen element in the first passivation layer is greater than that in the second passivation layer.

[0014] In an exemplary embodiment, the material of the first passivation layer is silicon oxide, and the material of the second passivation layer is silicon nitride.

[0015] In an exemplary embodiment, the polysilicon transistor layer includes a first semiconductor layer, a first conductive layer, and a second conductive layer that are sequentially disposed on a substrate, and the oxide transistor layer includes a second semiconductor layer and a third conductive layer that are sequentially disposed on the first hydrogen barrier layer, where: the first semiconductor layer includes active layers of a plurality of polysilicon transistors, the first conductive layer includes gate electrodes of a plurality of polysilicon transistors and a first electrode plate of a storage capacitor, the second conductive layer includes a second electrode plate of the storage capacitor, the second semiconductor layer includes active layers of a plurality of oxide transistors, and the third conductive layer includes gate electrodes of a plurality of oxide transistors.

[0016] In an exemplary embodiment, the polysilicon transistor layer includes a first semiconductor layer and a first conductive layer that are sequentially disposed on a substrate, and the oxide transistor layer includes a second semiconductor layer, a second conductive layer, and a third conductive layer that are sequentially disposed on the first hydrogen barrier layer, where: the first semiconductor layer includes active layers of a plurality of polysilicon transistors, the first conductive layer includes gate electrodes of a plurality of polysilicon transistors and a first electrode plate of a storage capacitor; the second semiconductor layer includes active layers of a plurality of oxide transistors, the second conductive layer includes a second electrode plate of the storage capacitor, and the third conductive layer includes gate electrodes of a plurality of oxide transistors.

[0017] An embodiment of the present disclosure further provides a display device, including: the display substrate as described above.

[0018] An embodiment of the present disclosure further provides a method for manufacturing a display substrate, including: forming a polysilicon transistor layer on a substrate, the polysilicon transistor layer including active layers and gate electrodes of a plurality of polysilicon transistors; sequentially forming a first interlayer insulating layer, a first hydrogen barrier layer, and a second buffer layer on the polysilicon transistor layer, where the hydrogen content of the first interlayer insulating layer is greater than that of the first hydrogen barrier layer, or the atomic ratio of silicon element to oxygen element of the first hydrogen barrier layer is greater than that of the second buffer layer; forming an oxide transistor layer on the second buffer layer, the oxide transistor layer including active layers and gate electrodes of a plurality of oxide transistors.

[0019] The display substrate, the method for manufacturing the same, and the display device according to the embodiments of the present disclosure reduce the influence of hydrogen elements in the polysilicon transistor layer on the oxide transistor layer by disposing the first interlayer insulating layer, the first hydrogen barrier layer, and the second buffer layer between the polysilicon transistor layer and the oxide transistor layer, and ensure the stability of the polysilicon transistor and oxide transistor devices. In addition, the manufacturing process of the present disclosure can be well compatible with the existing manufacturing process, the process implementation is simple, easy to implement, has high production efficiency, low production cost, and high yield.

[0020] Other features and advantages of the present disclosure will be set forth in the following description, and in part will be obvious from the description, or may be learned by practice of the present disclosure. Other advantages of the present disclosure may be realized and obtained by the means set forth in the description and the drawings. Description of the Drawings

[0021] The drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the description. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure.

[0022] Figure 1 It is a schematic structural diagram of a display device;

[0023] Figure 2 It is a schematic plan view of a display substrate;

[0024] Figure 3 It is a schematic equivalent circuit diagram of a pixel driving circuit;

[0025] Figure 4 It is a timing diagram of the operation of a pixel driving circuit;

[0026] Figure 5a It is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0027] Figure 5b It is Figure 5a a cross-sectional view taken along the line B-B in

[0028] Figure 5c and Figure 5d It is a test result diagram of the O2 release amount and NOx release amount of the first buffer layer;

[0029] Figure 5e It is a test result diagram of the Si-O bond position of the first buffer layer;

[0030] Figure 5f It is a test result diagram of the NOx defect state of the second buffer layer;

[0031] Figure 6a It is a schematic diagram of a display substrate according to the present disclosure after forming a first semiconductor layer pattern;

[0032] Figure 6b It is Figure 6a a cross-sectional view taken along the line B-B in

[0033] Figure 7a It is a schematic diagram of a display substrate according to the present disclosure after forming a first conductive layer pattern;

[0034] Figure 7b It is Figure 7a a cross-sectional view taken along the line B-B in

[0035] Figure 8a Schematic diagram of a display substrate after forming a second interlayer insulating layer pattern according to the present disclosure;

[0036] Figure 8b is Figure 8a Cross-sectional view taken along line B-B in

[0037] Figure 9a Schematic diagram of a display substrate after forming a second semiconductor layer pattern according to the present disclosure;

[0038] Figure 9b is Figure 9a Cross-sectional view taken along line B-B in

[0039] Figure 10a Schematic diagram of a display substrate after forming a third conductive layer pattern according to the present disclosure;

[0040] Figure 10b is Figure 10a Cross-sectional view taken along line B-B in

[0041] Figure 11a Schematic diagram of a display substrate after forming a polysilicon via pattern according to the present disclosure;

[0042] Figure 11b is Figure 11a Cross-sectional view taken along line B-B in

[0043] Figure 12a Schematic diagram of a display substrate after forming an oxide via pattern according to the present disclosure;

[0044] Figure 12b is Figure 12a Cross-sectional view taken along line B-B in

[0045] Figure 13a Schematic diagram of a display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0046] Figure 13b is Figure 13a Cross-sectional view taken along line B-B in

[0047] Figure 14a Schematic diagram of a display substrate after forming a first planarization layer pattern according to the present disclosure;

[0048] Figure 14b is Figure 14a Cross-sectional view taken along line B-B in Detailed implementation manners

[0049] To make the objectives, technical solutions, and advantages of the present disclosure more clearly understood, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The implementation manners can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the manners and contents can be transformed into various forms without departing from the gist and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following implementation manners. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined arbitrarily with each other.

[0050] The drawing ratios in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in the present disclosure are only schematic diagrams of the structure, and one implementation manner of the present disclosure is not limited to the shapes, values, etc. shown in the drawings.

[0051] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of components, rather than to limit the quantity.

[0052] In this specification, for convenience, terms indicating orientation or positional relationships such as "middle part", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of the components with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationships of the components are appropriately changed according to the directions describing each component. Therefore, it is not limited to the terms described in the specification, and can be appropriately replaced according to the situation.

[0053] In this specification, unless otherwise clearly defined and limited, the terms "mounted", "connected", and "coupled" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific situations.

[0054] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0055] In this specification, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In cases such as when using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" sometimes swap with each other. Therefore, in this specification, the "source electrode" and "drain electrode" can swap with each other, and the "source terminal" and "drain terminal" can swap with each other.

[0056] In this specification, "electrically connected" includes cases where components are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0057] In this specification, "parallel" means a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. Additionally, "perpendicular" means a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes an angle state of 85° or more and 95° or less.

[0058] In this specification, "film" and "layer" can be swapped with each other. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0059] In this specification, triangles, rectangles, trapezoids, pentagons, hexagons, etc. are not strictly defined and can be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc. There can be some small deformations due to tolerances, and there can be chamfers, rounded edges, and deformations, etc.

[0060] "About" in this disclosure means not strictly defining the boundary and allowing values within the process and measurement error ranges.

[0061] Figure 1 It is a schematic structural diagram of a display device. As Figure 1As shown, the OLED display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light-emitting signal lines (E1 to Eo), and a plurality of sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide a gray value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light-emitting driver to the light-emitting driver. The data driver may generate data voltages to be provided to the data signal lines D1, D2, D3,..., and Dn by using the gray value and the control signal received from the timing controller. For example, the data driver may sample the gray value using a clock signal and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, and n may be a natural number. The scan driver may generate scan signals to be provided to the scan signal lines S1, S2, S3,..., and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide scan signals having conductive level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register and may generate scan signals in such a way that a scan start signal provided in the form of a conductive level pulse is sequentially transmitted to a next-stage circuit under the control of a clock signal, and m may be a natural number. The light-emitting driver may generate emission signals to be provided to the light-emitting signal lines E1, E2, E3,..., and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light-emitting driver may sequentially provide emission signals having cut-off level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver may be configured in the form of a shift register and may generate emission signals in such a way that an emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to a next-stage circuit under the control of a clock signal, and o may be a natural number. The pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light-emitting signal line, and i and j may be natural numbers. The sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and the j-th data signal line.

[0062] Figure 2 It is a schematic plan view of a display substrate. As Figure 2As shown, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first light-emitting unit (sub-pixel) P1 that emits first-color light, a second light-emitting unit P2 that emits second-color light, and a third light-emitting unit P3 that emits third-color light. The first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to the pixel driving circuits of the respective light-emitting units, and the light-emitting devices are configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuits of the respective light-emitting units.

[0063] In an exemplary embodiment, the pixel unit P may include a red (R) light-emitting unit, a green (G) light-emitting unit, and a blue (B) light-emitting unit, or may include a red light-emitting unit, a green light-emitting unit, a blue light-emitting unit, and a white light-emitting unit, which is not limited herein in the present disclosure. In an exemplary embodiment, the shape of the light-emitting unit in the pixel unit may be rectangular, diamond-shaped, pentagonal, or hexagonal. When the pixel unit includes three light-emitting units, the three light-emitting units may be arranged in a horizontal side-by-side, vertical side-by-side, or triangular pattern. When the pixel unit includes four light-emitting units, the four light-emitting units may be arranged in a horizontal side-by-side, vertical side-by-side, or square pattern, which is not limited herein in the present disclosure.

[0064] In some exemplary embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 3 It is an equivalent circuit schematic diagram of a pixel driving circuit. As Figure 3 shown, the pixel driving circuit may include seven transistors (a first transistor T1 to a seventh transistor T7), one storage capacitor C, and a plurality of signal lines (a data signal line Da, a first scan signal line G1, a second scan signal line G2, a first reset signal line Re1, a second reset signal line Re2, a first initialization signal line INIT1, a second initialization signal line INIT2, a first power supply line VDD, a second power supply line VSS, and a light-emitting signal line EM).

[0065] In some exemplary embodiments, the gate electrode of the first transistor T1 is connected to the second reset signal line Re2, the first pole of the first transistor T1 is connected to the second initial signal line INIT2, and the second pole of the first transistor is connected to the first node N1. The gate electrode of the second transistor T2 is connected to the second scan signal line G2, the first pole of the second transistor T2 is connected to the first node N1, and the second pole of the second transistor T2 is connected to the third node N3. The gate electrode of the third transistor T3 is connected to the first node N1, the first pole of the third transistor T3 is connected to the second node N2, and the second pole of the third transistor T3 is connected to the third node N3. The gate electrode of the fourth transistor T4 is connected to the first scan signal line G1, the first pole of the fourth transistor T4 is connected to the data signal line Da, and the second pole of the fourth transistor T4 is connected to the second node N2. The gate electrode of the fifth transistor T5 is connected to the emission signal line EM, the first pole of the fifth transistor T5 is connected to the first power supply line VDD, and the second pole of the fifth transistor T5 is connected to the second node N2. The gate electrode of the sixth transistor T6 is connected to the emission signal line EM, the first pole of the sixth transistor T6 is connected to the third node N3, and the second pole of the sixth transistor T6 is connected to the fourth node N4 (i.e., the first pole of the light-emitting element EL). The gate electrode of the seventh transistor T7 is connected to the first reset signal line Re1, the first pole of the seventh transistor T7 is connected to the first initial signal line INIT1, and the second pole of the seventh transistor T7 is connected to the fourth node N4. The first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C1 is connected to the first node N1.

[0066] In some exemplary embodiments, the third transistor T3 to the seventh transistor T7 may be N-type thin film transistors, and the first transistor T1 and the second transistor T2 may be P-type thin film transistors; alternatively, the third transistor T3 to the seventh transistor T7 may be P-type thin film transistors, and the first transistor T1 and the second transistor T2 may be N-type thin film transistors.

[0067] In some exemplary embodiments, the third transistor T3 to the seventh transistor T7 may be low-temperature poly-silicon (LTPS) thin film transistors (TFTs), and the first transistor T1 and the second transistor T2 may be indium gallium zinc oxide (IGZO) thin film transistors.

[0068] In this embodiment, compared with a low-temperature polycrystalline silicon thin-film transistor, the indium gallium zinc oxide thin-film transistor generates less leakage current. Therefore, setting the first transistor T1 and the second transistor T2 as indium gallium zinc oxide thin-film transistors can significantly reduce the generation of leakage current, thereby improving the problem of low-frequency and low-brightness flicker of the display panel. The pixel driving circuit of the embodiment of the present disclosure combines the good switching characteristics of LTPS-TFT and the low leakage characteristics of Oxide-TFT, and can achieve low-frequency driving (1 Hz to 60 Hz), greatly reducing the power consumption of the display screen.

[0069] In some exemplary embodiments, the second pole of the light-emitting element EL is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal, and the signal of the first power supply line VDD is a continuously provided high-level signal. For the nth display row, the first scan signal line G1 is G1(n), and the first reset signal line Re1 is G1(n - 1). The signal of the first reset signal line Re1 of this display row and the signal of the first scan signal line G1 in the pixel driving circuit of the previous display row can be the same signal; similarly, for the nth display row, the second scan signal line G2 is G2(n), and the second reset signal line Re2 is G2(n - 1). The signal of the second reset signal line Re2 of this display row and the signal of the second scan signal line G2 in the pixel driving circuit of the previous display row can be the same signal, so as to reduce the signal lines of the display panel and achieve a narrow border of the display panel.

[0070] In some exemplary embodiments, the light-emitting element EL may be an organic light-emitting diode (OLED), including a stacked first pole (anode), an organic light-emitting layer, and a second pole (cathode).

[0071] Figure 4 It is a timing diagram of the operation of a pixel driving circuit. The following will illustrate the exemplary embodiments of the present disclosure through Figure 4 the operation process of the exemplary pixel driving circuit. Figure 3 The pixel driving circuit in the embodiment includes 7 transistors (the first transistor T1 to the seventh transistor T7) and 1 storage capacitor C. In this embodiment, the third transistor T3 to the seventh transistor T7 are taken as P-type transistors, and the first transistor T1 and the second transistor T2 are taken as N-type transistors for illustration.

[0072] In some exemplary embodiments, the driving method of the pixel driving circuit may include a reset stage t1, a compensation stage t2, and a light-emitting stage t3.

[0073] In the reset stage t1: The second reset signal line Re2 outputs a high-level signal, and the first reset signal line Re1 outputs a low-level signal. The first transistor T1 and the seventh transistor T7 are turned on. The voltage of the first node N1 is reset to the second initial voltage Vinit2 provided by the second initial signal line INIT2, and the voltage of the fourth node N4 is reset to the first initial voltage Vinit1 provided by the first initial signal line INIT1. The second initial signal line INIT2 inputs an initial signal to the first node N1, and the first initial signal terminal Vinit1 inputs an initial signal to the second pole of the sixth transistor T6. The high-level signal of the light-emitting signal line EM turns off the fifth transistor T5 and the sixth transistor T6. In this stage, the light-emitting element EL does not emit light.

[0074] In the compensation stage t2: The first scan signal line G1 outputs a low-level signal, and the second scan signal line G2 outputs a high-level signal. The fourth transistor T4 and the second transistor T2 are turned on. In this stage, since the first node N1 is at a low level, the third transistor T3 is turned on. At the same time, the data signal line Da outputs a data driving signal, and the data driving signal is provided to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 to write a voltage Vdata + Vth to the first node N1, where Vdata is the voltage of the data driving signal and Vth is the threshold voltage of the third transistor T3 (driving transistor).

[0075] In the light-emitting stage t3: The light-emitting signal line EM outputs a low-level signal. The sixth transistor T6 and the fifth transistor T5 are turned on. The power supply voltage output by the first power supply line VDD provides a driving voltage to the first pole (i.e., the fourth node N4) of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light-emitting element EL to emit light. It should be understood that Figure 3 The pixel driving circuit shown may also have other driving methods. For example, the seventh transistor T7 may be turned on in the compensation stage t2, etc.

[0076] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (i.e., the driving transistor) is determined by the voltage difference between its gate electrode and the first pole. Since the voltage of the first node N1 is Vdata + Vth, the driving current of the third transistor T3 is:

[0077] I = K * (Vgs - Vth) 2 = K * [(Vdata + Vth - Vdd) - Vth] 2 = K * [(Vdata - Vdd)] 2

[0078] Among them, I is the driving current flowing through the third transistor T3, which is also the driving current for driving the light-emitting element EL. K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the voltage of the data driving signal output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply terminal VDD.

[0079] As can be seen from the above formula, the current I flowing through the light-emitting element EL is independent of the threshold voltage Vth of the third transistor T3, eliminating the influence of the threshold voltage Vth of the third transistor T3 on the current I and ensuring the uniformity of brightness.

[0080] Based on the above working timing, the pixel driving circuit eliminates the residual positive charge after the light-emitting element EL last emitted light, realizes the compensation of the gate voltage of the third transistor, avoids the influence of the threshold voltage drift of the third transistor on the driving current of the light-emitting element EL, and improves the uniformity of the displayed image and the display quality of the display panel.

[0081] The pixel driving circuit of the present disclosure embodiment can adjust the reset voltage of the light-emitting element EL and the reset voltage of the first node N1 respectively by initializing the fourth node N4 to the signal of the first initialization signal line INIT1 and initializing the fifth node N5 to the signal of the second initialization signal line INIT2, so as to achieve a better display effect and improve problems such as low-frequency flicker.

[0082] Two types of semiconductors, LTPS and oxide, have attracted much attention in the display industry. Each has its own advantages and is equally good. LTPS has the advantages of high mobility and fast charging, while oxide has the advantage of low leakage current. If the advantages of these two materials can be combined to form a Low Temperature Polycrystalline Oxide (LTPO) product, the user experience of the display product will be greatly improved. However, due to the relatively large differences in the preparation processes of LTPS and oxide, that is, there is a problem of difficult process compatibility, and the process stability is difficult to guarantee.

[0083] In order to supplement hydrogen elements to the LTPS polysilicon (p-Si) channel, the hydrogen content in the LTPS related film layers is relatively high. However, the hydrogen elements in the LTPS related film layers will diffuse upward through the annealing process, thereby affecting the characteristics of the oxide transistor. In some related technologies, in order to prevent excessive hydrogen from deteriorating the characteristics of the oxide transistor, the related technology sets a buffer layer between the LTPS related film layer and the oxide film layer. The buffer layer uses a silicon oxide (SiO) film with low hydrogen content and relatively high density. On the one hand, the high density can block the diffusion of hydrogen elements in the LTPS related film layers. On the other hand, the low hydrogen content can reduce the influence of hydrogen elements on the characteristics of the oxide transistor.

[0084] However, due to the high content of hydrogen in the LTPS-related film layer, even with the buffer layer as a barrier, hydrogen may still diffuse upward to the IGZO channel through the annealing process. In addition, since the buffer layer needs to be formed with a higher nitrous oxide (N2O) or lower silicon tetrahydride (SiH4) gas flow rate to increase the density of the film, there are more oxygen defects in the buffer layer film, which are not easy to neutralize through the annealing process. There are more oxygen defects at the interface between the IGZO channel and the buffer layer. When the gate electrode of the oxide transistor is applied with a forward bias, the oxygen defects will capture electrons, reducing the number of carriers in the channel, which in turn causes the threshold voltage (Vth) to drift forward, affecting the stability of the oxide transistor device.

[0085] It is precisely because of the compatibility issue between the hydrogen replenishing process of LTPS transistors and the low hydrogen process of oxide transistors in LTPO products that how to simultaneously ensure the characteristics of LTPS transistors and oxide transistors in LTPO products has become a technical development problem for LTPO products.

[0086] Figure 5a is a schematic diagram of a planar structure of a display substrate according to an embodiment of the present disclosure, Figure 5b for Figure 5a The cross-sectional view in the BB direction is as follows: Figure 5a and Figure 5b As shown, in a plane perpendicular to the display substrate, the display substrate includes a polysilicon transistor layer, a first interlayer insulating layer 941, a first hydrogen barrier layer, a second buffer layer 944 and an oxide transistor layer sequentially arranged on a substrate, wherein:

[0087] The polysilicon transistor layer includes an active layer and a gate electrode of a plurality of polysilicon transistors, and the oxide transistor layer includes an active layer and a gate electrode of a plurality of oxide transistors;

[0088] The hydrogen element content of the first interlayer insulating layer 941 is greater than that of the first hydrogen-blocking layer, or the atomic ratio of silicon element to oxygen element of the first hydrogen-blocking layer is greater than that of the second buffer layer 944.

[0089] For the display substrate according to an embodiment of the present disclosure, by disposing the first interlayer insulating layer 941, the first hydrogen-blocking layer, and the second buffer layer 944 between the polysilicon transistor layer and the oxide transistor layer, the influence of the hydrogen element in the polysilicon transistor layer on the oxide transistor layer is reduced, ensuring the stability of the polysilicon transistor and oxide transistor devices. In addition, the manufacturing process of the present disclosure can be well compatible with the existing manufacturing process, with simple process implementation, easy to implement, high production efficiency, low production cost, and high yield.

[0090] In some exemplary embodiments, the first hydrogen-blocking layer includes a second interlayer insulating layer 942, wherein the atomic ratio of silicon element to nitrogen element of the first interlayer insulating layer 941 is greater than that of the second interlayer insulating layer 942 and less than twice that of the second interlayer insulating layer 942.

[0091] Exemplarily, the atomic ratio of silicon element to nitrogen element of the second interlayer insulating layer 942 is between 0.7 and 0.8.

[0092] In some exemplary embodiments, the Si-H bond content of the second interlayer insulating layer 942 is 2 to 5 times that of the first interlayer insulating layer 941.

[0093] Exemplarily, the Si-H bond content of the second interlayer insulating layer 942 is 1% to 3%.

[0094] In some exemplary embodiments, the refractive index of the second interlayer insulating layer 942 is between 1.8 and 1.9.

[0095] In some exemplary embodiments, the stress of the second interlayer insulating layer 942 is controlled between -200 Mpa and 400 Mpa, and the N-H bond content is 5% to 10%.

[0096] In some exemplary embodiments, the atomic ratio of silicon element to nitrogen element of the first interlayer insulating layer 941 is between 1.1 and 1.2.

[0097] In some exemplary embodiments, the Si-H bond content of the first interlayer insulating layer 941 is 5% to 15%.

[0098] In some exemplary embodiments, the refractive index of the first interlayer insulating layer 941 is between 1.9 and 2.0.

[0099] In some exemplary embodiments, the stress of the first interlayer insulating layer 941 is controlled between -100 Mpa and 100 Mpa, and the nitrogen-hydrogen bond content is 5% to 15%.

[0100] In some exemplary embodiments, the thickness of the first interlayer insulating layer 941 is about 100 nm, and the material used is a silicon nitride (SiN) thin film with a relatively high hydrogen element content. The first interlayer insulating layer 941 can play a role in supplementing hydrogen elements to the polysilicon transistor layer.

[0101] In some exemplary embodiments, the thickness of the second interlayer insulating layer 942 is about 50 nm to 100 nm, and the material used is a silicon nitride (SiN) thin film with a relatively low hydrogen element content. The second interlayer insulating layer 942 has two functions. First, the SiN thin film has good compactness, and the highly compact second interlayer insulating layer 942 can block the upward diffusion of hydrogen elements in the first interlayer insulating layer to the IGZO channel. Second, the hydrogen element content of the second interlayer insulating layer 942 is relatively low, thereby reducing the number of upward-diffusing hydrogen elements and improving the stability of the Oxide transistor.

[0102] In some exemplary embodiments, the first hydrogen barrier layer includes a first buffer layer 943, wherein the atomic ratio of silicon to oxygen in the first buffer layer 943 is greater than that in the second buffer layer 944 and less than twice that in the second buffer layer 944.

[0103] Exemplarily, the atomic ratio of silicon to oxygen in the first buffer layer 943 is between 1.1 and 1.2.

[0104] In some exemplary embodiments, the thickness of the first buffer layer 943 is about 50 nm to 200 nm, and the material used is a relatively highly compact silicon oxide (SiO) thin film. The first buffer layer 943 plays a role in blocking the diffusion of hydrogen elements in the underlying first interlayer insulating layer 941 and second interlayer insulating layer 942. When forming the first buffer layer, a relatively high nitrous oxide (N2O) or a relatively low silane (SiH4) gas flow rate is required to increase the compactness of the thin film.

[0105] In some exemplary embodiments, when the first buffer layer 943 is formed, the gas flow ratio of N2O:SiH4 is generally 60:1 to 90:1, and the film quality is relatively dense. The film denseness is defined as follows: its wet etching rate is less than 10 nm / min (the concentration of hydrofluoric acid HF is 0.5%), and the O2 release amount measured by a Thermal Desorption Spectroscopy (TDS) is in the range of 6E14 to 9E14 molec / cm2, where molec / cm2 represents the number of molecules per square centimeter, and its NOx release amount is less than 5E14 molec / cm2, as Figure 5c and Figure 5d shown, Figure 5c and Figure 5d the abscissas of both are temperature, and the ordinates of both are release amounts. The position of the Si-O bond measured by Fourier Transform Infrared (FTIR) is at 1065 - 1070 cm-1, where cm-1 is the number of wave numbers contained in 1 centimeter, as Figure 5e shown, Figure 5e the abscissa of which is wave number, and the ordinate is absorbance.

[0106] In some exemplary embodiments, the thickness of the second buffer layer 944 is about 100 nm to 200 nm, and the material used is a silicon oxide (SiO) thin film with relatively low denseness. The film denseness of the second buffer layer 944 is poorer than that of the first buffer layer 943. When the second buffer layer 944 is formed, a relatively lower nitrous oxide (N2O) or a relatively higher silane (SiH4) gas flow is used compared to the first buffer layer 943. By this method, the oxygen defects in the second buffer layer 944 thin film are reduced, and further the oxygen defects at the interface between the IGZO channel and the first buffer layer 943 are reduced, improving the stability of the Oxide transistor device.

[0107] In some exemplary embodiments, when the second buffer layer 944 is formed, the gas flow ratio of N2O:SiH4 is generally 20:1 to 60:1, and the oxygen defects in the thin film are relatively few. The film defects are defined as follows: the thin film of SiO2 is tested by Electron Spin Resonance (ESR), and its thin film NOx defect state is less than 1E18 spins / cm3, as Figure 5f shown, Figure 5f the abscissa of which is the g factor, and the ordinate is the defect state.

[0108] In some exemplary embodiments, the first hydrogen-blocking layer includes a second interlayer insulating layer 942 and a first buffer layer 943 disposed on the second interlayer insulating layer 942, wherein the atomic ratio of silicon to nitrogen in the second interlayer insulating layer 942 is between 0.7 and 0.8, and the atomic ratio of silicon to oxygen in the first buffer layer 943 is between 1.1 and 1.2.

[0109] In some exemplary embodiments, the display substrate further includes a fourth conductive layer on the oxide transistor layer and a second hydrogen-blocking layer covering the fourth conductive layer, wherein:

[0110] The fourth conductive layer includes the first and second poles of a plurality of polysilicon transistors and the first and second poles of a plurality of oxide transistors, and the second hydrogen-blocking layer includes a first passivation layer 971 and a second passivation layer 972 disposed on the first passivation layer 971. The hydrogen element content in the first passivation layer 971 is lower than that in the second passivation layer 972, and the atomic ratio of silicon to oxygen in the second passivation layer 972 is higher than that in the first passivation layer 971.

[0111] In some exemplary embodiments, the material of the first passivation layer 971 is silicon oxide, and the material of the second passivation layer 972 is silicon nitride.

[0112] In the related art, the passivation layer (PVX) generally uses a silicon oxide (SiO) thin film instead of a silicon nitride (SiN) thin film because the hydrogen element content in the silicon oxide thin film is less than that in the silicon nitride thin film and will not affect the characteristics of Oxide transistors. However, the film compactness of silicon oxide is relatively poor, and the hydrogen element in the subsequent evaporation and encapsulation (EVEN) process may still affect the characteristics of Oxide transistors. In the embodiments of the present disclosure, the passivation layer uses a double-layer structure, namely, the first passivation layer 971 and the second passivation layer 972. The first passivation layer 971 uses a silicon oxide thin film. The hydrogen element content in the silicon oxide thin film is small. On the one hand, it will not affect the characteristics of Oxide transistors. On the other hand, it can block the downward diffusion of hydrogen elements in the upper silicon nitride thin film and thus affect the characteristics of Oxide transistors. The second passivation layer 972 uses a silicon nitride thin film with a lower hydrogen element content. On the one hand, it avoids excessive downward diffusion of hydrogen elements and affects the characteristics of Oxide transistors. On the other hand, the film compactness of the silicon nitride thin film of the second passivation layer 972 is higher than that of the silicon oxide thin film of the first passivation layer, which can block the influence of hydrogen elements in the subsequent EVEN process on the characteristics of Oxide transistors, thereby improving the stability of Oxide transistors.

[0113] In some exemplary embodiments, the polysilicon transistor layer includes a first semiconductor layer, a first conductive layer, and a second conductive layer sequentially disposed on a substrate, and the oxide transistor layer includes a second semiconductor layer and a third conductive layer sequentially disposed on a first hydrogen-blocking layer, wherein:

[0114] The first semiconductor layer includes active layers of a plurality of polysilicon transistors, the first conductive layer includes gate electrodes of a plurality of polysilicon transistors and a first electrode plate of a storage capacitor, the second conductive layer includes a second electrode plate of the storage capacitor, the second semiconductor layer includes active layers of a plurality of oxide transistors, and the third conductive layer includes gate electrodes of a plurality of oxide transistors.

[0115] In some other exemplary embodiments, the polysilicon transistor layer includes a first semiconductor layer and a first conductive layer sequentially disposed on a substrate, and the oxide transistor layer includes a second semiconductor layer, a second conductive layer, and a third conductive layer sequentially disposed on a first hydrogen-blocking layer, wherein:

[0116] The first semiconductor layer includes active layers of a plurality of polysilicon transistors, the first conductive layer includes gate electrodes of a plurality of polysilicon transistors and a first electrode plate of a storage capacitor; the second semiconductor layer includes active layers of a plurality of oxide transistors, the second conductive layer includes a second electrode plate of the storage capacitor, and the third conductive layer includes gate electrodes of a plurality of oxide transistors.

[0117] In some exemplary embodiments, the display substrate further includes a fifth conductive layer disposed on the second hydrogen-blocking layer, and the fifth conductive layer includes a first power supply line 62 and a data signal line 61.

[0118] In some exemplary embodiments, the first conductive layer may further include a first scan signal line 21, a second scan signal line 22, and a light emission control line 23, the second conductive layer may further include a plate connection line 35, a node electrode, a first shielding layer, and a second shielding layer, the third conductive layer may further include a first auxiliary signal line 48 and a second auxiliary signal line 49, the fourth conductive layer may further include a power connection line 51, an initial signal line 52, a fifth connection electrode, a sixth connection electrode, a seventh connection electrode, and an eighth connection electrode, and the fifth conductive layer may further include an anode connection electrode 63.

[0119] In an exemplary embodiment, the gate electrode of the first transistor is connected to the second auxiliary signal line, the first pole of the first transistor is connected to the initial signal line 52, and the second pole of the first transistor is respectively connected to the first pole of the second transistor, the gate electrode of the third transistor, and the first plate. The gate electrode of the second transistor is connected to the first auxiliary signal line, and the second pole of the second transistor is respectively connected to the second pole of the third transistor and the first pole of the sixth transistor. The first pole of the third transistor is respectively connected to the second pole of the fourth transistor and the second pole of the fifth transistor. The gate electrode of the fourth transistor is connected to the first scan signal line 21, the first pole of the fourth transistor is connected to the data signal line 61 through the eighth connection electrode 56, and the second pole of the fourth transistor is connected to the first pole of the third transistor. The gate electrode of the fifth transistor is connected to the light-emitting signal line 23, and the first pole of the fifth transistor is respectively connected to the first power supply line 62 and the second plate 32. The gate electrode of the sixth transistor is connected to the light-emitting signal line 23, and the second pole of the sixth transistor is connected to the anode of the light-emitting device through the seventh connection electrode and the anode connection electrode 63. The gate electrode of the seventh transistor is connected to the second scan signal line 22, the first pole of the seventh transistor is connected to the initial signal line 52, and the second pole of the seventh transistor is connected to the second pole of the sixth transistor.

[0120] An exemplary description is given below through the manufacturing process of the display substrate. The "patterning process" as referred to in the present disclosure, for metal materials, inorganic materials, or transparent conductive materials, includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping. For organic materials, it includes processes such as coating organic materials, mask exposure, and development. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be any one or more of spraying, spin coating, and inkjet printing. Etching can be any one or more of dry etching and wet etching. The present disclosure does not make any limitations. A "thin film" refers to a thin film made of a certain material on a substrate by using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" requires a patterning process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The statement "A and B are disposed in the same layer" as referred to in the present disclosure means that A and B are formed simultaneously through the same patterning process. The "thickness" of a film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, the statement "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The statement "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0121] In an exemplary embodiment, the preparation process of the present exemplary embodiment for the substrate may include the following operations.

[0122] (11) Form a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating thin film and a first semiconductor thin film on a substrate, patterning the first semiconductor thin film through a patterning process to form a first insulating layer covering the substrate, and a first semiconductor layer provided on the first insulating layer, as Figure 6a and Figure 6b shown, Figure 6b for Figure 6a the cross-sectional view taken along line B-B in

[0123] In an exemplary embodiment, the substrate 10 may be a flexible substrate or a rigid substrate. The flexible substrate may be a single-layer structure or a laminated structure. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier plate. In an exemplary embodiment, the rigid substrate may be glass or quartz.

[0124] As Figure 6a shown, the first semiconductor layer of each sub-pixel may include the third active layer 13 of the third transistor T3 to the seventh active layer 17 of the seventh transistor T7, and the third active layer 13 to the seventh active layer 17 are an integrally connected structure.

[0125] In an exemplary embodiment, the fourth active layer 14 of the fourth transistor T4 is disposed in the first region R1, the third active layer 13 of the third transistor T3 is disposed in the second region R2, and the fifth active layer 15 of the fifth transistor T5, the sixth active layer 16 of the sixth transistor T6, and the seventh active layer 17 of the seventh transistor T7 are disposed in the third region R3. The seventh active layer 17 is disposed on a side of the third region R3 away from the second region R2, and the fifth active layer 15 and the sixth active layer 16 are disposed on a side of the third region R3 adjacent to the second region R2.

[0126] In an exemplary embodiment, the shape of the third active layer 13 may be in a "ji" shape, the shape of the fourth active layer 14 may be in a "1" shape, and the shapes of the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 may be in an "L" shape.

[0127] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the first region 13-1 of the third active layer 13 serves simultaneously as the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15, that is, the first region 13-1 of the third active layer 13, the second region 14-2 of the fourth active layer 14, and the second region 15-2 of the fifth active layer 15 are interconnected. The second region 13-2 of the third active layer 13 serves simultaneously as the first region 16-1 of the sixth active layer 16, that is, the second region 13-2 of the third active layer 13 and the first region 16-1 of the sixth active layer 16 are interconnected. The second region 16-2 of the sixth active layer 16 serves simultaneously as the second region 17-2 of the seventh active layer 17, that is, the second region 16-2 of the sixth active layer 16 and the second region 17-2 of the seventh active layer 17 are interconnected. The first regions 14-1 of the fourth active layer 14, 15-1 of the fifth active layer 15, and 17-1 of the seventh active layer 17 are provided separately.

[0128] In an exemplary embodiment, the first semiconductor layer may be made of polysilicon (p-Si), that is, the third, fourth, fifth, sixth, and seventh transistors are LTPS thin-film transistors.

[0129] As Figure 6b shown, after this process, the display substrate includes a first insulating layer 91 provided on the substrate 10 and a first semiconductor layer provided on the first insulating layer 91.

[0130] (12) Form a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first metal film on the substrate on which the foregoing patterns are formed, patterning the first metal film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern provided on the second insulating layer. The first conductive layer pattern at least includes: a first scan signal line 21, a second scan signal line 22, a light emission control line 23, and a first electrode plate 24 of a storage capacitor, as Figure 7a and Figure 7b shown, Figure 7b is Figure 7a a cross-sectional view taken along the B-B direction in. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE 1) layer.

[0131] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, and the light emission control line 23 extend along the first direction X. The first scan signal line 21 is disposed in the first region R1, the second scan signal line 22 and the light emission control line 23 are disposed in the third region R3, the second scan signal line 22 is located on a side of the light emission control line 23 away from the second region R2, and the first electrode plate 24 of the storage capacitor is disposed in the second region R2.

[0132] In an exemplary embodiment, the first electrode plate 24 may be rectangular, chamfers may be provided at corners of the rectangular shape, there is an overlapping region between the orthographic projection of the first electrode plate 24 on the substrate and the orthographic projection of the third active layer of the third transistor T3 on the substrate, the first electrode plate 24 simultaneously serves as the gate electrode of the third transistor T3, and the region where the third active layer of the third transistor T3 overlaps with the first electrode plate 24 serves as the channel region of the third transistor T3. One end of the channel region is connected to the first region of the third active layer, and the other end is connected to the second region of the third active layer. The region where the first scan signal line 21 overlaps with the fourth active layer of the fourth transistor T4 serves as the gate electrode of the fourth transistor T4, the region where the first electrode plate 24 overlaps with the third active layer of the third transistor T3 serves as the gate electrode of the third transistor T3, the region where the light emission control line 23 overlaps with the fifth active layer of the fifth transistor T5 serves as the gate electrode of the fifth transistor T5, the region where the light emission control line 23 overlaps with the sixth active layer of the sixth transistor T6 serves as the gate electrode of the sixth transistor T6, and the region where the second scan signal line 22 overlaps with the seventh active layer of the seventh transistor T7 serves as the gate electrode of the seventh transistor T7.

[0133] In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer may be conductorized using the first conductive layer as a mask. The semiconductor layer in the region shielded by the first conductive layer forms the channel regions of the third transistor T3 to the seventh transistor T7, and the semiconductor layer in the region not shielded by the first conductive layer is conductorized, that is, the first regions and the second regions of the third active layer to the seventh active layer are all conductorized.

[0134] As Figure 7b shown, after this process, the display substrate includes a first insulating layer 91 disposed on the substrate 10, a first semiconductor layer disposed on the first insulating layer 91, a second insulating layer 92 covering the first semiconductor layer, and a first conductive layer disposed on the second insulating layer 92.

[0135] (13)Form a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second metal film on the substrate on which the foregoing pattern is formed, patterning the second metal film using a patterning process to form a third insulating layer 93 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 93. The second conductive layer pattern at least includes: a second electrode plate 32 of the storage capacitor, an electrode plate connection line 35, a node electrode 36, a first shielding layer 37, and a second shielding layer 38, as Figure 8a and Figure 8b shown Figure 8b in Figure 8a the cross-sectional view taken along line B-B in

[0136] As Figure 8a shown, in an exemplary embodiment, the second electrode plate 32 of the storage capacitor is disposed in the second region R2, between the second shielding layer 38 and the light emission control line 23. The contour of the second electrode plate 32 may be rectangular, and chamfers may be provided at the corners of the rectangular shape. There is an overlapping area between the orthographic projection of the second electrode plate 32 on the substrate and the orthographic projection of the first electrode plate 24 on the substrate. An opening 34 is provided on the second electrode plate 32, and the opening 34 may be located in the middle of the second region R2. The opening 34 may be rectangular, so that the second electrode plate 32 forms an annular structure. The opening 34 exposes the third insulating layer 93 covering the first electrode plate 24, and the orthographic projection of the first electrode plate 24 on the substrate includes the orthographic projection of the opening 34 on the substrate. In an exemplary embodiment, the opening 34 is configured to accommodate a first via formed subsequently. The first via is located within the opening 34 and exposes the first electrode plate 24, so that the second pole of the first transistor T1 formed subsequently is connected to the first electrode plate 24.

[0137] In an exemplary embodiment, the electrode plate connection line 35 is disposed between the second electrode plates 32 of adjacent sub-pixels in the first direction X. The first end of the electrode plate connection line 35 is connected to the second electrode plate 32 of the present sub-pixel, and the second end of the electrode plate connection line 35 extends along the first direction X and is connected to the second electrode plate 32 of the sub-pixel adjacent in the first direction X. That is, the electrode plate connection line 35 is configured to connect the second electrode plates of adjacent sub-pixels in the first direction X to each other. In an exemplary embodiment, through the electrode plate connection line 35, the second electrode plates in adjacent sub-pixels form an integrally connected structure. The second electrode plates of the integrally connected structure can be reused as power signal lines, ensuring that the second electrode plates in adjacent sub-pixels have the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0138] In an exemplary embodiment, the positive projection of the edge of the second electrode plate 32 adjacent to the first region R1 on the substrate overlaps with the positive projection of the boundary line between the first region R1 and the second region R2 on the substrate, and the positive projection of the edge of the second electrode plate 32 adjacent to the third region R3 on the substrate overlaps with the positive projection of the boundary line between the second region R2 and the third region R3 on the substrate, that is, the length of the second electrode plate 32 is equal to the length of the second region R2.

[0139] In an exemplary embodiment, the node electrode 36 is disposed in the first region R1, and the positive projection of the node electrode 36 on the substrate is within the range of the positive projection of the first scan signal line 21 on the substrate.

[0140] In an exemplary embodiment, the first shielding layer 37 and the second shielding layer 38 extend along the first direction X and are disposed in the first region R1. The first shielding layer 37 is located on the side of the first scan signal line 21 away from the second region R2, and the second shielding layer 38 is located on the side of the first scan signal line 21 adjacent to the second region R2. In an exemplary embodiment, the first shielding layer 37 is configured to be the shielding layer of the first transistor to shield the channel of the first transistor, and the second shielding layer 38 is configured to be the shielding layer of the second transistor to shield the channel of the second transistor, so as to ensure the electrical performance of the oxide first transistor and the oxide second transistor.

[0141] In an exemplary embodiment, after forming the second conductive layer pattern, on the substrate where the foregoing pattern is formed, a fourth insulating film and a fifth insulating film are sequentially deposited to form a first interlayer insulating layer (ILD-1) 941 and a second interlayer insulating layer (ILD-2) 942 covering the substrate. The fourth insulating film is a SiN film with a thickness of about 100 nm and a high hydrogen (H) content, and the first interlayer insulating layer 941 serves to supplement hydrogen elements to polycrystalline silicon (p-Si); the fifth insulating film is a SiN film with a thickness of about 50 nm to 100 nm and a low hydrogen content. The second interlayer insulating layer 942 has two functions. First, the SiN film has good compactness, and the highly compact second interlayer insulating layer 942 can block the upward diffusion of hydrogen elements in the first interlayer insulating layer 941 to the IGZO channel. Second, the hydrogen element content of the second interlayer insulating layer 942 is low, thereby reducing the number of upward diffused hydrogen elements and improving the stability of the Oxide transistor.

[0142] In some exemplary embodiments, the atomic ratio of silicon to nitrogen in the first interlayer insulating layer 941 is greater than the atomic ratio of silicon to nitrogen in the second interlayer insulating layer 942 and less than twice the atomic ratio of silicon to nitrogen in the second interlayer insulating layer 942.

[0143] In some exemplary embodiments, the atomic ratio of silicon to nitrogen in the first interlayer insulating layer 941 is between 1.1 and 1.2.

[0144] In some exemplary embodiments, the Si-H bond content of the second interlayer insulating layer 942 is 2 to 5 times that of the Si-H bond content of the first interlayer insulating layer 941.

[0145] In some exemplary embodiments, the Si-H bond content of the first interlayer insulating layer 941 is 5% to 15%, and the refractive index is between 1.9 and 2.0.

[0146] In some exemplary embodiments, the stress of the first interlayer insulating layer 941 is controlled between -100 Mpa and 100 Mpa, and the N-H bond content is 5% to 15%.

[0147] In some exemplary embodiments, the atomic ratio of silicon element to nitrogen element in the second interlayer insulating layer 942 is between 0.7 and 0.8.

[0148] In some exemplary embodiments, the Si-H bond content of the second interlayer insulating layer 942 is 1% to 3%, and the refractive index is between 1.8 and 1.9.

[0149] In some exemplary embodiments, the stress of the second interlayer insulating layer 942 is controlled between -200 Mpa and 400 Mpa, and the N-H bond content is 5% to 10%.

[0150] As Figure 8b shown, in a plane perpendicular to the substrate, the first insulating layer 91 is disposed on the substrate 10, the semiconductor layer is disposed on the first insulating layer 91, the second insulating layer 92 covers the semiconductor layer, the first conductive layer is disposed on the second insulating layer 92, the third insulating layer 93 covers the first conductive layer, the second conductive layer is disposed on the third insulating layer 93, the first interlayer insulating layer 941 covers the second conductive layer, and the second interlayer insulating layer 942 covers the first interlayer insulating layer 941.

[0151] (14) Form a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: sequentially depositing a sixth insulating film, a seventh insulating film, and a second semiconductor film on the substrate on which the foregoing pattern is formed, and patterning the second semiconductor film through a patterning process to form a first buffer layer (Buffer-1) 943 covering the substrate, a second buffer layer (Buffer-2) 944 covering the first buffer layer 943, and a second semiconductor layer disposed on the second buffer layer 944, as Figure 9a and Figure 9b shown, Figure 9b is Figure 9a a cross-sectional view taken along the line B-B in

[0152] Among them, the sixth insulating film is a SiO film with a thickness of 50 nm to 200 nm and relatively high density. The first buffer layer 943 functions to block the diffusion of hydrogen elements in the underlying first interlayer insulating layer 941 and second interlayer insulating layer 942. When forming the first buffer layer 943, a relatively high N2O or a relatively low SiH4 gas flow rate is required to increase the density of the film. The film density of the seventh insulating film can be worse than that of the sixth insulating film. Compared with the formation of the first buffer layer 943, when forming the second buffer layer 944, a relatively low N2O or a relatively high SiH4 gas flow rate is used. By this method, the oxygen defects in the second buffer layer 944 are reduced, and further the oxygen defects at the interface between the subsequently formed IGZO channel and the second buffer layer 944 are reduced, improving the stability of the subsequently formed Oxide transistor device.

[0153] In some exemplary embodiments, the atomic ratio of silicon element to oxygen element in the first buffer layer 943 is greater than that in the second buffer layer 944 and less than twice that in the second buffer layer 944.

[0154] In some exemplary embodiments, the atomic ratio of silicon element to oxygen element in the first buffer layer 943 is between 1.1 and 1.2.

[0155] In some exemplary embodiments, the first buffer layer 943 has a thickness of about 50 nm to 200 nm and is made of a relatively high-density silicon oxide (SiO) film. The first buffer layer 943 functions to block the diffusion of hydrogen elements in the underlying first interlayer insulating layer and second interlayer insulating layer. When forming the first buffer layer 943, a relatively high nitrous oxide (N2O) or a relatively low silane (SiH4) gas flow rate is required to increase the density of the film.

[0156] In some exemplary embodiments, when forming the first buffer layer 943, the gas flow ratio of N2O:SiH4 is generally 60:1 to 90:1, and the film quality is relatively dense. The film density is defined as follows: its wet etching rate is less than 10 nm / min (0.5% HF), the NOx release amount measured by TDS is less than 5E14 molec / cm2, the O2 release amount is between 6E14 and 9E14 molec / cm2, and the Si-O bond position measured by FTIR is at 1065 - 1070 cm-1.

[0157] In some exemplary embodiments, the thickness of the second buffer layer 944 is about 100 nm to 200 nm, and the material used is a silicon oxide (SiO) thin film with relatively low density. The film density of the second buffer layer 944 is poorer than that of the first buffer layer 943. When forming the second buffer layer 944, a relatively lower nitrous oxide (N2O) or a relatively higher silane (SiH4) gas flow rate is used compared to the first buffer layer 943. By this method, the oxygen defects in the second buffer layer 944 thin film are reduced, and further the oxygen defects at the interface between the IGZO channel and the first buffer layer 943 are reduced, improving the stability of the Oxide transistor device.

[0158] In some exemplary embodiments, when forming the second buffer layer 944, the gas flow ratio of N2O:SiH4 is generally 20:1 to 60:1, and the oxygen defects in the thin film are relatively few. The defects of its thin film are defined as follows: For the SiO2 thin film, an ESR test is performed, and the NOx defect state of its thin film is less than 1E18 spins / cm3.

[0159] As Figure 9a shown, the second semiconductor layer of each sub-pixel may include the first active layer 11 of the first transistor T1 and the second active layer 12 of the second transistor T2, and the first active layer 11 and the second active layer 12 may be an integrally connected structure.

[0160] In an exemplary embodiment, the shapes of the first active layer 11 and the second active layer 12 may be in the shape of "1". The first region of the first active layer 11 is adjacent to the first region of the seventh active layer. The second region of the first active layer 11 simultaneously serves as the first region of the second active layer 12, and the second region of the second active layer is adjacent to the second region of the third active layer.

[0161] In an exemplary embodiment, the second semiconductor layer may be made of an oxide, that is, the first transistor and the second transistor are oxide thin film transistors.

[0162] As Figure 9b shown, in a plane perpendicular to the substrate, the first insulating layer 91 is disposed on the substrate 10, the semiconductor layer is disposed on the first insulating layer 91, the second insulating layer 92 covers the semiconductor layer, the first conductive layer is disposed on the second insulating layer 92, the third insulating layer 93 covers the first conductive layer, the second conductive layer is disposed on the third insulating layer 93, the first interlayer insulating layer 941 covers the second conductive layer, the second interlayer insulating layer 942 covers the first interlayer insulating layer 941, the first buffer layer 943 covers the second interlayer insulating layer 942, the second buffer layer 944 covers the first buffer layer 943, and the second semiconductor layer is disposed on the second buffer layer 944.

[0163] (15)Form a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: sequentially depositing an eighth insulating film and a third metal film on a substrate on which the foregoing pattern is formed, patterning the third metal film and the eighth insulating film by a patterning process to form a fifth insulating layer disposed on the second semiconductor layer and a third conductive layer pattern disposed on the fifth insulating layer. The third conductive layer pattern at least includes: a first auxiliary signal line 48 and a second auxiliary signal line 49, as Figure 10a and Figure 10b shown Figure 10b is Figure 10a a cross-sectional view taken along line B-B in

[0164] As Figure 10a shown, in an exemplary embodiment, the first auxiliary signal line 48 and the second auxiliary signal line 49 extend along a first direction X and are disposed in a first region R1. The first auxiliary signal line 48 is close to the first scan signal line 21 and has the same signal as the first scan signal line 21. The second auxiliary signal line 49 is close to the second scan signal line 22 on one side in a second direction Y and has the same signal as the second scan signal line 22. In an exemplary embodiment, the first auxiliary signal line 48 and the first scan signal line 21 may be connected to the same signal source, and the second auxiliary signal line 49 and the second scan signal line 22 may be connected to the same signal source. In an exemplary embodiment, a region where the first auxiliary signal line 48 overlaps with the second active layer serves as a second gate electrode of a second transistor, and a region where the second auxiliary signal line 49 overlaps with the first active layer serves as a first gate electrode of a first transistor.

[0165] In an exemplary embodiment, a region where a positive projection of the first auxiliary signal line 48 on the substrate overlaps with a positive projection of the second shielding layer 38 on the substrate, and a region where a positive projection of the second auxiliary signal line 49 on the substrate overlaps with a positive projection of the first shielding layer 37 on the substrate. Thus, the first shielding layer 37 may serve as a shielding layer of the first transistor, and the second shielding layer 38 may serve as a shielding layer of the second transistor.

[0166] As Figure 10bAs shown, in a plane perpendicular to the substrate, a first insulating layer 91 is disposed on the substrate 10, a semiconductor layer is disposed on the first insulating layer 91, a second insulating layer 92 covers the semiconductor layer, a first conductive layer is disposed on the second insulating layer 92, a third insulating layer 93 covers the first conductive layer, a second conductive layer is disposed on the third insulating layer 93, a first interlayer insulating layer 941 covers the second conductive layer, a second interlayer insulating layer 942 covers the first interlayer insulating layer 941, a first buffer layer 943 covers the second interlayer insulating layer 942, a second buffer layer 944 covers the first buffer layer 943, a second semiconductor layer is disposed on the second buffer layer 944, a fifth insulating layer 95 is disposed on a second active layer 12 in the second semiconductor layer, and a first auxiliary signal line 48 is disposed on the fifth insulating layer 95. In an exemplary embodiment, a positive projection of the first auxiliary signal line 48 and a second auxiliary signal line 49 on the substrate is substantially the same as a positive projection of the fifth insulating layer 95 on the substrate, or alternatively, the positive projection of the fifth insulating layer 95 on the substrate may extend outward from the positive projections of the first auxiliary signal line 48 and the second auxiliary signal line 49 on the substrate to prevent the first auxiliary signal line 48 and the second auxiliary signal line 49 from contacting the second active layer 12 during a fabrication process. In an exemplary embodiment, the fifth insulating thin film may not be patterned, and only the third metal thin film is patterned to form the fifth insulating layer 95 covering the second active layer 12, and the fifth insulating layer 95 covers the entire substrate.

[0167] (16) Form a polysilicon via pattern. In an exemplary embodiment, forming the polysilicon via pattern may include: depositing a ninth insulating thin film on the substrate on which the foregoing pattern is formed, patterning the ninth insulating thin film using a patterning process to form a sixth insulating layer covering the third conductive layer, and a plurality of vias are provided on the sixth insulating layer, and the plurality of vias at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, and a thirteenth via V13, as Figure 11a and Figure 11b shown, Figure 11b is Figure 11a a cross-sectional view taken along line B-B in

[0168] As Figure 11a shown, in an exemplary embodiment, the first via V1 is located within an opening 34 of the second electrode plate 32, a positive projection of the first via V1 on the substrate is within a range of a positive projection of the opening 34 on the substrate, and the sixth insulating layer 96, the second buffer layer 944, the first buffer layer 943, the second interlayer insulating layer 942, the first interlayer insulating layer 941, and the third insulating layer 93 within the first via V1 are etched away to expose a surface of the first electrode plate 24. The first via V1 is configured to connect a second pole of a subsequent formed first transistor T1 to the first electrode plate 24 through the via.

[0169] In an exemplary embodiment, the second via V2 is located in the region where the second electrode plate 32 is located. The orthographic projection of the second via V2 on the substrate is within the range of the orthographic projection of the second electrode plate 32 on the substrate. The sixth insulating layer 96, the second buffer layer 944, the first buffer layer 943, the second interlayer insulating layer 942, and the first interlayer insulating layer 941 within the second via V2 are etched away, exposing the surface of the second electrode plate 32. The second via V2 is configured to enable a first power supply line formed subsequently to be connected to the second electrode plate 32 through this via. In an exemplary embodiment, the second via V2 serving as a power supply via may include a plurality of vias, and the plurality of second vias V2 may be arranged in sequence along the second direction Y, increasing the connection reliability between the first power supply line and the second electrode plate 32.

[0170] In an exemplary embodiment, the third via V3 is located in the third region R3. The sixth insulating layer 96, the second buffer layer 944, the first buffer layer 943, the second interlayer insulating layer 942, the first interlayer insulating layer 941, the third insulating layer 93, and the second insulating layer 92 within the third via V3 are etched away, exposing the surface of the first region of the fifth active layer. The third via V3 is configured to enable a first power supply line formed subsequently to be connected to the fifth active layer through this via.

[0171] In an exemplary embodiment, the fourth via V4 is located in the third region R3. The sixth insulating layer 96, the second buffer layer 944, the first buffer layer 943, the second interlayer insulating layer 942, the first interlayer insulating layer 941, the third insulating layer 93, and the second insulating layer 92 within the fourth via V4 are etched away, exposing the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer). The fourth via V4 is configured to enable the second pole of the sixth transistor T6 formed subsequently to be connected to the sixth active layer through this via, and enable the second pole of the seventh transistor T7 formed subsequently to be connected to the seventh active layer through this via.

[0172] In an exemplary embodiment, the fifth via V5 is located in the first region R1. The sixth insulating layer 96, the second buffer layer 944, the first buffer layer 943, the second interlayer insulating layer 942, the first interlayer insulating layer 941, the third insulating layer 93, and the second insulating layer 92 within the fifth via V5 are etched away, exposing the surface of the first region of the fourth active layer. The fifth via V5 is configured to enable a data signal line formed subsequently to be connected to the fourth active layer through this via.

[0173] In an exemplary embodiment, the sixth via V6 is located in the second region R2. The sixth insulating layer 96, the second buffer layer 944, the first buffer layer 943, the second interlayer insulating layer 942, the first interlayer insulating layer 941, the third insulating layer 93, and the second insulating layer 92 within the sixth via V6 are etched away, exposing the surface of the first region of the sixth active layer (which is also the second region of the third active layer). The sixth via V6 is configured to connect the first pole of the subsequently formed sixth transistor T6 (which is also the second pole of the first transistor T1 and the first pole of the second transistor T2) to the sixth active layer through this via.

[0174] In an exemplary embodiment, the seventh via V7 is located in the third region R3. The sixth insulating layer 96, the second buffer layer 944, the first buffer layer 943, the second interlayer insulating layer 942, the first interlayer insulating layer 941, the third insulating layer 93, and the second insulating layer 92 within the seventh via V7 are etched away, exposing the surface of the first region of the seventh active layer. The seventh via V7 is configured to connect the first pole of the subsequently formed seventh transistor T7 to the seventh active layer through this via.

[0175] In an exemplary embodiment, the thirteenth via V13 is located in the first region R1. The sixth insulating layer 96, the second buffer layer 944, the first buffer layer 943, the second interlayer insulating layer 942, and the first interlayer insulating layer 941 within the thirteenth via V13 are etched away, exposing the surface of the node electrode 36. The thirteenth via V13 is configured to connect the second pole of the subsequently formed first transistor T1 and the first pole of the second transistor T2 to the node electrode 36 through this via.

[0176] (17) Form an oxide via pattern. In an exemplary embodiment, forming the oxide via pattern may include: on the substrate on which the foregoing patterns are formed, forming a plurality of vias using a patterning process. The plurality of vias at least include: the fourteenth via V14, the fifteenth via V15, and the sixteenth via V16, as Figure 12a and Figure 12b shown, Figure 12b which is Figure 12a a cross-sectional view taken along the B-B direction in

[0177] In an exemplary embodiment, the fourteenth via V14 is located in the first region R1. The sixth insulating layer 96 within the fourteenth via V14 is etched away, exposing the surface of the first region of the second active layer (which is also the second region of the first active layer). The fifteenth via V15 is located in the second region R2. The sixth insulating layer 96 within the fifteenth via V15 is etched away, exposing the surface of the second region of the second active layer. The sixteenth via V16 is located in the third region R3. The sixth insulating layer 96 within the sixteenth via V16 is etched away, exposing the surface of the first region of the first active layer.

[0178] AsFigure 12b As shown, in a plane perpendicular to the substrate, a first insulating layer 91 is disposed on the substrate 10, a semiconductor layer is disposed on the first insulating layer 91, a second insulating layer 92 covers the semiconductor layer, a first conductive layer is disposed on the second insulating layer 92, a third insulating layer 93 covers the first conductive layer, a second conductive layer is disposed on the third insulating layer 93, a first interlayer insulating layer 941 covers the second conductive layer, a second interlayer insulating layer 942 covers the first interlayer insulating layer 941, a first buffer layer 943 covers the second interlayer insulating layer 942, a second buffer layer 944 covers the first buffer layer 943, a second semiconductor layer is disposed on the second buffer layer 944, a fifth insulating layer 95 is disposed on a second active layer 12 in the second semiconductor layer, a first auxiliary signal line 48 is disposed on the fifth insulating layer 95, a sixth insulating layer 96 covers a third conductive layer, and a plurality of vias are provided on the sixth insulating layer 96. The plurality of vias at least include a fourth via V4, a sixth via V6, a fourteenth via V14, and a fifteenth via V15. The sixth insulating layer 96, the second buffer layer 944, the first buffer layer 943, the second interlayer insulating layer 942, the first interlayer insulating layer 941, the third insulating layer 93, and the second insulating layer 92 within the fourth via V4 and the sixth via V6 are etched away to respectively expose the surfaces at both ends of the sixth active layer. The sixth insulating layer 94 within the fourteenth via V14 and the fifteenth via V15 is etched away to respectively expose the surfaces at both ends of the second active layer.

[0179] (18) Form a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth metal thin film on the substrate on which the foregoing pattern is formed, and patterning the fourth metal thin film using a patterning process to form a fourth conductive layer disposed on the sixth insulating layer. The fourth conductive layer at least includes: a power supply connection line 51, an initial signal line 52, a fifth connection electrode 53, a sixth connection electrode 54, a seventh connection electrode 55, and an eighth connection electrode 56, as Figure 13a and Figure 13b shown. Figure 13b is Figure 13a a cross-sectional view taken along the line B-B in

[0180] As Figure 13a shown, in an exemplary embodiment, the zigzag power supply connection line 51 generally extends along the second direction Y. On the one hand, the power supply connection line 51 is connected to the second electrode plate 32 through a second via V2, and on the other hand, it is connected to the fifth active layer through a third via V3. The power supply connection line 51 is configured to be connected to a first power supply line formed subsequently.

[0181] In an exemplary embodiment, the initial signal line 52 extends along the first direction X and is disposed within the third region R3. On the one hand, the initial signal line 52 is connected to the first region of the seventh active layer through the seventh via V7, and on the other hand, it is connected to the first region of the first active layer through the sixteenth via V16, such that the first pole of the seventh transistor T7 and the first pole of the first transistor T1 have the same potential as the initial signal line 52.

[0182] In an exemplary embodiment, the fifth connection electrode 53 may be in a "C" shape. Its first end is connected to the first electrode plate 24 through the first via V1, its second end is connected to the first region (which is also the second region of the first active layer) of the second active layer through the fourteenth via V14, and the region between its first end and second end is connected to the node electrode 36 through the thirteenth via V13, such that the first electrode plate 24, the second pole of the first transistor T1, the first pole of the second transistor T2, and the node electrode 36 have the same potential. In an exemplary embodiment, the fifth connection electrode 53 may serve as the second pole of the first transistor T1 and the first pole of the second transistor T2.

[0183] In an exemplary embodiment, the orthographic projection of the fifth connection electrode 53 on the substrate completely covers the orthographic projection of the fourteenth via V14 on the substrate. Since the fifth connection electrode 53 is connected to the first region (which is also the second region of the first active layer) of the second active layer through the fourteenth via V14, and the second transistor (and the first transistor) is an oxide transistor, in this embodiment, covering the fourteenth via V14 completely with the fifth connection electrode 53 can prevent hydrogen elements from entering the IGZO channel at the position of the fourteenth via V14.

[0184] In an exemplary embodiment, the shortest distance between the edge of the orthographic projection of the fifth connection electrode 53 on the substrate and the edge of the orthographic projection of the fourteenth via V14 on the substrate is greater than the thickness of the first interlayer insulating layer 941 and / or the second interlayer insulating layer 942.

[0185] In an exemplary embodiment, the sixth connection electrode 54 may be rectangular. On the one hand, the sixth connection electrode 54 is connected to the first region (which is also the second region of the third active layer) of the sixth active layer through the sixth via V6, and on the other hand, it is connected to the second region of the second active layer through the fifteenth via V15, such that the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor have the same potential. In an exemplary embodiment, the sixth connection electrode 54 may serve as the second pole of the third transistor T3 and the second pole of the second transistor T2.

[0186] In an exemplary embodiment, the orthographic projection of the sixth connection electrode 54 on the substrate completely covers the orthographic projection of the fifteenth via V15 on the substrate. Since the sixth connection electrode 54 is connected to the second region of the second active layer through the fifteenth via V15, and the second transistor is an oxide transistor, in this embodiment, completely covering the fifteenth via V15 with the sixth connection electrode 54 can prevent hydrogen elements from entering the IGZO channel from the position of the fifteenth via V15.

[0187] In an exemplary embodiment, the shortest distance between the edge of the orthographic projection of the sixth connection electrode 54 on the substrate and the edge of the orthographic projection of the fifteenth via V15 on the substrate is greater than the thickness of the first interlayer insulating layer 941 and / or the second interlayer insulating layer 942.

[0188] In an exemplary embodiment, the seventh connection electrode 55 can be rectangular. The seventh connection electrode 55 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the fourth via V4, so that the second poles of the sixth transistor T6 and the seventh transistor T7 have the same potential. In an exemplary embodiment, the seventh connection electrode 55 can serve as the second poles of the sixth transistor T6 and the seventh transistor T7. In an exemplary embodiment, the seventh connection electrode 55 is configured to be connected to an anode connection electrode formed subsequently.

[0189] In an exemplary embodiment, the eighth connection electrode 56 is connected to the first region of the fourth active layer through the fifth via V5. In an exemplary embodiment, the eighth connection electrode 56 is configured to be connected to a data signal line formed subsequently, so that the data signal transmitted by the data signal line is written into the fourth transistor T4.

[0190] As Figure 13bAs shown, in a plane perpendicular to the substrate, a first insulating layer 91 is disposed on the substrate 10, a semiconductor layer is disposed on the first insulating layer 91, a second insulating layer 92 covers the semiconductor layer, a first conductive layer is disposed on the second insulating layer 92, a third insulating layer 93 covers the first conductive layer, a second conductive layer is disposed on the third insulating layer 93, a first interlayer insulating layer 941 covers the second conductive layer, a second interlayer insulating layer 942 covers the first interlayer insulating layer 941, a first buffer layer 943 covers the second interlayer insulating layer 942, a second buffer layer 944 covers the first buffer layer 943, a second semiconductor layer is disposed on the second buffer layer 944, a fifth insulating layer 95 is disposed on a second active layer 12 in the second semiconductor layer, a first auxiliary signal line 48 is disposed on the fifth insulating layer 95, a sixth insulating layer 96 covers a third conductive layer, a plurality of vias are provided on the sixth insulating layer 96, a fourth conductive layer is disposed on the sixth insulating layer 96, the fourth conductive layer includes at least a fifth connection electrode 53, a sixth connection electrode 54, and a seventh connection electrode 55, the seventh connection electrode 55 is connected to one end of a sixth active layer through a fourth via V4, the sixth connection electrode 54 is connected to the other end of the sixth active layer through a sixth via V6 on the one hand and is connected to one end of the second active layer through a fifteenth via V15 on the other hand, and the fifth connection electrode 53 is connected to the other end of the second active layer through a fourteenth via V14.

[0191] (19) Form a first passivation layer, a second passivation layer, and a first planarization layer pattern. In an exemplary embodiment, forming the first passivation layer, the second passivation layer, and the first planarization layer pattern may include: on the substrate on which the foregoing pattern is formed, first deposit a tenth insulating thin film and an eleventh insulating thin film in sequence, then coat a first planarizing thin film, and perform patterning on the tenth insulating thin film, the eleventh insulating thin film, and the first planarizing thin film by a patterning process to form a first passivation layer covering the fourth conductive layer, a second passivation layer covering the first passivation layer, and a first planarization layer covering the second passivation layer. A plurality of vias are provided on the first passivation layer, the second passivation layer, and the first planarization layer, and the plurality of vias include at least a twentieth via V20, a twenty-first via V21, and a twenty-second via V22, as Figure 14a and Figure 14b shown, Figure 14b is Figure 14a a cross-sectional view taken along line B-B in

[0192] As Figure 14aAs shown, the twentieth via V20 is located in the area where the seventh connection electrode 55 is located. The first planarization layer 98, the second passivation layer 972, and the first passivation layer 971 in the twentieth via V20 are removed, exposing the surface of the seventh connection electrode 55. The twentieth via V20 is configured to enable the subsequently formed anode connection electrode to be connected to the seventh connection electrode 55 through this via. The twenty-first via V21 is located in the area where the eighth connection electrode 56 is located. The first planarization layer 98, the second passivation layer 972, and the first passivation layer 971 in the twenty-first via V21 are removed, exposing the surface of the eighth connection electrode 56. The twenty-first via V21 is configured to enable the subsequently formed data signal line to be connected to the eighth connection electrode 56 through this via. The twenty-second via V22 is located in the area where the power supply connection line 51 is located. The first planarization layer 98, the second passivation layer 972, and the first passivation layer 971 in the twenty-second via V22 are removed, exposing the surface of the power supply connection line 51. The twenty-second via V22 is configured to enable the subsequently formed first power supply line to be connected to the power supply connection line 51 through this via.

[0193] In some exemplary embodiments, the hydrogen element content of the first passivation layer 971 is lower than that of the second passivation layer 972, and the film density of the second passivation layer 972 is higher than that of the first passivation layer 971.

[0194] In some exemplary embodiments, the material of the first passivation layer 971 is silicon oxide, and the material of the second passivation layer 972 is silicon nitride.

[0195] The passivation layer (PVX) in the related art generally uses a silicon oxide (SiO) film instead of a silicon nitride (SiN) film because the hydrogen element content in the silicon oxide film is less than that in the silicon nitride film and will not affect the characteristics of the Oxide transistor. However, the film density of silicon oxide is relatively poor, and the hydrogen element in the subsequent EVEN process may still affect the characteristics of the Oxide transistor. In the embodiments of the present disclosure, the passivation layer uses a double-layer structure, namely, two layers of the first passivation layer 971 and the second passivation layer 972. The first passivation layer 971 uses a silicon oxide film. The hydrogen element content in the silicon oxide film is small. On the one hand, it will not affect the characteristics of the Oxide transistor. On the other hand, it can block the downward diffusion of the hydrogen element in the upper silicon nitride film and thus affect the characteristics of the Oxide transistor. The second passivation layer 972 uses a silicon nitride film with a lower hydrogen element content. On the one hand, it avoids excessive downward diffusion of hydrogen elements and affects the characteristics of the Oxide transistor. On the other hand, the film density of the silicon nitride film of the second passivation layer 972 is higher than that of the silicon oxide film of the first passivation layer, which can block the influence of hydrogen elements in the subsequent EVEN process on the characteristics of the Oxide transistor, thereby improving the stability of the Oxide transistor.

[0196] Such asFigure 14b As shown, in a plane perpendicular to the substrate, a first insulating layer 91 is provided on the substrate 10, a semiconductor layer is provided on the first insulating layer 91, a second insulating layer 92 covers the semiconductor layer, a first conductive layer is provided on the second insulating layer 92, a third insulating layer 93 covers the first conductive layer, a second conductive layer is provided on the third insulating layer 93, a first interlayer insulating layer 941 covers the second conductive layer, a second interlayer insulating layer 942 covers the first interlayer insulating layer 941, a first buffer layer 943 covers the second interlayer insulating layer 942, a second buffer layer 944 covers the first buffer layer 943, a second semiconductor layer is provided on the second buffer layer 944, a fifth insulating layer 95 is provided on the second active layer 12 in the second semiconductor layer, a first auxiliary signal line 48 is provided on the fifth insulating layer 95, a sixth insulating layer 96 covers the third conductive layer, a plurality of vias are provided on the sixth insulating layer 96, a fourth conductive layer is provided on the sixth insulating layer 96, a first passivation layer 971, a second passivation layer 972 and a first planarizing layer 98 cover the fourth conductive layer, a plurality of vias are formed in the first passivation layer 971, the second passivation layer 972 and the first planarizing layer 98, and the plurality of vias at least include a 20th via V20. The first planarizing layer 98, the second passivation layer 972 and the first passivation layer 971 within the 20th via V20 are removed to expose the surface of the seventh connection electrode 55.

[0197] (20) Form a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth metal thin film on the substrate on which the foregoing pattern is formed, patterning the fifth metal thin film using a patterning process to form a fifth conductive layer provided on the first planarizing layer, and the fifth conductive layer at least includes: a data signal line 61, a first power supply line 62, and an anode connection electrode 63, as Figure 5a and Figure 5b shown, Figure 5b as Figure 5a shown in the cross-sectional view taken along line B-B in

[0198] As Figure 5a ​As shown, the data signal line 61 extends along the second direction Y, and the data signal line 61 is connected to the eighth connection electrode 56 through the twenty-first via V21. Since the eighth connection electrode 56 is connected to the first region of the fourth active layer through the fifth via, the connection between the data signal line 61 and the first pole of the fourth transistor T4 is realized, and the data signal transmitted by the data signal line is written into the fourth transistor T4. The first power supply line 62 generally extends along the second direction Y and is connected to the power supply connection line 51 through the twenty-second via V22, so that the power supply connection line 51 has the same potential as the first power supply line 62. In the first region R1 and the second region R2, the first power supply line 62 can be rectangular, so that the first power supply line 62 can effectively shield the key nodes of the pixel driving circuit, avoid the influence on the potential of the key nodes of the pixel driving circuit, and improve the display effect. The anode connection electrode 63 can be rectangular, and the anode connection electrode 63 is connected to the seventh connection electrode 55 through the twentieth via V20. The anode connection electrode 63 is configured to be connected to the anode formed subsequently.

[0199] As Figure 5b shown, in a plane perpendicular to the substrate, the first insulating layer 91 is disposed on the substrate 10, the semiconductor layer is disposed on the first insulating layer 91, the second insulating layer 92 covers the semiconductor layer, the first conductive layer is disposed on the second insulating layer 92, the third insulating layer 93 covers the first conductive layer, the second conductive layer is disposed on the third insulating layer 93, the first interlayer insulating layer 941 covers the second conductive layer, the second interlayer insulating layer 942 covers the first interlayer insulating layer 941, the first buffer layer 943 covers the second interlayer insulating layer 942, the second buffer layer 944 covers the first buffer layer 943, the second semiconductor layer is disposed on the second buffer layer 944, the fifth insulating layer 95 is disposed on the second active layer 12 in the second semiconductor layer, the first auxiliary signal line 48 is disposed on the fifth insulating layer 95, the sixth insulating layer 96 covers the third conductive layer, a plurality of vias are provided on the sixth insulating layer 96, the fourth conductive layer is disposed on the sixth insulating layer 96, the first passivation layer 971, the second passivation layer 972 and the first planarization layer 98 cover the fourth conductive layer, the fifth conductive layer is disposed on the first planarization layer 98, the fifth conductive layer at least includes the anode connection electrode 63, and the anode connection electrode 63 is connected to the seventh connection electrode 55 through the twentieth via V20.

[0200] (21) Form a second planarization layer pattern. In an exemplary embodiment, forming the second planarization layer pattern may include: coating a second planarization thin film on the substrate on which the foregoing pattern is formed, patterning the second planarization thin film by a patterning process to form a second planarization layer covering the fifth conductive layer, and at least the twenty-third via is provided on the second planarization layer.

[0201] In an exemplary embodiment, the twenty-third via is located in the region where the anode connection electrode is located. The second planar layer within the twenty-third via is removed to expose the surface of the anode connection electrode. The twenty-third via is configured to enable the subsequently formed anode to be connected to the anode connection electrode through this via.

[0202] (22) Form an anode pattern. In an exemplary embodiment, forming the anode pattern may include: depositing a transparent conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the transparent conductive thin film using a patterning process to form an anode disposed on the second planar layer.

[0203] In an exemplary embodiment, the anode may be hexagonal in shape, and the anode is connected to the anode connection electrode through the twenty-third via. Since the anode connection electrode is connected to the seventh connection electrode through the twentieth via, and the seventh connection electrode is connected to the sixth active layer through the fourth via, the pixel driving circuit can drive the light-emitting element to emit light.

[0204] In an exemplary embodiment, the subsequent preparation process may include: coating a pixel definition film, patterning the pixel definition film using a patterning process to form a pixel definition layer, and a pixel opening is provided in the pixel definition layer of each sub-pixel, and the pixel opening exposes the anode. An organic light-emitting layer is formed by evaporation or inkjet printing, and a cathode is formed on the organic light-emitting layer. A packaging layer is formed. The packaging layer may include a stacked first packaging layer, a second packaging layer, and a third packaging layer. The first packaging layer and the third packaging layer may use inorganic materials, and the second packaging layer may use an organic material. The second packaging layer is disposed between the first packaging layer and the third packaging layer, which can ensure that external moisture cannot enter the light-emitting structure layer.

[0205] The foregoing structure shown in the present disclosure and its preparation process are merely an exemplary illustration. In the exemplary embodiment, the corresponding structure may be changed according to actual needs, and the lithography process may be increased or decreased. For example, any one or more of the second interlayer insulating layer, the first buffer layer, and the second hydrogen barrier layer may be prepared. The display substrate of the present disclosure may be applied to other display devices having a pixel driving circuit, such as quantum dot displays, etc., and the present disclosure does not make a limitation herein.

[0206] As can be seen from the structure and manufacturing process of the display substrate described above, in the display substrate provided by the present disclosure, by providing a first interlayer insulating layer, a first hydrogen-blocking layer, and a second buffer layer between the polysilicon transistor layer and the oxide transistor layer, and the first hydrogen-blocking layer includes a second interlayer insulating layer and / or a first buffer layer, the influence of hydrogen elements in the polysilicon transistor layer on the oxide transistor layer is reduced, ensuring the stability of the polysilicon transistor and oxide transistor devices. In addition, the manufacturing process of the present disclosure can be well compatible with existing manufacturing processes, with simple process implementation, easy to implement, high production efficiency, low production cost, and high yield. The manufacturing process of the present disclosure can be well compatible with existing manufacturing processes, with simple process implementation, easy to implement, high production efficiency, low production cost, and high yield.

[0207] The present disclosure also provides a method for manufacturing a display substrate to manufacture the display substrate provided in the above embodiment.

[0208] In an exemplary embodiment, the manufacturing method may include:

[0209] Form a polysilicon transistor layer on a substrate, where the polysilicon transistor layer includes active layers and gate electrodes of a plurality of polysilicon transistors;

[0210] Sequentially form a first interlayer insulating layer, a first hydrogen-blocking layer, and a second buffer layer on the polysilicon transistor layer, where the hydrogen element content of the first interlayer insulating layer is greater than that of the first hydrogen-blocking layer, or the atomic ratio of silicon elements and oxygen elements of the first hydrogen-blocking layer is greater than that of the second buffer layer;

[0211] Form an oxide transistor layer on the second buffer layer, where the oxide transistor layer includes active layers and gate electrodes of a plurality of oxide transistors.

[0212] In an exemplary embodiment, the first hydrogen-blocking layer includes a second interlayer insulating layer, where the atomic ratio of silicon elements and nitrogen elements of the first interlayer insulating layer is greater than that of the second interlayer insulating layer and less than twice that of the second interlayer insulating layer.

[0213] In an exemplary embodiment, the first hydrogen-blocking layer includes a first buffer layer, where the atomic ratio of silicon elements and oxygen elements of the first buffer layer is greater than that of the second buffer layer and less than twice that of the second buffer layer.

[0214] In an exemplary embodiment, the manufacturing method may further include:

[0215] A fourth conductive layer is formed on the oxide transistor layer, and the fourth conductive layer includes first and second poles of a plurality of polysilicon transistors and first and second poles of a plurality of oxide transistors;

[0216] A first passivation layer is formed on the fourth conductive layer;

[0217] A second passivation layer is formed on the first passivation layer. The hydrogen element content of the first passivation layer is lower than that of the second passivation layer, and the atomic ratio of silicon element and oxygen element of the first passivation layer is greater than that of the second passivation layer.

[0218] The present disclosure also provides a display device, and the display device includes the foregoing display substrate. The display device may be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any product or component with a display function. The embodiments of the present invention are not limited thereto.

[0219] Although the disclosed embodiments are as above, the above content is only an embodiment adopted for facilitating the understanding of the present disclosure, and is not used to limit the present invention. Any person skilled in the art can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present disclosure. However, the scope of patent protection of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized in that, In a plane perpendicular to the display substrate, the display substrate includes a polysilicon transistor layer, a first interlayer insulating layer, a first hydrogen-blocking layer, a second buffer layer, and an oxide transistor layer that are sequentially disposed on a substrate, where: The polysilicon transistor layer includes active layers and gate electrodes of a plurality of polysilicon transistors, and the oxide transistor layer includes active layers and gate electrodes of a plurality of oxide transistors; The hydrogen element content of the first interlayer insulating layer is greater than that of the first hydrogen-blocking layer, or the atomic ratio of silicon to oxygen in the first hydrogen-blocking layer is greater than the atomic ratio of silicon to oxygen in the second buffer layer; The first hydrogen-blocking layer includes a second interlayer insulating layer, where the atomic ratio of silicon to nitrogen in the first interlayer insulating layer is greater than the atomic ratio of silicon to nitrogen in the second interlayer insulating layer and less than twice the atomic ratio of silicon to nitrogen in the second interlayer insulating layer.

2. The display substrate according to claim 1, characterized in that, The atomic ratio of silicon to nitrogen in the second interlayer insulating layer is between 0.7 and 0.

8.

3. The display substrate according to claim 1, characterized in that, The Si-H bond content of silicon hydride in the second interlayer insulating layer is 2 to 5 times that of the first interlayer insulating layer.

4. The display substrate according to claim 3, characterized in that, The Si-H bond content of silicon hydride in the second interlayer insulating layer is 1% to 3%.

5. The display substrate according to claim 1, characterized in that, The refractive index of the second interlayer insulating layer is between 1.8 and 1.9, the stress is controlled between -200 Mpa and 400 Mpa, and the N-H bond content is 5% to 10%.

6. The display substrate according to claim 1, characterized in that, The first hydrogen-blocking layer includes a first buffer layer, where the atomic ratio of silicon to oxygen in the first buffer layer is greater than the atomic ratio of silicon to oxygen in the second buffer layer and less than twice the atomic ratio of silicon to oxygen in the second buffer layer.

7. The display substrate according to claim 6, characterized in that, The atomic ratio of silicon to oxygen in the first buffer layer is between 1.1 and 1.

2.

8. The display substrate according to claim 1, characterized in that, The first hydrogen-blocking layer further includes a first buffer layer disposed on the second interlayer insulating layer, where The atomic ratio of silicon to oxygen in the first buffer layer is greater than the atomic ratio of silicon to oxygen in the second buffer layer and less than twice the atomic ratio of silicon to oxygen in the second buffer layer.

9. The display substrate according to claim 1, characterized in that, The polysilicon transistor layer includes a first semiconductor layer, a first conductive layer, and a second conductive layer that are sequentially disposed on a substrate, and the oxide transistor layer includes a second semiconductor layer and a third conductive layer that are sequentially disposed on the first hydrogen-blocking layer, where: The first semiconductor layer includes active layers of a plurality of polysilicon transistors, the first conductive layer includes gate electrodes of a plurality of polysilicon transistors and a first electrode plate of a storage capacitor, the second conductive layer includes a second electrode plate of the storage capacitor, the second semiconductor layer includes active layers of a plurality of oxide transistors, and the third conductive layer includes gate electrodes of a plurality of oxide transistors.

10. The display substrate according to claim 1, characterized in that, The polysilicon transistor layer includes a first semiconductor layer and a first conductive layer that are sequentially disposed on a substrate, and the oxide transistor layer includes a second semiconductor layer, a second conductive layer, and a third conductive layer that are sequentially disposed on the first hydrogen-blocking layer, where: The first semiconductor layer includes the active layers of a plurality of polysilicon transistors, and the first conductive layer includes the gate electrodes of the plurality of polysilicon transistors and the first electrode plate of the storage capacitor; the second semiconductor layer includes the active layers of a plurality of oxide transistors, the second conductive layer includes the second electrode plate of the storage capacitor, and the third conductive layer includes the gate electrodes of the plurality of oxide transistors.

11. A display device, characterized in that, A display substrate comprising the display substrate according to any one of claims 1 to 10.

12. A method for manufacturing a display substrate, characterized in that, Comprising: Forming a polysilicon transistor layer on a substrate, the polysilicon transistor layer including the active layers and gate electrodes of a plurality of polysilicon transistors; Forming a first interlayer insulating layer, a first hydrogen barrier layer, and a second buffer layer in sequence on the polysilicon transistor layer, wherein the hydrogen element content of the first interlayer insulating layer is greater than that of the first hydrogen barrier layer, or the atomic ratio of silicon element to oxygen element of the first hydrogen barrier layer is greater than that of the second buffer layer; the first hydrogen barrier layer includes a second interlayer insulating layer, wherein the atomic ratio of silicon element to nitrogen element of the first interlayer insulating layer is greater than that of the second interlayer insulating layer and less than twice that of the second interlayer insulating layer; Forming an oxide transistor layer on the second buffer layer, the oxide transistor layer including the active layers and gate electrodes of a plurality of oxide transistors.

13. A display substrate, characterized in that, In a plane perpendicular to the plane of the display substrate, the display substrate includes a polysilicon transistor layer, a first interlayer insulating layer, a first hydrogen barrier layer, a second buffer layer, and an oxide transistor layer sequentially disposed on a substrate, wherein: The polysilicon transistor layer includes the active layers and gate electrodes of a plurality of polysilicon transistors, and the oxide transistor layer includes the active layers and gate electrodes of a plurality of oxide transistors; The hydrogen element content of the first interlayer insulating layer is greater than that of the first hydrogen barrier layer, or the atomic ratio of silicon element to oxygen element of the first hydrogen barrier layer is greater than that of the second buffer layer; The display substrate further includes a fourth conductive layer disposed on the oxide transistor layer and a second hydrogen barrier layer covering the fourth conductive layer, wherein: The fourth conductive layer includes the first and second electrodes of a plurality of polysilicon transistors and the first and second electrodes of a plurality of oxide transistors; The second hydrogen barrier layer includes a first passivation layer and a second passivation layer disposed on the first passivation layer, the hydrogen element content of the first passivation layer is lower than that of the second passivation layer, and the atomic ratio of silicon element to oxygen element of the first passivation layer is greater than that of the second passivation layer.

14. The display substrate according to claim 13, wherein The material of the first passivation layer is silicon oxide, and the material of the second passivation layer is silicon nitride.

15. A display device, wherein A display substrate comprising the display substrate according to any one of claims 13 to 14.

16. A method for preparing a display substrate, wherein Comprising: Forming a polysilicon transistor layer on a substrate, the polysilicon transistor layer including the active layers and gate electrodes of a plurality of polysilicon transistors; A first interlayer insulating layer, a first hydrogen barrier layer, and a second buffer layer are sequentially formed on the polysilicon transistor layer. The hydrogen element content of the first interlayer insulating layer is greater than that of the first hydrogen barrier layer, or the atomic ratio of silicon to oxygen in the first hydrogen barrier layer is greater than that of silicon to oxygen in the second buffer layer; An oxide transistor layer is formed on the second buffer layer. The oxide transistor layer includes active layers and gate electrodes of a plurality of oxide transistors; A fourth conductive layer and a second hydrogen barrier layer covering the fourth conductive layer are sequentially formed on the oxide transistor layer. The fourth conductive layer includes first and second poles of a plurality of polysilicon transistors and first and second poles of a plurality of oxide transistors; the second hydrogen barrier layer includes a first passivation layer and a second passivation layer disposed on the first passivation layer. The hydrogen element content of the first passivation layer is lower than that of the second passivation layer, and the atomic ratio of silicon to oxygen in the first passivation layer is greater than that of silicon to oxygen in the second passivation layer.

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