Hard interrupt method and related apparatus
By pre-writing the breakpoint address within the process control block and writing it to the debug address register during scheduling, a hard interrupt for a single process is achieved even when the debug unit has not set the scontext, thus solving the problem that hardware breakpoints cannot distinguish between processes.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING ESWIN COMPUTING TECH CO LTD
- Filing Date
- 2021-09-27
- Publication Date
- 2026-05-29
AI Technical Summary
In the existing technology, if the debug unit does not set scontext, it is impossible to execute hardware breakpoints on a single process, making it impossible to distinguish which process the hardware breakpoint is set for, and thus impossible to implement hardware interrupts for a single process.
Hard interrupts are achieved by pre-writing breakpoint addresses within the process control block and writing the breakpoint addresses into the cleared debug address register when the process is scheduled to run.
Even when the debug unit does not have an scontext set, a hardware interrupt can be executed on a single process, solving the problem that hardware breakpoints cannot distinguish between processes.
Smart Images
Figure CN113961452B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the technical field of program debugging, specifically to a process hardware interruption method and related apparatus. Background Technology
[0002] Debuggers can stop program execution at will, mainly through software breakpoints and hardware breakpoints. Software breakpoints are breakpoint instructions added to the program; the program stops when it reaches the breakpoint instruction (i.e., a software interrupt). Hardware breakpoints are breakpoint addresses stored in the debug address register; the debug module monitors the program execution and controls the program to stop when it reaches the breakpoint address (also known as a hardware interrupt).
[0003] The debugging unit specifically includes the aforementioned debug address register, control register, and debug controller. There are four debug address registers, each storing a breakpoint address. There is one control register, used to store the status of each hardware breakpoint, such as breakpoint type and length. The debug controller monitors the instruction fetch address of the instruction fetch unit and determines whether the fetch address is a breakpoint address. If so, it generates an interrupt instruction to control the instruction execution unit to interrupt program execution. For a certain processor architecture, if the debug unit does not have an scontext that stores context information (used to mark which process a hardware breakpoint is set for), it cannot distinguish which process each hardware breakpoint is set for. Therefore, each hardware breakpoint will be configured for all processes that fetch instructions from its breakpoint address during execution, resulting in the technical problem of not being able to set hardware breakpoints for individual processes. Summary of the Invention
[0004] To address the aforementioned technical problems, this disclosure provides a process hardware interrupt method and related apparatus, enabling the processor to perform a hardware interrupt on a single process even when no scontext is set in the debug unit.
[0005] According to a first aspect of this disclosure, a process hardware interruption method is provided, wherein a breakpoint address is pre-written into the process control block of the process, and the process hardware interruption method includes:
[0006] When the process is scheduled to run, the breakpoint address is obtained from the process control block;
[0007] The obtained breakpoint address is written into the cleared debug address register so that the debugging unit can execute a hard interrupt based on the breakpoint address stored in the debug address register during the execution of the process.
[0008] Optionally, if the process belongs to the process being debugged, the breakpoint address will be pre-written into the process control block, and the process hard interrupt method further includes:
[0009] Determine whether a breakpoint address exists within the process control block;
[0010] If a breakpoint address exists within the process control block, the breakpoint address is obtained from the process control block.
[0011] Optionally, the breakpoint address within the process control block is pre-written using the "hbreak" command within the gdb debugging tool.
[0012] Optionally, the process hard interrupt method further includes: erasing the breakpoint address stored in the debug address register when the process is scheduled out of the running state.
[0013] Optionally, if the process belongs to the process being debugged, the breakpoint address will be pre-written into the process control block, and the process hard interrupt method further includes:
[0014] Determine whether a breakpoint address exists within the process control block;
[0015] If a breakpoint address exists in the process control block, the breakpoint address stored in the debug address register is erased.
[0016] Optionally, the process hard interrupt method further includes: deleting individual or all breakpoint addresses pre-written in the process control block before the process runs.
[0017] Optionally, the breakpoint address within the process control block is deleted using the "deletebreak" command within the gdb debugging tool.
[0018] Optionally, the process hard interrupt method further includes: during the execution of the process, erasing individual or all breakpoint addresses stored in the debug address registers.
[0019] According to a second aspect of this disclosure, an electronic device is provided, comprising: a processor and a memory, wherein the memory stores a program executable by the processor, the program being executed by the processor to implement the steps of any of the methods described in the first aspect.
[0020] According to a third aspect of this disclosure, a computer-readable storage medium is provided, characterized in that a computer program is stored on the computer-readable storage medium, which, when executed by a processor, implements the steps of any of the methods described in the first aspect.
[0021] The beneficial effects of this disclosure are:
[0022] In this disclosure, the process control block of the process is pre-written with the breakpoint address. When the process is scheduled to run, the breakpoint address is obtained from the process control block and written into the cleared debug address register. This ensures that the debug address register only stores the breakpoint address of the process during the process's execution, thus enabling the setting of hardware breakpoints for the process. This allows the processor to execute a hardware interrupt for a single process even if no scontext is set in the debug unit.
[0023] It should be noted that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this disclosure. Attached Figure Description
[0024] Figure 1 A schematic diagram of an electronic device provided in an embodiment of this disclosure is shown;
[0025] Figure 2 A schematic diagram of the memory and processor provided in an embodiment of this disclosure is shown;
[0026] Figure 3 This diagram illustrates a process hard interruption method provided in an embodiment of the present disclosure.
[0027] Figure 4 This diagram illustrates another process hard interruption method provided in an embodiment of the present disclosure;
[0028] Figure 5 This diagram illustrates another process hard interruption method provided in an embodiment of the present disclosure. Detailed Implementation
[0029] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure. However, this disclosure may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure.
[0030] System Overview
[0031] Figure 1 A schematic block diagram of an electronic device according to an embodiment of this disclosure is shown. This electronic device 10 can be built based on various processors currently available on the market and powered by Windows. TM Operating system versions, UNIX operating systems, Linux operating systems, and other operating system drivers. In addition, electronic device 10 can be hardware such as PCs, desktops, laptops, servers, and mobile communication devices.
[0032] like Figure 1As shown, the electronic device 10 of this disclosure embodiment may include one or more processors 12 and a memory 14.
[0033] The memory 14 may be main memory (or simply main memory or RAM). It is used to store instruction information and / or data information represented by data signals, such as data provided by the processor 12 (e.g., calculation results), and may also be used to realize data exchange between the processor 12 and the external storage device 17 (or auxiliary memory or external memory).
[0034] In some situations, the processor 12 may need to access memory 14 to retrieve or modify data in memory 14. Because memory 14 has a relatively slow access speed, to alleviate the speed difference between the processor 12 and memory 14, the electronic device 10 also includes a cache memory 18 coupled to the bus 11. The cache memory 18 is used to cache program data or message data that may be repeatedly accessed in memory 14. The cache memory 18 is implemented, for example, by a storage device of the type Static Random Access Memory (SRAM). The cache memory 18 can be a multi-level structure, such as a three-level cache structure with a Level 1 cache (L1 cache), a Level 2 cache (L2 cache), and a Level 3 cache (L3 cache), or a cache structure with more than three levels or other types of cache structures. In some embodiments, a portion of the cache memory 18 (e.g., the Level 1 cache, or the Level 1 cache and the Level 2 cache) can be integrated inside the processor 12 or integrated with the processor 12 on the same on-chip system.
[0035] The processor 12 may include an instruction execution unit 121, a memory management unit 122, and other components. When executing instructions that require modification of memory (such as modifying the process control block stored in memory), the instruction execution unit 121 initiates a write access request. This write access request specifies the data to be written to memory and the corresponding physical address. The memory management unit 122 is used to translate the virtual address specified by these instructions into the physical address mapped by that virtual address. The physical address specified by the write access request may be the same as the physical address specified by the corresponding instruction.
[0036] Information exchange between memory 14 and cache memory 18 is typically organized in blocks. In some embodiments, cache memory 18 and memory 14 may be divided into data blocks of the same spatial size, and a data block may serve as the smallest unit of data exchange between cache memory 18 and memory 14 (including one or more data of a preset length). For clarity, each data block in cache memory 18 will be referred to as a cache block (or cache line), and different cache blocks will have different cache block addresses; each data block in memory 14 will be referred to as a memory block, and different memory blocks will have different memory block addresses. Cache block addresses may include, for example, physical address tags used to locate the data blocks.
[0037] Due to space and resource limitations, cache memory 18 cannot cache all the contents of memory 14; that is, the storage capacity of cache memory 18 is usually smaller than that of memory 14, and the addresses of individual cache blocks provided by cache memory 18 cannot correspond to all the memory block addresses provided by memory 14. When processor 12 needs to access memory, it first accesses cache memory 18 via bus 11 to determine whether the content to be accessed is already stored in cache memory 18. If so, cache memory 18 is hit, and processor 12 directly retrieves the content to be accessed from cache memory 18. If the content to be accessed by processor 12 is not in cache memory 18, processor 12 needs to access memory 14 via bus 11 to find the corresponding information in memory 14. Because the access speed of cache memory 18 is very fast, when cache memory 18 is hit, the efficiency of processor 12 can be significantly improved, thereby improving the performance and efficiency of the entire electronic device 10.
[0038] In addition, electronic device 10 may also include input / output devices such as storage device 17, display device 13, audio device 15, and mouse / keyboard 16. Storage device 17 is, for example, a hard disk, optical disk, or flash memory that is coupled to bus 11 via a corresponding interface for information storage and retrieval. Display device 13 is, for example, coupled to bus 11 via a corresponding graphics card for displaying information according to display signals provided by bus 11.
[0039] Electronic device 10 typically also includes communication device 19, thus enabling communication with networks or other devices in various ways. Communication device 19 may include, for example, one or more communication modules. As an example, communication device 19 may include a wireless communication module adapted to a specific wireless communication protocol. For instance, communication device 19 may include a WLAN module for implementing Wi-Fi™ communication conforming to the IEEE 802.11 standard; communication device 19 may also include a WWAN module for implementing wireless wide area communication conforming to cellular or other wireless wide area protocols; communication device 19 may also include communication modules employing other protocols, such as Bluetooth modules, or other custom-type communication modules; communication device 19 may also be a port for serial data transmission.
[0040] Of course, the structure of different electronic devices 10 may vary depending on the motherboard, operating system, and instruction set architecture. For example, many electronic devices 10 currently have an input / output control center connected between the bus 11 and various input / output devices, and this input / output control center may be integrated into the processor 12 or independent of the processor 12.
[0041] processor
[0042] Figure 2 This is a schematic block diagram of the processor 12 in an embodiment of this disclosure.
[0043] In some embodiments, each processor 12 may include one or more processor cores 120 for processing instructions, the processing and execution of which can be controlled by a user (e.g., through an application) and / or the system platform. In some embodiments, each processor core 120 may be used to process a specific instruction set. In some embodiments, the instruction set may support Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation based on Very Long Instruction Word (VLIW). Different processor cores 120 may each process different or the same instruction sets. In some embodiments, the processor core 120 may also include other processing modules, such as a Digital Signal Processor (DSP). As an example, Figure 2 The diagram shows processor cores 1 through m, where m is a non-zero natural number.
[0044] In some embodiments, Figure 1The cache memory 18 shown can be wholly or partially integrated into the processor 12. Depending on the architecture, the cache memory 18 can be a single or multi-level internal high-speed cache memory located within and / or outside each processor core 120 (e.g., ...). Figure 2 The three-level high-speed cache memory L1 to L3 are shown. Figure 2 The cache, uniformly identified as 18, may also include an instruction-oriented cache and a data-oriented cache. In some embodiments, the various components in the processor 12 may share at least a portion of the cache memory, such as... Figure 2 As shown, processor cores 1 to m share a common level 3 cache memory L3. Processor 12 may also include an external cache (not shown), and other cache structures may also serve as external caches for processor 12.
[0045] In some embodiments, such as Figure 2 As shown, processor 12 may include a register file 126, which may include multiple registers for storing different types of data and / or instructions. These registers may be of different types. For example, register file 126 may include integer registers, floating-point registers, status registers, instruction registers, and pointer registers. The registers in register file 126 may be implemented using general-purpose registers, or a specific design may be adopted according to the actual needs of processor 12.
[0046] Processor 12 may include a Memory Management Unit (MMU) 122 for translating virtual addresses to physical addresses. The MMU 122 caches a portion of the entries in the page table and can also retrieve uncached entries from memory. Each processor core 120 may have one or more MMUs 122. The MMUs 122 in different processor cores 120 can be synchronized with those in other processors or processor cores, allowing each processor 12 or processor core 120 to share a unified virtual memory system.
[0047] Processor 12 is used to execute a sequence of instructions (i.e., a program). The process of processor 12 executing each instruction includes: fetching the instruction from the memory where the instructions are stored, decoding the fetched instruction, executing the decoded instruction, and saving the instruction execution result, etc., and so on, until all instructions in the instruction sequence are executed or a halt instruction is encountered (e.g., a breakpoint instruction set in the program sequence for software interruption, or an interrupt instruction sent by debug unit 123 for hardware breakpoint).
[0048] To implement the above process, the processor 12 may include an instruction fetch unit 124, an instruction decode unit 125, an instruction issue unit 127, an instruction execution unit 121, and an instruction de-instruction unit 128, etc.
[0049] The instruction fetch unit 124 serves as the boot engine of the processor 12, used to move instructions from memory 14 to the instruction register (which may be...). Figure 2 The instruction is stored in one of the registers in the register file 26 shown, and the next fetch address is received or calculated according to the fetch algorithm, which may include, for example, incrementing or decrementing the address based on the instruction length.
[0050] After the instruction is fetched, the processor 12 enters the instruction decoding stage. The instruction decoding unit 125 decodes the fetched instruction according to a predetermined instruction format to obtain the operand fetch information required by the fetched instruction, thereby preparing for the operation of the instruction execution unit 121. Operand fetch information includes, for example, pointers to immediate values, registers, or other software / hardware that can provide source operands.
[0051] The instruction dispatch unit 127, typically located within the high-performance processor 12, lies between the instruction decoding unit 125 and the instruction execution unit 121. It is used for instruction scheduling and control, efficiently allocating instructions to different instruction execution units 121, thus enabling parallel operation of multiple instructions. After an instruction is fetched, decoded, and scheduled to the corresponding instruction execution unit 121, the unit begins executing the instruction, performing the operation indicated by the instruction and implementing the corresponding function (e.g., writing a breakpoint address to or erasing a breakpoint address already written to the debug address register included in the debug unit 123).
[0052] The instruction write-back unit 128 (or instruction write-back unit) is mainly responsible for writing the execution results generated by the instruction execution unit 121 back to the corresponding storage location (e.g., a register inside the processor 12), so that subsequent instructions can quickly obtain the corresponding execution results from that storage location.
[0053] Different instruction execution units 121 can be set up in the processor 12 for different types of instructions. The instruction execution unit 121 can be an arithmetic unit (e.g., containing an arithmetic logic unit, vector arithmetic unit, etc., used to perform operations based on operands and output the results), a memory execution unit (e.g., used to access memory according to instructions to read data from memory, write specified data to memory, or erase data stored in memory), or a coprocessor, etc. In the processor 12, each instruction execution unit 121 can run in parallel and output corresponding execution results.
[0054] When executing a certain type of instruction (such as a memory access instruction), the instruction execution unit 121 needs to access the memory 14 to obtain information stored in the memory 14 or to provide data that needs to be written to the memory 14.
[0055] It should be noted that the instruction execution unit 121 used to execute memory access instructions can also be simply referred to as the memory execution unit. This memory execution unit is, for example, a load store unit (LSU) and / or other units used for memory access.
[0056] After the memory access instruction is fetched by the instruction fetch unit 124, the instruction decoding unit 125 can decode the memory access instruction so that the source operand of the memory access instruction can be fetched. The decoded memory access instruction is provided to the corresponding instruction execution unit 121, which can perform corresponding operations on the source operand of the memory access instruction (for example, the arithmetic logic unit performs operations on the source operand stored in the register) to obtain the address information corresponding to the memory access instruction, and initiate corresponding requests based on the address information, such as address translation requests, write access requests, etc.
[0057] The source operand of a memory access instruction typically includes an address operand. The instruction execution unit 121 performs operations on this address operand to obtain the virtual or physical address corresponding to the memory access instruction. When the memory management unit 122 is disabled, the instruction execution unit 121 can directly obtain the physical address of the memory access instruction through logical operations. When the memory management unit 122 is enabled, the corresponding instruction execution unit 121 initiates an address translation request based on the virtual address corresponding to the memory access instruction. This address translation request includes the virtual address corresponding to the address operand of the memory access instruction. The memory management unit 122 responds to the address translation request and converts the virtual address in the address translation request into a physical address based on the entry matching the virtual address, so that the instruction execution unit 121 can access the cache memory 18 and / or memory 14 according to the translated physical address.
[0058] Depending on their function, memory access instructions may include load instructions and store instructions. The execution of a load instruction typically does not require modification of the information in memory 14 or cache memory 18. The instruction execution unit 121 only needs to read the data stored in memory 14, cache memory 18, or an external storage device according to the address operand of the load instruction.
[0059] Unlike load instructions, store instructions include not only address operands but also data information as their source operands. The execution of store instructions typically requires modification of memory 14 and / or cache memory 18. The data information in a store instruction can point to data to be written. This written data can originate from the execution results of arithmetic instructions, load instructions, or other instructions, as well as data provided by registers or other storage units in processor 12, or even immediate values.
[0060] During program development, debugging is often required; therefore, a debugging unit 123 is also included in the processor 12. The debugging unit 123 includes a debug address register, a control register, and a debug controller. There are four debug address registers, each used to store a breakpoint address, thus preventing the number of hardware breakpoints in a process from being unlimited. There is one control register used to store the status of each hardware breakpoint, such as the breakpoint type and breakpoint length. The debug controller monitors the instruction fetch address of the instruction fetch unit 124 and determines whether the fetch address is a breakpoint address. If so, it generates an interrupt instruction to control the instruction execution unit 121 to interrupt the program execution.
[0061] Process hardware interrupt method
[0062] In some processors, the debug unit has an scontext stored in a control register. The scontext stores context information (context ID), which identifies the process for which a hardware breakpoint is set. Therefore, a hardware breakpoint is only valid within the specific process identified by its context information. For the processor 12, which does not have an scontext set in the debug unit 123, executing a hardware interrupt for a single process using existing technology is difficult. Therefore, this disclosure provides a process hardware interrupt method, which is executed by the processor 12 executing a program stored in memory 14. The relevant program can also be stored on a computer-readable storage medium and then read into memory 14.
[0063] Figure 3 The diagram shows a flowchart of the process hard interrupt method. See also... Figure 3 The process control block of the process pre-writes the breakpoint address, and the process's hardware interrupt methods include:
[0064] Step S120: When the process is scheduled to run, obtain the breakpoint address from the process control block.
[0065] Step S140: Write the obtained breakpoint address into the cleared debug address register so that the debug unit 123 can execute a hard interrupt based on the breakpoint address stored in the debug address register during the process execution.
[0066] It should be noted that the Process Control Block (PCB) is a dedicated data structure set up by the system for managing processes, and it is loaded into memory 14. In Linux, the kernel's PCB is a `task_struct` structure. The PCB is used to record the external characteristics of a process, describe the process's movement and changes, and can also be used to control and manage the process. The PCB typically includes a program counter (i.e., the address of the instruction to be executed next) and memory management information (such as the page tab table). Therefore, the execution order of steps S120 and S140 can be set so that when the corresponding process is scheduled to run, the breakpoint address pre-written in the PCB can be specified to be written to the cleared debug address register.
[0067] Specifically, the processor 12 reads the interrupt address from the memory 14 and writes it into the cleared debug address register. This is a process in which the processor 12 reads data from the memory 14 and writes it into the register. This process is implemented by combining the instruction fetch unit 124, the instruction decode unit 125, the instruction issue unit 127, and the instruction execution unit 121. Please refer to the relevant description of the processor 12 above, which will not be repeated here.
[0068] The aforementioned debugging unit 123 executes a hard interrupt based on the breakpoint address stored in the debug address register during the process's execution. This is an existing technology, and the relevant description of the debugging unit 123 above can be referred to, so it will not be repeated here.
[0069] In this embodiment of the disclosure, when a process is scheduled to run, the processor 12 executes a program and writes an interrupt address into the cleared debug address register. Therefore, during the process's execution, the debug address register contains the interrupt address stored for that process. In other words, the data in the debug address register is bound to the process. Thus, the debug unit 123 executes a hard interrupt for the current process based on the interrupt address in the debug address register, thereby realizing a hard interrupt for a single process and solving the technical problem that the debug unit 123 cannot set a hard interrupt for a single process without setting scontext.
[0070] In some examples, all processes executed by processor 12 include processes that require debugging and processes that do not require debugging; only processes that require debugging have a need for hardware interrupts. Therefore, breakpoint addresses are pre-written into the process control block only when the process is being debugged; see [link to relevant documentation]. Figure 4The process hard interrupt method includes: step S110, determining whether there is a breakpoint address in the process control block, wherein if there is, it means that the process belongs to the process being debugged, and step S120 is executed; if there is no breakpoint, it means that the process does not belong to the process being debugged, and the processor 12 does not need to stop at step S120 in the execution process of the process hard interrupt method, and can directly end.
[0071] Specifically, the breakpoint address within the process control block is pre-written using the "hbreak" command within the gdb debugging tool. The "hbreak" command has the following usage methods:
[0072] 1) `hbreak x.cpp:y` means adding a breakpoint at line y in the program `x.cpp`.
[0073] 2) hbreak 0xN, which means adding a breakpoint at address N, where N must be a valid program segment address;
[0074] 3) `hbreak x.cpp:func` means adding a breakpoint at the entry point of the `func` function in the program `x.cpp`;
[0075] The above usage of the "hbreak" command demonstrates that the breakpoint address set in the process control block is specified in the program.
[0076] In one optional embodiment of this disclosure, see [link to relevant documentation]. Figure 5 The process hard interrupt method also includes: step S160, when the process is scheduled out of the running state, the breakpoint address stored in the debug address register is erased, that is, the data in the debug address register is cleared in time after a process finishes execution, so as to ensure that the debug address register is in a cleared state when the next process is executed.
[0077] Similarly, considering that all processes executed by processor 12 may include both processes that need debugging and processes that do not need debugging, only processes that need debugging have a need for hard interrupts. Therefore, when a process is a process being debugged, the breakpoint address will be pre-written into the process control block. Subsequently, the execution of step S140 will write the breakpoint address into the debug address register. In view of this, the process hard interrupt method also includes: when a process is scheduled out of the running state, first checking whether there is a breakpoint address in the process control block. If it exists, step S160 is executed; if it does not exist, it means that no breakpoint address has been written for the current process in the debug address register, so the invalid execution of step S160 is not performed, and the process ends directly.
[0078] In another optional embodiment of this disclosure, the process hard interrupt method further includes: deleting individual or all breakpoint addresses pre-written in the process control block before the process runs. This step is often used to adjust the hardware breakpoints in the process before it runs.
[0079] Specifically, the breakpoint address within the process control block is deleted using the "delete break" command within the gdb debugging tool. The "delete break" command performs the inverse operation of the "hbreak" command; for usage instructions, please refer to the section on "hbreak" command usage above.
[0080] In another optional embodiment of this disclosure, the process hardware interrupt method further includes: erasing breakpoint addresses stored in individual debug address registers or all debug address registers during the execution of the process. This step is often used to adjust hardware breakpoints within the process during its execution. It should be understood that since the hardware breakpoints set in the embodiments of this disclosure are only valid within the currently running process, adjusting hardware breakpoints during process execution also adjusts the hardware breakpoints of the currently running process. Thus, the erased debug address registers are those that the process has not yet reached its internal breakpoint addresses.
[0081] Whether erasing data within the process control block or erasing data within the debug address register, both are performed by the memory execution unit, which is an instruction execution unit 121. For details, please refer to the above description of the processor 12, which will not be repeated here.
[0082] It should be understood that the above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. For those skilled in the art, there are many variations of the embodiments in this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.
[0083] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.
[0084] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0085] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.
[0086] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.
Claims
1. A method for hard interrupting a process, characterized in that, The process control block of the process is pre-written with breakpoint addresses, and the hard interrupt method includes: When the process is scheduled to run, the breakpoint address is obtained from the process control block; The obtained breakpoint address is written into the cleared debug address register, so that the breakpoint address stored in the debug address register is bound to the running process, so that the debugging unit can execute a hard interrupt based on the breakpoint address stored in the debug address register during the running of the process. When the process is scheduled out of the running state, the breakpoint addresses stored in the debug address register are erased. The breakpoint addresses within the process control block are pre-written using the "hbreak" command within the gdb debugging tool.
2. The process hard interrupt method according to claim 1, characterized in that, The process control block will only pre-write breakpoint addresses if the process belongs to the process being debugged. The process hard interrupt method also includes: Determine whether a breakpoint address exists within the process control block; If a breakpoint address exists within the process control block, the breakpoint address is obtained from the process control block.
3. The process hard interrupt method according to claim 1, characterized in that, The process control block will only pre-write breakpoint addresses if the process belongs to the process being debugged. The process hard interrupt method also includes: Determine whether a breakpoint address exists within the process control block; If a breakpoint address exists in the process control block, the breakpoint address stored in the debug address register is erased.
4. The process hard interrupt method according to claim 1, characterized in that, Also includes: Before the process runs, delete individual or all breakpoint addresses that were pre-written in the process control block.
5. The process hard interruption method according to claim 4, characterized in that, The breakpoint address within the process control block was deleted using the "delete break" command within the gdb debugging tool.
6. The process hard interrupt method according to claim 1, characterized in that, Also includes: During the execution of the process, breakpoint addresses stored in individual or all of the debug address registers are erased.
7. An electronic device, characterized in that, include: A processor and a memory, wherein the memory stores a program that can be executed by the processor, the program being executed by the processor to implement the steps of the method as described in any one of claims 1-6.
8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method as described in any one of claims 1-6.