Apparatus including threshold voltage compensated sense amplifier and compensation method thereof

Abstract

Disclosed are devices including threshold-voltage compensated sense amplifiers and methods of compensation thereof. Example threshold-voltage compensated sense amplifiers according to the present disclosure include circuitry for providing threshold-voltage compensation, such as an isolation transistor and at least one pre-charge transistor.

Description

Technical Field

[0001] This disclosure relates to memory devices, and more specifically, to devices comprising threshold voltage compensated sensing amplifiers and methods thereof. Background Technology

[0002] A memory device is structured as an array of one or more memory cells logically arranged in rows and columns. Each memory cell stores data as a charge for access on a digital line associated with the memory cell. When a charged memory cell is accessed, the memory cell causes a positive voltage change on the associated digital line, and an uncharged accessed memory cell causes a negative voltage change on the associated digital line. A sense amplifier senses and amplifies the voltage changes on the digital lines to indicate the value of the data state stored in the memory cell.

[0003] Conventional sense amplifiers are typically coupled to a pair of complementary digital lines coupled to a large number of memory cells (not shown). As is known in the art, when a memory cell is accessed, a row of memory cells is activated, and the sense amplifier amplifies the data state of the corresponding activated column of memory cells by coupling each of the digital lines in the selected column to a voltage supply such that the digital lines have complementary logic levels.

[0004] When a memory cell is accessed, depending on whether the memory cell coupled to the digital line is charged, the voltage of one of the digital lines increases or decreases slightly, creating a voltage difference between the digital lines. When the voltage of one digital line increases or decreases slightly, the other digital line does not act as a reference for sensing operation. Due to the voltage difference, a corresponding transistor is activated, which in turn couples the slightly higher voltage digital line to the supply voltage and the other digital line to a reference voltage (e.g., ground), further driving each of the digital lines in the opposite direction and amplifying the signal on the selected digital line.

[0005] The digital lines are precharged to a precharge voltage (e.g., half the supply voltage) during the precharge period, enabling accurate sensing and amplification of voltage differences during subsequent sensing operations. However, due to random threshold voltage mismatches in the transistor components, the digital lines may suddenly become unbalanced before sensing and amplifying a voltage change on one of the digital lines. Such threshold voltage deviations can cause the sensing amplifier to incorrectly amplify the input signal in the wrong direction.

[0006] To address the aforementioned threshold voltage deviation, sensing amplifiers designed to mitigate threshold voltage mismatch have been developed. However, these sensing amplifier designs incorporating such voltage compensation increase the area of ​​the sensing amplifier region. Therefore, it is necessary to reduce the area of ​​the sensing amplifier region. Summary of the Invention

[0007] On one hand, this disclosure provides an apparatus comprising: a first transistor including a first source coupled to a first power node, a first drain coupled to the first node, and a first gate coupled to a second node; a second transistor including a second source coupled to the first power node, a second drain coupled to the second node, and a second gate coupled to the first node; a third transistor including a third source coupled to the second power node, a third gate coupled to the second node, and a third drain; a fourth transistor including a fourth source coupled to the second power node, a fourth gate coupled to the first node, and a fourth drain; and a fifth transistor including a fifth source coupled to the third drain, a fifth drain coupled to the first node, and a third drain. A fifth gate configured to receive a first control signal; a sixth transistor comprising a sixth source coupled to the fourth drain, a sixth drain coupled to the second node, and a sixth gate configured to receive the first control signal; a seventh transistor comprising a seventh source coupled to the second node, a seventh drain coupled to the third drain, and a seventh gate configured to receive a second control signal; an eighth transistor comprising an eighth source coupled to the first node, an eighth drain coupled to the fourth drain, and an eighth gate configured to receive the second control signal; and a ninth transistor comprising a ninth source configured to receive a voltage, a ninth drain coupled to at least one of the first or second nodes, and a ninth gate configured to receive a third control signal.

[0008] On the other hand, this disclosure further provides an apparatus comprising: first, second, and third transistors coupled in series between a first power node and a second power node; fourth, fifth, and sixth transistors coupled in series between the first power node and the second power node; a seventh transistor coupled to a second node between the second and third transistors and the fourth and fifth transistors; an eighth transistor coupled to the third and fourth transistors and a first node between the first and second transistors; and a ninth transistor coupled to at least one of the first and second nodes, wherein the gates of the first and third transistors are coupled to the second node, and the gates of the fourth and sixth transistors are coupled to the first node.

[0009] On the other hand, this disclosure further provides a method comprising: precharging first and second sensing nodes of a sensing amplifier to a precharge voltage, wherein first and second transistors are respectively coupled to the first and second sensing nodes; deactivating a first isolation transistor coupled to the first sensing node and a third transistor, and deactivating a second isolation transistor coupled to the second sensing node and a fourth transistor, so as to isolate the first and second sensing nodes from the third and fourth transistors coupled to a ground node at a ground voltage level, respectively; and coupling the drain and gate of the third and fourth transistors to the second and first sensing nodes, respectively. Attached Figure Description

[0010] Figure 1 This is a schematic block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2 This is a schematic diagram of a sense amplifier and a pair of complementary digital lines according to an embodiment of the present disclosure.

[0012] Figure 3 This is a schematic diagram of a sense amplifier according to an embodiment of the present disclosure.

[0013] Figure 4A and 4B This is a timing diagram of various signals during the operation of the sense amplifier according to an embodiment of the present disclosure.

[0014] Figure 5 This is a diagram illustrating the layout of a portion of the peripheral region and memory subarray region of a memory according to embodiments of the present disclosure.

[0015] Figure 6 This is a schematic diagram of a sense amplifier according to an embodiment of the present disclosure.

[0016] Figure 7A and 7B This is a timing diagram of various signals during the operation of the sense amplifier according to an embodiment of the present disclosure. Detailed Implementation

[0017] Various embodiments of this disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects and embodiments of this disclosure. The detailed description contains sufficient detail to enable those skilled in the art to practice embodiments of this disclosure. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0018] Figure 1This is a schematic block diagram of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 may include a clock input circuit 105, an internal clock generator 107, a timing generator 109, an address command input circuit 115, an address decoder 120, a command decoder 125, multiple row (e.g., first access line) decoders 130, a memory cell array 145 including a sense amplifier 150 and a transfer gate 195, multiple column (e.g., second access line) decoders 140, multiple read / write amplifiers 165, input / output (I / O) circuitry 170, and a voltage generator 190. The semiconductor device 100 may include multiple external terminals, including address and command terminals coupled to a command / address bus 110, clock terminals CK and / or CK, data terminals DQ, DQS, and DM, and power supply terminals VDD, VSS, VDDQ, and VSSQ. In some instances, the terminals and signal lines associated with the command / address bus 110 may include a first set of terminals and signal lines configured to receive command signals and a separate second set of terminals and signal lines configured to receive address signals. In other instances, the terminals and signal lines associated with the command and address bus 110 may include common terminals and signal lines configured to receive both command signals and address signals. The semiconductor device may be mounted on a substrate, such as a memory module substrate, a motherboard, etc.

[0019] The memory cell array 145 comprises multiple groups BANK0-N, where N is a positive integer, such as 3, 7, 15, 31, etc. Each group BANK0-N may include multiple word lines WL, multiple digital lines DL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple digital lines DL. The selection of the word line WL for each group BANK0-N is performed by the corresponding row decoder 130, and the selection of the digital line DL is performed by the corresponding column decoder 140. Multiple sense amplifiers 150 are positioned for their corresponding digital lines DL and coupled to at least one corresponding local I / O line via a transfer gate TG 195 acting as a switch, the local I / O line being further coupled to a corresponding one of at least two main I / O line pairs. The sense amplifiers 150 and the transfer gate TG 195 may operate based on control signals from a decoder circuitry, which may include command decoder 120, row decoder 130, column decoder 140, any control circuitry of the memory cell array 145 of groups BANK0-N, or any combination thereof. In some instances, the tRCD of the semiconductor device 100 may involve the operation of the circuitry of the row decoder 130, the column decoder 140, and the memory cell array 145 of each of the plurality of groups BANK0-N (e.g., including a plurality of sense amplifiers 150 and a transfer gate TG 195).

[0020] In some instances, multiple sense amplifiers 150 may include a threshold voltage compensation circuitry to compensate for threshold voltage differences between components of the sense amplifier 150. As circuit components become smaller, clock speeds increase, and voltage / power consumption requirements decrease, small performance differences between circuit components of the sense amplifier 150 (e.g., due to process, voltage, and temperature (PVT) differences) may reduce the operational reliability of the semiconductor device 100. To mitigate the effects of these variations, compensation for some of these threshold voltage differences (Vt) may be included by using internal node biases in the sense amplifier 150 configured to provide sense data to the output node, coupled to digital lines DL and DLb of the sense amplifier 150, before activating the sense amplifier 150 to sense data. The biases of the digital lines DL and DLb may be based on threshold voltage differences between at least two circuit components (e.g., transistors) of the sense amplifier 150. Compensating for threshold voltage differences (Vt) between circuit components within the sense amplifier 150 can improve reliability.

[0021] Address / command input circuit 115 can receive address signals and group address signals from the outside via command / address bus 110 at the command / address terminal, and transmit the address signals and group address signals to address decoder 120. Address decoder 120 can decode the address signals received from address / command input circuit 115, and provide row address signal XADD to row decoder 130 and column address signal YADD to column decoder 140. Address decoder 120 can also receive group address signals, and provide group address signal BADD to row decoder 130 and column decoder 140.

[0022] Address / command input circuitry 115 can receive command signals from an external source, such as memory controller 105, via command / address bus 110 at command / address terminals and provide the command signals to command decoder 125. Command decoder 125 can decode the command signals and generate various internal command signals. Internal command signals can be used to control the operation and timing of various circuits in semiconductor device 100. For example, internal command signals may include row and column command signals, such as read or write commands, sent to control circuitry to perform access operations on selected word lines and digital lines.

[0023] Therefore, when an activation and read command is issued and the row and column addresses are supplied in a timely manner with the activation and read command, read data is read from the memory cell array 145 specified by the row and column addresses. The read / write amplifier 165 can receive the read data DQ and provide the read data DQ to the I / O circuit 170. The I / O circuit 170 can provide the read data DQ, the data strobe signal at DQS, and the data mask signal at DM to the outside via data terminals DQ, DQS, and DM. Similarly, when an activation and write command is issued and the row and column addresses are supplied in a timely manner with the activation and write command, the input / output circuit 170 can receive the write data at data terminals DQ, DQS, and DM, the data strobe signal at DQS, and the data mask signal at DM, and provide the write data to the memory cell array 145 via the read / write amplifier 165. Therefore, write data can be written to the memory cell specified by the row and column addresses.

[0024] Turning to the description of external terminals included in semiconductor device 100, clock terminals CK and / CK can receive an external clock signal and a complementary external clock signal, respectively. The external clock signal (including the complementary external clock signal) can be supplied to clock input circuit 105. Clock input circuit 105 can receive the external clock signal and generate an internal clock signal ICLK. Clock input circuit 105 can provide the internal clock signal ICLK to internal clock generator 107. Internal clock generator 107 can generate a phase-controlled internal clock signal LCLK based on the received internal clock signal ICLK and a clock enable signal CKE from address / command input circuit 115. A DLL circuit can be used as internal clock generator 107, but is not limited to it. Internal clock generator 107 can provide the phase-controlled internal clock signal LCLK to IO circuit 170 and timing generator 109. IO circuit 170 can use the phase-controlled internal clock signal LCLK as a timing signal for determining the output timing of read data. Timing generator 109 can receive the internal clock signal ICLK and generate individual internal clock signals.

[0025] The power supply terminals can receive power supply voltages VDD and VSS. These power supply voltages VDD and VSS can be supplied to voltage generator circuit 190. Voltage generator circuit 190 can generate various internal voltages VPP, VOD, VBLP, NSA_BIAS, VARY, VPERI, etc., based on the power supply voltages VDD and VSS. Internal voltage VPP is mainly used for line decoder 130, internal voltages VOD, VBLP, NSA_BIAS, and VARY are mainly used for sense amplifier 150 included in memory cell array 145, and internal voltage VPERI is used for many other circuit blocks. I / O circuit 170 can receive power supply voltages VDD and VSSQ. For example, power supply voltages VDDQ and VSSQ can be the same voltages as power supply voltages VDD and VSS, respectively. However, dedicated power supply voltages VDDQ and VSSQ can be used for I / O circuit 170.

[0026] Figure 2 This is a schematic diagram of a portion of a memory 200 including a sense amplifier 210 and a pair of complementary digital lines DL 220 and DLb221 according to an embodiment of the present disclosure. Figure 2 As shown, the sense amplifier 210 is coupled to the pair of true and complementary digital (or bit) lines DL 220 and DLb 221 at sense nodes 230 and 231, respectively. Memory cells 240(0)-(N) can be selectively coupled to digital line DL 220 via corresponding access devices (e.g., transistors) 250(0)-(N), and memory cells 241(0)-(N) can be selectively coupled to digital line DLb 221 via corresponding access devices (e.g., transistors) 251(0)-(N). Word lines WL 260(0)-(N) can be controlled to determine which of the memory cells 240(0)-(N) are coupled to digital line DL 220 by controlling the gates of the corresponding access devices 250(0)-(N). Similarly, word lines WL261(0)-(N) can control which memory cells 241(0)-(N) are coupled to digital lines DLb221 by controlling the gates of the corresponding access devices 251(0)-(N). Sensing amplifier 210 can be controlled via control signal 270, received via decoder circuitry, for example, commanding the decoder (e.g., Figure 1 Command decoder 125), line decoder (e.g., Figure 1 The row decoder 130), column decoder (e.g., Figure 1 The column decoder 140), memory array control circuitry (e.g., Figure 1 The control circuitry of the memory cell array 145 of the memory group BANK0-N (or any combination thereof).

[0027] In some instances, memory 200 can operate in a general phase or mode. A first phase (e.g., a precharge phase) can be initiated in response to a precharge command. During the precharge phase, word lines WL 260(0)-(N) and 261(0)-(N) can be set to an inactive state, and in response, access devices 250(0)-(N) and 251(0)-(N) can be completely deactivated. Furthermore, internal nodes in digital lines DL 220 and DLb 221 and sense amplifier 210 configured to provide sensed data states to output nodes can be precharged to and remain at a precharge voltage, such as the digital line precharge voltage VBLP, until transitioning to the second phase.

[0028] In some instances, the sense amplifier 210 includes a threshold voltage compensation circuitry system that compensates for threshold voltage mismatch between components of the sense amplifier 210 during a threshold voltage compensation phase. To perform threshold voltage compensation, the sense amplifier 210 may precharge or bias sensing nodes 230 and 231 coupled to digital lines DL 220 and DLb 221 during the threshold voltage compensation phase, such that the voltage difference between sensing nodes 230 and 231 is approximately equal to the threshold voltage difference between at least two circuit components of the sense amplifier 210. In some instances, the threshold voltage difference may be based on the threshold voltage of the transistors in the sense amplifier 210. Compensating for the threshold voltage Vt difference between circuit components within the sense amplifier 210 improves reliability and accuracy.

[0029] The third stage can be a cell information sampling stage. During the sampling stage, word lines WL 260(0)-(N) and 261(0)-(N) can be set to an active state, and in response, access devices in access devices 250(0)-(N) and 251(0)-(N) can be activated to couple the corresponding memory cells in memory cells 240(0)-(N) and 241(0)-(N) to one of digital lines DL 220 and DLb 221. When activated, the memory cells provide the stored data state in the form of voltage (and / or charge) to the digital lines and to the sensing nodes in the sensing amplifier 210 coupled to the digital lines.

[0030] The fourth stage is the sense amplifier activation stage. The sense amplifier 210 can be activated to perform a sensing operation that senses the data state of the activated memory cell. That is, during the sensing operation, the data state stored in the activated memory cell is sensed and amplified by the sense amplifier 210 to drive one of the digital lines DL 220 or DLb 221 to a high or low voltage level corresponding to the sensed data state, and to drive the other digital line of DL 220 and DLb 221 to a complementary (opposite) voltage level. The circuitry of the memory 200 can remain in the activation stage or transition back to the precharge stage in response to a precharge command.

[0031] Reference memory cells 240(0)-(N), in response to the corresponding word line 260(0)-(N) becoming active, one memory cell in memory cells 240(0)-(N) is coupled to digital line DL 220 via a corresponding access device 250(0)-(N). The data state stored in the memory cell is sensed and amplified by sense amplifier 210 to drive digital line DL 220 to a high or low voltage level corresponding to the sensed data state. During sensing operation, another digital line DLb 221 is driven to a complementary voltage level (e.g., high voltage level is complementary to low voltage level, and low voltage level is complementary to high voltage level). Similarly, in response to the corresponding word line 261(0)-(N) becoming active, one memory cell in memory cells 241(0)-(N) is coupled to digital line DLb 221 via a corresponding access device 251(0)-(N). The data state stored in the memory cell is sensed and amplified by the sensing amplifier 210 to drive the digital line DLb 221 to a high or low voltage level corresponding to the sensed data state. During sensing operation, another digital line DL 220 is driven to a complementary voltage level.

[0032] During threshold voltage compensation operation, sensing nodes 230 and 231 of sensing amplifier 210 may be isolated from each other in response to a control signal 270 (e.g., from decoder circuitry). For example, during a pre-charge phase, sensing nodes 230 and 231 of sensing amplifier 210 may be coupled to each other and coupled to a pre-charge voltage to be pre-charged to that voltage. When sensing nodes 230 and 231 of sensing amplifier 210 are pre-charged, the control signal 270 may configure sensing amplifier 210 to isolate sensing nodes 230 and 231 from each other. A voltage difference may then be generated at sensing nodes 230 and 231 to provide threshold voltage compensation.

[0033] Figure 3 This is a schematic diagram of a sensing amplifier 300 according to an embodiment of the present disclosure. The sensing amplifier 300 may be included in... Figure 1 The sensing amplifier 150 and / or Figure 2 One or more of the sensing amplifiers 210.

[0034] The sense amplifier 300 includes transistors of a first type (e.g., p-type field-effect transistors (PFETs)) 310 and 311, each having a drain coupled to (sensing) nodes 314 and 315, respectively. The sense amplifier 300 further includes transistors of a second type (e.g., n-type field-effect transistors (NFETs)) 312 and 313, each having a drain coupled to nodes 314 and 315 via isolation transistors 351 and 352, respectively. The sources of transistors 351 and 352 are coupled to nodes 314 and 315, respectively, and the drains of transistors 351 and 352 are coupled to the sources of transistors 312 and 313, respectively. The respective gates of transistors 310 and 312 are coupled to node 315, and the respective gates of transistors 311 and 313 are coupled to node 314. The sources of transistors 310 and 311 are coupled to a power supply node ACT, and the sources of transistors 312 and 313 are coupled to a ground node GND at a ground voltage level. Digital line DL is coupled to node 314, and digital line DLb is coupled to node 315. In some embodiments of this disclosure, digital line DL may represent Figure 2 The digital line DL 220, and the digital line DLb can represent the digital line DLb 221, and the nodes 314 and 315 can represent the sensing nodes 230 and 231, respectively.

[0035] The sense amplifier 300 further includes a transistor 318 having a drain and a source coupled to nodes 314 and 315, respectively, and includes a pre-charged transistor 319 coupled to node 315. In this embodiment, transistor 319 is coupled to node 315; however, in some embodiments, transistor 319 may additionally or alternatively be coupled to node 314. When activated by an active control signal BLEQ (e.g., a high logic level), transistor 319 provides a voltage from its source to node 315. In some embodiments of this disclosure, when transistor 319 is active, voltage VBLP is provided to node 315. And, when activated by the active control signal BLEQ, transistor 318 provides a conductive path between nodes 314 and 315 to equalize the respective node voltages. In some embodiments of this disclosure, voltage VBLP may be approximately 0.5V.

[0036] The sense amplifier 300 further includes transistors 316 and 317. Transistor 316 is coupled to the drain of transistor 312, and nodes 315 and 317 are coupled to the drain of transistor 313 and node 314. Transistors 316 and 317 are activated by an active control signal BLECP (e.g., an active high logic level).

[0037] exist Figure 3In the diagram, transistors 310 and 311 are shown as PFETs, and transistors 312, 313, 316, 317, 318, 319, 351, and 352 are shown as NFETs. However, without departing from the scope of this disclosure, one or more of the transistors may be converted to another conductivity type, and / or to another transistor or another circuit.

[0038] As will be described below, the sense amplifier 300 can provide threshold voltage compensation. The sense amplifier 300 can offer advantages over conventional sense amplifiers that provide threshold voltage compensation. For example, compared to these other sense amplifier designs, the sense amplifier 300 or related circuitry may contain fewer circuit components (e.g., transistors), such as omitting a row N sense amplifier latch (RNL) driver. Therefore, the sense amplifier 300, and other sense amplifiers according to embodiments of this disclosure, can provide a more compact circuit design and lower circuit complexity.

[0039] Reference Figure 4A and 4B Example operation of a sense amplifier 300 according to an embodiment of the present disclosure is described. In example operation, it is assumed that transistors 312 and 313 should be matched and have the same threshold voltage vth. However, typically due to variations in the manufacture of transistors 312 and 313, the respective threshold voltages vth of transistors 312 and 313 are mismatched and not the same. For example, assuming that transistors 312 and 313 are designed to have a nominal threshold voltage vth, the threshold voltage mismatch between transistors 312 and 313 can be characterized as Δvth. That is, the threshold voltage of transistor 313 deviates from the threshold voltage of transistor 312 by Δvth. Similarly, due to variations in the manufacture of transistors 310 and 311, the respective threshold voltages of transistors 310 and 311 are mismatched and not the same. A local threshold voltage mismatch between transistors 310 and 311 can be characterized as Δ. Threshold voltage compensation can be provided by a compensation voltage provided to one or both of nodes 314 and 315 when the sense amplifier 300 is ready to be activated. The compensation voltages provided to nodes 314 and 315 can compensate for the threshold voltage mismatch between transistors 312, 313, 310 and 311, which can be expressed as (Δvth+Δ), which is the total threshold voltage deviation.

[0040] Figure 4A and 4B This is a diagram of various signals during operation of the sensing amplifier 300 according to an embodiment of the present disclosure. Figure 4A The voltages of the control signals BLEQ, BLECP, and ISO, as well as the power node ACT and access line WL, are shown. Figure 4B The voltages of digital lines DL and DLb are shown.

[0041] Before time T1, the sense amplifier and digital line have been precharged during the precharge phase. Transistor 319 is activated by the active control signal BLEQ to provide voltage VBLP to node 315. The control signal BLEQ is the active level that activates transistor 318 to form a conductive path between nodes 314 and 315. Therefore, when the BLEQ signal is active, nodes 314 and 315 have the same voltage level, i.e., the voltage VBLP provided by the activated transistor 319. Also before time T1, the control signal ISO is at an inactive level (e.g., ground voltage GND, negative voltage, etc.) to deactivate transistors 351 and 352. Therefore, nodes 314 and 315 are isolated from transistors 312 and 313, respectively. In some embodiments of this disclosure, the control signal ISO may be inactive when at, for example, a negative voltage of -0.2V, to control any leakage current. Before time T1, the power node ACT is approximately half the voltage VARY (e.g., 0.5V). Therefore, before time T1, digital lines DL and DLb (which are coupled to nodes 314 and 315, respectively) are at the VBLP voltage. Additionally, the gate and drain of transistor 310 are coupled together via activated transistor 318, and the gate and drain of transistor 311 are coupled together, while the gates and drains of transistors 312 and 313 are isolated from each other via inactive transistors 316 and 317.

[0042] Next, the operation during the threshold voltage compensation (VtC) phase between times T1 and T2 is described. After time T1, transistors 319 and 318 are deactivated by the inactive BLEQ signal (e.g., at ground level), no longer supplying voltage VBLP to nodes 315 and 314. Transistors 316 and 317 can be activated by the active signal BLECP. Upon activation, transistor 316 couples the drain of transistor 312 to the gate of transistor 312 and node 315, and transistor 317 couples the drain of transistor 313 to the gate of transistor 313 and node 314. The voltage supplied to power node ACT changes from approximately half the voltage VARY to a high voltage level, such as VARY. The voltages at nodes 314 and 315 change due to the VARY voltage supplied to power node ACT and the fact that transistors 318 and 319 no longer supply voltage VBLP to nodes 314 and 315. As explained above, transistors 312 and 313 should be matched and have the same threshold voltage vth, but transistor 313 actually has a threshold voltage (vth + Δvth) that deviates from the threshold voltage vth of transistor 312 by Δvth. Furthermore, transistor 311 may also have a threshold voltage that deviates partially by Δvth from the threshold voltage of transistor 311. Therefore, the compensation level difference between nodes 314 and 315 can be expressed as (Δvth + Δ), which is the total threshold voltage deviation. The resulting voltages at nodes 314 and 315 change the voltages of digital lines DL and DLb, respectively. In this example operation, the voltage of digital line DL is greater than the voltage of digital line DLb (e.g., the voltage at node 314 is greater than the voltage at node 315), and the voltage difference between nodes 314 and 315 is, for example, (Δvth + Δvth).

[0043] The difference between the corresponding voltages at nodes 314 and 315 (e.g., Δvth + Δ) can represent the sum of the threshold voltage offset (Δvth) between the threshold voltages of transistors 312 and 313 and the local threshold voltage offset (Δ) between the threshold voltages of transistors 310 and 311. Threshold voltage compensation (e.g., for transistors 310 and 311 and 312 and 313) can be provided by generating corresponding voltages at nodes 314 and 315.

[0044] The next operation between times T2 and T3 is the third stage, namely the cell information sampling operation. The access line WL can be activated after time T2 (e.g., by making it high) to couple the memory cell to the digital line DL or digital line DLb, as previously referenced. Figure 2Description. A memory cell coupled to a digital line DL or DLb causes a voltage change on the corresponding digital line based on the data state stored in the memory cell. For example, when the stored data state corresponds to a positive charge stored in the memory cell, the memory cell can increase the voltage of the corresponding digital line. The change in the corresponding digital line DL or DLb from the memory cell is reflected at the corresponding node 314 or 315. Node 314 is coupled to the gate of the corresponding transistors 311 and 313, and node 315 is coupled to the gate of the corresponding transistors 310 and 312.

[0045] The difference between the corresponding voltages at nodes 314 and 315 (e.g., Vsig + Δvth + Δ) can represent the sum of the signal difference (Vsig) on ​​digital lines DL and DLb, the threshold voltage offset (Δvth) between the threshold voltages of transistors 312 and 313, and the local threshold voltage offset (Δ) between the threshold voltages of transistors 310 and 311. Therefore, in addition to the signal difference, threshold voltage compensation can also be provided (e.g., for transistors 310 and 311, and 312 and 313).

[0046] The next operation between times T3 and T4 is the fourth stage, the sense amplifier activation stage. After time T3, the control signal ISO becomes active to activate transistors 351 and 352, which couple the conductive paths between nodes 314 and 315 and transistors 312 and 313, respectively. After time T3, the voltage supplied to the power node ACT also changes from approximately half the voltage VARY back to a high voltage level VARY to "activate" the sense amplifier 300. The corresponding voltages under the power nodes ACT and GND amplify the voltage difference between digital lines DL and DLb by driving the sense node and digital lines to opposite voltage levels (e.g., high and low activation voltages) based on the voltage difference.

[0047] In this example, when the voltage of the digital line DL is increased in the memory cell, the activation level of transistor 313 is greater than that of transistor 312. Therefore, the digital line DLb is initially pulled down to a low activation voltage supplied to the power node (e.g., GND), which in turn activates transistor 310 to pull up the sensing node 314 and further activates transistor 313. Through the positive feedback loop of transistors 313 and 310, the digital line DLb (and sensing node 315) are driven to a low activation voltage, and the digital line DL (and sensing node 314) are driven to a high activation voltage. Before time T4, the access line WL becomes inactive (e.g., becomes inactive (low) voltage level) to isolate the memory cell from the digital line DL.

[0048] During the sense amplifier activation phase, the sense amplifier is activated by providing high and low activation voltages, and the voltage difference between digital lines DL and DLb is amplified by driving digital lines DL and DLb to opposite activation voltages based on the voltage difference (e.g., generated by a memory cell coupled to a digital line).

[0049] After the sense amplifier activation phase is completed, operation returns to the pre-charge phase from time T4. After time T4, the sense amplifier can be prepared for another sensing operation by pre-charging digital lines DL and DLb, as previously described. For example, the control signal BLEQ becomes active again and activates transistors 318 and 319. Additionally, after time T4, the control signal ISO also becomes inactive again to deactivate transistors 351 and 352, thereby isolating nodes 314 and 315 from transistors 312 and 313, respectively. The voltage supplied to power node ACT changes from a high voltage level to approximately half the voltage VARY (e.g., 0.5V). Therefore, digital lines DL and DLb are coupled through active transistor 318 and set to the pre-charge voltage, and through active transistor 319 to approximately half the voltage VARY. The sense amplifier 300 is in the same pre-charge state as at time T0 previously described and is ready for another access operation.

[0050] exist Figure 4A In some examples, the power supply voltage ACT and control signals BLEQ, ISO, and BLECP are shown at specific timings relative to other voltages and control signals. However, embodiments of this disclosure include those different from the references. Figure 4A Other voltage and signal timings are described. Therefore, the scope of this disclosure is not limited to... Figure 4A This is a specific example. Because the sense amplifier 300 is directly coupled to the node GND, the minimum number of clock cycles required to enable a row of memory and access its columns can be relaxed (e.g., RAS to CAS delay, tRCD).

[0051] exist Figure 4A In this example, the control signals BLEQ, ISO, and BLECP can be activated at or slightly above the voltage VARY. The control signal ISO can use the same voltage VARY as the other control signals, rather than a voltage significantly higher than VARY, which improves reliability. (See reference...) Figure 4A The power supply voltage provided to the power node ACT, as described, can be provided by a voltage circuit. This voltage circuit can be, for example, from a command decoder (e.g., in some embodiments of this disclosure, for...). Figure 1 The internal signal control of the command decoder 125).

[0052] Figure 5This is a schematic diagram illustrating the layout of a portion of the peripheral region 510 of the memory and the memory subarray region 520 according to embodiments of the present disclosure. In some embodiments of the present disclosure, the memory subarray region 520 may be included in a memory cell array (e.g., included in...). Figure 1 In the memory cell array 145), and the peripheral area 510 may be arranged adjacent to the memory subarray area and / or between the memory subarray areas.

[0053] Peripheral region 510 includes a sub-word line driver (SWD) region 530. SWD region 530 may include sub-word line driver circuitry that selectively drives sub-word lines of memory subarray region 520 to activate selected memory cells for access. Peripheral region 510 may further include a sense amplifier (SA) region 540 in which a sense amplifier (e.g., sense amplifier 300 in some embodiments of this disclosure) may be included.

[0054] The microgap region 535 included in the peripheral region 510 may have dimensions based on the SWD height of the SWD region 530 and the SA height of the SA region 540. The microgap region 535 may include circuitry used when operating the sub-word line driver of the SWD region 530 and / or the sense amplifier (including sense amplifier 300) operating the SA region 540. For example, the microgap region 535 may include voltage circuitry providing various voltages for operating the sense amplifier of the SA region 540.

[0055] In examples where the microgap region 535 and SA region 540 are relatively compact, including some circuitry can be challenging, such as voltage circuitry traditionally used to provide RNL drivers. Voltage circuitry can have relatively large dimensions because it needs to be sufficiently drivable to obtain the various voltages. A sense amplifier 300 without row N-sensor amplifier latch (RNL) drivers in the microgap region 535 and SA region 540 can function with a compact peripheral region 510.

[0056] Figure 6 This is a schematic diagram of a sensing amplifier 600 according to an embodiment of the present disclosure. The sensing amplifier 600 may be included in... Figure 1 The sensing amplifier 150 and / or Figure 2 One or more of the sensing amplifiers 210.

[0057] The sense amplifier 600 includes transistors of a first type (e.g., p-type field-effect transistors (PFETs)) 610 and 611, each having a drain coupled to nodes 614 and 615, respectively. The sense amplifier 600 further includes transistors of a second type (e.g., n-type field-effect transistors (NFETs)) 612 and 613, each having a drain coupled to nodes 614 and 615 via isolation transistors 651 and 652, respectively. The sources of transistors 651 and 652 are coupled to nodes 614 and 615, respectively, and the drains of transistors 651 and 652 are coupled to nodes 616 and 617, respectively. The respective gates of transistors 610 and 612 are coupled to node 615, and the respective gates of transistors 611 and 613 are coupled to node 614. The sources of transistors 610 and 611 are coupled to power node ACT, and the sources of transistors 612 and 613 are coupled to power node RNL, which receives voltage from the row N sense amplifier latch (RNL) driver. Digital line DL is coupled to node 614, and digital line DLb is coupled to node 615. In some embodiments of this disclosure, digital line DL may represent Figure 2 The digital line DL 220, and the digital line DLb can represent the digital line DLb 221.

[0058] The sense amplifier 600 further includes a pre-charged transistor 619 coupled to node 615. When activated by an active control signal BLEQ (e.g., a high logic level), transistor 619 provides a voltage from its source to node 615. In some embodiments of this disclosure, a voltage VBLP is provided to node 615 when transistor 619 is active. In some embodiments of this disclosure, the voltage VBLP may be approximately 0.5V.

[0059] The sense amplifier 600 further includes transistors 616 and 617. Transistor 616 is coupled to the drain of transistor 612 and node 615, and transistor 617 is coupled to the drain of transistor 613 and node 614. Transistors 616 and 617 are activated by an active control signal BLECP (e.g., an active high logic level).

[0060] exist Figure 6 In the diagram, transistors 610 and 611 are shown as PFETs, and transistors 612, 613, 616, 617, 651, 652 and 619 are shown as NFETs. However, one or more of the transistors may be replaced with another type, another transistor, or another circuit without departing from the scope of this disclosure.

[0061] As will be described below, the sense amplifier 600 can provide threshold voltage compensation. The sense amplifier 600 offers advantages over conventional sense amplifiers that provide threshold voltage compensation. For example, compared to these other sense amplifier designs, the sense amplifier 600 can include fewer circuit components (e.g., transistors), such as a relatively small row N sense amplifier latch (RNL) driver with weaker drive capability. Therefore, the sense amplifier 600, and other sense amplifiers according to embodiments of this disclosure, can provide a more compact circuit design.

[0062] Reference Figure 7A and 7B Example operation of a sense amplifier 600 according to an embodiment of the present disclosure is described. In example operation, it is assumed that transistors 612 and 613 should be matched and have the same threshold voltage vth. However, typically due to variations in the manufacture of transistors 612 and 613, the respective threshold voltages vth of transistors 612 and 613 are mismatched and not the same. For example, assuming that transistors 612 and 613 are designed to have a nominal threshold voltage vth, the threshold voltage mismatch between transistors 612 and 613 can be characterized as Δvth. That is, the threshold voltage of transistor 613 deviates from the threshold voltage of transistor 612 by Δvth. Similarly, due to variations in the manufacture of transistors 610 and 611, the respective threshold voltages of transistors 610 and 611 are mismatched and not the same. A local threshold voltage mismatch between transistors 610 and 611 can be characterized as Δ. Threshold voltage compensation can be provided by a compensation voltage provided to one or both of nodes 614 and 615 when the sense amplifier 600 is ready to be activated. The compensation voltage provided to nodes 614 and 615 can compensate for the threshold voltage mismatch between transistors 612, 613, 610 and 711, which can be expressed as (Δvth+Δ), which is the total threshold voltage deviation.

[0063] Figure 7A and 7B This is a diagram of various signals during operation of the sensing amplifier 600 according to an embodiment of the present disclosure. Figure 7A The voltages of the control signals BLEQ, BLECP, and ISO, as well as the power node ACT and access line WL, are shown. Figure 7B The voltages of digital lines DL and DLb are shown.

[0064] Before time T1, the sense amplifier and digital lines have already been precharged during the precharge phase. Transistor 619 is activated by the active control signal BLEQ to provide voltage VBLP to node 615. Furthermore, the control signal ISO activates transistors 651 and 652 to maintain the active level of the conductive paths between transistors 610 and 611, respectively, through nodes 614 and 615 and transistors 612 and 613. Additionally, transistors 616 and 617 can be activated by the active signal BLECP. Upon activation, transistor 616 couples the gate and drain of transistor 612 to node 615, and transistor 617 couples the gate and drain of transistor 613 to node 614. Therefore, through the activation of transistors 616, 617, 651, and 652, digital lines DL and DLb (which are coupled to nodes 614 and 615, respectively) change from complementary voltage levels to VBLP at time T1.

[0065] The voltage supplied to power node ACT changes from a high voltage level to approximately half the voltage VARY (e.g., 0.5V), and the voltage supplied to power node RNL changes from a low voltage level to approximately half the voltage VARY.

[0066] Next, the operation during the threshold voltage compensation (VtC) phase between times T1 and T2 is described. After time T1, transistor 619 is deactivated by the inactive BLEQ signal (e.g., at ground level) and no longer supplies voltage VBLP to nodes 615 and 614. The voltage supplied to power node ACT changes from approximately half the voltage VARY to a high voltage level, e.g., VARY, while the voltage supplied to power node RNL changes from approximately half the voltage VARY to a low voltage level, e.g., ground level (GND). In response to the active control signals BLECP and ISO, the voltages of nodes 614 and 615 change due to the VARY voltage supplied to power node ACT and the fact that transistor 619 no longer supplies voltage VBLP to node 615, but nodes 614 and 615 remain coupled together via transistors 616, 617, 651, and 652. In response to the inactive BLEQ signal, the high voltage at power node ACT, and the ground voltage at power node RNL, the signal levels of DL and DLb begin to change.

[0067] As explained above, transistors 612 and 613 should be matched and have the same threshold voltage vth, but transistor 613 actually has a threshold voltage (vth + Δvth) that deviates from the threshold voltage vth of transistor 612 by Δvth. Furthermore, transistor 611 may also have a threshold voltage that deviates partially by Δvth from the threshold voltage of transistor 610. Therefore, the compensation level difference between nodes 614 and 615 can be expressed as (Δvth + Δ), which is the total threshold voltage deviation. The resulting voltages at nodes 614 and 615 change the voltages of digital lines DL and DLb, respectively. In this example operation, the voltage of digital line DL is greater than the voltage of digital line DLb (e.g., the voltage at node 614 is greater than the voltage at node 615), and the voltage difference between nodes 614 and 615 is, for example, (Δvth + Δvth).

[0068] The difference between the corresponding voltages at nodes 614 and 615 (e.g., Δvth + Δ) can represent the sum of the threshold voltage offset (Δvth) between the threshold voltages of transistors 612 and 613 and the local threshold voltage offset (Δ) between the threshold voltages of transistors 610 and 611. Threshold voltage compensation (e.g., for transistors 610 and 611 and 612 and 613) can be provided by generating corresponding voltages at nodes 614 and 615.

[0069] After a short while, the control signal BLECP is deactivated, and nodes 614 and 615 are isolated from transistors 652 and 613, and 651 and 612, respectively. The voltage supplied to power node ACT becomes approximately half of voltage VARY again. In this way, the threshold voltage compensation phase is performed.

[0070] The next operation between times T2 and T3 is the third stage, namely the cell information sampling operation. The access line WL can be activated after time T2 (e.g., by making it high) to couple the memory cell to the digital line DL or digital line DLb, as previously referenced. Figure 2 Description. A memory cell coupled to a digital line DL or DLb causes a voltage change on the corresponding digital line based on the data state stored in the memory cell. For example, when the stored data state corresponds to a positive charge stored in the memory cell, the memory cell can increase the voltage of the corresponding digital line. The change in the corresponding digital line DL or DLb from the memory cell is reflected at the corresponding node 614 or 615. Node 614 is coupled to the gate of the corresponding transistors 611 and 613, and node 615 is coupled to the gate of the corresponding transistors 610 and 612.

[0071] The difference between the corresponding voltages at nodes 614 and 615 (e.g., Vsig + Δvth + Δ) can represent the sum of the signal difference (Vsig) on ​​digital lines DL and DLb, the threshold voltage offset (Δvth) between the threshold voltages of transistors 612 and 613, and the local threshold voltage offset (Δ) between the threshold voltages of transistors 610 and 611. Therefore, in addition to the signal difference, threshold voltage compensation can also be provided (e.g., for transistors 610 and 611, and 612 and 613).

[0072] The next operation between times T3 and T4 is the fourth stage, the sense amplifier activation stage. After time T3, the control signal ISO becomes active to activate transistors 651 and 652, which couple the conductive paths between nodes 614 and 615 and transistors 612 and 613, respectively. After time T3, the voltage supplied to power node ACT also changes from approximately half the voltage VARY back to a high voltage level VARY to “activate” sense amplifier 600. The voltage supplied to power node RNL remains at ground level. The corresponding voltages under power nodes ACT and RNL amplify the voltage difference between digital lines DL and DLb by driving the sense node and digital lines to opposite voltage levels (e.g., high and low activation voltages) based on the voltage difference.

[0073] In this example, when the voltage of the digital line DL is increased in the memory cell, transistor 613 is more activated than transistor 612. Therefore, the digital line DLb is initially pulled down to a low activation voltage supplied to the power node (e.g., GND), which in turn activates transistor 610 to pull up the sensing node 614 and further activates transistor 613. Through the positive feedback loop of transistors 613 and 610, the digital line DLb (and sensing node 615) are driven to a low activation voltage, and the digital line DL (and sensing node 614) are driven to a high activation voltage. Before time T4, the access line WL becomes inactive (e.g., becomes inactive (low) voltage level) to isolate the memory cell from the digital line DL.

[0074] During the sense amplifier activation phase, the sense amplifier is activated by providing high and low activation voltages, and the voltage difference between digital lines DL and DLb is amplified by driving digital lines DL and DLb to opposite activation voltages based on the voltage difference (e.g., generated by a memory cell coupled to a digital line).

[0075] After the sense amplifier activation phase is completed, operation returns from T4 to the pre-charge phase. After time T4, the sense amplifier can be prepared for another sensing operation by pre-charging digital lines DL and DLb, as previously described. For example, control signal BLEQ becomes active again and activates transistor 619. Control signal BLECP becomes active again, while control signal ISO remains active, thereby activating transistors 616, 617, 651, and 652 together to couple the conductive path between nodes 614 and 615. The voltage supplied to power nodes ACT and RNL becomes approximately half the voltage VARY (e.g., 0.5V). Therefore, digital lines DL and DLb are equalized by active transistors 616, 617, 651, and 652 and set to the pre-charge voltage VBLP by active transistor 619. The sense amplifier 600 is in the same pre-charge state as at time T0 previously described and is ready for another access operation.

[0076] exist Figure 7A In some examples, the power supply voltage ACT and control signals BLEQ, ISO, and BLECP are shown at specific timings relative to other voltages and control signals. However, embodiments of this disclosure include those different from the references. Figure 6 Other voltage and signal timings are described. Therefore, the scope of this disclosure is not limited to... Figure 6 This is a specific example. Because the power node RNL remains at ground level from the voltage compensation phase, amplification can be performed without waiting for a voltage change at the power node RNL, as is known. The size of the RNL driver does not affect the activation speed of the sense amplifier 600. Therefore, the minimum number of clock cycles required to enable a row of memory and access its columns can be relaxed (e.g., RAS to CAS delay, tRCD).

[0077] For reference Figure 6 The power supply voltage provided to the power node ACT, as described, can be provided by a voltage circuit. This voltage circuit can be, for example, from a command decoder (e.g., in some embodiments of this disclosure, for...). Figure 1 The internal signal control of the command decoder 125).

[0078] Based on the foregoing, it should be understood that although specific embodiments of this disclosure have been described herein for illustrative purposes, various modifications may be made without departing from the spirit and scope of this disclosure. Therefore, the scope of this disclosure should not be limited to any of the specific embodiments described herein.

Claims

1. A semiconductor device comprising: The first transistor includes a first source coupled to a first power node, a first drain coupled to the first node, and a first gate coupled to a second node; The second transistor includes a second source coupled to the first power node, a second drain coupled to the second node, and a second gate coupled to the first node; The third transistor includes a third source coupled to the second power node, a third gate coupled to the second node, and a third drain. A fourth transistor includes a fourth source coupled to the second power node, a fourth gate coupled to the first node, and a fourth drain. A fifth transistor includes a fifth source coupled to the third drain, a fifth drain coupled to the first node, and a fifth gate configured to receive a first control signal; A sixth transistor includes a sixth source coupled to the fourth drain, a sixth drain coupled to the second node, and a sixth gate configured to receive the first control signal. A seventh transistor includes a seventh source coupled to the second node, a seventh drain coupled to the third drain, and a seventh gate configured to receive a second control signal; An eighth transistor includes an eighth source coupled to the first node, an eighth drain coupled to the fourth drain, and an eighth gate configured to receive the second control signal. as well as A ninth transistor includes a ninth source configured to receive a voltage, a ninth drain coupled to at least one of the first or second nodes, and a ninth gate configured to receive a third control signal.

2. The semiconductor device of claim 1, wherein the threshold voltages of the third and fourth transistors differ by a first offset, and The first node and the second node are configured to have a voltage level difference before the cell information is sampled to compensate for the first offset.

3. The semiconductor device according to claim 1, wherein the second power node is a ground node at a ground voltage level.

4. The semiconductor device of claim 1, further comprising a tenth transistor, the tenth transistor including a tenth source coupled to the second node, a tenth drain coupled to the first node, and a tenth gate configured to receive the third control signal.

5. The semiconductor device of claim 1, wherein the second power node is coupled to a driver.

6. The semiconductor device of claim 1, wherein the first node is further coupled to a first digital line, and the second node is further coupled to a second digital line.

7. The semiconductor device of claim 1, wherein the high voltage level of the first power node is lower than the high voltage levels of the first, second, and third control signals.

8. The semiconductor device according to claim 1, wherein the high voltage level of the first control signal is the same as the high voltage level of the second and third control signals.

9. The semiconductor device of claim 1, wherein the low voltage level of the first control signal is lower than the ground voltage level.

10. The semiconductor device of claim 1, wherein the first and second transistors comprise p-type field-effect transistors, and wherein the third and fourth transistors comprise n-type field-effect transistors.

11. The semiconductor device of claim 10, wherein the fifth, sixth, seventh, eighth and ninth transistors comprise n-type field-effect transistors.

12. A semiconductor device comprising: The first, second and third transistors are coupled in series between the first power node and the second power node; The fourth, fifth, and sixth transistors are coupled in series between the first power node and the second power node; A seventh transistor is coupled to a second node between the second and third transistors and the fourth and fifth transistors; as well as An eighth transistor is coupled to the third and fourth transistors and to a first node between the first and second transistors; as well as A ninth transistor, which is coupled to at least one of the first and second nodes, The gates of the first and third transistors are coupled to the second node, and the gates of the fourth and sixth transistors are coupled to the first node.

13. The semiconductor device of claim 12, wherein the ninth transistor is configured to be activated during the pre-charge phase. The seventh and eighth transistors are configured to be activated during the threshold voltage compensation phase, and the second, fifth, and ninth transistors are deactivated during the threshold voltage compensation phase. The second, fifth, seventh, and eighth transistors are configured to be activated during the activation phase.

14. The semiconductor device of claim 13, wherein the seventh and eighth transistors are configured to be deactivated during a cell sampling phase between the threshold voltage compensation phase and the activation phase.

15. The semiconductor device of claim 12, further comprising a tenth transistor, The ninth and tenth transistors are configured to be activated during the precharge phase, and the seventh and eighth transistors are configured to be deactivated during the precharge phase.

16. The semiconductor device of claim 12, wherein the second power node includes a ground node at a ground voltage level.

17. A method for operating a semiconductor device according to claim 1, comprising: The first node and the second node of the semiconductor device are precharged to a precharge voltage, wherein the first transistor and the second transistor are respectively coupled to the first node and the second node; Deactivate the fifth transistor coupled to the first node and the third transistor, and deactivate the sixth transistor coupled to the second node and the fourth transistor, so as to isolate the first node and the second node from the third transistor and the fourth transistor coupled to the ground node at the ground voltage level, respectively. as well as The drain and gate of the third transistor are coupled to the first node and the second node, respectively, and the drain and gate of the fourth transistor are coupled to the second node and the first node, respectively.

18. The method of claim 17, wherein a voltage difference is provided between the corresponding voltages of the second node and the first node to compensate for the difference between the corresponding threshold voltages of the fourth transistor and the third transistor.

19. The method of claim 17, further comprising activating transistors coupled to the first node and the second node to equalize the first node and the second node.

20. The method of claim 17, wherein the fifth transistor and the sixth transistor are deactivated in response to a first control signal. In response to a second control signal, the drain and gate of the third transistor are coupled to the first node and the second node, respectively, and the drain and gate of the fourth transistor are coupled to the second node and the first node, respectively. The high voltage level of the first control signal is the same as the high voltage level of the second control signal.

21. The method of claim 20, wherein the low voltage level of the first control signal is lower than the ground voltage level.

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