Display substrate, display panel and display device

Abstract

Embodiments of the present invention disclose a display substrate, a display panel, and a display device. By arranging the anode in the third sub-pixel so as not to overlap with the orthographic projection of the grid-shaped power line on the base substrate, particles (foreign matter, dust, and other particles) on the grid-shaped power line will not pierce the flat layer between the first source / drain metal layer and the anode and directly contact the anode (short-circuiting the power line and the anode), thereby avoiding the problem of poor bright spots when the screen is illuminated at the back end.

Description

Technical Field

[0001] The present invention relates to the field of vehicle-mounted display technology, and in particular to a display substrate, a display panel, and a display device. Background Art

[0002] At present, display technology is widely used in the automotive field, and automotive displays have high requirements on the product yield of display screens. Summary of the Invention

[0003] Embodiments of the present invention provide a display substrate, a display panel, and a display device for solving the problem of bad bright spots when the screen of an in-vehicle display product is turned on, thereby improving the product yield.

[0004] An embodiment of the present invention provides a display substrate, comprising: a base substrate, a first source-drain metal layer located on one side of the base substrate, and a plurality of sub-pixels located on a side of the first source-drain metal layer facing away from the base substrate;

[0005] The plurality of sub-pixels are divided into a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the plurality of sub-pixels are divided into a plurality of sub-pixel columns; the plurality of sub-pixel columns include: a first sub-pixel column composed of the first sub-pixels and the second sub-pixels arranged alternately, and a second sub-pixel column composed of the third sub-pixel; the first sub-pixel column and the second sub-pixel column are arranged alternately;

[0006] The first source-drain metal layer includes a grid-shaped power line, each of the sub-pixels includes an anode, and the anode in the third sub-pixel does not overlap with the orthographic projection of the power line on the base substrate.

[0007] Optionally, the display substrate provided in the embodiment of the present invention further includes: a second source-drain metal layer located between the base substrate and the first source-drain metal layer, and a first planarization layer located between the first source-drain metal layer and the second source-drain metal layer;

[0008] The grid-shaped power line includes a first grid arranged around the third sub-pixel, wherein the first grid is formed by sequentially connecting first grid lines arranged in a row direction and second grid lines arranged in a column direction;

[0009] The grid-shaped power line also includes a connecting portion that is arranged to cross and electrically connected to the second grid line. The connecting portion is located between adjacent third sub-pixels, and the connecting portion and the second grid line are an integral structure. The end of the connecting portion close to the third sub-pixel is electrically connected to the second source and drain metal layer through a via hole penetrating the first flat layer.

[0010] Optionally, in the display substrate provided by an embodiment of the present invention, the width of the connecting portion along the row direction is 2.7 μm to 3.3 μm, and the width of the second grid line along the column direction is 1.8 μm to 2.4 μm.

[0011] Optionally, in the display substrate provided by an embodiment of the present invention, the grid-shaped power lines further include a second grid arranged around the first sub-pixel and the second sub-pixel, and the second grid is formed by sequentially connecting third grid lines arranged along the row direction and fourth grid lines arranged along the column direction;

[0012] The orthographic projection of the third grid line on the substrate overlaps with the orthographic projections of the first sub-pixel and the second sub-pixel on the substrate, and the fourth grid line is located between adjacent first sub-pixels and second sub-pixels.

[0013] Optionally, in the above-mentioned display substrate provided by an embodiment of the present invention, the fourth grid line is electrically connected to the center position of the first grid line, the second grid line is electrically connected to the center position of the third grid line, and the first grid line and the third grid line are an integral structure extending along the column direction and have a common part.

[0014] Optionally, in the above display substrate provided by an embodiment of the present invention, the width of the third grid lines along the row direction is 2.2 μm to 2.8 μm, and the width of the fourth grid lines along the column direction is 1.8 μm to 2.4 μm.

[0015] Optionally, in the display substrate provided by an embodiment of the present invention, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

[0016] Optionally, the display substrate provided in the embodiment of the present invention further includes a second planarization layer located between the first source / drain metal layer and the anode.

[0017] Correspondingly, an embodiment of the present invention further provides a display panel including the above-mentioned display substrate.

[0018] Correspondingly, an embodiment of the present invention further provides a display device, comprising the above-mentioned display panel.

[0019] The beneficial effects of the embodiments of the present invention are as follows:

[0020] Embodiments of the present invention provide a display substrate, a display panel, and a display device. By arranging the anode in the third sub-pixel so as not to overlap with the orthographic projection of the grid-shaped power line on the base substrate, particles (foreign matter, dust, and other particles) on the grid-shaped power line will not penetrate the flat layer between the first source / drain metal layer and the anode and directly contact the anode (short-circuiting the power line and the anode), thereby avoiding the problem of poor bright spots when lighting the screen at the back end. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of a top view structure of a display substrate provided in the related art;

[0022] Figure 2 for Figure 1 Schematic diagram of the cross section along the AA' direction;

[0023] Figure 3 A schematic top view of the structure of a display substrate provided in an embodiment of the present invention;

[0024] Figure 4 for Figure 3 A schematic cross-sectional view along the CC' direction;

[0025] Figure 5 for Figure 3 Another cross-sectional schematic diagram along CC' direction;

[0026] Figure 6 Schematic diagram of the structure of the pixel circuit;

[0027] Figure 7 Schematic diagram of the cross-sectional structure of a sub-pixel. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the present invention more clear, the following detailed description of the specific embodiments of the display substrate, display panel and display device provided by the embodiments of the present invention is provided with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only used to illustrate and explain the present invention and are not intended to limit the present invention. In addition, the embodiments and features in the embodiments of this application can be combined with each other if there is no conflict.

[0029] The thickness, size and shape of each film layer in the drawings do not reflect the actual proportion of the display substrate, and are only intended to illustrate the content of the present invention.

[0030] Organic Light-Emitting Diode (OLED) display technology has the advantages of self-luminescence, wide viewing angle, almost infinite contrast, low power consumption, and extremely high response speed. It is known as a new generation of display technology. Full-screen OLED products have become the mainstream of development. The power line (VDD) of OLED products generally uses a double-layer SD trace, and the SD trace closest to the anode (hereinafter referred to as the first trace) and the anode generally overlap with each other. For display products that pursue high PPI (pixel resolution), such as mobile phones, the Anode (anode) size of OLED full-screen products is smaller and the first trace is narrower, and the area of ​​the first trace covered by the anode is also small. As for automotive OLED full-screen products, since the requirements for pixel resolution of automotive displays are not so high, the anode size is larger and the first trace is wider, such as Figure 1 and Figure 2 As shown, Figure 1 This is a top view of some film layers in an in-vehicle display product. Figure 2 for Figure 1 The cross-section diagram along the AA' direction is the same. The vehicle-mounted display product includes a first source-drain metal layer 2, a first flat layer 3, a second source-drain layer (the film layer where the first wiring 4 mentioned above is located), a second flat layer 5 and an anode layer 6 stacked in sequence on a base substrate 1. The anode layer 6 includes multiple anodes (represented by R, G, and B) corresponding to sub-pixels of different colors. Since the vehicle-mounted display does not have such high requirements for pixel resolution, the R, G, and B are generally arranged with R and G in the same column and B in a separate column, and R and G are arranged closely and B is arranged sparsely. The first wiring 4 is in a grid shape. In the pattern design, the area of ​​the first wiring 4 covered by the anode (R, G, and B) is also correspondingly larger. Because first trace 4 is relatively wide, particles (such as foreign matter and dust) on first trace 4 can penetrate the second flat layer 5 between first trace 4 and the anode (R, G, B) and come into direct contact with the anode (R, G, or B). This short-circuit between first trace 4 and the anode (R, G, B) results in a defective bright spot when the screen is turned on at the rear end. The inventors of this case have found that 5% of automotive full-screen OLED products have defective bright spots, of which 30% can be traced back to particles on first trace 4. Therefore, particles on the first trace of automotive full-screen OLED products have a greater impact on the anode layer, reducing product yield.

[0031] In view of this, an embodiment of the present invention provides a display substrate, such as Figure 3 and Figure 4 As shown, Figure 3 This is a schematic diagram showing a top view of some film layers in the substrate. Figure 4 for Figure 3The cross-section diagram along the CC' direction is the same, including: a base substrate 10, a first source and drain metal layer 20 located on one side of the base substrate 10, and a plurality of sub-pixels (for example, R, G, B) located on a side of the first source and drain metal layer 20 away from the base substrate 10;

[0032] The plurality of sub-pixels are divided into a first sub-pixel (e.g., a red sub-pixel R), a second sub-pixel (e.g., a green sub-pixel G), and a third sub-pixel (e.g., a blue sub-pixel B). The plurality of sub-pixels (R, G, B) are divided into a plurality of sub-pixel columns. The plurality of sub-pixel columns include: a first sub-pixel column composed of alternating first sub-pixels R and second sub-pixels G, and a second sub-pixel column composed of third sub-pixels B. The first sub-pixel column and the second sub-pixel column are alternately arranged.

[0033] The first source-drain metal layer 20 includes a grid-shaped power line VDD. Each sub-pixel includes an anode 30 . The anode 30 in the third sub-pixel B does not overlap with the orthographic projection of the power line VDD on the base substrate 10 .

[0034] The above-mentioned display substrate provided by an embodiment of the present invention, by arranging the anode 30 in the third sub-pixel B to not overlap with the orthographic projection of the grid-shaped power line VDD on the base substrate 10, particles (foreign matter, dust and other particles) on the grid-shaped power line VDD will not penetrate the flat layer between the first source-drain metal layer 20 and the anode 30 and directly contact the anode 30 (the power line VDD and the anode 30 are short-circuited), thereby avoiding the problem of poor bright spots when the screen is lit at the back end.

[0035] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present invention, as Figure 3 and 4 As shown, it also includes: a second source-drain metal layer 40 located between the base substrate 10 and the first source-drain metal layer 20, and a first planarization layer 50 located between the first source-drain metal layer 20 and the second source-drain metal layer 40;

[0036] The grid-shaped power line VDD includes a first grid 201 arranged around the third sub-pixel B. The first grid 201 is formed by sequentially connecting first grid lines 2011 arranged along the row direction X and second grid lines 2012 arranged along the column direction Y.

[0037] The grid-shaped power line VDD further includes a connecting portion 2013 that is arranged to intersect and electrically connect with the second grid line 2012. The connecting portion 2013 is located between adjacent third sub-pixels B, and the connecting portion 2013 and the second grid line 2012 are an integral structure. The end of the connecting portion 2013 near the third sub-pixel B is electrically connected to the second source-drain metal layer 40 through a via hole penetrating the first flat layer 50. The display substrate further includes a second flat layer 60 located between the first source-drain metal layer 20 and the anode 30. Specifically, when manufacturing the grid-shaped power line VDD in the embodiment of the present invention, the first step is to manufacture the second source-drain metal layer 40. Figure 1 In the shape of VDD, by Figure 1 The portion where the power line VDD overlaps with the B pixel is etched away, so that the anode 30 does not overlap with the grid-shaped power line VDD, and the particles on the power line VDD will not pierce the second flat layer 60, that is, the power line VDD and the anode 30 will not be short-circuited, thereby preventing the problem of poor bright spots. In addition, the end of the connecting portion 2013 close to the third sub-pixel B is electrically connected to the second source-drain metal layer 40 through a via penetrating the first flat layer 50, which can prevent the problem of poor display caused by tip discharge.

[0038] It should be noted that if Figure 3 As shown, the first planar layer 50 is a film layer between the first source-drain metal layer 20 and the second source-drain metal layer 40. Figure 3 The first planar layer 50 is illustrated as a substantially circular pattern, which is actually a via hole on the first planar layer 50 .

[0039] In specific implementation, Figure 1 As shown, the width d1 of the wiring arranged along the row direction X is generally about 2.7 μm to 3.3 μm, and the width d2 of the wiring arranged along the column direction Y is generally about 1.3 μm to 1.9 μm. Figure 3 Since a part of the power line VDD is removed, the resistance value of the power line VDD becomes larger accordingly. In order to keep the resistance value of the design of the present invention consistent with that of the original design, in the above-mentioned display substrate provided by the embodiment of the present invention, Figure 3 and 4 As shown, the width w1 of the connecting portion 2013 along the row direction X can be 2.7 μm to 3.3 μm (maintaining the original design width), and the width w2 of the second grid line 2012 along the column direction Y can be 1.8 μm to 2.4 μm, that is, the width w2 of the second grid line 2012 along the column direction Y is greater than that of the original design. Figure 1 Increase, thereby increasing the resistance value accordingly to be consistent with the original design resistance value.

[0040] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present invention, as Figure 3As shown, the grid-shaped power line VDD further includes a second grid 202 arranged around the first sub-pixel R and the second sub-pixel G. The second grid 202 is composed of third grid lines 2021 arranged along the row direction X and fourth grid lines 2022 arranged along the column direction Y connected in sequence.

[0041] The orthographic projection of the third grid line 2021 on the base substrate 10 overlaps with the orthographic projections of the first sub-pixel R and the second sub-pixel G on the base substrate 10 , and the fourth grid line 2022 is located between adjacent first sub-pixels R and second sub-pixels G.

[0042] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present invention, as Figure 3 As shown, the fourth grid line 2022 is electrically connected to the center position of the first grid line 2011, and the second grid line 2012 is electrically connected to the center position of the third grid line 2021. The first grid line 2011 and the third grid line 2021 are an integral structure extending along the column direction Y and have a common part (the oval dotted box part).

[0043] In specific implementation, Figure 1 As shown, since the sub-pixels R and G overlap with the first traces 4 arranged along the row direction X, and the width d1 of the first traces 4 is about 2.7 μm to 3.3 μm, the particles on the power line VDD will penetrate the flat layer between the anode and the first traces 4 and short-circuit with the anode. Therefore, in the above-mentioned display substrate provided by the embodiment of the present invention, Figure 3 As shown, the width w3 of the third grid line 2021 along the row direction X can be 2.2 μm to 2.8 μm, that is, the width w3 of the third grid line 2021 along the row direction X is larger than that of the original design. Figure 1 The third grid line 2021 is reduced, thereby reducing the overlapping area of ​​the anode of the first sub-pixel R and the second sub-pixel G, and relatively reducing the probability of particles in the first sub-pixel R and the second sub-pixel G piercing the second flat layer 60, thereby further avoiding the problem of bad bright spots; since the width w3 of the third grid line 2021 along the row direction X is smaller than that of the original design Figure 1 The resistance of the power line VDD increases accordingly. In order to keep the resistance value of the design of the present invention consistent with that of the original design, the width w4 of the fourth grid line 2022 along the column direction Y can be 1.8 μm to 2.4 μm, that is, the width w4 of the fourth grid line 2022 along the column direction Y is larger than that of the original design. Figure 1 The resistance value is reduced accordingly to match the original design resistance value.

[0044] It should be noted that if Figure 3 As shown, the power line VDD overlapping the first sub-pixel R and the second sub-pixel G is as close to the edges of R and G as possible, which can reduce the risk of poor display.

[0045] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present invention, as Figure 5 As shown, it also includes: an active layer 70 located between the base substrate 10 and the second source-drain metal layer 40, an insulating layer 80 located between the second source-drain metal layer 40 and the active layer 70, and the second source-drain metal layer 40 is electrically connected to the active layer 70 through a via hole penetrating the insulating layer 80.

[0046] In a specific implementation, each sub-pixel includes a light-emitting device and a pixel circuit for driving the light-emitting device to emit light, such as Figure 6 and Figure 7 As shown, Figure 6 Schematic diagram of a pixel circuit and a light-emitting device L in each sub-pixel. The pixel circuit uses a 7T1C structure as an example, but other structures are also possible. Figure 7 is a schematic diagram of a cross-sectional view of a sub-pixel film layer; specifically, Figure 6 As shown, the pixel circuit includes: a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, an anode reset transistor T7, and a storage capacitor Cst; wherein, the first electrode S5 of the first light-emitting control transistor T5 is located in the second source-drain metal layer 40 in the embodiment of the present invention, and the first electrode S5 of the first light-emitting control transistor T5 is electrically connected to the power line VDD.

[0047] Specifically, Figure 6The timing sequence for the pixel circuit shown driving the light-emitting device to emit light is as follows: During the reset phase, the reset transistor T4 and the anode reset transistor T7 are turned on, while the data write transistor T2, the first light-emission control transistor T5, and the second light-emission control transistor T6 are turned off. The signal from the initialization signal terminal RL initializes the gate of the drive transistor T1 and the anode of the light-emitting device L. This initialization of the gate of the drive transistor T1 causes the drive transistor T1 to turn on. During the data write compensation phase, the data write transistor T2 and the threshold compensation transistor T3 are turned on, while the reset transistor T4, the first light-emission control transistor T5, the second light-emission control transistor T6, and the anode reset transistor T7 are turned off. The data voltage Vdata is applied to the gate of the drive transistor T1 via the data write transistor T2, the drive transistor T1, and the threshold compensation transistor T3. At this time, the voltage applied to the gate of the drive transistor T1 is the compensation voltage Vdata + Vth (threshold voltage), and the compensation voltage applied to the gate of the drive transistor T1 is also applied to the first electrode CE1 of the storage capacitor Cst. In the light-emitting stage, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the data writing transistor T2, the threshold compensation transistor T3, the reset transistor T4, and the anode reset transistor T7 are turned off, so that the first light-emitting control transistor T5 applies the driving voltage VDD to the driving transistor T1, so that the light-emitting devices of each sub-pixel emit light.

[0048] like Figure 7 As shown, each sub-pixel includes a buffer layer 90, an active layer 70, a first gate insulating layer 100, a first gate layer 110, a second gate insulating layer 120, a second gate layer 130, an interlayer insulating layer 140, a second source-drain metal layer 40, a passivation layer 150, a first flat layer 50, a first source-drain metal layer 20, a second flat layer 60, an anode 30, a pixel defining layer 160, a light-emitting layer 1 / 70, a cathode 180, an inorganic encapsulation layer 190, an organic encapsulation layer 200, and an inorganic encapsulation layer 210, which are sequentially stacked on a base substrate 10; wherein, Figure 4 and Figure 5 Only part of the membrane structure is shown. Figure 6 The first gate insulating layer 100, the second gate insulating layer 120 and the interlayer insulating layer 140 constitute Figure 5 Insulating layer 80.

[0049] It should be noted that, in the embodiment of the present invention, both the second source-drain metal layer 40 and the first source-drain metal layer 20 are provided with a power line VDD, that is, a double-layer VDD routing is adopted to reduce the resistance of the power line, the power line VDD of the first source-drain metal layer 20 is a grid structure, and the power line VDD of the second source-drain metal layer 40 can be designed as one for each column. The power line VDD of the first source-drain metal layer 20 is projected in each sub-pixel and at least partially overlaps with the power line VDD of the second source-drain metal layer 40, so as to realize electrical connection between the power line VDD of the first source-drain metal layer 20 and the power line VDD of the second source-drain metal layer 40.

[0050] Specifically, such as Figure 7 As shown, the second source-drain metal layer 40 and the first source-drain metal layer 20 are electrically connected through a first via V1 penetrating the first flat layer 50 and the passivation layer 150, and the anode 30 is electrically connected through a second via V2 penetrating the second flat layer 60, and the orthographic projections of the first via V1 and the second via V2 on the substrate do not overlap.

[0051] In summary, the display substrate provided by the embodiment of the present invention reduces the overlapping area between the anode of the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B and the power line VDD by changing the pattern and width design of the power line VDD of the first source-drain metal layer 20. This correspondingly reduces the probability of particles in the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B regions piercing the second flat layer 60 and shorting to the anode, thereby reducing bright spot defects related to particles in the first source-drain metal layer 20 and improving the yield of automotive full-screen OLED products by 1.5%.

[0052] In specific implementation, the display substrate provided by the embodiment of the present invention further includes other functional film layers well known to those skilled in the art, such as a touch layer and a cover plate located on the side of the inorganic encapsulation layer facing away from the base substrate.

[0053] Based on the same inventive concept, an embodiment of the present invention further provides a display panel, comprising the display substrate provided in the embodiment of the present invention. The implementation of the display panel can refer to the embodiment of the display substrate, and the repeated parts will not be repeated.

[0054] Based on the same inventive concept, embodiments of the present invention further provide a display device comprising the display panel described above. The display device may be, without limitation, a vehicle display screen, a laptop computer, a television, a tablet computer, a mobile phone, or a medical display device. The implementation of the display device can be referenced to the display panel embodiments described above, and any repetitions will not be repeated.

[0055] Embodiments of the present invention provide a display substrate, a display panel, and a display device. By arranging the anode in the third sub-pixel so as not to overlap with the orthographic projection of the grid-shaped power line on the base substrate, particles (foreign matter, dust, and other particles) on the grid-shaped power line will not penetrate the flat layer between the first source / drain metal layer and the anode and directly contact the anode (short-circuiting the power line and the anode), thereby avoiding the problem of poor bright spots when lighting the screen at the back end.

[0056] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A display substrate, characterized in that: include: A base substrate, a first source-drain metal layer located on one side of the base substrate, and a plurality of sub-pixels located on a side of the first source-drain metal layer facing away from the base substrate; The plurality of sub-pixels are divided into a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the plurality of sub-pixels are divided into a plurality of sub-pixel columns; the plurality of sub-pixel columns include: a first sub-pixel column composed of the first sub-pixels and the second sub-pixels arranged alternately, and a second sub-pixel column composed of the third sub-pixel; the first sub-pixel column and the second sub-pixel column are arranged alternately; The first source-drain metal layer includes a grid-shaped power line, each of the sub-pixels includes an anode, and the anode in the third sub-pixel does not overlap with the orthographic projection of the power line on the base substrate.

2. The display substrate according to claim 1, wherein: Also includes: a second source-drain metal layer located between the base substrate and the first source-drain metal layer, and a first planarization layer located between the first source-drain metal layer and the second source-drain metal layer; The grid-shaped power line includes a first grid arranged around the third sub-pixel, wherein the first grid is formed by sequentially connecting first grid lines arranged in a row direction and second grid lines arranged in a column direction; The grid-shaped power line also includes a connecting portion that is arranged to cross and electrically connected to the second grid line. The connecting portion is located between adjacent third sub-pixels, and the connecting portion and the second grid line are an integral structure. The end of the connecting portion close to the third sub-pixel is electrically connected to the second source and drain metal layer through a via hole penetrating the first flat layer.

3. The display substrate according to claim 2, wherein: The width of the connecting portion along the row direction is 2.7 μm to 3.3 μm, and the width of the second grid line along the column direction is 1.8 μm to 2.4 μm.

4. The display substrate according to claim 2, wherein: The grid-shaped power line further includes a second grid arranged around the first sub-pixel and the second sub-pixel, wherein the second grid is formed by sequentially connecting third grid lines arranged along the row direction and fourth grid lines arranged along the column direction; The orthographic projection of the third grid line on the substrate overlaps with the orthographic projections of the first sub-pixel and the second sub-pixel on the substrate, and the fourth grid line is located between adjacent first sub-pixels and second sub-pixels.

5. The display substrate according to claim 4, wherein: The fourth grid line is electrically connected to the center of the first grid line, the second grid line is electrically connected to the center of the third grid line, and the first grid line and the third grid line are an integral structure extending along the column direction and have a common portion.

6. The display substrate according to claim 5, wherein: The width of the third grid line along the row direction is 2.2 μm to 2.8 μm, and the width of the fourth grid line along the column direction is 1.8 μm to 2.4 μm.

7. The display substrate according to any one of claims 1 to 6, characterized in that: The first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

8. The display substrate according to any one of claims 1 to 6, characterized in that: The invention also includes a second planar layer located between the first source / drain metal layer and the anode.

9. A display panel, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 8.

10. A display device, characterized in that: The display panel according to claim 9 is included.

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