Ceramic chip based low pass filter

Abstract

The present invention discloses a low-pass filter based on a ceramic patch, comprising a main structure, a pad structure group, a capacitor structure group, and an inductor structure group; the pad structure group is arranged on the main structure; the capacitor structure and the inductor structure are arranged inside the main structure; the pad structure group is electrically connected to the capacitor structure group and the inductor structure group, respectively; the capacitor structure group and the inductor structure group include a resonance control structure to enable the standing wave ratio of the low-pass filter to be within a preset range. The low-pass filter based on the ceramic patch of the present invention adopts a low-power miniaturized device filtering design scheme to achieve a significant improvement in filtering effect while reducing the circuit patch area and the number of capacitor and inductor components. Application to integrated circuits and devices can ensure performance and save space, and has good application value.

Description

Technical Field

[0001] The present invention relates to the technical field of low-pass filters, and in particular to a low-pass filter based on ceramic patches. Background Art

[0002] Low-temperature co-fired ceramic (LTCC) is a high-density packaging technology that offers excellent electronic, mechanical, and thermal properties for integrated and modular electronic component applications. In addition to the advantages of integrated packaging, it also offers numerous advantages in terms of wiring line width and spacing, low-impedance metallization, design diversity, and high-frequency performance. It is well-suited for modular multi-layer chip circuit design, and is particularly well-suited for use in electronic devices such as filters, antennas, and couplers, particularly with the current trend toward miniaturization and higher frequencies. However, low-pass filters often struggle to achieve satisfactory filtering performance due to their limited space or relatively small number of components. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to overcome the defect of poor filtering effect of the low-pass filter in the prior art due to the limitation of space and number of components, and to provide a low-pass filter based on ceramic patches.

[0004] The present invention solves the above technical problems through the following technical solutions:

[0005] The present invention provides a low-pass filter based on ceramic patch.

[0006] The low-pass filter includes a main body structure, a pad structure group, a capacitor structure group, and an inductor structure group;

[0007] The pad structure group is arranged on the main structure;

[0008] The capacitor structure and the inductor structure are arranged inside the main body structure;

[0009] The pad structure group is electrically connected to the capacitor structure group and the inductor structure group respectively;

[0010] The capacitor structure group and the inductor structure group include a resonance control structure so that the standing wave ratio of the low-pass filter is within a preset range.

[0011] Preferably, the pad structure group includes a first pad, a second pad, a third pad, and a fourth pad;

[0012] The inductor structure group includes a first inductor structure, a second inductor structure, a third inductor structure, and a fourth inductor structure;

[0013] The capacitor structure group includes a first capacitor structure and a second capacitor structure;

[0014] The resonance control structure includes a first resonance control structure and a second resonance control structure;

[0015] The first inductor structure is electrically connected to the first pad;

[0016] The second inductor structure is electrically connected to the fourth pad;

[0017] The third inductor structure is electrically connected to the second pad;

[0018] The fourth inductor structure is electrically connected to the first inductor structure and the second inductor structure respectively;

[0019] The first capacitor structure is electrically connected to the first pad and the third pad respectively;

[0020] The first capacitor structure is coupled to the fourth inductor to form the first resonance control structure;

[0021] The second capacitor structure is electrically connected to the fourth pad;

[0022] The second capacitance structure and the third inductor are coupled to form the second resonance control structure.

[0023] Preferably, the first pad, the second pad, the third pad, and the fourth pad are all L-shaped structures including a vertical surface and a horizontal surface;

[0024] The vertical surface of the first pad is embedded in the first side surface of the main structure;

[0025] The horizontal plane of the first pad is embedded in the bottom surface of the main structure;

[0026] The vertical surface of the second pad is embedded in the first side surface of the main structure;

[0027] The transverse plane of the second pad is embedded in the bottom surface of the main structure;

[0028] The vertical surface of the third pad is embedded in the second side surface of the main structure;

[0029] The transverse plane of the third pad is embedded in the bottom surface of the main structure;

[0030] The vertical surface of the fourth pad is embedded in the second side surface of the main structure;

[0031] The transverse plane of the fourth pad is embedded in the bottom surface of the main structure;

[0032] Wherein, the first side surface and the second side surface of the main structure are opposite surfaces.

[0033] Preferably, the first inductor structure includes a first inductor layer, a second inductor layer, a third inductor layer, a fourth inductor layer, and a fifth inductor layer, which are arranged parallel to the bottom surface of the main structure from near to far and are electrically connected in sequence;

[0034] The second inductor structure includes a sixth inductor layer, a seventh inductor layer, an eighth inductor layer, a ninth inductor layer, and a tenth inductor layer, which are arranged parallel to the bottom surface of the main structure from near to far and are electrically connected in sequence;

[0035] The third inductor structure includes an eleventh inductor layer, a twelfth inductor layer, a thirteenth inductor layer, a fourteenth inductor layer, a fifteenth inductor layer, and a sixteenth inductor layer, which are arranged parallel to the bottom surface of the main structure from near to far and are electrically connected in sequence;

[0036] The fourth inductor structure includes a seventeenth inductor layer, an eighteenth inductor layer, and a nineteenth inductor layer, which are arranged parallel to the bottom surface of the main structure from near to far and are electrically connected in sequence;

[0037] The first capacitor structure includes a first capacitor plate layer, a second capacitor plate layer, and a third capacitor plate layer arranged parallel to the bottom surface of the main structure from near to far;

[0038] The second capacitor structure includes a fourth capacitor plate layer and a fifth capacitor plate layer arranged parallel to the bottom surface of the main structure from near to far;

[0039] The first inductor layer is electrically connected to the vertical surface of the first pad; the sixth inductor layer is electrically connected to the vertical surface of the fourth pad;

[0040] The eleventh inductor layer is electrically connected to the vertical surface of the second pad;

[0041] The seventeenth inductor layer is electrically connected to the first inductor structure and the second inductor structure respectively;

[0042] The first capacitor plate layer, the third capacitor plate layer and the vertical surface of the third pad are electrically connected;

[0043] The second capacitor plate layer is electrically connected to the vertical surface of the first pad;

[0044] The fourth capacitor plate layer, the fifth capacitor plate layer, and the vertical surface of the fourth pad are electrically connected.

[0045] Preferably, the first inductor layer and the sixth inductor layer are arranged on the same plane;

[0046] The second inductor layer, the seventh inductor layer, and the eleventh inductor layer are arranged on the same plane;

[0047] The third inductor layer, the eighth inductor layer, and the twelfth inductor layer are arranged on the same plane;

[0048] The fourth inductor layer, the ninth inductor layer, and the thirteenth inductor layer are arranged on the same plane;

[0049] The fifth inductor layer, the tenth inductor layer, and the fourteenth inductor layer are arranged on the same plane;

[0050] The sixteenth inductor layer and the eighteenth inductor layer are arranged on the same plane;

[0051] The fourth capacitor plate layer and the first capacitor plate layer are arranged on the same plane;

[0052] The fifth capacitor plate layer and the second capacitor plate layer are arranged on the same plane.

[0053] Preferably, the second capacitor and the third inductor are coupled in the sixteenth inductor layer.

[0054] Preferably, the first inductor layer is electrically connected to the vertical surface of the first pad via a first PIN pin;

[0055] The sixth inductor layer is electrically connected to the vertical surface of the fourth pad via the fourth PIN pin;

[0056] The eleventh inductor layer is electrically connected to the vertical surface of the second pad via the second PIN pin;

[0057] The first capacitor plate layer and the third capacitor plate layer are electrically connected via the third PIN pin and the vertical surface of the third pad;

[0058] The second capacitor plate layer is electrically connected to the vertical surface of the first pad via the first PIN pin;

[0059] The fourth capacitor plate layer and the fifth capacitor plate layer are electrically connected via the fourth PIN pin and the vertical surface of the fourth pad.

[0060] Preferably, the first PIN pin is an input terminal and the fourth PIN pin is an output terminal, or the first PIN pin is an output terminal and the fourth PIN pin is an input terminal;

[0061] The second PIN pin and the third PIN pin are grounded.

[0062] Preferably, the main structure is made of ceramic material with a dielectric constant of 6-8.

[0063] Preferably, the preset range is 0-3 GHz (Gigahertz).

[0064] The positive advances of this invention lie in the fact that the ceramic patch-based low-pass filter utilizes a low-power, miniaturized device filtering design, significantly improving filtering effectiveness while reducing circuit patch area and the number of capacitor and inductor components. Application to integrated circuits and devices ensures performance while saving space, demonstrating its promising application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 This is a schematic diagram of the main structure of a low-pass filter based on a ceramic patch according to a preferred embodiment of the present invention.

[0066] Figure 2 This is a schematic diagram of the basic circuit principle of a low-pass filter based on a ceramic patch according to a preferred embodiment of the present invention.

[0067] Figure 3 FIG. 1 is an overall schematic diagram of a low-pass filter based on a ceramic patch according to a preferred embodiment of the present invention.

[0068] Figure 4 FIG. 1 is an internal schematic diagram of a low-pass filter based on a ceramic patch according to a preferred embodiment of the present invention.

[0069] Figure 5 This is a schematic diagram of the transmission loss of the basic model circuit of a ceramic patch-based low-pass filter in a preferred embodiment of the present invention.

[0070] Figure 6 Schematic diagram of the structural path transmission loss of a low-pass filter based on a ceramic patch according to a preferred embodiment of the present invention.

[0071] Figure 7 Schematic diagram of the input and output standing wave ratio of a low-pass filter based on a ceramic patch according to a preferred embodiment of the present invention.

[0072] Figure 8 A side view of a ceramic patch-based low-pass filter according to a preferred embodiment of the present invention from a first angle.

[0073] Figure 9 A side view from a second angle of a low-pass filter based on a ceramic patch according to a preferred embodiment of the present invention.

[0074] Figure 10 Schematic diagram of the connection relationship between the first inductor structure and the pad structure group of the ceramic patch-based low-pass filter in a preferred embodiment of the present invention.

[0075] Figure 11 Schematic diagram of the connection relationship between the second inductor structure and the pad structure group of the ceramic patch-based low-pass filter in a preferred embodiment of the present invention.

[0076] Figure 12 Schematic diagram of the connection relationship between the third inductor structure and the pad structure group of the ceramic patch-based low-pass filter according to a preferred embodiment of the present invention.

[0077] Figure 13 Schematic diagram of the connection relationship between the inductor structure group and the pad structure group of the ceramic patch-based low-pass filter in a preferred embodiment of the present invention.

[0078] Figure 14 Schematic diagram of the connection relationship between the first capacitor structure and the pad structure group of the ceramic patch-based low-pass filter in a preferred embodiment of the present invention.

[0079] Figure 15 Schematic diagram of the connection relationship between the second capacitor structure and the pad structure group of the ceramic patch-based low-pass filter in a preferred embodiment of the present invention.

[0080] Figure 16 Schematic diagram of the structure of each layer of the first inductor structure of a low-pass filter based on ceramic patch according to a preferred embodiment of the present invention.

[0081] Figure 17 Schematic diagram of the structure of each layer of the second inductor structure of the low-pass filter based on ceramic patch according to a preferred embodiment of the present invention.

[0082] Figure 18 Schematic diagram of the structure of each layer of the third inductor structure of the low-pass filter based on ceramic patch according to a preferred embodiment of the present invention.

[0083] Figure 19 Schematic diagram of the structures of each layer of the fourth inductor structure of the low-pass filter based on ceramic patch according to a preferred embodiment of the present invention.

[0084] Figure 20 Schematic diagram of the structure of each layer of the first capacitor structure of a low-pass filter based on ceramic patches according to a preferred embodiment of the present invention.

[0085] Figure 21 Schematic diagram of the structure of each layer of the second capacitor structure of a low-pass filter based on ceramic patches according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0086] The present invention is further described below by way of examples, but the present invention is not limited to the scope of the examples.

[0087] Example 1

[0088] See also Figure 1As shown, this embodiment specifically provides a low-pass filter based on ceramic patches, which forms a material structure design by converting the preliminary circuit rules to achieve better high-frequency filtering requirements for radio frequency circuit debugging. Figure 2 The figure shows a schematic diagram of the basic circuit principle, and the low-pass filter of this embodiment is designed based on this basic circuit. As an optional implementation, two of the four ports in the circuit are ground terminals, one is an input terminal, and one is an output terminal. That is, port 1 is output and port 2 is input; or port 1 is input and port 2 is output. The device parameters are L1 = 1.4nH (nanohenry, unit of inductance), L2 = 2.5nH, L3 = 2.5nH, L4 = 0.6nH, C1 = 1.3pF (picofarad, unit of capacitance), and C2 = 0.7pf.

[0089] In this embodiment, the ceramic patch-based low-pass filter includes a main structure 1, a pad structure group, a capacitor structure group, and an inductor structure group; wherein the pad structure group includes a plurality of pads, all of which are arranged on the main structure. In order to facilitate the description of the specific structure, the A1 surface of the main structure is defined as the bottom surface, and A2 is defined as the first side surface. It can be understood that the first side surface A2 also has an opposite side surface (not shown in the figure), that is, the second side surface of the main structure.

[0090] The main structure is made of ceramic material, and its dielectric constant can be 6 to 8. Preferably, the dielectric constant can be 7.

[0091] It is understood that the pad can be set in the main structure in an embedded manner (see Figure 1 ), that is, forming an internal space together with the main structure, the inner and outer sides of the pad are respectively kept flush with the inner and outer sides of the main structure of the low-pass filter.

[0092] See also Figure 3-4 , which respectively show the overall structural schematic diagram (including the pad) and the internal structural schematic diagram (excluding the pad) of the ceramic patch-based low-pass filter of this embodiment.

[0093] The capacitor and inductor structures are located inside the main structure, within the aforementioned internal space. The pad structure is electrically connected to the capacitor and inductor structures, respectively. The capacitor and inductor structures form a resonant control structure. Through impedance design, two resonant points are created to control the out-of-band filtering effect, keeping the standing wave ratio of the low-pass filter within a preset range.

[0094] In a circuit including capacitors and inductors, if the capacitors and inductors are connected in series, it is possible that within a very short period of time, the voltage of the capacitor gradually increases while the current gradually decreases; at the same time, the current of the inductor gradually increases, while the voltage of the inductor gradually decreases. And within another very short period of time: the voltage of the capacitor gradually decreases while the current gradually increases; at the same time, the current of the inductor gradually decreases, while the voltage of the inductor gradually increases. The increase in voltage can reach a positive maximum value, and the decrease in voltage can also reach a negative maximum value. Similarly, the direction of the current can also change between positive and negative directions during this process, forming circuit resonance. The resonant structure formed by the capacitor structure group and the inductor structure group of this embodiment can achieve better out-of-band filtering effect, preferably, the preset range is 0-3GHz.

[0095] See also Figure 5 and Figure 6 , respectively showing the Figure 2 The transmission loss of the basic circuit shown in FIG. 1 and the actual transmission loss of the low-pass filter based on the ceramic patch of this embodiment are shown in FIG. 1 , where Figure 7 The input and output standing wave ratios of the ceramic patch-based low-pass filter of this embodiment are shown. It can be seen that due to the design of this embodiment, an ideal standing wave ratio range is achieved.

[0096] As a preferred embodiment, the pad structure group includes a first pad P1, a second pad P2, a third pad P3, and a fourth pad P4;

[0097] The inductor structure group includes a first inductor structure L1, a second inductor structure L2, a third inductor structure L3, and a fourth inductor structure L4; the capacitor structure group includes a first capacitor structure C1 and a second capacitor structure C2; ​​the resonance control structure includes a first resonance control structure and a second resonance control structure; it can be understood that the elements and Figure 2 The components in the figure are designed accordingly. The PIN pins of the four soldering plates correspond to Figure 2 Each port in.

[0098] The first inductor structure L1 is electrically connected to the first pad P1; the second inductor structure L2 is electrically connected to the fourth pad P4; the third inductor structure L3 is electrically connected to the second pad P2; the fourth inductor structure L4 is electrically connected to the first inductor structure L1 and the second inductor structure L2 respectively; the first capacitor structure C1 is electrically connected to the first pad P1 and the third pad P3 respectively. At the top of the low-pass filter, it is connected to the signal terminal through capacitive coupling, pulling out two resonances and adjusting the resonance position to achieve an optimal standing wave ratio. The first capacitor structure C1 is coupled with the fourth inductor structure L4 to form a first resonance control structure; the second capacitor structure C2 is electrically connected to the fourth pad P4; and the second capacitor structure C2 is coupled with the third inductor structure L3 to form a second resonance control structure. Figure 8 and Figure 9 The side views of the above structures are shown respectively.

[0099] As a preferred embodiment, the first solder pad P1, the second solder pad P2, the third solder pad P3, and the fourth solder pad P4 are all L-shaped structures including vertical surfaces and horizontal planes; the vertical surface of the first solder pad P1 is embedded in the first side surface A2 of the main structure; the horizontal plane of the first solder pad P1 is embedded in the bottom surface A1 of the main structure; the vertical surface of the second solder pad P2 is embedded in the first side surface A2 of the main structure; the horizontal plane of the second solder pad P2 is embedded in the bottom surface A1 of the main structure; the vertical surface of the third solder pad P3 is embedded in the second side surface of the main structure; the horizontal plane of the third solder pad P3 is embedded in the bottom surface A1 of the main structure; the vertical surface of the fourth solder pad P4 is embedded in the second side surface of the main structure; the horizontal plane of the fourth solder pad P4 is embedded in the bottom surface A1 of the main structure; wherein, the first side surface A2 and the second side surface of the main structure are opposite surfaces.

[0100] The solder pad in this embodiment is an L-shaped structure, which is embedded in the main structure. Therefore, it can be understood that the two sections of the L-shape are respectively arranged corresponding to the bottom surface A1 and a side surface of the main structure, such as the first side surface A2. At the same time, the L-shaped structure is arranged as an integral whole.

[0101] As a preferred embodiment, the first inductor structure L1 includes a first inductor layer L1-1, a second inductor layer L1-2, a third inductor layer L1-3, a fourth inductor layer L1-4, and a fifth inductor layer L1-5, which are arranged parallel to the bottom surface A1 of the main structure from near to far and are electrically connected in sequence;

[0102] The second inductor structure L2 includes a sixth inductor layer L2-1, a seventh inductor layer L2-2, an eighth inductor layer L2-3, a ninth inductor layer L2-4, and a tenth inductor layer L2-5, which are arranged parallel to the bottom surface of the main structure and electrically connected in sequence from near to far.

[0103] The third inductor structure L3 includes an eleventh inductor layer L3-1, a twelfth inductor layer L3-2, a thirteenth inductor layer L3-3, a fourteenth inductor layer L3-4, a fifteenth inductor layer L3-5, and a sixteenth inductor layer L3-6, which are arranged parallel to the bottom surface of the main structure and electrically connected in sequence from near to far.

[0104] The fourth inductor structure L4 includes a seventeenth inductor layer L4-1, an eighteenth inductor layer L4-2, and a nineteenth inductor layer L4-3, which are arranged parallel to the bottom surface of the main structure from near to far and are electrically connected in sequence;

[0105] The first capacitor structure C1 includes a first capacitor plate layer C1-1, a second capacitor plate layer C1-2, and a third capacitor plate layer C1-3 arranged parallel to the bottom surface of the main structure from near to far;

[0106] The second capacitor structure C2 includes a fourth capacitor plate layer C2-1 and a fifth capacitor plate layer C2-2 arranged parallel to the bottom surface of the main structure from near to far;

[0107] The first inductor layer is electrically connected to the vertical surface of the first pad P1;

[0108] The sixth inductor layer is electrically connected to the vertical surface of the fourth pad P4;

[0109] The eleventh inductor layer is electrically connected to the vertical surface of the second pad P2;

[0110] The seventeenth inductor layer is electrically connected to the first inductor structure L1 and the second inductor structure L2 respectively;

[0111] The first capacitor plate layer C1-1, the third capacitor plate layer C1-3 and the vertical surface of the third pad P3 are electrically connected;

[0112] The second capacitor plate layer C1-2 is electrically connected to the vertical surface of the first pad P1;

[0113] The fourth capacitor plate layer C2-1, the fifth capacitor plate layer C2-2, and the vertical surface of the fourth pad P4 are electrically connected.

[0114] In the above-mentioned pad structure, components such as capacitors and inductors are electrically connected to the vertical surfaces of the pads via PIN pins. Specifically, the first inductor layer L1-1 is electrically connected to the vertical surface of the first pad P1 via the first PIN pin PIN1; the sixth inductor layer L2-1 is electrically connected to the vertical surface of the fourth pad P4 via the fourth PIN pin PIN4; the eleventh inductor layer L3-1 is electrically connected to the vertical surface of the second pad P2 via the second PIN pin PIN2; the first capacitor plate layer C1-1 and the third capacitor plate layer C1-3 are electrically connected to the vertical surface of the third pad P3 via the third PIN pin PIN3; the second capacitor plate layer C1-2 is electrically connected to the vertical surface of the first pad P1 via the first PIN pin PIN1; and the fourth capacitor plate layer C2-1 and the fifth capacitor plate layer C2-2 are electrically connected to the vertical surface of the fourth pad P4 via the fourth PIN pin PIN4.

[0115] See also Figure 10 , shows the first inductor structure L1 and its connection relationship. Figure 11 , shows the second inductor structure L2 and its connection relationship. Figure 12 , shows the third inductor structure L3 and its connection relationship. Figure 13 , shows the fourth inductor structure L4 and its connection relationship. Figure 14 , shows the first capacitor structure C1 and its connection relationship. Figure 15 , showing the second capacitor structure C2 and its connection relationship.

[0116] As described above, in an optional embodiment, the first inductor layer L1-1 and the sixth inductor layer L2-1 are arranged in the same plane; the second inductor layer L1-2, the seventh inductor layer L2-2, and the eleventh inductor layer L3-1 are arranged in the same plane; the third inductor layer L1-3, the eighth inductor layer L2-3, and the twelfth inductor layer L3-2 are arranged in the same plane; the fourth inductor layer L1-4, the ninth inductor layer L2-4, and the thirteenth inductor layer L3-3 are arranged in the same plane; the fifth inductor layer L1-5, the tenth inductor layer L2-5, and the fourteenth inductor layer L3- 4 are arranged in the same plane; the seventeenth inductor layer L4-1, the first capacitor plate layer C1-1, the eighteenth inductor layer L4-2, the second capacitor plate layer C2-2, the nineteenth inductor layer L4-3, and the third capacitor plate layer C1-3 are arranged parallel to the bottom surface of the main structure from near to far; the sixteenth inductor layer L3-6 and the eighteenth inductor layer L4-2 are arranged in the same plane; the fourth capacitor plate layer C2-1 and the first capacitor plate layer C1-1 are arranged in the same plane; the fifth capacitor plate layer C2-2 and the second capacitor plate layer C1-2 are arranged in the same plane. Specifically, Figure 16 shows the structure of each layer of the first inductor structure L1; Figure 17 shows the structure of each layer of the second inductor structure L2; Figure 18 shows the structure of each layer of the third inductor structure L3; Figure 19 shows the structure of each layer of the fourth inductor structure L4; Figure 20 shows the structure of each layer of the first capacitor structure C1; Figure 21 The structure of each layer of the second capacitor structure C2 is shown. Of course, based on the above descriptions of each pad, inductor structure, and capacitor structure, the relative relationship between each inductor layer and capacitor layer can be preferably set to the above structure. Of course, those skilled in the art will know that the setting allows for a certain degree of error.

[0117] Specifically, according to circuit simulation, the inductive structure controls the inductive impedance position by the winding area and number of winding turns, while the capacitive structure controls the capacitive impedance position by the metal area. It should be understood that the specific parameters shown in this embodiment are merely optimized results obtained by the inventors through extensive experiments and tests, and do not constitute any limitation to the present invention.

[0118] In this embodiment, the first inductor structure L1 has four turns, with an internal winding area equal to the internal trace length * internal trace width = 0.3mm * 0.1mm. The second inductor structure L2 has five turns, with an internal winding area equal to the internal trace length * internal trace width = 0.38mm * 0.15mm. The coil spacing between the first and second inductor structures L1 and L2 is 32μm. The fourth inductor structure L4 has lower inductance and, to support the capacitor's in-band and out-of-band impedance control, consists of three rectangular metal sheets with a length and width of approximately 0.55mm and 0.4mm, respectively, with a spacing of 45μm. The metal cylinder has a diameter of approximately 45μm. The third capacitor plate layer C1-3 of the first capacitor structure C1 has an area of ​​approximately 0.4mm*0.35mm, the second capacitor plate layer C1-2 has an area of ​​approximately 0.25mm*0.2mm, and the first capacitor plate layer C1-1 has an area of ​​approximately 0.25mm*0.15mm. The second capacitor structure C2 is coupled to the top of the third inductor structure L3. The second capacitor structure C2 has an area of ​​approximately 0.22mm*0.22mm and is approximately 18μm away from the top of the third inductor structure L3.

[0119] As a preferred embodiment, the second capacitor and the third inductor are coupled in the sixteenth inductor layer. As described above, the three capacitor plate layers of the first capacitor structure C1 are located on top of the first inductor structure L1 and the second inductor structure L2, respectively, and together with the first capacitor plate layer C1-1 at the bottom of the first capacitor structure C1, they control the 0-3 GHz bandwidth requirement. The second capacitor plate layer C1-2 in the middle of the first capacitor structure C1 is mainly used to control out-of-band frequency suppression.

[0120] In addition, as an optional embodiment, in the above Figure 2 In the circuit shown, the first PIN pin PIN1 is an input end and the fourth PIN pin PIN4 is an output end. In another optional implementation, the first PIN pin PIN1 is an output end and the fourth PIN pin PIN4 is an input end; at the same time, the second PIN pin PIN2 and the third PIN pin PIN3 are grounded.

[0121] The ceramic patch-based low-pass filter of this embodiment adopts a low-power miniaturized device filtering design solution, thereby significantly improving the filtering effect while reducing the circuit patch area and the number of capacitor and inductor components.

[0122] Although specific embodiments of the present invention have been described above, those skilled in the art will appreciate that these are merely illustrative and that the scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, and such changes and modifications are intended to fall within the scope of the present invention.

Claims

1. A low-pass filter based on a ceramic patch, characterized in that: The low-pass filter includes a main body structure, a pad structure group, a capacitor structure group, and an inductor structure group; The pad structure group is arranged on the main structure; The capacitor structure and the inductor structure are arranged inside the main body structure; The pad structure group is electrically connected to the capacitor structure group and the inductor structure group respectively; The capacitor structure group and the inductor structure group include a resonance control structure so that the standing wave ratio of the low-pass filter is within a preset standing wave ratio range; The pad structure group includes a first pad, a second pad, a third pad, and a fourth pad; The inductor structure group includes a first inductor structure, a second inductor structure, a third inductor structure, and a fourth inductor structure; The capacitor structure group includes a first capacitor structure and a second capacitor structure; the first capacitor structure includes a first capacitor plate layer, a second capacitor plate layer, and a third capacitor plate layer arranged parallel to the bottom surface of the main structure from near to far; The resonance control structure includes a first resonance control structure and a second resonance control structure; The first inductor structure is electrically connected to the first pad; The second inductor structure is electrically connected to the fourth pad; The third inductor structure is electrically connected to the second pad; The fourth inductor structure is electrically connected to the first inductor structure and the second inductor structure respectively; The first capacitor structure is coupled to the fourth inductor to form the first resonance control structure; The second capacitor structure is electrically connected to the fourth pad; The second capacitance structure and the third inductor are coupled to form the second resonance control structure; The first capacitor structure is electrically connected to the first pad and the third pad respectively, and specifically includes: The first capacitor plate layer, the third capacitor plate layer and the vertical surface of the third pad are electrically connected; The second capacitor plate layer is electrically connected to the vertical surface of the first pad.

2. The low-pass filter based on ceramic patch according to claim 1, characterized in that The first pad, the second pad, the third pad, and the fourth pad are all L-shaped structures including a vertical surface and a horizontal surface; The vertical surface of the first pad is embedded in the first side surface of the main structure; The horizontal plane of the first pad is embedded in the bottom surface of the main structure; The vertical surface of the second pad is embedded in the first side surface of the main structure; The transverse plane of the second pad is embedded in the bottom surface of the main structure; The vertical surface of the third pad is embedded in the second side surface of the main structure; The transverse plane of the third pad is embedded in the bottom surface of the main structure; The vertical surface of the fourth pad is embedded in the second side surface of the main structure; The transverse plane of the fourth pad is embedded in the bottom surface of the main structure; Wherein, the first side surface and the second side surface of the main structure are opposite surfaces.

3. The low-pass filter based on ceramic patch according to claim 2, characterized in that: The first inductor structure includes a first inductor layer, a second inductor layer, a third inductor layer, a fourth inductor layer, and a fifth inductor layer, which are arranged parallel to the bottom surface of the main structure from near to far and are electrically connected in sequence; The second inductor structure includes a sixth inductor layer, a seventh inductor layer, an eighth inductor layer, a ninth inductor layer, and a tenth inductor layer, which are arranged parallel to the bottom surface of the main structure from near to far and are electrically connected in sequence; The third inductor structure includes an eleventh inductor layer, a twelfth inductor layer, a thirteenth inductor layer, a fourteenth inductor layer, a fifteenth inductor layer, and a sixteenth inductor layer, which are arranged parallel to the bottom surface of the main structure from near to far and are electrically connected in sequence; The fourth inductor structure includes a seventeenth inductor layer, an eighteenth inductor layer, and a nineteenth inductor layer, which are arranged parallel to the bottom surface of the main structure from near to far and are electrically connected in sequence; The second capacitor structure includes a fourth capacitor plate layer and a fifth capacitor plate layer arranged parallel to the bottom surface of the main structure from near to far; The first inductor layer is electrically connected to the vertical surface of the first pad; the sixth inductor layer is electrically connected to the vertical surface of the fourth pad; The eleventh inductor layer is electrically connected to the vertical surface of the second pad; The seventeenth inductor layer is electrically connected to the first inductor structure and the second inductor structure respectively; The fourth capacitor plate layer, the fifth capacitor plate layer, and the vertical surface of the fourth pad are electrically connected.

4. The low-pass filter based on ceramic patch according to claim 3, characterized in that: The first inductor layer and the sixth inductor layer are arranged on the same plane; The second inductor layer, the seventh inductor layer, and the eleventh inductor layer are arranged on the same plane; The third inductor layer, the eighth inductor layer, and the twelfth inductor layer are arranged on the same plane; The fourth inductor layer, the ninth inductor layer, and the thirteenth inductor layer are arranged on the same plane; The fifth inductor layer, the tenth inductor layer, and the fourteenth inductor layer are arranged on the same plane; The sixteenth inductor layer and the eighteenth inductor layer are arranged on the same plane; The fourth capacitor plate layer and the first capacitor plate layer are arranged on the same plane; The fifth capacitor plate layer and the second capacitor plate layer are arranged on the same plane.

5. The low-pass filter based on ceramic patch according to claim 3, characterized in that: The second capacitor and the third inductor are coupled in the sixteenth inductor layer.

6. The low-pass filter based on ceramic patch according to claim 3, characterized in that: The first inductor layer is electrically connected to the vertical surface of the first pad via the first PIN pin; The sixth inductor layer is electrically connected to the vertical surface of the fourth pad via the fourth PIN pin; The eleventh inductor layer is electrically connected to the vertical surface of the second pad via the second PIN pin; The first capacitor plate layer and the third capacitor plate layer are electrically connected via a third PIN pin and a vertical surface of the third pad; The second capacitor plate layer is electrically connected to the vertical surface of the first pad via the first PIN pin; The fourth capacitor plate layer and the fifth capacitor plate layer are electrically connected via the fourth PIN pin and the vertical surface of the fourth pad.

7. The low-pass filter based on ceramic patch according to claim 6, characterized in that: described The first PIN pin is an input terminal and the fourth PIN pin is an output terminal, or the first PIN pin is an output terminal and the fourth PIN is an input terminal; The second PIN pin and the third PIN pin are grounded.

8. The ceramic patch-based low-pass filter according to any one of claims 1 to 7, characterized in that: The main structure is made of ceramic material with a dielectric constant of 6-8.

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