LED driver and LED driving method

Abstract

This invention provides an LED driving device and an LED driving method, relating to LED driving technology. According to this invention, grayscale precision can be improved without increasing the clock frequency by combining multiple driving current sources to generate a driving current supplied to a single driving line.

Description

Technical Field

[0001] This invention relates to light-emitting diode (LED) driving technology. Background Technology

[0002] With the development of information technology, various display devices capable of visualizing information are being developed. Liquid crystal displays (LCDs), organic light-emitting diode (OLEDs), and plasma display panels (PDPs) are typical examples of display devices that have been developed recently or are currently under development. These display devices are constantly improving to properly display high-resolution images.

[0003] However, despite the advantages of high resolution, these display devices face the challenge of scaling up. For example, the large OLED displays developed to date are only 80 inches (approximately 2m) to 100 inches (approximately 2.5m) in size, making them unsuitable for producing large displays with a width of 10m or more.

[0004] Recently, there has been increased attention on light-emitting diode (LED) display devices as a method to address the issue of larger displays. In LED display device technology, a single large panel can be constructed by configuring a desired number of modular LED pixels. Alternatively, in LED display device technology, a single large panel structure can be constructed by configuring a desired number of unit panels comprising multiple LED pixels. As mentioned above, in LED display device technology, large display devices can be easily realized by expanding and arranging multiple LED pixels as needed.

[0005] LED display devices offer advantages in terms of panel size diversity and large panel size. In LED display technology, both horizontal and vertical sizes can be adjusted based on the appropriate arrangement of LED pixels.

[0006] On the other hand, LED display devices can adjust the brightness of LEDs through pulse width modulation (PWM) control, but traditional LED display devices do not have many adjustable brightness levels, resulting in poor color performance. In other words, traditional LED display devices cannot finely adjust grayscale. Summary of the Invention

[0007] In this context, in one aspect, the present invention provides a technique for allowing more accurate grayscale representation in LED display devices. In another aspect, the present invention provides a technique for increasing the range of grayscale values ​​in LED display devices without changing the clock. In yet another aspect, the present invention provides a technique for controlling grayscale in LED display devices by combining multiple drive current sources. Furthermore, the present invention provides a technique for reducing electromagnetic interference (EMI) caused by the clock in LED display devices.

[0008] In view of the above, in one aspect, the present invention provides an LED (light-emitting diode) driving device for driving a plurality of LEDs arranged on a panel, the LED driving device comprising: a plurality of driving current sources connected in parallel with each other; a PWM control circuit, i.e., a pulse width modulation control circuit, configured to generate a plurality of PWM signals based on grayscale values ​​for the LEDs; and a plurality of switching circuits configured to control the output of each driving current source for the LEDs based on each PWM signal.

[0009] Each PWM signal may include an ON interval and an OFF interval, and the length of the ON interval may be adjusted in units of clock cycles.

[0010] The difference in length between the ON intervals of the PWM signals can be within the length of one clock cycle.

[0011] The grayscale values ​​can have a range corresponding to 2 raised to the power of N (N is a natural number).

[0012] The number of the plurality of drive current sources can be N.

[0013] The PWM control circuit can be configured to assign the quotient obtained by dividing the gray value by N to each drive current source, and to allocate the remainder R (R is a natural number less than N) to each of the R drive current sources to generate the plurality of PWM signals.

[0014] The levels of the drive currents output from each drive current source can be basically the same.

[0015] The plurality of driving current sources can be implemented in the form of a current mirror relative to a common current source.

[0016] Another embodiment provides an LED driving device for driving LEDs arranged on a panel. The LED driving device may include: a first driving current source; a second driving current source connected in parallel with the first driving current source; a PWM control circuit configured to generate a first PWM signal and a second PWM signal by assigning grayscale values ​​for the LEDs; a first switching circuit configured to control the output of the first driving current source to the LEDs according to the first PWM signal; and a second switching circuit configured to control the output of the second driving current source to the LEDs according to the second PWM signal.

[0017] The PWM control circuit can be configured to adjust the length of the ON interval of the first PWM signal and the second PWM signal in units of clock cycles.

[0018] The PWM control circuit can control the first PWM signal and the second PWM signal such that the lengths of the ON intervals of the first PWM signal and the second PWM signal are the same, or that the difference in the lengths of the ON intervals of the first PWM signal and the second PWM signal is within the length of one cycle of the clock.

[0019] Another embodiment provides a method for driving a plurality of LEDs arranged on a panel, the method comprising: connecting one LED to a drive line according to a scan signal; identifying image data, the image data including grayscale values ​​for the one LED; dividing the grayscale values ​​into N (N is a natural number of 2 or greater) grayscale values, and generating a plurality of PWM signals according to the divided grayscale values; and controlling the outputs of N drive current sources connected to the one drive line according to the plurality of PWM signals.

[0020] Controlling the output of the N drive current sources may include: dividing a frame into M subframes, controlling the output of the N drive current sources such that the ON intervals of each of the (M-1) subframes have the same length, and controlling the output of the N drive current sources such that the length of the ON interval of the remaining subframe differs from the length of the ON intervals in the (M-1) subframes by the length of one clock cycle, where M is a natural number of 2 or greater.

[0021] Controlling the output of the N drive current sources may include: dividing a frame into M (M is a natural number of 2 or greater) subframes, and controlling the output of the N drive current sources such that the difference between the two ON intervals of the two drive current sources in each subframe is within one clock cycle, and the difference between any two sums of the ON intervals of the N drive current sources assigned to the two subframes is within one clock cycle.

[0022] As described above, according to the present invention, the LED display device allows for more accurate grayscale representation. Furthermore, according to the present invention, the LED display device allows for an increase in the range of grayscale values ​​without changing the clock, and allows for reduction of electromagnetic interference (EMI) caused by the clock. Attached Figure Description

[0023] Figure 1 This is a diagram illustrating the structure of a display device according to an embodiment.

[0024] Figure 2 This is a diagram showing the waveform of the scan signal in the display device according to an embodiment.

[0025] Figure 3 This is a diagram illustrating the structure of an LED driver device according to a first example of an embodiment.

[0026] Figure 4 This is a diagram showing the main waveform in the first example.

[0027] Figure 5A This is a diagram illustrating an example of the structure of the drive current source circuit and the switching circuit section in the first example.

[0028] Figure 5B This is a diagram illustrating another example of the structure of the drive current source circuit and the switching circuit section in the first example.

[0029] Figure 6 This is a diagram illustrating the structure of an LED driver device according to a second example of an embodiment.

[0030] Figure 7 This is a diagram showing the main waveform in the second example.

[0031] Figure 8 This is a flowchart illustrating a third example of an LED driving method according to an embodiment.

[0032] Figure 9 This is a diagram showing the main waveform in the third example. Detailed Implementation

[0033] Figure 1 This is a diagram illustrating the structure of a display device according to an embodiment.

[0034] refer to Figure 1 The display device 100 may include a driving device 110 and a panel 120.

[0035] Panel 120 may have along a first direction (e.g., Figure 1 (horizontal direction) and second direction (e.g., Figure 1 Multiple pixels P arranged in a matrix in the vertical direction (in the image).

[0036] At least one light-emitting diode (LED) can be configured in each pixel P, and the brightness of pixel P can be determined based on the brightness of the LED.

[0037] A drive line DL and a scan line SL can be arranged on panel 120. The drive line DL can connect to one side of a pixel along a second direction, and the scan line SL can connect to the opposite side of the pixel along a first direction. For example, the anode of an LED disposed in pixel P can be electrically connected to the drive line DL, and the cathode of the LED can be electrically connected to the scan line SL. In the aspect where the cathodes of the LEDs are commonly connected, Figure 1 The example shown may be referred to as a "common cathode structure", but the present invention is not limited to this structure.

[0038] Scan switches SWc1, SWc2, ..., and SWcN can be configured on each scan line SL, and the scan line SL through which the supply drive current Ie passes can be determined based on the opening and closing of the scan switches SWc1, SWc2, ..., and SWcN.

[0039] Figure 2 This is a diagram showing the waveform of the scan signal in the display device according to an embodiment.

[0040] refer to Figure 1 and Figure 2 It can scan the signal for each frame unit. <1> Scan <2> ... and Scan <n>The signal is sequentially supplied to each scan switch SWc1, SWc2, ..., SWcN. The signal can be adjusted according to the scan signal. <1> Scan <2> ... and Scan <n>Drive current Ie is sequentially supplied to the first scan line, the second scan line, ..., and the Nth scan line.

[0041] The scan line SL can be connected to a low-voltage portion of the display device 100, such as ground. Additionally, according to an embodiment, scan switches SWc1, SWc2, ..., and SWcN can be formed on the panel 120, or on a separate substrate, and can be formed inside the driving device 110.

[0042] Scan signal <1> Scan <2> ... and Scan <n>It can be supplied by the drive unit 110, or it can be supplied by a separate control unit.

[0043] The brightness of the LEDs arranged in each pixel P can be determined based on the amount of driving power supplied within a predetermined time. The LEDs can be driven by pulse width modulation (PWM), and their brightness can be determined based on the ratio of the lighting time to the PWM control time. When the LED is lit by the driving current Ie, a positive voltage is formed in the LED, and the amount of driving power supplied to the LED can be obtained by accumulating the product of the positive voltage and the driving current Ie during the lighting time within the PWM control time, so that the brightness of the LED can be determined based on this amount of driving power. Assuming that the magnitudes of the LED's positive voltage and the driving current Ie are fixed variables, the amount of driving power is proportional to the lighting time within the PWM control time, and the driving device 110 can control the lighting time within the PWM control time according to this principle, thereby controlling the brightness of the LEDs and the brightness of the pixel P.

[0044] The driving device 110 may include multiple (N) channels connected to the driving line DL, and may supply driving current Ie to each pixel P in each channel N.

[0045] On the other hand, the PWM signal that determines the grayscale of pixel P can be configured into an ON (on) interval and an OFF (off) interval, and the length of the ON interval can be adjusted by the clock cycle. Therefore, to improve the grayscale precision, the clock cycle must be shortened. However, shortening the clock cycle (i.e., increasing the clock frequency) is not easy, making it difficult to improve grayscale precision in traditional LED display devices.

[0046] The LED driver can receive image data from the image control device, and can also receive a data clock capable of reading image data bit by bit. Furthermore, the LED driver can generate an internal clock using the externally received data clock as described above. This internal clock is referred to as "GCLK," and since GCLK interacts with the externally received data clock, changing GCLK is not easy. For this reason, it is difficult to improve grayscale precision in conventional LED display devices.

[0047] To overcome this problem, embodiments provide techniques for improving grayscale fineness by combining multiple drive current sources.

[0048] Figure 3 This is a diagram illustrating the structure of an LED driver device according to a first example of an embodiment.

[0049] refer to Figure 3 The LED driver 110 may include a drive current source circuit 310, a PWM control circuit 320, and a switching circuit 330.

[0050] The drive current source circuit 310 may include a first drive current source 312 and a second drive current source 314. The first drive current source 312 and the second drive current source 314 may be connected in parallel with each other and may supply a drive current Ie to a drive line DL. The first drive current source 312 may supply a first drive current Ip1 to the drive line DL, and the second drive current source 314 may supply a second drive current Ip2 to the drive line DL. The drive current Ie flowing through the drive line DL may be the sum of the first drive current Ip1 and the second drive current Ip2.

[0051] Multiple LEDs can be connected to a single drive line DL, and each LED can be connected to the drive line DL sequentially according to the scan signal.

[0052] The PWM control circuit 320 can receive image data RGB through the input terminal Ti, and can generate PWM signals SP1 and SP2 according to the gray values ​​included in the image data RGB.

[0053] The PWM control circuit 320 can assign grayscale values ​​to the first drive current source 312 and the second drive current source 314 respectively. For example, if the grayscale value is 9, the PWM control circuit 320 can assign 6 to the first drive current source 312 and 3 to the second drive current source 314.

[0054] The PWM control circuit 320 can distribute grayscale values ​​evenly to the first drive current source 312 and the second drive current source 314. For example, if the grayscale value is 8, the PWM control circuit 320 can allocate 4 to the first drive current source 312 and 4 to the second drive current source 314. If the grayscale value is divisible by the number of drive current sources, the PWM control circuit 320 can distribute the grayscale value evenly to the first drive current source 312 and the second drive current source 314.

[0055] If the grayscale value is not divisible by the number of drive current sources, the PWM control circuit 320 can evenly distribute the grayscale value among the drive current sources until the last portion can be evenly distributed. Then, the remainder can be evenly distributed among some selected drive current sources. For example, the PWM control circuit 320 can distribute the quotient Q obtained by dividing the grayscale value by the number of drive current sources among the drive current sources, and can evenly distribute the remainder R among the selected drive current sources. In the case of two drive current sources as shown in the first embodiment, the PWM control circuit 320 can distribute the quotient Q obtained by dividing the grayscale value by 2 among the first drive current source 312 and the second drive current source 314, and can allocate the remainder R to the first drive current source 312. For example, if the grayscale value is 9, the PWM control circuit 320 can allocate 5 to the first drive current source 312 and 4 to the second drive current source 314.

[0056] The PWM control circuit 320 can use the values ​​allocated to each drive current source to generate PWM signals SP1 and SP2. The PWM control circuit 320 can use the value allocated to the first drive current source 312 to generate the first PWM signal SP1, and can use the value allocated to the second drive current source 314 to generate the second PWM signal SP2.

[0057] The output Ip1 of the first drive current source 312 can be controlled according to the first PWM signal SP1, and the output Ip2 of the second drive current source 314 can be controlled according to the second PWM signal SP2.

[0058] Multiple switching circuits can be configured in the switching circuit section 330, and each switching circuit can control the output of its corresponding drive current source. For example, the first switching circuit 332 can control the output of the first drive current source 312 according to the first PWM signal SP1, and the second switching circuit 334 can control the output of the second drive current source 314 according to the second PWM signal SP2.

[0059] The drive current Ie controlled by PWM signals SP1 and SP2 can be supplied to the drive line DL through the output terminal To.

[0060] Figure 4 This is a diagram showing the main waveform in the first example.

[0061] refer to Figure 4 The PWM control time Tpwm of PWM signal SP1 or SP2 can be configured to ON and OFF intervals. The LED driver can supply the output of each drive current source to the drive line in the ON interval and can block the output of each drive current source in the OFF interval.

[0062] The LED driver can have a clock GCLK, and the length of the ON interval in the PWM signal SP1 or SP2 can be adjusted according to the clock GCLK. The LED driver can adjust the length of the ON interval so that one unit of grayscale value corresponds to one period Δt of the clock GCLK. For example, if the grayscale value is 1, the length of the ON interval can be equal to one period of the clock GCLK.

[0063] The LED driver can adjust the lengths of the ON intervals Ton1 and Ton2 of the first PWM signal SP1 and the second PWM signal SP2 in units of clock period Δt, so that the length of the ON interval Ton1 of the first PWM signal is the same as the length of the ON interval Ton2 of the second PWM signal, or so that the difference Δd between the length of the ON interval of the first PWM signal and the length of the ON interval of the second PWM signal is one clock period Δt.

[0064] For example, if the grayscale value included in the RGB image data is 9, the LED driver can configure the ON interval of the first PWM signal to correspond to 5 clock cycles Δt, and can configure the ON interval of the second PWM signal to correspond to 4 clock cycles Δt.

[0065] The magnitude of the driving current Ie can be equal to the sum of the first driving current output from the first driving current source and the second driving current output from the second driving current source. In this case, the magnitude ΔI of the current in the interval where only the first driving current source outputs current can be smaller than the magnitude of the current in the interval where both the first and second driving current sources output current, thereby improving the fineness of the grayscale value.

[0066] The first driving current output from the first driving current source and the second driving current output from the second driving current source can have substantially the same magnitude. In this case, according to the LED driving method described above, the fineness of the grayscale value can be doubled.

[0067] Figure 5A This is a diagram illustrating an example of the structure of the drive current source circuit and the switching circuit section in the first example, and Figure 5B This is a diagram illustrating another example of the structure of the drive current source circuit and the switching circuit section in the first example.

[0068] refer to Figure 5A and Figure 5B The LED driving device may include: a first transistor TR1, whose first terminal (e.g., a source terminal or a drain terminal) is connected to the driving voltage VLED; and a basic current source 510, which is connected to a second terminal (e.g., a drain terminal or a source terminal) of the first transistor TR1.

[0069] In addition, the first driving current source 312 and the second driving current source 314 of the LED driver can be implemented in the form of a current mirror relative to the basic current source 510.

[0070] The first drive current source 312 can use a second transistor TR2 to form a current mirror structure relative to the basic current source 510. The gate of the second transistor TR2 is connected to the first transistor TR1 and its first terminal is connected to the drive voltage VLED.

[0071] The second drive current source 314 can use a third transistor TR3 to form a current mirror structure relative to the basic current source 510. The gate of the third transistor TR3 is connected to the first transistor TR1 and its first terminal is connected to the drive voltage VLED.

[0072] The first drive current source 312 may further include a fourth transistor TR4 connected in series with the second transistor TR2, and the second drive current source 314 may further include a fifth transistor TR5 connected in series with the third transistor TR3. Additionally, the gate of the fourth transistor TR4 may be connected to the output of the amplifier AMP, with the second terminals of the first transistor TR1 and the second transistor TR2 serving as inputs to the amplifier AMP. Furthermore, the gate of the fifth transistor TR5 may be connected to the output of the amplifier AMP, with the second terminals of the first transistor TR1 and the third transistor TR3 serving as inputs to the amplifier AMP.

[0073] The first switching circuit 332 may include: a first switch SW1 for controlling the connection between the second terminal of the second transistor TR2 and the input of the amplifier AMP; and a second switch SW2 for controlling the connection between the gate of the fourth transistor TR4 and the output of the amplifier AMP. Additionally, the first switch SW1 and the second switch SW2 can be switched on and off using a first PWM signal SP1.

[0074] The second switching circuit 334 may include: a third switch SW3 for controlling the connection between the second terminal of the third transistor TR3 and the input of the amplifier AMP; and a fourth switch SW4 for controlling the connection between the gate of the fifth transistor TR5 and the output of the amplifier AMP. Additionally, the third switch SW3 and the fourth switch SW4 can be switched on and off using a second PWM signal SP2.

[0075] Here, the first transistor TR1, the second transistor TR2, the third transistor TR3, the fourth transistor TR4, and the fifth transistor TR5 can be PNP type transistors.

[0076] On the other hand, reference Figure 5A In the example, the gate of the first transistor TR1 and the second terminal can be connected to each other.

[0077] Additionally, refer to Figure 5B The example may also include another amplifier AMP'. For ease of illustration, if the aforementioned amplifier AMP is the first amplifier and the other amplifier AMP' is the second amplifier, a voltage reduced from the drive voltage VLED to voltage Vx can be applied as an input to the second amplifier AMP', and this other input can be shared with the input of the first amplifier AMP. Additionally, the output of the second amplifier AMP' can be connected to the gate of the first transistor TR1. According to the above structure, one input voltage of the first amplifier AMP can be freely configured as VLED-Vx using an adjustable voltage Vx.

[0078] Although the first example describes an embodiment where the number of drive current sources is two, the number of drive current sources can be two or more. Specifically, if the grayscale values ​​included in the image data have a range corresponding to powers of 2, the number of drive current sources can be N (N is a power of 2). For example, if the grayscale values ​​are 0 to 255 or 0 to 512, the number of drive current sources can be a number corresponding to powers of 2, such as 2, 4, 8, ..., 16, etc.

[0079] Figure 6 This is a diagram illustrating the structure of an LED driver device according to a second example of an embodiment.

[0080] refer to Figure 6 The LED driver 600 may include a drive current source circuit 610, a PWM control circuit 620, and a switching circuit 630, etc.

[0081] The drive current source circuit 610 may include N drive current sources 612, 614, and 616. These N drive current sources 612, 614, and 616 may be connected in parallel and may supply drive currents Ip1, Ip2, and IpN to an LED connected to a drive line DL according to a scan signal. For example, the first drive current source 612 may supply a first drive current Ip1 to the drive line DL, the second drive current source 614 may supply a second drive current Ip2 to the drive line DL, and the Nth drive current source 616 may supply an Nth drive current IpN to the drive line DL. The currents supplied from the various drive current sources may be combined into a single drive current Ie, which then flows to the drive line DL through the output terminal To.

[0082] The PWM control circuit 620 can receive image data RGB and a clock (not shown) through the input terminal Ti, and can read the image data RGB according to the clock. In addition, the PWM control circuit 620 can convert the grayscale values ​​included in the image data RGB into multiple PWM signals SP1, SP2 and SPN corresponding to each drive current source according to the clock.

[0083] The PWM control circuit 620 can assign grayscale values ​​to the first drive current source 612, the second drive current source 614, ..., and the Nth drive current source 616 respectively. In this case, the PWM control circuit 620 can distribute the grayscale values ​​to each drive current source in a balanced manner. For example, if the grayscale values ​​are divided into N values, the PWM control circuit 620 can distribute the grayscale values ​​evenly to each drive current source.

[0084] The PWM control circuit 620 can allocate the quotient obtained by dividing the gray value or (gray value + 1) by N to each drive current source, and can allocate the remainder R (R is a natural number less than N) to the selected R drive current sources so that each of the R drive current sources is assigned one.

[0085] The PWM control circuit 620 can use the values ​​allocated to each drive current source to generate PWM signals SP1, SP2, and SPN. The PWM control circuit 620 can use the value allocated to the first drive current source 612 to generate the first PWM signal SP1, use the value allocated to the second drive current source 614 to generate the second PWM signal SP2, and use the value allocated to the Nth drive current source 616 to generate the Nth PWM signal SPN.

[0086] The switching circuit section 630, which includes multiple switching circuits 632, 634, and 636, can perform PWM control on the output of the drive current source according to various PWM signals SP1, SP2, and SPN. For example, the first switching circuit 632 can control the output of the first drive current source 612 according to the first PWM signal SP1, and the second switching circuit 634 can control the output of the second drive current source 614 according to the second PWM signal SP2. In addition, the Nth switching circuit 636 can control the output of the Nth drive current source 616 according to the Nth PWM signal SPN.

[0087] The drive current Ie controlled by the PWM signals SP1, SP2 and SPN can be supplied to the drive line DL through the output terminal To.

[0088] Figure 7 This is a diagram showing the main waveform in the second example. Figure 7 The waveform is shown when N is 4.

[0089] refer to Figure 7 The PWM control time Tpwm of PWM signals SP1, SP2, SP3, or SP4 can be configured into ON and OFF intervals. The LED driver can supply the output of each drive current source to the drive line in the ON interval and can block the output of each drive current source in the OFF interval. Although the diagram shows the positions of the ON intervals overlapping within a frame, the ON intervals can be allocated and configured in several parts. For example, if a frame is divided into two subframes for driving, the ON intervals can be allocated and configured in each subframe.

[0090] The LED driver can have a clock GCLK, and the length of the ON interval in the PWM signal SP1 or SP2 can be adjusted according to the clock GCLK. The LED driver can adjust the length of the ON interval by corresponding one unit of grayscale value to one period Δt of the clock GCLK. For example, if the grayscale value is 1, the length of the ON interval can be equal to one period of the clock GCLK.

[0091] The LED driver can adjust the lengths of the ON intervals Ton1, Ton2, Ton3, and Ton4 of the first PWM signal SP1, the second PWM signal SP2, the third PWM signal SP3, and the fourth PWM signal SP4 in units of clock period Δt, so that the lengths of the ON intervals Ton1, Ton2, Ton3, and Ton4 of the first PWM signal, the second PWM signal, and the third PWM signal are equal, or the difference Δd is one clock period Δt.

[0092] For example, if the grayscale value included in the RGB image data is 17, the LED driver can configure the ON interval of the first PWM signal to correspond to five clock cycles Δt, and the ON interval of the second PWM signal to correspond to four clock cycles Δt. Furthermore, the LED driver can configure the ON interval of the third PWM signal to correspond to four clock cycles Δt, and the ON interval of the fourth PWM signal to correspond to four clock cycles Δt.

[0093] The magnitude of the drive current Ie can be equal to the sum of the first drive current output from the first drive current source, the second drive current output from the second drive current source, the third drive current output from the third drive current source, and the fourth drive current output from the fourth drive current source. In this case, the current magnitude B in the last clock cycle interval can have four levels of value compared to the current magnitude A in other intervals that generate the drive current Ie. For example, B can have a magnitude of 1 / 4A, 2 / 4A, 3 / 4A, or 4 / 4A. Therefore, compared to the prior art, the fineness of the grayscale value can be increased by N times (in... Figure 7 (4 times). In this case, it is assumed that the magnitude of the drive current output from each drive current source is basically the same.

[0094] In order to generate substantially the same amount of drive current from each drive current source, the drive current sources can be implemented as current mirrors relative to a common current source.

[0095] Figure 8 This is a flowchart illustrating a third example of an LED driving method according to an embodiment.

[0096] The LEDs arranged on the panel can be driven in units of scan lines, and each scan line can be selected according to the scan signal. The LED driver can have multiple channels, and each channel can be connected to a drive line. In this structure, one LED can be connected to one drive line according to the scan signal (S800).

[0097] In addition, the LED driver can recognize image data (S802), which includes grayscale values ​​for an LED connected to a drive line.

[0098] In addition, the LED driver can divide the grayscale value into N values ​​(N is a natural number of 2 or greater) (S804).

[0099] In addition, the LED driver can generate multiple PWM signals based on the separated grayscale values ​​(S806).

[0100] In addition, the LED driver can control the output of N drive current sources connected to a drive line based on these multiple PWM signals (S808).

[0101] In step S808, which controls the output of N driving current sources, the LED driver can divide a frame into two sub-frames and control the output so that the N driving current sources have the same ON interval in the first sub-frame, and the difference between the ON intervals of the N driving current sources is within one clock cycle.

[0102] Figure 9 This is a diagram showing the main waveform in the third example.

[0103] refer to Figure 9 The LED driver can allocate and configure the ON intervals of PWM signals SP1 and SP2 in multiple subframes. Furthermore, the LED driver can be configured such that PWM signals SP1 and SP2 have the same ON interval in one subframe, and that the difference in the length of the ON intervals between PWM signals SP1 and SP2 in another subframe is within one clock cycle.

[0104] For example, when dividing a frame into two subframes, providing two drive current sources, and having a grayscale value of 9, the LED driver can first distribute the grayscale value to the two subframes in an equal manner. In other words, the LED driver can be controlled so that the difference between the grayscale values ​​assigned to the subframes is 1 or less. Figure 9 In the example, grayscale value 4 is assigned to the first subframe, and grayscale value 5 is assigned to the second subframe.

[0105] Furthermore, the LED driver can redistribute the grayscale values ​​allocated to each subframe to each drive current source in a balanced manner. In other words, when redistributing the grayscale values ​​allocated to each subframe to each drive current source, the LED driver can control the redistribution so that the difference between the redistributed grayscale values ​​is 1 or less.

[0106] exist Figure 9 In the first subframe, control is implemented such that the lengths of the ON intervals of PWM signals SP1 and SP2 are the same, and that the difference Δd between the lengths of the ON intervals of the first PWM signal SP1 and the second PWM signal SP2 in the second subframe is one clock cycle Δt. Based on this control, the range of grayscale values ​​that can be represented by the drive current Ie can be doubled.

[0107] A frame can be configured with M subframes (M is a natural number of 2 or greater), and the LED driver can be controlled such that the difference between the gray values ​​assigned to each driving power supply in each subframe is within 1, or the difference in the length of the ON interval between the PWM signals of each driving power supply in each subframe is within one clock cycle.

[0108] In addition, the LED driver can be controlled such that the sum of the gray values ​​assigned to each subframe is less than 1, or the difference in the total length of the ON interval of the PWM signal of each driving power supply in each subframe is within one clock cycle.

[0109] In terms of grayscale value allocation, the LED driver can equally distribute the grayscale values ​​to each sub-frame, and can equally redistribute the grayscale values ​​allocated to each sub-frame to each driver power supply.

[0110] On the other hand, although not described above, the circuit that generates the PWM signal in the PWM control circuit can be configured as a logic circuit that performs binary number operations.

[0111] Cross-reference to related applications

[0112] This application claims priority to Korean Patent Application No. 10-2020-0090175, filed on July 21, 2020, the entire contents of which are incorporated herein by reference.< / n> < / n> < / n>

Claims

1. An LED driving device for driving a plurality of LEDs arranged on a panel, the LED driving device comprising: a plurality of driving current sources connected in parallel to each other; a PWM control circuit configured to generate a plurality of PWM signals in accordance with a gray value for the LEDs; and a plurality of switching circuits configured to control the output of each driving current source for the LEDs in accordance with each PWM signal, wherein each driving current source supplies a driving current to one driving line, and wherein the driving current flowing through the one driving line is the sum of the outputs of the driving current sources, wherein the plurality of driving current sources are connected to one driving voltage, wherein the number of the plurality of driving current sources is N, and the PWM control circuit is configured to assign a value of a quotient obtained by dividing the gray value by N to each driving current source, and to allocate a remainder R to R driving current sources, respectively, to generate the plurality of PWM signals, where N is a natural number, and where R is 0 or a natural number smaller than N, wherein the PWM control circuit generates a first PWM signal and a second PWM signal using the value assigned to the respective driving current source, and wherein the output of a first driving current source is controlled in accordance with the first PWM signal, and the output of a second driving current source is controlled in accordance with the second PWM signal.

2. The LED driving apparatus according to claim 1, wherein The PWM signal includes an ON interval and an OFF interval, wherein the length of the ON interval is adjusted in units of a period of a clock.

3. The LED driving apparatus according to claim 2, wherein The difference in the length of the ON interval between the PWM signals is within the length of one period of the clock.

4. The LED driving apparatus according to claim 1, wherein The gray value has a range corresponding to 2 raised to the power of N.

5. The LED driving apparatus according to claim 1, wherein The driving current output from each driving current source is the same.

6. The LED driving apparatus according to claim 1, wherein The plurality of driving current sources are implemented in the form of a current mirror with respect to one common current source.

7. An LED driving device for driving an LED arranged on a panel, the LED driving device comprising: a first driving current source supplying a first driving current to one driving line; a second driving current source connected in parallel to the first driving current source and supplying a second driving current to the one driving line; a PWM control circuit configured to generate a first PWM signal and a second PWM signal by allocating a gray value for the LED; a first switching circuit configured to control the output of the first driving current source for the LED in accordance with the first PWM signal; and a second switching circuit configured to control the output of the second driving current source for the LED in accordance with the second PWM signal, wherein the driving current flowing through the one driving line is the sum of the first driving current and the second driving current, wherein a plurality of driving current sources are connected to one driving voltage, wherein the number of the plurality of drive current sources is N, and the PWM control circuit is configured to assign a value of a quotient obtained by dividing the gray scale value by N to each drive current source, and to allocate a remainder R to R drive current sources, respectively, to generate a plurality of PWM signals, where N is equal to 2, where R is 0 or a natural number smaller than N, wherein the PWM control circuit generates a first PWM signal and a second PWM signal using the values assigned to the respective drive current sources, and wherein the output of the first drive current source is controlled in accordance with the first PWM signal, and the output of the second drive current source is controlled in accordance with the second PWM signal.

8. The LED driving apparatus according to claim 7, wherein The PWM control circuit is configured to adjust the length of the ON interval of the first PWM signal and the second PWM signal in units of a period of a clock.

9. The LED driving apparatus according to claim 8, wherein The PWM control circuit controls the first PWM signal and the second PWM signal such that the length of the ON interval of the first PWM signal and the second PWM signal is the same as each other, or such that the difference in the length of the ON interval of the first PWM signal and the second PWM signal is within the length of one period of the clock.

10. The LED driving apparatus according to claim 7, further comprising: a first transistor having a first terminal connected to a drive voltage; and a basic current source connected to a second terminal of the first transistor, wherein the first drive current source forms a current mirror structure with respect to the basic current source using a second transistor having a gate commonly connected with the first transistor, and a first terminal connected to the drive voltage, and wherein the second drive current source forms a current mirror structure with respect to the basic current source using a third transistor having a gate commonly connected with the first transistor, and a first terminal connected to the drive voltage.

11. The LED driving apparatus according to claim 10, wherein The first drive current source further includes a fourth transistor connected in series with the second transistor, and the second drive current source further includes a fifth transistor connected in series with the third transistor, wherein a gate of the fourth transistor is connected to an output terminal of a first amplifier, wherein a second terminal of the first transistor and a second terminal of the second transistor are connected to the first amplifier as input terminals, and wherein a gate of the fifth transistor is connected to an output terminal of a second amplifier, wherein a second terminal of the first transistor and a second terminal of the third transistor are connected to the second amplifier as input terminals.

12. The LED driving apparatus according to claim 11, wherein The first switch circuit includes a first switch configured to control connection between a second terminal of the second transistor and the first amplifier, and a second switch configured to control connection between a gate of the fourth transistor and the first amplifier, and the second switch circuit includes a third switch configured to control connection between a second terminal of the third transistor and the second amplifier, and a fourth switch configured to control connection between a gate of the fifth transistor and the second amplifier, wherein the first amplifier and the second amplifier have the same properties.

13. The LED driving apparatus according to claim 11, wherein The first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are PNP type transistors.

14. A method for driving a plurality of LEDs arranged on a panel, the method comprising: connecting one LED to one drive line according to a scan signal; identifying image data including a gray scale value for the one LED; dividing the gray scale value into N gray scale values, and generating a plurality of PWM signals according to the divided gray scale values, where N is a natural number of 2 or more; and controlling outputs of N drive current sources connected to the one drive line according to the plurality of PWM signals through N switch circuits, respectively, wherein the N drive current sources are connected in parallel to each other, and wherein a drive current flowing through the one drive line is a sum of the outputs of the drive current sources, wherein the N drive current sources are connected to one drive voltage, wherein a PWM control circuit is configured to assign a value of a quotient obtained by dividing the gray scale value by N to each drive current source, and to allocate a remainder R to R drive current sources, respectively, to generate the plurality of PWM signals, where R is a natural number of 0 or less than N, wherein the PWM control circuit generates a first PWM signal and a second PWM signal using the values assigned to the respective drive current sources, and wherein an output of a first drive current source is controlled according to the first PWM signal, and an output of a second drive current source is controlled according to the second PWM signal.

15. The method of claim 14, wherein, Controlling the outputs of the N drive current sources includes dividing one frame into M sub-frames, controlling the outputs of the N drive current sources so that ON intervals of (M-1) sub-frames each have the same length, and controlling the outputs of the N drive current sources so that a length of an ON interval of a remaining one sub-frame differs from lengths of the ON intervals in the (M-1) sub-frames by a length of one period of a clock, where M is a natural number of 2 or more.

16. The method of claim 14, wherein, Controlling the outputs of the N drive current sources includes dividing one frame into M sub-frames, and controlling the outputs of the N drive current sources so that a difference between two ON intervals of two drive current sources in each sub-frame is within one period of a clock, and so that a difference between any two sums of ON intervals of N drive current sources assigned to two sub-frames is within one period of a clock, where M is a natural number of 2 or more.

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