Display device performing multi-frequency driving and method of operating display device

Abstract

A display device performing multi-frequency driving and a method of operating the display device are provided. The display device includes a display panel including a first partial panel area and a second partial panel area, and a panel driver driving the display panel. The panel driver determines a first driving frequency for the first partial panel area and a second driving frequency for the second partial panel area. In a case where the first driving frequency and the second driving frequency are different from each other, the panel driver sets a boundary portion including a boundary between the first partial panel area and the second partial panel area, and determines a third driving frequency for the boundary portion to be between the first driving frequency and the second driving frequency.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a display device, and more particularly, to a display device performing multi-frequency driving (MFD). BACKGROUND

[0002] In a display device used in a portable device such as a smart phone, a tablet, etc., it is desirable to reduce power consumption. Recently, a low frequency driving technique of driving or refreshing a display panel at a frequency lower than a normal driving frequency (e.g., about 60 Hz, about 100 Hz, about 120 Hz, etc.) can be used to reduce power consumption of the display device. SUMMARY

[0003] In a display device to which the low frequency driving technique is applied, when a still image is not displayed in the entire area of the display panel, or when a still image is displayed only in a partial area of the display panel, the entire area of the display panel can be driven at a normal driving frequency. Accordingly, in this case, the low frequency driving can not be performed, and power consumption can not be reduced.

[0004] Embodiments provide a display device having reduced power consumption by performing multi-frequency driving (MFD) and having improved display quality by reducing a luminance difference between a high frequency area and a low frequency area.

[0005] Embodiments provide a method of operating a display device for reducing power consumption by performing MFD and reducing a luminance difference between a high frequency area and a low frequency area.

[0006] According to embodiments, a display device includes a display panel including a first partial panel area and a second partial panel area, and a panel driver driving the display panel. In such embodiments, the panel driver determines a first driving frequency for the first partial panel area and a second driving frequency for the second partial panel area. In such embodiments, in a case where the second driving frequency is lower than the first driving frequency, the panel driver provides a data voltage to the first partial panel area and the second partial panel area in a first frame period, provides the data voltage to the first partial panel area in a second frame period, determines a voltage level of a blank voltage for the second partial panel area, and provides the blank voltage to the second partial panel area in the second frame period.

[0007] In embodiments, in the first frame period, data writing and bias operations can be performed on pixels of the first partial panel area and the second partial panel area based on the data voltage. In such embodiments, in the second frame period, data writing and bias operations can be performed on pixels of the first partial panel area based on the data voltage, and bias operations can be performed on pixels of the second partial panel area based on the blank voltage.

[0008] In an embodiment, in the first frame period, through the data write and bias operation, a voltage generated by subtracting the threshold voltage of the driving transistor of the pixel of the first partial panel area and the second partial panel area from the data voltage can be stored in the storage capacitor of the pixel of the first partial panel area and the second partial panel area, and a first turn-on bias based on the data voltage can be applied to the driving transistor of the pixel of the first partial panel area and the second partial panel area. In such an embodiment, in the second frame period, through the data write and bias operation, a voltage generated by subtracting the threshold voltage of the driving transistor of the pixel of the first partial panel area from the data voltage can be stored in the storage capacitor of the pixel of the first partial panel area, and a first turn-on bias based on the data voltage can be applied to the driving transistor of the pixel of the first partial panel area. In such an embodiment, in the second frame period, through the bias operation, a second turn-on bias based on the blank voltage can be applied to the driving transistor of the pixel of the second partial panel area.

[0009] In an embodiment, the panel driver can determine the voltage level of the blank voltage for the second partial panel area as the voltage level of the data voltage corresponding to a gray level higher than a black gray level.

[0010] In an embodiment, the panel driver can divide input image data for the display panel into first partial image data for the first partial panel area and second partial image data for the second partial panel area, and can determine the voltage level of the blank voltage for the second partial panel area by analyzing the second partial image data for the second partial panel area.

[0011] In an embodiment, the panel driver can determine a maximum gray level among gray levels represented by the second partial image data for the second partial panel area, and can determine the voltage level of the blank voltage for the second partial panel area as the voltage level of the data voltage corresponding to the maximum gray level.

[0012] In an embodiment, the panel driver can determine a maximum gray level among gray levels represented by the second partial image data for the second partial panel area, and can determine the voltage level of the blank voltage for the second partial panel area as the voltage level of the data voltage corresponding to a gray level higher than a black gray level and lower than the maximum gray level.

[0013] In an embodiment, the panel driver can determine an average gray level among gray levels represented by the second partial image data for the second partial panel area, and can determine the voltage level of the blank voltage for the second partial panel area as the voltage level of the data voltage corresponding to the average gray level.

[0014] In an embodiment, the panel driver can divide input image data for the display panel into first partial image data for a first partial panel area and second partial image data for a second partial panel area, and can determine a voltage level of a blank voltage for the second partial panel area by analyzing the first partial image data for the first partial panel area.

[0015] In an embodiment, the panel driver can determine a voltage level of a blank voltage for the second partial panel area based on a maximum gray level or an average gray level among gray levels represented by the first partial image data for the first partial panel area.

[0016] In an embodiment, each pixel in the first partial panel area and the second partial panel area can include a driving transistor generating a driving current, a switching transistor transmitting a data voltage or a blank voltage to a source of the driving transistor in response to a gate write signal, a compensation transistor diode-connecting the driving transistor in response to a gate compensation signal, a storage capacitor storing a voltage generated by subtracting a threshold voltage of the driving transistor from the data voltage, a first initialization transistor providing a first initialization voltage to the storage capacitor and a gate of the driving transistor in response to a gate initialization signal, a first emission transistor coupling a line of a power voltage to the source of the driving transistor in response to an emission signal, a second emission transistor coupling a drain of the driving transistor to an organic light emitting diode in response to the emission signal, a second initialization transistor providing a second initialization voltage to the organic light emitting diode in response to a gate write signal of a next pixel row, and the organic light emitting diode emitting light based on the driving current.

[0017] In an embodiment, at least one selected from the driving transistor, the switching transistor, the compensation transistor, the first initialization transistor, the first emission transistor, the second emission transistor, and the second initialization transistor can be implemented with a P-Type Metal-Oxide-Semiconductor (PMOS) transistor, and at least one selected from the driving transistor, the switching transistor, the compensation transistor, the first initialization transistor, the first emission transistor, the second emission transistor, and the second initialization transistor can be implemented with an N-Type Metal-Oxide-Semiconductor (NMOS) transistor.

[0018] In an embodiment, the panel driver can include a data driver to provide a data voltage or a blank voltage to the display panel, a scan driver to provide a gate initialization signal, a gate write signal, and a gate compensation signal to the display panel, an emission driver to provide an emission signal to the display panel, and a controller to control the data driver, the scan driver, and the emission driver, to determine a first driving frequency and a second driving frequency for the first partial panel area and the second partial panel area, and to determine a voltage level of the blank voltage for the second partial panel area.

[0019] In an embodiment, the controller can include a still image detector to divide input image data for the display panel into first partial image data for the first partial panel area and second partial image data for the second partial panel area, and to determine whether each of the first partial image data and the second partial image data represents a still image, a driving frequency decider to determine a first driving frequency for the first partial panel area according to whether the first partial image data represents a still image, and to determine a second driving frequency for the second partial panel area according to whether the second partial image data represents a still image, and a blank voltage decider to determine a voltage level of the blank voltage.

[0020] In an embodiment, in a case where the first partial image data represents a moving image and the second partial image data represents a still image, the driving frequency decider can determine the first driving frequency as a normal driving frequency, and determine the second driving frequency as a low frequency lower than the normal driving frequency. In such an embodiment, the scan driver can provide the gate initialization signal, the gate write signal, and the gate compensation signal to each pixel of the first partial panel area at the normal driving frequency. In such an embodiment, the scan driver can provide the gate write signal to each pixel of the second partial panel area at the normal driving frequency, and can provide the gate initialization signal and the gate compensation signal to each pixel of the second partial panel area at the low frequency.

[0021] In an embodiment, the display apparatus can be a foldable display apparatus, and a boundary between the first partial panel area and the second partial panel area can correspond to a folding line of the foldable display apparatus.

[0022] According to embodiments, a method of operating a display apparatus includes determining a first driving frequency for a first partial panel area of a display panel and a second driving frequency for a second partial panel area of the display panel, providing a data voltage to the first partial panel area and the second partial panel area in a first frame period in a case where the second driving frequency is lower than the first driving frequency, providing the data voltage to the first partial panel area in a second frame period in the case where the second driving frequency is lower than the first driving frequency, determining a voltage level of a blank voltage for the second partial panel area in the case where the second driving frequency is lower than the first driving frequency, and providing the blank voltage to the second partial panel area in the second frame period in the case where the second driving frequency is lower than the first driving frequency.

[0023] In embodiments, the voltage level of the blank voltage for the second partial panel area can be determined as a voltage level of the data voltage corresponding to a gray level higher than a black gray level.

[0024] In embodiments, input image data for the display panel can be divided into first partial image data for the first partial panel area and second partial image data for the second partial panel area, and the voltage level of the blank voltage for the second partial panel area can be determined by analyzing the second partial image data for the second partial panel area.

[0025] In embodiments, input image data for the display panel can be divided into first partial image data for the first partial panel area and second partial image data for the second partial panel area, and the voltage level of the blank voltage for the second partial panel area can be determined by analyzing the first partial image data for the first partial panel area.

[0026] As described above, in embodiments of a display apparatus and a method of operating a display apparatus, a first driving frequency for a first partial panel area of a display panel and a second driving frequency for a second partial panel area of the display panel can be determined. In such embodiments, in a case where the second driving frequency is lower than the first driving frequency, a data voltage can be provided to the first partial panel area and the second partial panel area in a first frame period. In such embodiments, in a second frame period, the data voltage can be provided to the first partial panel area, a voltage level of a blank voltage for the second partial panel area can be determined, and the blank voltage can be provided to the second partial panel area. Accordingly, since the first partial panel area and the second partial panel area are driven at different driving frequencies from each other, power consumption of the display apparatus can be reduced. In such embodiments, a bias operation can be performed on pixels in the second partial panel area based on the blank voltage rather than black data voltage, and thus a difference in brightness between the first partial panel area and the second partial panel area driven at different driving frequencies can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0027] The above and other features of the present application will become more apparent by describing in more detail embodiments thereof with reference to the attached drawings.

[0028] Figure 1 is a block diagram illustrating a display device according to an embodiment.

[0029] Figure 2A is a diagram illustrating Figure 1 the display device of FIG. 1 is a diagram of an embodiment of an inner folding display device, and Figure 2B is a diagram illustrating Figure 1 the display device of FIG. 1 is a diagram of an embodiment of an outer folding display device.

[0030] Figure 3 is a diagram illustrating an embodiment in which a portion of a display panel displaying a moving image is set as a first partial panel area and another portion of the display panel displaying a still image is set as a second partial panel area.

[0031] Figure 4 is a circuit diagram illustrating an embodiment of a pixel included in a display device according to an embodiment.

[0032] Figure 5 is a timing diagram for describing an operation of a display device in which a first partial panel area and a second partial panel area are all driven at a normal driving frequency, an embodiment.

[0033] Figure 6 is a timing diagram for describing an operation of a display device in which a first partial panel area is driven at a normal driving frequency and a second partial panel area is driven at a low frequency, an embodiment.

[0034] Figure 7 is a diagram illustrating luminance of a first partial panel area driven at a normal driving frequency and a second partial panel area driven at a low frequency during a driving time, an embodiment.

[0035] Figure 8 is a flowchart illustrating a method of operating a display device according to an embodiment.

[0036] Figure 9 is a timing diagram for describing an operation of a display device in which a first partial panel area is driven at a normal driving frequency and a second partial panel area is driven at a low frequency, an embodiment.

[0037] Figure 10 is a diagram for describing an embodiment of data writing and bias operations of a pixel in a data writing period.

[0038] Figure 11 is a diagram for describing an embodiment of a bias operation of a pixel in a holding period.

[0039] Figure 12 FIG. 2 is a flowchart illustrating a method of operating a display apparatus according to an embodiment.

[0040] Figure 13 FIG. 3 is a diagram illustrating an embodiment of a histogram of second partial image data for a second partial panel region.

[0041] Figure 14 FIG. 4 is a flowchart illustrating a method of operating a display apparatus according to another embodiment.

[0042] Figure 15 FIG. 5 is a block diagram illustrating an electronic apparatus including a display apparatus according to an embodiment. DETAILED DESCRIPTION

[0043] The present application will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. The present application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. Like reference numerals refer to like elements throughout.

[0044] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements can be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0045] It will be understood that, although the terms "first", "second", "third", etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first "element", "component", "region", "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the terms "a," "an," "the," and "at least one" are not intended to signify a limitation on the number of embodiments. For example, "a" or "an" can mean one or more than one. Unless otherwise clear from the context, the use of "at least one" will not limit the number of embodiments to a single reference. "Or" means "and / or." As used herein, the phrase "and / or" includes any and all combinations of one or more of the associated listed items. It will also be understood that the use of the term "comprise" and / or "comprising" or "include" and / or "including" when used in this specification, specifies the presence of stated features, regions, integers, steps, operations, elements, and / or components but does not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0047] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" can be used herein to describe one element's or feature's relationship to another element or feature as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on the "upper" sides of the other elements. The term "lower" can then encompass both an "lower" and "upper" orientation. Likewise, the term "upper" can encompass both an "upper" and "lower" orientation. The terms "upwardly", "downwardly", "upwards" and "downwards" can be used herein to describe the relative orientation of one element to another element as illustrated in the figures. It will be understood that the relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being "upwardly" or "upwards" of other elements would then be oriented "downwardly" or "downwards" of the other elements. The terms "upwardly" and "downwardly" can encompass both an "upwardly" and "downwards" orientation. The terms "upwards" and "downwards" can encompass both an "upwards" and "downwards" orientation.

[0048] "About" or "approximately," as used herein, includes the recited value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the recited value.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0050] The implementations described herein are not to be interpreted so as to be limited to the specific shapes of the regions shown herein, but are to include deviations from the shapes caused, for example, by manufacturing. For example, regions shown or described as flat can generally have rough and / or nonlinear features. Also, shown corners can be rounded. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to show the precise shape of the regions and are not intended to limit the scope of the present claims.

[0051] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0052] Figure 1 is a block diagram illustrating a display device 100 according to an embodiment, Figure 2A is a block diagram illustrating Figure 1 is a diagram of the display device 100 that is an embodiment of an inner folding display device 100a, Figure 2B is a diagram illustrating Figure 1 is a diagram of the display device 100 that is an embodiment of an outer folding display device 100b, Figure 3 is a diagram illustrating an embodiment in which a part of the display panel 110c displaying a moving image is set as a first partial panel region PPR1c and another part of the display panel 110c displaying a still image is set as a second partial panel region PPR2c, Figure 4 is a circuit diagram illustrating an embodiment of a pixel PX included in the display device 100 according to an embodiment, Figure 5 is a timing diagram for describing an embodiment of an operation of the display device 100 in which the first partial panel region PPR1 and the second partial panel region PPR2 are all driven at a normal driving frequency, Figure 6 is a timing diagram for describing an embodiment of an operation of the display device 100 in which the first partial panel region PPR1 is driven at a normal driving frequency and the second partial panel region PPR2 is driven at a low frequency, and Figure 7 is a diagram illustrating an embodiment of luminance of the first partial panel region PPR1 driven at a normal driving frequency and the second partial panel region PPR2 driven at a low frequency during a driving time.

[0053] Referring to Figure 1The embodiment of the display device 100 can include the display panel 110 and a panel driver 190 that drives the display panel 110. In an embodiment, the panel driver 190 can include a data driver 120 that provides a data voltage VDATA or a blank voltage VBLANK to the display panel 110, a scan driver 130 that provides a gate initialization signal GI, a gate write signal GW, and a gate compensation signal GC to the display panel 110, an emission driver 140 that provides an emission signal EM to the display panel 110, and a controller 150 that controls the data driver 120, the scan driver 130, and the emission driver 140.

[0054] The display panel 110 can include a first partial panel region PPR1 and a second partial panel region PPR2. In an embodiment, for example, the display panel 110 can be divided into the first partial panel region PPR1 and the second partial panel region PPR2, and each of the first partial panel region PPR1 and the second partial panel region PPR2 includes two or more scan lines or two or more pixel rows connected to the two or more scan lines.

[0055] In an embodiment, the first partial panel region PPR1 and the second partial panel region PPR2 can have fixed partial regions within the display panel 110. In an embodiment, for example, the display device 100 can be a foldable display device, and a boundary between the first partial panel region PPR1 and the second partial panel region PPR2 can correspond to a folding line of the foldable display device.

[0056] In an embodiment, as shown in FIG. 1A, the display device 100 can be a foldable display device 100a including a foldable display panel 110a folded such that the first partial panel region PPR1a and the second partial panel region PPR2a face each other, and a boundary PPRB between the first partial panel region PPR1a and the second partial panel region PPR2a can have a fixed position corresponding to a folding line FL when the foldable display panel 110a is folded. Figure 2A In an embodiment, as shown in FIG. 1A, the display device 100 can be a foldable display device 100a including a foldable display panel 110a folded such that the first partial panel region PPR1a and the second partial panel region PPR2a face each other, and a boundary PPRB between the first partial panel region PPR1a and the second partial panel region PPR2a can have a fixed position corresponding to a folding line FL when the foldable display panel 110a is folded. Figure 2B In an embodiment, as shown in FIG. 1A, the display device 100 can be a foldable display device 100a including a foldable display panel 110a folded such that the first partial panel region PPR1a and the second partial panel region PPR2a face each other, and a boundary PPRB between the first partial panel region PPR1a and the second partial panel region PPR2a can have a fixed position corresponding to a folding line FL when the foldable display panel 110a is folded. Figure 2A and Figure 2BIt is shown that the display device 100 is an embodiment of a foldable display device 100a or 100b, but the embodiment is not limited thereto. In alternative embodiments, the display device 100 can be any flexible display device such as a curved display device, a bendable display device, a rollable display device, a stretchable display device, etc. In another alternative embodiment, the display device 100 can be a flat (e.g., rigid) display device.

[0057] In embodiments, the first partial panel region PPR1 and the second partial panel region PPR2 can be dynamically changed within the display panel 110. In one embodiment, for example, as shown in FIG. 1C, in a case where a moving image is displayed in a portion of the display panel 110c and a still image is displayed in another portion of the display panel 110c, the first partial panel region PPR1c can be set as the portion of the display panel 110c displaying the moving image, and the second partial panel region PPR2c can be set as the other portion of the display panel 110c displaying the still image. In this case, to set the first partial panel region PPR1c and the second partial panel region PPR2c, the controller 150 can divide the display panel 110c into the portion of the display panel 110c displaying the moving image and the other portion of the display panel 110c displaying the still image by analyzing the input image data IDAT. Figure 3

[0058] Although Figures 1 to 3 It is shown that the display panel is divided into two partial panel regions, but the embodiment is not limited thereto. In alternative embodiments, the display panel can be divided into three or more partial panel regions that can be driven at different driving frequencies.

[0059] ​The display panel 110 can include a plurality of data lines, a plurality of scan lines, a plurality of emission lines, and a plurality of pixels PX coupled thereto. In such an embodiment, each of the first partial panel region PPR1 and the second partial panel region PPR2 can include a plurality of pixels PX. In an embodiment, the plurality of scan lines can include a plurality of gate initialization lines, a plurality of gate write lines, and a plurality of gate compensation lines. In such an embodiment, each pixel PX can include at least one capacitor, at least two transistors, and an organic light emitting diode (OLED), and the display panel 110 can be an OLED display panel. In an embodiment, each pixel PX can be a hybrid oxide polycrystalline (HOP) pixel suitable for low frequency driving capable of reducing power consumption. In one embodiment, for example, in a HOP pixel, at least one first transistor can be implemented with a low-temperature polycrystalline silicon (LTPS) p-type metal oxide semiconductor (PMOS) transistor, and at least one second transistor can be implemented with an oxide n-type metal oxide semiconductor (NMOS) transistor.

[0060] In one embodiment, for example, as Figure 4As shown in FIG. 1, each pixel PX can include a drive transistor Tl generating a drive current, a switching transistor T2 transferring a data voltage VDATA or a blank voltage VBLANK to a source of the drive transistor Tl in response to a gate write signal GW[n], a compensation transistor T3 diode-connecting the drive transistor Tl in response to a gate compensation signal GC[n], a storage capacitor CST storing a voltage generated by subtracting a threshold voltage of the drive transistor Tl from the data voltage VDATA, a first initialization transistor T4 supplying a first initialization voltage VINTl to the storage capacitor CST and a gate of the drive transistor Tl in response to a gate initialization signal GI[n], a first emission transistor T5 coupling or connecting a line of a first power voltage ELVDD to a source of the drive transistor Tl in response to an emission signal EM[n], a second emission transistor T6 coupling or connecting a drain of the drive transistor Tl to an organic light emitting diode EL in response to the emission signal EM[n], a second initialization transistor T7 supplying a second initialization voltage VINT2 to the organic light emitting diode EL in response to a gate write signal GW[n+1] for a pixel PX in a next pixel row or a next row, and the organic light emitting diode EL emitting light based on the drive current flowing from the line of the first power voltage ELVDD to a line of a second power voltage ELVSS. According to an embodiment, the first initialization voltage VINTl and the second initialization voltage VINT2 can be substantially the same voltage as each other, or can be different voltages from each other.

[0061] At least one selected from the drive transistor Tl, the switching transistor T2, the compensation transistor T3, the first initialization transistor T4, the first emission transistor T5, the second emission transistor T6, and the second initialization transistor T7 can be implemented with a PMOS transistor, and at least one selected from the drive transistor Tl, the switching transistor T2, the compensation transistor T3, the first initialization transistor T4, the first emission transistor T5, the second emission transistor T6, and the second initialization transistor T7 can be implemented with an NMOS transistor. In one embodiment, for example, as shown in FIG. 1, the compensation transistor T3 and the first initialization transistor T4 can be implemented with NMOS transistors, and the other transistors Tl, T2, T5, T6, and T7 can be implemented with PMOS transistors. In this case, the gate compensation signal GC[n] applied to the compensation transistor T3 and the gate initialization signal GI[n] applied to the first initialization transistor T4 can be high-level active signals suitable for NMOS transistors. In such an embodiment, since the compensation transistor T3 and the first initialization transistor T4 directly coupled to the storage capacitor CST are implemented with NMOS transistors, a leakage current from / to the storage capacitor CST can be reduced, and thus the pixel PX can be suitable for low frequency driving. Although Figure 4 Figure 4 ​Embodiments in which the compensation transistor T3 and the first initialization transistor T4 are implemented with NMOS transistors are shown, but the configuration of each pixel PX according to embodiments is not limited to Figure 4 The display panel 110 can be a Liquid Crystal Display (LCD) panel or any other type of display panel in alternative embodiments.

[0062] Referring again to Figure 1 , the data driver 120 can generate the data voltage VDATA based on the output image data ODAT and the data control signals DCTRL received from the controller 150, and can provide the data voltage VDATA to the plurality of pixels PX through the plurality of data lines in the data write period. In embodiments, the data driver 120 can provide a blank voltage VBLANK to the pixels PX driven at a low frequency through the plurality of data lines in the hold period. The data control signals DCTRL can include a blank voltage level signal indicating the voltage level of the blank voltage VBLANK. In embodiments, the data control signals DCTRL can include, but are not limited to, an output data enable signal, a horizontal start signal, and a load signal. In embodiments, the data driver 120 and the controller 150 can be implemented with a single integrated circuit, and the integrated circuit can be referred to as a Timing Controller Embedded Data Driver (TED). In alternative embodiments, the data driver 120 and the controller 150 can be implemented by separate integrated circuits, respectively.

[0063] The scan driver 130 can generate a plurality of scan signals GI, GW, and GC based on a scan control signal SCTRL received from the controller 150, and can sequentially provide the plurality of scan signals GI, GW, and GC to the plurality of pixels PX row by row through a plurality of scan lines. In an embodiment, the plurality of scan signals GI, GW, and GC can include a gate initialization signal GI, a gate write signal GW, and a gate compensation signal GC. In one embodiment, for example, the scan driver 130 can apply the gate initialization signal GI to the pixels PX for each row, and then can apply the gate write signal GW and the gate compensation signal GC to the pixels PX. In an embodiment, in a hold period, the scan driver 130 can not apply the gate initialization signal GI and the gate compensation signal GC to the pixels PX driven at a low frequency, but can apply only the gate write signal GW to the pixels PX driven at a low frequency. In an embodiment, the scan control signal SCTRL can include, but is not limited to, a scan start signal and a scan clock signal. In an embodiment, the scan driver 130 can be integrated or formed in a peripheral portion of the display panel 110. In an alternative embodiment, the scan driver 130 can be implemented with one or more integrated circuits.

[0064] The emission driver 140 can generate an emission signal EM based on an emission control signal EMCTRL received from the controller 150, and can sequentially provide the emission signal EM to the plurality of pixels PX row by row through a plurality of emission lines. In an embodiment, the emission control signal EMCTRL can include, but is not limited to, an emission start signal and an emission clock signal. In an embodiment, the emission driver 140 can be integrated or formed in a peripheral portion of the display panel 110. In an alternative embodiment, the emission driver 140 can be implemented with one or more integrated circuits.

[0065] A controller (e.g., a timing controller (TCON)) 150 can receive input image data IDAT and control signals CTRL from an external host (e.g., a graphic processing unit (GPU) or a graphic card). In an embodiment, the control signals CTRL can include, but are not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, etc. The controller 150 can generate output image data ODAT, data control signals DCTRL, scan control signals SCTRL, and emission control signals EMCTRL based on the input image data IDAT and the control signals CTRL. The controller 150 can control the operation of the data driver 120 by providing the output image data ODAT and the data control signals DCTRL to the data driver 120, can control the operation of the scan driver 130 by providing the scan control signals SCTRL to the scan driver 130, and can control the operation of the emission driver 140 by providing the emission control signals EMCTRL to the emission driver 140.

[0066] In an embodiment, the panel driver 190 of the display apparatus 100 can determine a first driving frequency for the first partial panel region PPR1 and a second driving frequency for the second partial panel region PPR2. In an embodiment, the first driving frequency and the second driving frequency can be different from each other, and the panel driver 190 can perform multi-frequency driving (MFD) so that the first partial panel region PPR1 and the second partial panel region PPR2 are driven at the first driving frequency and the second driving frequency, which are different from each other. In one embodiment, for example, in a case where a moving image is displayed in the first partial panel region PPR1 and a still image is displayed in the second partial panel region PPR2, the panel driver 190 can determine the first driving frequency for the first partial panel region PPR1 as a normal driving frequency (e.g., about 60 Hz, about 100 Hz, about 120 Hz, etc.), can determine the second driving frequency as a low frequency lower than the normal driving frequency, can drive the first partial panel region PPR1 at the normal driving frequency, and can drive the second partial panel region PPR2 at the low frequency. In an embodiment, the controller 150 of the panel driver 190 can include a still image detector 160 and a driving frequency decider 170 to determine the first driving frequency for the first partial panel region PPR1 and the second driving frequency for the second partial panel region PPR2.

[0067] The still image detector 160 can divide the input image data IDAT for the display panel 110 into first partial image data for the first partial panel region PPR1 and second partial image data for the second partial panel region PPR2, and can determine whether each of the first partial image data and the second partial image data represents a still image. In an embodiment, the still image detector 160 can determine whether the first partial image data represents a still image by comparing the first partial image data in a previous frame period with the first partial image data in a current frame period, and can determine whether the second partial image data represents a still image by comparing the second partial image data in the previous frame period with the second partial image data in the current frame period.

[0068] The driving frequency decider 170 can determine a first driving frequency for the first partial panel region PPR1 according to whether the first partial image data represents a still image, and can determine a second driving frequency for the second partial panel region PPR2 according to whether the second partial image data represents a still image. In an embodiment, when the first partial image data does not represent a still image (or when the first partial image data represents a moving image), the driving frequency decider 170 can determine the first driving frequency for the first partial panel region PPR1 as a normal driving frequency (e.g., about 60 Hz, about 100 Hz, about 120 Hz, etc.), and when the first partial image data represents a still image, can determine the first driving frequency for the first partial panel region PPR1 as a low frequency lower than the normal driving frequency. In such an embodiment, when the second partial image data does not represent a still image (or when the second partial image data represents a moving image), the driving frequency decider 170 can determine the second driving frequency for the second partial panel region PPR2 as the normal driving frequency, and when the second partial image data represents a still image, can determine the second driving frequency for the second partial panel region PPR2 as a low frequency lower than the normal driving frequency. In an embodiment, in the case where the second partial image data represents a still image, the driving frequency decider 170 can determine a flicker value (representing a level of flicker perceived by a user) according to a gray level (or brightness) of the second partial image data by using a flicker lookup table in which flicker values corresponding to respective gray levels are stored, and can determine the second driving frequency according to the flicker value. In such an embodiment, determining the flicker value can be performed pixel by pixel, segment by segment, or partial panel region by partial panel region.

[0069] In a case where the still image detector 160 and the driving frequency decider 170 determine all of the first driving frequency and the second driving frequency for the first partial panel region PPR1 and the second partial panel region PPR2 as the normal driving frequency, the panel driver 190 can drive the first partial panel region PPR1 and the second partial panel region PPR2 at the normal driving frequency. In an embodiment, for example, as shown in FIG. 2A, the panel driver 190 can drive the first partial panel region PPR1 and the second partial panel region PPR2 at the normal driving frequency. Figure 5 In each of the first frame period FP1 and the second frame period FP2 defined by the vertical synchronization signal VSYNC, the scan driver 130 can supply the scan signal SCAN (or the gate initialization signal GI, the gate write signal GW, and the gate compensation signal GC) to each of the pixels PX of the first partial panel region PPR1 and the second partial panel region PPR2, and the data driver 120 can supply the data voltage VDATA corresponding to the output image data ODAT as the voltage V_DL of the data line DL to each of the pixels PX of the first partial panel region PPR1 and the second partial panel region PPR2. Since the gate initialization signal GI, the gate write signal GW, and the gate compensation signal GC are supplied to each of the pixels PX in each of the first frame period FP1 and the second frame period FP2, the gate initialization signal GI, the gate write signal GW, and the gate compensation signal GC can be supplied to each of the pixels PX at the normal driving frequency.

[0070] In an embodiment, the gate initialization signal GI can be applied first to each of the pixels PX, and then the gate write signal GW and the gate compensation signal GC can be applied to each of the pixels PX together with the data voltage VDATA. While the gate write signal GW, the gate compensation signal GC, and the data voltage VDATA are applied to each of the pixels PX, the data write and bias operation for the pixel PX can be performed based on the data voltage VDATA as shown in FIG. 3A. Figure 10 Figure 10 Through the data write and bias operation as shown in FIG. 3A, the voltage VDATA-VTH generated by subtracting the threshold voltage VTH of the driving transistor T1 of the pixel PX from the data voltage VDATA can be stored in the storage capacitor CST of the pixel PX, and the first turn-on bias based on the data voltage VDATA can be applied to the driving transistor T1 of the pixel PX. In an embodiment, for example, as the first turn-on bias based on the data voltage VDATA, the data voltage VDATA can be applied to the source of the driving transistor T1, and the voltage VDATA-VTH generated by subtracting the threshold voltage VTH from the data voltage VDATA can be applied to the gate of the driving transistor T1. The driving transistor T1 can be turned on based on the first turn-on bias, and the hysteresis of the driving transistor T1 can be initialized based on the first turn-on bias.

[0071] ​In the case where the still image detector 160 and the driving frequency determiner 170 respectively determine the first driving frequency for the first partial panel area PPR1 and the second driving frequency for the second partial panel area PPR2 as the normal driving frequency and the low frequency lower than the normal driving frequency, the panel driver 190 may drive the first partial panel area PPR1 at the normal driving frequency and may drive the second partial panel area PPR2 at the low frequency. In one embodiment, for example, Figure 6 As shown in , when the normal driving frequency is approximately 60 Hz and the low frequency is approximately 30 Hz, the first partial panel area PPR1 can be driven in each of the first frame period FP1 and the second frame period FP2, and the second partial panel area PPR2 can be driven only in the first frame period FP1. Therefore, with respect to the first partial panel area PPR1, in each of the data write period DWP for the first partial panel area PPR1 in the first frame period FP1 and the data write period DWP for the first partial panel area PPR1 in the second frame period FP2, the scan driver 130 can provide the gate initialization signal GI, the gate write signal GW, and the gate compensation signal GC to each pixel PX in the first partial panel area PPR1, and the data driver 120 can provide the data voltage VDATA corresponding to the output image data ODAT as the voltage V_DL of the data line DL to each pixel PX in the first partial panel area PPR1. Therefore, in each of the first frame period FP1 and the second frame period FP2, data write and bias operations can be performed for each pixel PX in the first partial panel area PPR1 based on the data voltage VDATA. Since the gate initialization signal GI, the gate write signal GW and the gate compensation signal GC are provided to each pixel PX of the first partial panel area PPR1 in each of the first frame period FP1 and the second frame period FP2, the gate initialization signal GI, the gate write signal GW and the gate compensation signal GC can be provided to each pixel PX of the first partial panel area PPR1 at a normal driving frequency.

[0072] However, in order to drive the second partial panel area PPR2 at a low frequency, the period allocated to the second partial panel area PPR2 in the first frame period FP1 may be set as the data writing period DWP, and the period allocated to the second partial panel area PPR2 in the second frame period FP2 may be set as the holding period HP. Figure 6The embodiment in which the period allocated to the second partial panel area PPR2 within the second frame period FP2 among the two frame periods FP1 and FP2 is set as the hold period HP is shown, but the number of hold periods HP in the consecutive frame periods FP1 and FP2 can be determined according to the normal driving frequency and the low frequency. In one embodiment, for example, in the case where the normal driving frequency is about 100 Hz and the second driving frequency or the low frequency for the second partial panel area PPR2 is about 1 Hz, the period allocated to the second partial panel area PPR2 within one frame period among one hundred consecutive frame periods can be set as the data write period DWP, and the period allocated to the second partial panel area PPR2 within the remaining ninety-nine frame periods can be set as the hold period HP. Thus, the second partial panel area PPR2 can be driven at about 1 Hz.

[0073] In the embodiment shown in FIG. 1, the data write period DWP for the second partial panel area PPR2 in the first frame period FP1 can be set as a period in which the data voltage VDATA corresponding to the output image data ODAT is supplied to each pixel PX of the second partial panel area PPR2. Figure 6 In the embodiment shown in FIG. 1, the data write period DWP for the second partial panel area PPR2 in the first frame period FP1 can be set as a period in which the data voltage VDATA corresponding to the output image data ODAT is supplied to each pixel PX of the second partial panel area PPR2.

[0074] However, with respect to the second partial panel region PPR2, in the hold period HP for the second partial panel region PPR2 in the second frame period FP2, the scan driver 130 can not provide the gate initialization signal GI and the gate compensation signal GC to each pixel PX of the second partial panel region PPR2, the data driver 120 can not provide the data voltage VDATA to each pixel PX of the second partial panel region PPR2, and the data driver 120 can provide the blank voltage VBLANK as the voltage V_DL of the data line DL to each pixel PX of the second partial panel region PPR2. In an embodiment, in the hold period HP for the second partial panel region PPR2 in the second frame period FP2, the scan driver 130 can provide the gate write signal GW to each pixel PX of the second partial panel region PPR2. Since the gate write signal GW is provided to each pixel PX of the second partial panel region PPR2 in each of the first frame period FP1 and the second frame period FP2 and the gate initialization signal GI and the gate compensation signal GC are provided to each pixel PX of the second partial panel region PPR2 only in the first frame period FP1, the gate write signal GW can be provided to each pixel PX of the second partial panel region PPR2 at a normal driving frequency, and the gate initialization signal GI and the gate compensation signal GC can be provided to each pixel PX of the second partial panel region PPR2 at a low frequency.

[0075] In the hold period HP in which the gate initialization signal GI and the gate compensation signal GC are not provided to each pixel PX of the second partial panel region PPR2 and the gate write signal GW and the blank voltage VBLANK are provided to each pixel PX of the second partial panel region PPR2, a bias operation for the pixel PX can be performed based on the blank voltage VBLANK, as shown in Figure 11 Figure 11 Through the bias operation as shown in Figure 11 In one embodiment, for example, as the second turn-on bias based on the blank voltage VBLANK, the blank voltage VBLANK can be applied to the source of the drive transistor T1, and the voltage VSTORED stored in the storage capacitor CST can be applied to the gate of the drive transistor T1. The drive transistor T1 can be turned on based on the second turn-on bias, and the hysteresis of the drive transistor T1 can be initialized based on the second turn-on bias.

[0076] In the case where the blank voltage VBLANK has a voltage level of the data voltage VDATA corresponding to a black grayscale (e.g., a minimum grayscale level 0 or 0G) or a voltage level of the black data voltage VBLACK, the second turn-on bias based on the blank voltage VBLANK may be different from the first turn-on bias based on the data voltage VDATA, and the hysteresis of the driving transistor T1 of the pixel PX to which the second turn-on bias is applied may be different from the hysteresis of the driving transistor T1 of the pixel PX to which the first turn-on bias is applied. In one embodiment, for example, Figure 7 As shown in , when the first partial panel area PPR1 is driven at a first driving frequency that is a normal driving frequency of about 100 Hz and the second partial panel area PPR2 is driven at a second driving frequency that is a low frequency of about 1 Hz, even if the first partial panel area PPR1 and the second partial panel area PPR2 display images corresponding to the same grayscale level (for example, grayscale level 32), the brightness 210 of the first partial panel area PPR1 may be different from the brightness 230 of the second partial panel area PPR2. In such an embodiment, since each pixel PX of the first partial panel area PPR1 receives the first turn-on bias in each of the one hundred frame periods, but each pixel PX of the second partial panel area PPR2 receives the first turn-on bias in one frame period of the one hundred frame periods and receives the second turn-on bias in ninety-nine frame periods of the one hundred frame periods, the hysteresis of the driving transistor T1 of the pixel PX of the first partial panel area PPR1 may be different from the hysteresis of the driving transistor T1 of the pixel PX of the second partial panel area PPR2. In such an embodiment, as the driving time of the display device 100 increases, the hysteresis difference between the driving transistors T1 of the first partial panel area PPR1 and the second partial panel area PPR2 may increase, and the difference between the brightness 210 and the brightness 230 of the first partial panel area PPR1 and the second partial panel area PPR2 may increase.

[0077] In an embodiment of the display device 100 according to the present invention, as Figure 1 As shown in , the controller 150 of the panel driver 190 may further include a blank voltage determiner 180, and the blank voltage determiner 180 determines the voltage level of the blank voltage VBLANK for the second partial panel region PPR2. In an embodiment, the blank voltage determiner 180 may determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 to be the voltage level of the data voltage VDATA corresponding to a gray level higher than the black gray level (0G). In one embodiment, for example, Figure 6As shown in FIG. 2, the blank voltage determiner 180 can determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 as the voltage level of the data voltage VDATA corresponding to the 128 gray scale (128G). In such an embodiment, the difference between the first on-bias based on the data voltage VDATA and the second on-bias based on the blank voltage VBLANK can be reduced, and the hysteresis difference between the drive transistors Tl of the first partial panel region PPRl and the second partial panel region PPR2 can be reduced. Accordingly, as shown in FIG. 2, the luminance 230 of the second partial panel region PPR2 can be changed to be closer to the luminance 210 of the first partial panel region PPRl, and the difference between the luminance 210 of the first partial panel region PPRl and the luminance 230 of the second partial panel region PPR2 can be reduced. Figure 7 As shown in FIG. 2, the luminance 230 of the second partial panel region PPR2 can be changed to be closer to the luminance 210 of the first partial panel region PPRl, and the difference between the luminance 210 of the first partial panel region PPRl and the luminance 230 of the second partial panel region PPR2 can be reduced.

[0078] In alternative embodiments, the input image data IDAT for the display panel 110 can be divided into first partial image data for the first partial panel region PPRl and second partial image data for the second partial panel region PPR2, and the blank voltage determiner 180 can determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 by analyzing the second partial image data for the second partial panel region PPR2. In one embodiment, for example, the blank voltage determiner 180 can determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 based on the maximum gray scale or the average gray scale among the gray scales represented by the second partial image data. In another alternative embodiment, the blank voltage determiner 180 can determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 by analyzing the first partial image data for the first partial panel region PPRl. In one embodiment, for example, the blank voltage determiner 180 can determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 based on the maximum gray scale or the average gray scale among the gray scales represented by the first partial image data.

[0079] As described above, in the embodiment of the display device 100 according to the present application, the first driving frequency for the first partial panel region PPR1 of the display panel 110 and the second driving frequency for the second partial panel region PPR2 of the display panel 110 can be determined. In a case where the second driving frequency is lower than the first driving frequency, the data voltage VDATA can be supplied to the first partial panel region PPR1 and the second partial panel region PPR2 in the first frame period FP1. Further, in the second frame period FP2, the data voltage VDATA can be supplied to the first partial panel region PPR1, the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 can be determined, and the blank voltage VBLANK can be supplied to the second partial panel region PPR2. Thus, in such an embodiment, the first partial panel region PPR1 and the second partial panel region PPR2 are driven at different driving frequencies from each other, so that the power consumption of the display device 100 can be reduced. In such an embodiment, the bias operation for the pixels PX in the second partial panel region PPR2 can be performed not based on the black data voltage VBLACK but based on the blank voltage VBLANK, and thus the difference in brightness between the first partial panel region PPR1 and the second partial panel region PPR2 when driven at different driving frequencies from each other can be reduced.

[0080] Figure 8 is a flowchart showing a method of operating the display device 100 according to the embodiment, Figure 9 is a timing chart for describing an embodiment of the operation of the display device 100 in which the first partial panel region PPR1 is driven at a normal driving frequency and the second partial panel region PPR2 is driven at a low frequency, Figure 10 is a graph for describing an embodiment of the data write and the bias operation of the pixel PX@DWP in the data write period DWP, and Figure 11 is a graph for describing an embodiment of the bias operation of the pixel PX@HP in the hold period HP.

[0081] Referring to Figure 1 and Figure 8In an embodiment of the method of operating the display apparatus 100, the panel driver 190 can determine a first driving frequency for the first partial panel region PPR1 of the display panel 110 and a second driving frequency for the second partial panel region PPR2 of the display panel 110 (S310). In an embodiment, for example, in a case where a moving image is displayed in the first partial panel region PPR1 and a still image is displayed in the second partial panel region PPR2, the panel driver 190 can determine the first driving frequency for the first partial panel region PPR1 as a normal driving frequency (e.g., about 60 Hz, about 100 Hz, about 120 Hz, etc.) and can determine the second driving frequency for the second partial panel region PPR2 as a low frequency lower than the normal driving frequency.

[0082] In a case where the second driving frequency is lower than the first driving frequency, for example, in a case where the first driving frequency for the first partial panel region PPR1 is determined as a normal driving frequency and the second driving frequency for the second partial panel region PPR2 is determined as a low frequency, the panel driver 190 can provide the data voltage VDATA to the first partial panel region PPR1 and the second partial panel region PPR2 in the first frame period FP1 (S330). In an embodiment, for example, as shown in FIG. 3B, in a data write period DWP for the first partial panel region PPR1 within the first frame period FP1, the scan driver 130 can sequentially provide a plurality of gate initialization signals GI[1], GI[2], …, a plurality of gate write signals GW[1], GW[2], …, and a plurality of gate compensation signals GC[1], GC[2], … to the pixels PX of the first partial panel region PPR1 row by row, and the data driver 120 can provide the data voltage VDATA corresponding to the output image data ODAT to the pixels PX of the first partial panel region PPR1. In such an embodiment, in a data write period DWP for the second partial panel region PPR2 within the first frame period FP1, the scan driver 130 can sequentially provide a plurality of gate initialization signals GI[k+1], GI[k+2], …, a plurality of gate write signals GW[k+1], GW[k+2], …, and a plurality of gate compensation signals GC[k+1], GC[k+2], … to the pixels PX of the second partial panel region PPR2 row by row, and the data driver 120 can provide the data voltage VDATA corresponding to the output image data ODAT to the pixels PX of the second partial panel region PPR2. Figure 9

[0083] In an embodiment, as shown in FIG. 4B, in a data write period DWP for the first partial panel region PPR1 within the first frame period FP1, the scan driver 130 can sequentially provide a plurality of gate initialization signals GI[1], GI[2], …, a plurality of gate write signals GW[1], GW[2], …, and a plurality of gate compensation signals GC[1], GC[2], … to the pixels PX of the first partial panel region PPR1 row by row, and the data driver 120 can provide the data voltage VDATA corresponding to the output image data ODAT to the pixels PX of the first partial panel region PPR1. In such an embodiment, in a data write period DWP for the second partial panel region PPR2 within the first frame period FP1, the scan driver 130 can sequentially provide a plurality of gate initialization signals GI[k+1], GI[k+2], …, a plurality of gate write signals GW[k+1], GW[k+2], …, and a plurality of gate compensation signals GC[k+1], GC[k+2], … to the pixels PX of the second partial panel region PPR2 row by row, and the data driver 120 can provide the data voltage VDATA corresponding to the output image data ODAT to the pixels PX of the second partial panel region PPR2.

[0083] In an embodiment, as shown in FIG. 4B, in a data write period DWP for the first partial panel region PPR1 within the first frame period FP1, the scan driver 130 can sequentially provide a plurality of gate initialization signals GI[1], GI[2], …, a plurality of gate write signals GW[1], GW[2], …, and a plurality of gate compensation signals GC[1], GC[2], … to the pixels PX of the first partial panel region PPR1 row by row, and the data driver 120 can provide the data voltage VDATA corresponding to the output image data ODAT to the pixels PX of the first partial panel region PPR1. In such an embodiment, in a data write period DWP for the second partial panel region PPR2 within the first frame period FP1, the scan driver 130 can sequentially provide a plurality of gate initialization signals GI[k+1], GI[k+2], …, a plurality of gate write signals GW[k+1], GW[k+2], …, and a plurality of gate compensation signals GC[k+1], GC[k+2], … to the pixels PX of the second partial panel region PPR2 row by row, and the data driver 120 can provide the data voltage VDATA corresponding to the output image data ODAT to the pixels PX of the second partial panel region PPR2. Figure 9As shown in FIG. 10, to the pixels PX in each row (e.g., the first row), a gate initialization signal (e.g., GI[1]) can be applied first, and then a gate write signal (e.g., GW[1]) and a gate compensation signal (e.g., GC[1]) can be applied substantially simultaneously. In such an embodiment, while the gate write signal (e.g., GW[1]) and the gate compensation signal (e.g., GC[1]) are applied, a data voltage VDATA can be applied to the pixels PX in the row (e.g., the first row). In an embodiment, as shown in FIG. 10, the data voltage VDATA can be applied to the pixels PX in the row (e.g., the first row) while the gate write signal (e.g., GW[1]) and the gate compensation signal (e.g., GC[1]) are applied. In such an embodiment, the data voltage VDATA can be applied to the pixels PX in the row (e.g., the first row) while the gate write signal (e.g., GW[1]) and the gate compensation signal (e.g., GC[1]) are applied. Figure 10 As shown in FIG. 10, to the pixels PX in each row (e.g., the first row), a gate initialization signal (e.g., GI[1]) can be applied first, and then a gate write signal (e.g., GW[1]) and a gate compensation signal (e.g., GC[1]) can be applied substantially simultaneously. In such an embodiment, while the gate write signal (e.g., GW[1]) and the gate compensation signal (e.g., GC[1]) are applied, a data voltage VDATA can be applied to the pixels PX in the row (e.g., the first row). In an embodiment, as shown in FIG. 10, the data voltage VDATA can be applied to the pixels PX in the row (e.g., the first row) while the gate write signal (e.g., GW[1]) and the gate compensation signal (e.g., GC[1]) are applied. In such an embodiment, the data voltage VDATA can be applied to the pixels PX in the row (e.g., the first row) while the gate write signal (e.g., GW[1]) and the gate compensation signal (e.g., GC[1]) are applied.

[0084] The panel driver 190 can provide the data voltage VDATA to the first partial panel region PPR1 in the second frame period FP2 (S350). In one embodiment, for example, as shown in FIG. 10, the panel driver 190 can provide the data voltage VDATA to the first partial panel region PPR1 in the second frame period FP2 (S350). Figure 9As shown in FIG. 3, in the data write period DWP for the first partial panel region PPR1 within the second frame period FP2, the scan driver 130 can sequentially provide the plurality of gate initialization signals GI[1], GI[2], …, the plurality of gate write signals GW[1], GW[2], …, and the plurality of gate compensation signals GC[1], GC[2], … to the pixels PX of the first partial panel region PPR1 row by row, and the data driver 120 can provide the data voltage VDATA corresponding to the output image data ODAT to the pixels PX of the first partial panel region PPR1. Accordingly, as shown in FIG. 3, in the data write period DWP for the first partial panel region PPR1 within the second frame period FP2, the pixels PX@DWP of the first partial panel region PPR1 can perform data writing and biasing operations based on the data voltage VDATA. Figure 10 As shown in FIG. 3, in the data write period DWP for the first partial panel region PPR1 within the second frame period FP2, the pixels PX@DWP of the first partial panel region PPR1 can perform data writing and biasing operations based on the data voltage VDATA.

[0085] The panel driver 190 can determine a voltage level of the blank voltage VBLANK for the second partial panel region PPR2 (S370). In an embodiment, the panel driver 190 can determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 as a voltage level of the data voltage VDATA corresponding to a gray level higher than a black gray level. In one embodiment, for example, the panel driver 190 can determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 as a voltage level of the data voltage VDATA corresponding to a 128 gray level (128G).

[0086] The panel driver 190 can provide the blank voltage VBLANK to the second partial panel region PPR2 in the second frame period FP2 (S390). In one embodiment, for example, as shown in FIG. 3, the panel driver 190 can provide the blank voltage VBLANK to the second partial panel region PPR2 in the data write period DWP for the second partial panel region PPR2 within the second frame period FP2. Figure 9 As shown in FIG. 3, in the hold period HP for the second partial panel region PPR2 within the second frame period FP2, the scan driver 130 can not provide the plurality of gate initialization signals GI[k+1], GI[k+2], … and the plurality of gate compensation signals GC[k+1], GC[k+2], … to the pixels PX of the second partial panel region PPR2, the scan driver 130 can sequentially provide only the plurality of gate write signals GW[k+1], GW[k+2], … to the pixels PX of the second partial panel region PPR2 row by row, and the data driver 120 can provide the blank voltage VBLANK to the pixels PX of the second partial panel region PPR2.

[0087] In the hold period HP for the second partial panel region PPR2 within the second frame period FP2, if the plurality of gate write signals GW[k+1], GW[k+2], … and the blank voltage VBLANK are applied to the pixels PX of the second partial panel region PPR2, as shown in FIG. 3, the pixels PX of the second partial panel region PPR2 can perform a hold operation based on the blank voltage VBLANK. Figure 11As illustrated in FIG. 1, the pixel PX@HP of the second partial panel region PPR2 can perform a bias operation based on the blank voltage VBLANK. That is, when the switching transistor T2 is turned on in response to the gate write signal GW[n], the blank voltage VBLANK can be applied to the source of the driving transistor T1, and the voltage VSTORED (e.g., the voltage VDATA-VTH stored in the storage capacitor CST in the first frame period FP1) stored in the storage capacitor CST can be applied to the gate of the driving transistor T1. Accordingly, the second turn-on bias based on the blank voltage VBLANK can be applied to the driving transistor T1. Accordingly, the driving transistor T1 of each pixel PX@HP of the second partial panel region PPR2 can be turned on based on the second turn-on bias, and the hysteresis of the driving transistor T1 can be initialized based on the second turn-on bias. Since the blank voltage VBLANK has a voltage level of the data voltage VDATA corresponding to a gray level (e.g., 128G) higher than a black gray level (e.g., 0G), a difference between the first turn-on bias based on the data voltage VDATA and the second turn-on bias based on the blank voltage VBLANK can be reduced, and a hysteresis difference between the driving transistors T1 of the first partial panel region PPR1 and the second partial panel region PPR2 can be reduced. Thereafter, when the gate write signal GW[n+1] for the next pixel row is applied, the second initialization transistor T7 can be turned on, and the organic light emitting diode EL can be initialized based on the second initialization voltage VINT2.

[0088] Figure 12 FIG. 10 is a flowchart illustrating a method of operating the display apparatus 100 according to an alternative embodiment. Figure 13 FIG. 11 is a diagram illustrating an embodiment of a histogram 500 of the second partial image data for the second partial panel region PPR2.

[0089] Figure 12 The method of FIG. 10 can be substantially the same as the method of Figure 8 The method of FIG. 10 can be substantially the same as the method of Figure 12 In the method of FIG. 10, a voltage level of the blank voltage for the second partial panel region PPR2 can be determined by analyzing the second partial image data for the second partial panel region PPR2.

[0090] Referring to Figure 1 and Figure 12 In an embodiment of the method of operating the display apparatus 100, the panel driver 190 can determine a first driving frequency for the first partial panel region PPR1 of the display panel 110 and a second driving frequency for the second partial panel region PPR2 of the display panel 110 (S410).

[0091] In case that the second driving frequency is lower than the first driving frequency, the panel driver 190 can provide the data voltage VDATA to the first partial panel area PPR1 and the second partial panel area PPR2 in the first frame period (S430). Accordingly, in the first frame period, data writing and bias operations to the pixels PX of the first partial panel area PPR1 and the second partial panel area PPR2 can be performed based on the data voltage VDATA, and a first turn-on bias based on the data voltage VDATA can be applied to the driving transistor of the pixels PX.

[0092] The panel driver 190 can provide the data voltage VDATA to the first partial panel area PPR1 in the second frame period (S450). Accordingly, in the second frame period, data writing and bias operations to the pixels PX of the first partial panel area PPR1 can be performed based on the data voltage VDATA, and a first turn-on bias based on the data voltage VDATA can be applied to the driving transistor of the pixels PX of the first partial panel area PPR1.

[0093] The panel driver 190 can divide input image data IDAT for the display panel 110 into first partial image data for the first partial panel area PPR1 and second partial image data for the second partial panel area PPR2, can analyze the second partial image data for the second partial panel area PPR2 (S460), and can determine a voltage level of the blank voltage VBLANK for the second partial panel area PPR2 based on the analysis result (S470). In one embodiment, for example, as shown in FIG. 5B, the panel driver 190 can generate a histogram 500 of the second partial image data by counting the number of each gray scale 0G, …, 50G, …, 100G, …, 150G, …, 200G, …, and 255G, … represented by the second partial image data, and can determine the voltage level of the blank voltage VBLANK by using the histogram 500 of the second partial image data. Figure 13

[0094] In some embodiments, the panel driver 190 can determine a maximum gray scale MGV among the gray scales represented by the second partial image data by using the histogram 500 of the second partial image data, and can determine the voltage level of the blank voltage VBLANK for the second partial panel area PPR2 as the voltage level of the data voltage VDATA corresponding to the maximum gray scale MGV. In an embodiment of FIG. 5B, the panel driver 190 can determine the voltage level of the blank voltage VBLANK for the second partial panel area PPR2 as the voltage level of the data voltage VDATA corresponding to the 150 gray scale 150G. Figure 13

[0095] ​​In an alternative embodiment, the panel driver 190 can determine a maximum gray level MGV among the gray levels represented by the second partial image data by using the histogram 500 of the second partial image data, and can determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 as the voltage level of the data voltage VDATA corresponding to a gray level higher than the black gray level 0G and lower than the maximum gray level MGV. In one embodiment, for example, the panel driver 190 can determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 as the voltage level of the data voltage VDATA corresponding to the 75 gray level which is an intermediate value between the 0 gray level 0G and the 150 gray level 150G.

[0096] In another alternative embodiment, the panel driver 190 can determine an average gray level of the gray levels represented by the second partial image data by using the histogram 500 of the second partial image data, and can determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 as the voltage level of the data voltage VDATA corresponding to the average gray level.

[0097] The panel driver 190 can provide the blank voltage VBLANK to the second partial panel region PPR2 in the second frame period (S490). Accordingly, in the second frame period, the bias operation of the pixels PX of the second partial panel region PPR2 can be performed based on the blank voltage VBLANK, and the second on-bias based on the blank voltage VBLANK can be applied to the driving transistor of the pixels PX of the second partial panel region PPR2. Since the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 is determined by analyzing the second partial image data for the second partial panel region PPR2, the difference between the first on-bias based on the data voltage VDATA and the second on-bias based on the blank voltage VBLANK can be reduced, and the hysteresis difference between the driving transistors of the first partial panel region PPR1 and the second partial panel region PPR2 can be reduced.

[0098] Figure 14 FIG. 10 is a flowchart illustrating a method of operating the display apparatus 100 according to another alternative embodiment.

[0099] Figure 14 The method of FIG. 10 can be substantially the same as the method of Figure 8 The method of FIG. 10 can be substantially the same as the method of Figure 14 In the method of FIG. 10, the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 can be determined by analyzing the first partial image data for the first partial panel region PPR1.

[0100] Referring to Figure 1 and Figure 14In an embodiment of the method of operating the display apparatus 100, the panel driver 190 can determine a first driving frequency for the first partial panel area PPR1 of the display panel 110 and a second driving frequency for the second partial panel area PPR2 of the display panel 110 (S610).

[0101] In case that the second driving frequency is lower than the first driving frequency, the panel driver 190 can provide the data voltage VDATA to the first partial panel area PPR1 and the second partial panel area PPR2 in the first frame period (S630). Accordingly, in the first frame period, data writing and bias operations to the pixels PX of the first partial panel area PPR1 and the second partial panel area PPR2 can be performed based on the data voltage VDATA, and a first turn-on bias based on the data voltage VDATA can be applied to the driving transistor of the pixels PX.

[0102] The panel driver 190 can provide the data voltage VDATA to the first partial panel area PPR1 in the second frame period (S650). Accordingly, in the second frame period, data writing and bias operations to the pixels PX of the first partial panel area PPR1 can be performed based on the data voltage VDATA, and a first turn-on bias based on the data voltage VDATA can be applied to the driving transistor of the pixels PX of the first partial panel area PPR1.

[0103] The panel driver 190 can divide the input image data IDAT for the display panel 110 into first partial image data for the first partial panel area PPR1 and second partial image data for the second partial panel area PPR2, can analyze the first partial image data for the first partial panel area PPR1 (S660), and can determine a voltage level of the blank voltage VBLANK for the second partial panel area PPR2 based on the analysis result (S670). In an embodiment, for example, the panel driver 190 can generate a histogram of the first partial image data, and can determine the voltage level of the blank voltage VBLANK for the second partial panel area PPR2 by using the histogram of the first partial image data. In an embodiment, the panel driver 190 can determine the voltage level of the blank voltage VBLANK for the second partial panel area PPR2 based on a maximum gray level or an average gray level among the gray levels represented by the first partial image data.

[0104] The panel driver 190 can provide the blank voltage VBLANK to the second partial panel area PPR2 in the second frame period (S690). Accordingly, in the second frame period, a bias operation of the pixels PX of the second partial panel area PPR2 can be performed based on the blank voltage VBLANK, and a second on-bias based on the blank voltage VBLANK can be applied to the driving transistor of the pixels PX of the second partial panel area PPR2. Since the voltage level of the blank voltage VBLANK for the second partial panel area PPR2 is determined by analyzing the first partial image data for the first partial panel area PPR1, a difference between the first on-bias based on the data voltage VDATA and the second on-bias based on the blank voltage VBLANK can be reduced, and a hysteresis difference between the driving transistors of the first partial panel area PPR1 and the second partial panel area PPR2 can be reduced.

[0105] Figure 15 FIG. 1 is a block diagram illustrating an electronic device 1100 including a display device 1160 according to an embodiment.

[0106] Referring to FIG. 1, Figure 15 Embodiments of the electronic device 1100 can include a processor 1110, a storage 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 can further include a plurality of ports for communication with a graphics card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0107] The processor 1110 can perform various computing functions or tasks. The processor 1110 can be an application processor (AP), a microprocessor, or a central processing unit (CPU), and the like. The processor 1110 can be coupled to other components via an address bus, a control bus, a data bus, and the like. In an embodiment, the processor 1110 can be further coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0108] The storage 1120 can store data for the operation of the electronic device 1100. In one embodiment, for example, the storage 1120 can include a nonvolatile storage such as an Erasable Programmable Read-Only Memory (EPROM) device, an Electrically Erasable Programmable Read-Only Memory (EEPROM) device, a flash memory device, a Phase Change Random Access Memory (PRAM) device, a Resistance Random Access Memory (RRAM) device, a Nano Floating Gate Memory (NFGM) device, a Polymer Random Access Memory (PoRAM) device, a Magnetic Random Access Memory (MRAM) device, a Ferroelectric Random Access Memory (FRAM) device, and / or the like, and / or a volatile storage such as a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a Mobile DRAM device, and / or the like.

[0109] The storage 1130 can be a Solid State Drive (SSD) device, a Hard Disk Drive (HDD) device, a CD-ROM device, and / or the like. The I / O device 1140 can be an input device such as a keyboard, a keypad, a mouse, a touch screen, and / or the like, and an output device such as a printer, a speaker, and / or the like. The power supply 1150 can supply power for the operation of the electronic device 1100. The display device 1160 can be coupled to the other components through a bus or other communication link.

[0110] In an embodiment of the display apparatus 1160, a first driving frequency for a first partial panel area of the display panel and a second driving frequency for a second partial panel area of the display panel can be determined. In a case in which the second driving frequency is lower than the first driving frequency, data voltages can be provided to the first partial panel area and the second partial panel area in a first frame period. In such an embodiment, in a second frame period, the data voltages can be provided to the first partial panel area, a voltage level of a blank voltage for the second partial panel area can be determined, and the blank voltage can be provided to the second partial panel area. Accordingly, since the first partial panel area and the second partial panel area are driven at different driving frequencies, power consumption of the display apparatus can be reduced. In such an embodiment, a bias operation can be performed on pixels in the second partial panel area based on the blank voltage rather than the black data voltage, and thus a difference in brightness between the first partial panel area and the second partial panel area driven at different driving frequencies can be reduced.

[0111] Embodiments of the present application can be applied to any display apparatus 1160 and any electronic apparatus 1100 including the display apparatus 1160. In one embodiment, for example, the present application can be applied to a mobile phone, a smart phone, a wearable electronic apparatus, a tablet, a television (TV), a digital TV, a three-dimensional (3D) TV, a personal computer (PC), a home appliance, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game machine, a navigation apparatus, etc.

[0112] The present application should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the concept of the present application to those skilled in the art.

[0113] While the present application has been particularly shown and described with reference to embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit or scope of the present application as defined by the following claims.

Claims

1. A display device, comprising: The display panel comprises a first panel area and a second panel area; as well as A panel driver drives the display panel, wherein the panel driver determines a first driving frequency for the first partial panel area and a second driving frequency for the second partial panel area, Wherein, when the second driving frequency is lower than the first driving frequency, the panel driver provides a data voltage to the first and second partial panel areas in a first frame period, provides the data voltage to the first partial panel area in a second frame period, determines a voltage level of a blank voltage for the second partial panel area, and provides the blank voltage to the second partial panel area in the second frame period, In the first frame period, data writing and biasing operations are performed on pixels in the first partial panel area and the second partial panel area based on the data voltage. wherein, in the second frame period, the data writing and biasing operations are performed on the pixels of the first partial panel area based on the data voltage, and the biasing operation is performed on the pixels of the second partial panel area based on the blank voltage, and In which, the panel driver divides the input image data for the display panel into first partial image data for the first partial panel area and second partial image data for the second partial panel area, and determines the voltage level of the blank voltage for the second partial panel area by analyzing the first partial image data for the first partial panel area.

2. The display device according to claim 1, in, In the first frame period, through the data writing and biasing operations, a voltage generated by subtracting the threshold voltage of the driving transistors of the pixels of the first partial panel area and the second partial panel area from the data voltage is stored in the storage capacitors of the pixels of the first partial panel area and the second partial panel area, and a first on-bias based on the data voltage is applied to the driving transistors of the pixels of the first partial panel area and the second partial panel area. wherein, in the second frame period, through the data writing and biasing operations, the voltage generated by subtracting the threshold voltage of the driving transistor of the pixel of the first partial panel area from the data voltage is stored in the storage capacitor of the pixel of the first partial panel area, and the first turn-on bias based on the data voltage is applied to the driving transistor of the pixel of the first partial panel area, and In the second frame period, a second conduction bias based on the blank voltage is applied to the driving transistor of the pixel in the second partial panel area through the bias operation.

3. The display device according to claim 1, wherein The panel driver determines the voltage level of the blank voltage for the second partial panel area to be a voltage level of the data voltage corresponding to a gray level higher than a black gray level.

4. The display device according to claim 1, wherein The voltage level of the blank voltage for the second partial panel area is determined by analyzing the second partial image data for the second partial panel area.

5. The display device according to claim 4, wherein The panel driver determines a maximum gray level among gray levels represented by the second partial image data for the second partial panel area, and determines the voltage level of the blank voltage for the second partial panel area to be a voltage level of the data voltage corresponding to the maximum gray level. The display device according to claim 4 , wherein: The panel driver determines a maximum gray level among gray levels represented by the second portion of the image data for the second portion of the panel area, and determines the voltage level of the blank voltage for the second portion of the panel area to be a voltage level of the data voltage corresponding to a gray level higher than a black gray level and lower than the maximum gray level.

7. The display device according to claim 4, wherein The panel driver determines an average grayscale of grayscales represented by the second partial image data for the second partial panel area, and determines the voltage level of the blank voltage for the second partial panel area to be a voltage level of the data voltage corresponding to the average grayscale.

8. A method for operating a display device, the method comprising: determining a first driving frequency for a first partial panel area of ​​a display panel and a second driving frequency for a second partial panel area of ​​the display panel; providing data voltages to the first and second partial panel areas in a first frame period when the second driving frequency is lower than the first driving frequency; providing the data voltage to the first partial panel area in a second frame period when the second driving frequency is lower than the first driving frequency; determining a voltage level of a blank voltage for the second partial panel area when the second driving frequency is lower than the first driving frequency; providing the blank voltage to the second partial panel area in the second frame period when the second driving frequency is lower than the first driving frequency; During the first frame period, performing data writing and biasing operations on pixels in the first partial panel area and the second partial panel area based on the data voltage; In the second frame period, performing the data writing and biasing operations on the pixels of the first partial panel area based on the data voltage, and performing the biasing operation on the pixels of the second partial panel area based on the blank voltage; dividing input image data for the display panel into first partial image data for the first partial panel area and second partial image data for the second partial panel area; and The voltage level of the blank voltage for the second partial panel area is determined by analyzing the first partial image data for the first partial panel area.

Images