Link delay adjustment method and storage device

Abstract

The present invention discloses a link delay adjustment method and storage device. After the preset delay adjustment condition is met, the delay value is set for the target link based on the delay setting range of the target link connected to the flash memory particle on the PHY; wherein the target link includes an input link and an output link; the validity of the delay value is determined according to the delay validity determination strategy corresponding to the target link to obtain the validity of all delay values ​​within the delay setting range; the delay effective range of the target link is determined according to the validity of all delay values, so as to adjust the delay value of the target link based on the delay effective range. It can be seen that the present application can automatically determine the delay effective range of the link between the PHY and the flash memory particle under the current situation after the delay adjustment condition is met, so as to adjust the delay value of the link based on the delay effective range, thereby ensuring the correctness of the read and write data; moreover, the present application adjusts the delay values ​​of the input link and the output link separately, and the adjustment effect is better.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a link delay adjustment method and a storage device. Background Art

[0002] NAND Flash (non-volatile flash memory) storage devices include NAND Flash particles for storing data and a flash memory controller for managing the data stored in the NAND Flash particles; wherein the NAND PHY (Port Physical Layer) in the flash memory controller is connected to the NAND Flash particles through IO (Input / Output) to manage the data stored in the NAND Flash particles.

[0003] At present, the connection relationship between NAND PHY and NAND Flash particles is as follows Figure 1 As shown, the connection link between the two includes: DQS (Bi-directional Data Strobe, bidirectional data control pin) link, DQ (Data I / O channel) link and DBI (Data Bus Inversion, data bus inversion) link; wherein, the DQ link is used to read and write NAND Flash particles, and the data signal transmitted on it is called the DQ signal; the DBI signal transmitted on the DBI link is used to indicate whether the current DQ signal needs to be flipped; the DQS signal transmitted on the DQS link is used as a reference signal for collecting DQ signals and DBI signals to determine when to collect DQ signals and DBI signals.

[0004] In order to ensure the correctness of data transmission between NAND PHY and NAND Flash particles, it is necessary to ensure that the phase relationship between the DQS signal, DQ signal and DBI signal is within a correct range. The phase relationship between the DQS signal, DQ signal and DBI signal is achieved through the delay value on each link (the link delay value setting inside the NAND PHY + IO delay). At present, before the storage device works, the link delay value inside the NAND PHY is usually fixed to ensure that the phase relationship between the DQS signal, DQ signal and DBI signal is within a correct range. However, if the working environment of the storage device (such as working temperature, working frequency, etc.) changes, the delay on the link will also change, resulting in a change in the phase relationship between the DQS signal, DQ signal and DBI signal, which may cause the phase relationship of the three to be not within a correct range, thereby reducing the correctness of reading and writing data.

[0005] Therefore, how to provide a solution to the above technical problems is a problem that technicians in this field need to solve at present. Summary of the invention

[0006] The purpose of the present invention is to provide a link delay adjustment method and storage device, which can automatically determine the effective delay range of the link between PHY and flash memory particles under the current situation (that is, the delay setting range that ensures the correctness of read and write data) after the delay adjustment conditions (such as excessive changes in operating temperature and / or operating frequency) are met, so as to adjust the delay value of the link based on the effective delay range, thereby ensuring the correctness of read and write data; moreover, the present application separately adjusts the delay values ​​of the input link and the output link connecting the PHY and the flash memory particles, and the adjustment effect is better.

[0007] In order to solve the above technical problems, the present invention provides a link delay adjustment method, which is applied to a flash memory controller including a PHY, comprising:

[0008] After the preset delay adjustment condition is met, based on the delay setting range of the target link connected to the flash memory particle on the PHY, a delay value is set for the target link; wherein the target link includes an input link and an output link;

[0009] Determine the validity of the delay value according to the delay validity determination strategy corresponding to the target link to obtain the validity of all delay values ​​within the delay setting range;

[0010] A delay validity range of the target link is determined according to the validity of all the delay values, so as to adjust the delay value of the target link based on the delay validity range.

[0011] Optionally, the target link includes a DQS signal input link, a DQ signal input link and a DBI signal input link; wherein the DBI function of the flash memory particle is in an on state;

[0012] Then determining the validity of the delay value according to the delay validity determination strategy corresponding to the target link includes:

[0013] Sending a read parameter page command to the flash memory particle, and receiving a first DQ signal value and a first DBI signal value returned by the flash memory particle;

[0014] Determine a first DQ actual value returned by the flash memory particle according to the first DQ signal value and the first DBI signal value;

[0015] If the first DQ actual value is consistent with the DQ standard value corresponding to the read parameter page command, it is determined that the delay values ​​currently set for the DQS signal input link, the DQ signal input link, and the DBI signal input link are valid values.

[0016] Optionally, the target link includes a DQS signal output link, a DQ signal output link and a DBI signal output link; wherein the DBI function of the flash memory particle is in an on state;

[0017] Then determining the validity of the delay value according to the delay validity determination strategy corresponding to the target link includes:

[0018] Writing preset standard data into the flash memory particles;

[0019] Sending a command to read the preset standard data to the flash memory particle, and receiving a second DQ signal value and a second DBI signal value returned by the flash memory particle;

[0020] Determine a second DQ actual value returned by the flash memory particle according to the second DQ signal value and the second DBI signal value;

[0021] If the second DQ actual value is consistent with the preset standard data, it is determined that the delay values ​​currently set for the DQS signal output link, the DQ signal output link, and the DBI signal output link are valid values.

[0022] Optionally, the target link includes a DQS signal input link and a DQ signal input link; wherein the DBI function of the flash memory particle is in a closed state;

[0023] Then determining the validity of the delay value according to the delay validity determination strategy corresponding to the target link includes:

[0024] Sending a read parameter page command to the flash memory particle, and receiving a third DQ signal value returned by the flash memory particle;

[0025] If the third DQ signal value is consistent with the DQ standard value corresponding to the read parameter page command, it is determined that the delay values ​​currently set for the DQS signal input link and the DQ signal input link are valid values.

[0026] Optionally, the target link further includes a DBI signal input link; wherein, after the delay values ​​of the DQS signal input link and the DQ signal input link are adjusted, the DBI function of the flash memory particle is turned on to execute a delay setting range based on the DBI signal input link and set a delay value for the DBI signal input link;

[0027] Then determining the validity of the delay value according to the delay validity determination strategy corresponding to the target link, further comprising:

[0028] Sending a read parameter page command to the flash memory particle, and receiving a fourth DQ signal value returned by the flash memory particle;

[0029] Determine the fourth DQ actual value returned by the flash memory particle according to the fourth DQ signal value and its corresponding flip strategy;

[0030] If the fourth DQ actual value is consistent with the DQ standard value corresponding to the read parameter page command, it is determined that the delay value currently set for the DBI signal input link is a valid value.

[0031] Optionally, the target link includes a DQS signal output link and a DQ signal output link; wherein the DBI function of the flash memory particle is in a closed state;

[0032] Then determining the validity of the delay value according to the delay validity determination strategy corresponding to the target link includes:

[0033] Writing preset standard data into the flash memory particles;

[0034] Sending a command to read the preset standard data to the flash memory particle, and receiving a fifth DQ signal value returned by the flash memory particle;

[0035] If the fifth DQ signal value is consistent with the preset standard data, it is determined that the delay values ​​currently set for the DQS signal output link and the DQ signal output link are valid values.

[0036] Optionally, the target link further includes a DBI signal output link; wherein, after the delay values ​​of the DQS signal output link and the DQ signal output link are adjusted, the DBI function of the flash memory particle is turned on to execute a delay setting range based on the DBI signal output link, and set a delay value for the DBI signal output link;

[0037] Then determining the validity of the delay value according to the delay validity determination strategy corresponding to the target link, further comprising:

[0038] Writing preset standard data into the flash memory particles;

[0039] Sending a command to read the preset standard data to the flash memory particle, and receiving a sixth DQ signal value returned by the flash memory particle;

[0040] Determine the sixth DQ actual value returned by the flash memory particle according to the sixth DQ signal value and its corresponding flipping strategy;

[0041] If the sixth DQ actual value is consistent with the preset standard data, it is determined that the delay value currently set for the DBI signal output link is a valid value.

[0042] Optionally, determining a delay validity range of the target link according to the validity of all the delay values, so as to adjust the delay value of the target link based on the delay validity range, includes:

[0043] Determine N continuous delay validity ranges corresponding to the target link according to the validity of all the delay values; wherein N is a positive integer;

[0044] A maximum effective delay range is selected from the N consecutive effective delay ranges, and the maximum effective delay range is used as a preferred effective delay range of the target link, so as to adjust the delay value of the target link based on the preferred effective delay range.

[0045] Optionally, setting a delay value for a target link connected to a flash memory particle on the PHY based on a delay setting range of the target link includes:

[0046] Based on the delay setting range of the input link connected to the flash memory particle on the PHY, setting a delay value for the input link;

[0047] After the delay values ​​of all the input links are adjusted, a delay value is set for the output link based on the delay setting range of the output link connected to the flash memory particle on the PHY to enter the delay value adjustment of the output link.

[0048] In order to solve the above technical problems, the present invention further provides a storage device, comprising:

[0049] Flash memory particles;

[0050] A flash memory controller including a PHY is used to implement the steps of any of the above-mentioned link delay adjustment methods when executing a computer program stored in the controller.

[0051] The present invention provides a link delay adjustment method, which is applied to a flash memory controller including PHY. After the preset delay adjustment condition is met, the delay value is set for the target link based on the delay setting range of the target link connected to the flash memory particle on the PHY; wherein the target link includes an input link and an output link; the validity of the delay value is determined according to the delay validity determination strategy corresponding to the target link to obtain the validity of all delay values ​​within the delay setting range; the delay effective range of the target link is determined according to the validity of all delay values, so as to adjust the delay value of the target link based on the delay effective range. It can be seen that the present application can automatically determine the delay effective range of the link between the PHY and the flash memory particle under the current situation (i.e., the delay setting range that ensures the correctness of the read and write data) after the delay adjustment condition (such as excessive changes in the operating temperature and / or operating frequency) is met, so as to adjust the delay value of the link based on the delay effective range, thereby ensuring the correctness of the read and write data; moreover, the present application adjusts the delay values ​​of the input link and the output link connected between the PHY and the flash memory particle separately, and the adjustment effect is better.

[0052] The present invention also provides a storage device, which has the same beneficial effects as the above delay adjustment method. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the prior art and the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 A schematic diagram of the connection relationship between a NAND PHY and a NAND Flash particle in the prior art;

[0055] Figure 2 A flowchart of a link delay adjustment method provided by an embodiment of the present invention;

[0056] Figure 3 A flowchart of a first input link delay adjustment method provided by an embodiment of the present invention;

[0057] Figure 4 A flowchart of a first output link delay adjustment method provided by an embodiment of the present invention;

[0058] Figure 5 A flow chart of a second DQS / DQ input link delay adjustment method provided by an embodiment of the present invention;

[0059] Figure 6 A flowchart of a second DBI input link delay adjustment method provided by an embodiment of the present invention;

[0060] Figure 7 A flowchart of a second DQS / DQ output link delay adjustment method provided by an embodiment of the present invention;

[0061] Figure 8 A flowchart of a second DBI output link delay adjustment method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0062] The core of the present invention is to provide a link delay adjustment method and storage device, which can automatically determine the effective delay range of the link between PHY and flash memory particles under the current situation (that is, the delay setting range that ensures the correctness of read and write data) after the delay adjustment conditions (such as excessive changes in operating temperature and / or operating frequency) are met, so as to adjust the delay value of the link based on the effective delay range, thereby ensuring the correctness of read and write data; moreover, the present application separately adjusts the delay values ​​of the input link and the output link connecting the PHY and the flash memory particles, and the adjustment effect is better.

[0063] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0064] Please refer to Figure 2 , Figure 2 A flowchart of a link delay adjustment method provided by an embodiment of the present invention.

[0065] The link delay adjustment method is applied to a flash memory controller including a PHY, and includes:

[0066] Step S1: after a preset delay adjustment condition is met, a delay value is set for a target link based on a delay setting range of a target link connected to a flash memory particle on a PHY.

[0067] It should be noted that the target link of the present application includes an input link and an output link, so as to separately adjust the delay values ​​of the input link and the output link connecting the PHY and the flash memory particles.

[0068] Specifically, considering that the operating temperature and operating frequency of the storage device composed of a flash memory controller and flash memory particles may change, resulting in changes in the delay on the link connecting the PHY and the flash memory particles, which may seriously affect the correctness of reading and writing data, the present application can set the delay adjustment condition in advance: taking the operating temperature and operating frequency of the storage device when the delay value of the link was adjusted last time as a reference, if the operating temperature change of the storage device is greater than the preset temperature threshold and / or the operating frequency change is greater than the preset frequency threshold, it is determined that the delay adjustment condition is currently met; otherwise, it is determined that the delay adjustment condition is not currently met.

[0069] Based on this, after the preset delay adjustment conditions are met, the present application sets a delay value for the target link based on the delay setting range of the target link connected to the flash memory particles on the PHY (the delay value set here affects the link delay inside the PHY), that is, the delay value set for the target link is selected from the delay setting range of the target link, so as to subsequently determine the delay setting range of the target link that can ensure the correctness of reading and writing data.

[0070] Step S2: Determine the validity of the delay value according to the delay validity determination strategy corresponding to the target link to obtain the validity of all delay values ​​within the delay setting range.

[0071] Specifically, the present application sets a corresponding delay validity determination strategy for the target link in advance, with the aim of determining whether the delay value set for the target link is valid. It can be understood that setting a valid delay value for the target link can ensure the correctness of data transmission between the PHY and the flash memory particles, so the ultimate purpose of setting a delay validity determination strategy is to determine a valid delay value for the target link.

[0072] Based on this, the present application determines the validity of the delay value currently set for the target link according to the delay validity determination strategy corresponding to the target link, and returns to execute the step of setting the delay value for the target link based on the delay setting range of the target link connected to the flash memory particles on the PHY, until the validity of all delay values ​​within the delay setting range of the target link is determined.

[0073] Step S3: determining a delay validity range of the target link according to the validity of all delay values, so as to adjust the delay value of the target link based on the delay validity range.

[0074] Specifically, the present application determines the delay effective range of the target link (i.e., the data range consisting of valid delay values ​​within the delay setting range of the target link) according to the validity of all delay values ​​within the delay setting range of the target link. The purpose is to adjust the delay value of the target link based on the delay effective range of the target link, that is, the target adjustment value of the delay value of the target link is selected from the delay effective range of the target link, which can ensure the correctness of reading and writing data.

[0075] It can be seen that the present application can automatically determine the effective delay range of the link between the PHY and the flash memory particles under the current circumstances (that is, the delay setting range that can ensure the correctness of the read and write data) after the delay adjustment conditions are met, so as to adjust the delay value of the link based on the effective delay range, thereby ensuring the correctness of the read and write data; moreover, the present application separately adjusts the delay values ​​of the input link and the output link connecting the PHY and the flash memory particles, and the adjustment effect is better.

[0076] Based on the above embodiments:

[0077] As an optional embodiment, the target link includes a DQS signal input link, a DQ signal input link, and a DBI signal input link; wherein the DBI function of the flash memory particle is in an open state;

[0078] The validity of the delay value is determined according to the delay validity determination strategy corresponding to the target link, including:

[0079] Sending a read parameter page command to the flash memory particle, and receiving a first DQ signal value and a first DBI signal value returned by the flash memory particle;

[0080] Determine a first DQ actual value returned by the flash memory particle according to the first DQ signal value and the first DBI signal value;

[0081] If the first DQ actual value is consistent with the DQ standard value corresponding to the read parameter page command, it is determined that the delay values ​​currently set for the DQS signal input link, the DQ signal input link, and the DBI signal input link are valid values.

[0082] Specifically, the target links of the present application include a DQS signal input link, a DQ signal input link and a DBI signal input link. When adjusting the delay value of the DQS / DQ / DBI signal input link, the DBI function of the flash memory particle needs to be in the turned-on state.

[0083] The process of adjusting the delay value of the DQS / DQ / DBI signal input link is as follows: 1) Setting the delay value for the DQS signal input link based on the delay setting range of the DQS signal input link, similarly setting the delay value for the DQ signal input link based on the delay setting range of the DQ signal input link, and setting the delay value for the DBI signal input link based on the delay setting range of the DBI signal input link, specifically by writing the corresponding value to the register used to set the delay value. 2) Sending a Read parameter page command to the flash memory particle, and receiving the first DQ signal value and the first DBI signal value returned by the flash memory particle under the Read parameter page command. 3) Determine the first DQ actual value returned by the flash memory particle according to the first DQ signal value and the first DBI signal value returned by the flash memory particle (for example, the first DBI signal value is "1" indicating that the first DQ signal value needs to be flipped, and the first DBI signal value is "0" indicating that the first DQ signal value does not need to be flipped. If the first DQ signal value is "00000111" and the first DBI signal value is "1", then the first DQ actual value is "11111000", which is the value actually read from the flash memory particle; if the first DQ signal value is "00000111" and the first DBI signal value is "0", then the first DQ actual value is still "00000111"). If the first DQ actual value returned by the flash memory particle is consistent with the DQ standard value corresponding to the read parameter page command, determine that the delay value currently set for the DQS signal input link, the DQ signal input link and the DBI signal input link is a valid value, and return to step 1) until the validity of all delay values ​​within the delay setting range of the DQS / DQ / DBI signal input link is determined. 4) According to the validity of all delay values ​​within the delay setting range of the DQS signal input link, determine the effective delay range of the DQS signal input link, so as to adjust the delay value of the DQS signal input link based on the effective delay range of the DQS signal input link; similarly, according to the validity of all delay values ​​within the delay setting range of the DQ signal input link, determine the effective delay range of the DQ signal input link, so as to adjust the delay value of the DQ signal input link based on the effective delay range of the DQ signal input link; according to the validity of all delay values ​​within the delay setting range of the DBI signal input link, determine the effective delay range of the DBI signal input link, so as to adjust the delay value of the DBI signal input link based on the effective delay range of the DBI signal input link.

[0084] As an optional embodiment, the target link includes a DQS signal output link, a DQ signal output link, and a DBI signal output link; wherein the DBI function of the flash memory particle is in an open state;

[0085] The validity of the delay value is determined according to the delay validity determination strategy corresponding to the target link, including:

[0086] Writing preset standard data into flash memory particles;

[0087] Sending a command to read preset standard data to the flash memory particle, and receiving a second DQ signal value and a second DBI signal value returned by the flash memory particle;

[0088] Determine the second DQ actual value returned by the flash memory particle according to the second DQ signal value and the second DBI signal value;

[0089] If the second DQ actual value is consistent with the preset standard data, it is determined that the delay values ​​currently set for the DQS signal output link, the DQ signal output link, and the DBI signal output link are valid values.

[0090] Specifically, the target links of the present application include a DQS signal output link, a DQ signal output link and a DBI signal output link. When adjusting the delay value of the DQS / DQ / DBI signal output link, the DBI function of the flash memory particle needs to be in the turned-on state.

[0091] The process of adjusting the delay value of the DQS / DQ / DBI signal output link is as follows: 1) Setting a delay value for the DQS signal output link based on the delay setting range of the DQS signal output link, and similarly setting a delay value for the DQ signal output link based on the delay setting range of the DQ signal output link, and setting a delay value for the DBI signal output link based on the delay setting range of the DBI signal output link, specifically by writing a corresponding value to a register for setting a delay value. 2) Writing the preset standard data into the flash memory particles. 3) Sending a command to read the preset standard data to the flash memory particles, and receiving a second DQ signal value and a second DBI signal value returned by the flash memory particles in response to the command to read the preset standard data. 4) Determine the second DQ actual value returned by the flash memory particle according to the second DQ signal value and the second DBI signal value returned by the flash memory particle. If the second DQ actual value returned by the flash memory particle is consistent with the preset standard data, determine that the delay value currently set for the DQS signal output link, the DQ signal output link and the DBI signal output link is a valid value, and return to step 1) until the validity of all delay values ​​within the delay setting range of the DQS / DQ / DBI signal output link is determined. 5) According to the validity of all delay values ​​within the delay setting range of the DQS signal output link, determine the effective delay range of the DQS signal output link, so as to adjust the delay value of the DQS signal output link based on the effective delay range of the DQS signal output link; similarly, according to the validity of all delay values ​​within the delay setting range of the DQ signal output link, determine the effective delay range of the DQ signal output link, so as to adjust the delay value of the DQ signal output link based on the effective delay range of the DQ signal output link; according to the validity of all delay values ​​within the delay setting range of the DBI signal output link, determine the effective delay range of the DBI signal output link, so as to adjust the delay value of the DBI signal output link based on the effective delay range of the DBI signal output link.

[0092] As an optional embodiment, the target link includes a DQS signal input link and a DQ signal input link; wherein the DBI function of the flash memory particle is in a closed state;

[0093] The validity of the delay value is determined according to the delay validity determination strategy corresponding to the target link, including:

[0094] Sending a read parameter page command to the flash memory particle, and receiving a third DQ signal value returned by the flash memory particle;

[0095] If the third DQ signal value is consistent with the DQ standard value corresponding to the read parameter page command, it is determined that the delay values ​​currently set for the DQS signal input link and the DQ signal input link are valid values.

[0096] Specifically, in addition to adjusting DQS / DQ and DBI together for the delay values ​​of the input link and the output link in the above embodiment, DQS / DQ and DBI may also be adjusted separately, specifically by first adjusting DQS and DQ and then adjusting DBI.

[0097] Based on this, the present application first adjusts the delay value only for the DQS / DQ signal input link. When adjusting the delay value for the DQS / DQ signal input link, the DBI function of the flash memory particles needs to be in a closed state.

[0098] The process of adjusting the delay value only for the DQS / DQ signal input link is as follows: 1) Set a delay value for the DQS signal input link based on the delay setting range of the DQS signal input link. Similarly, set a delay value for the DQ signal input link based on the delay setting range of the DQ signal input link. 2) Send a read parameter page command to the flash memory particle, and receive the third DQ signal value returned by the flash memory particle under the read parameter page command (the third DQ signal value is directly the value actually read from the flash memory particle). 3) If the third DQ signal value returned by the flash memory particle is consistent with the DQ standard value corresponding to the read parameter page command, determine that the delay value currently set for the DQS signal input link and the DQ signal input link is a valid value, and return to step 1) until the validity of all delay values ​​within the delay setting range of the DQS / DQ signal input link is determined. 4) According to the validity of all delay values ​​within the delay setting range of the DQS signal input link, determine the effective delay range of the DQS signal input link, so as to adjust the delay value of the DQS signal input link based on the effective delay range of the DQS signal input link. Similarly, according to the validity of all delay values ​​within the delay setting range of the DQ signal input link, determine the effective delay range of the DQ signal input link, so as to adjust the delay value of the DQ signal input link based on the effective delay range of the DQ signal input link.

[0099] As an optional embodiment, the target link also includes a DBI signal input link; wherein, after the delay values ​​of the DQS signal input link and the DQ signal input link are adjusted, the DBI function of the flash memory particle is turned on to execute the delay setting range based on the DBI signal input link, and set the delay value for the DBI signal input link;

[0100] Then, the validity of the delay value is determined according to the delay validity determination strategy corresponding to the target link, which also includes:

[0101] Sending a read parameter page command to the flash memory particle, and receiving a fourth DQ signal value returned by the flash memory particle;

[0102] Determine the fourth DQ actual value returned by the flash memory particle according to the fourth DQ signal value and its corresponding flip strategy;

[0103] If the fourth DQ actual value is consistent with the DQ standard value corresponding to the read parameter page command, it is determined that the delay value currently set for the DBI signal input link is a valid value.

[0104] Specifically, after adjusting the delay value of the DQS / DQ signal input link, the present application adjusts the delay value of the DBI signal input link. When adjusting the delay value of the DBI signal input link, the DBI function of the flash memory particles needs to be turned on, so after adjusting the delay values ​​of the DQS signal input link and the DQ signal input link, turn on the DBI function of the flash memory particles.

[0105] The process of adjusting the delay value of the DBI signal input link is as follows: 1) Setting the delay value for the DBI signal input link based on the delay setting range of the DBI signal input link (the delay values ​​of the DQS signal input link and the DQ signal input link have been adjusted at this stage and will not change). 2) Sending a read parameter page command to the flash memory particle, and receiving the fourth DQ signal value returned by the flash memory particle under the read parameter page command. 3) Determining the fourth DQ actual value returned by the flash memory particle according to the fourth DQ signal value returned by the flash memory particle and its corresponding flip strategy (this is the value actually read from the flash memory particle), if the fourth DQ actual value returned by the flash memory particle is consistent with the DQ standard value corresponding to the read parameter page command, then determining that the delay value currently set for the DBI signal input link is a valid value (principle: if the fourth DQ actual value is correct, it means that the fourth DQ signal value is correct, and the fourth DQ signal value is adjusted based on the DBI signal, which means that the DBI signal is not wrong, that is, the delay value currently set for the DBI signal input link is valid), and returning to step 1), until the validity of all delay values ​​within the delay setting range of the DBI signal input link is determined. 4) According to the validity of all delay values ​​within the delay setting range of the DBI signal input link, determine the delay effective range of the DBI signal input link, so as to adjust the delay value of the DBI signal input link based on the delay effective range of the DBI signal input link.

[0106] As an optional embodiment, the target link includes a DQS signal output link and a DQ signal output link; wherein the DBI function of the flash memory particle is in a closed state;

[0107] The validity of the delay value is determined according to the delay validity determination strategy corresponding to the target link, including:

[0108] Writing preset standard data into flash memory particles;

[0109] Sending a command to read preset standard data to the flash memory particle, and receiving a fifth DQ signal value returned by the flash memory particle;

[0110] If the fifth DQ signal value is consistent with the preset standard data, it is determined that the delay values ​​currently set for the DQS signal output link and the DQ signal output link are valid values.

[0111] Specifically, the present application firstly adjusts the delay value of the DQS / DQ signal output link only. When the delay value of the DQS / DQ signal output link is adjusted, the DBI function of the flash memory particles needs to be in a closed state.

[0112] The process of adjusting the delay value only for the DQS / DQ signal output link is as follows: 1) Set a delay value for the DQS signal output link based on the delay setting range of the DQS signal output link. Similarly, set a delay value for the DQ signal output link based on the delay setting range of the DQ signal output link. 2) Write the preset standard data into the flash memory particles. 3) Send a command to read the preset standard data to the flash memory particles, and receive the fifth DQ signal value returned by the flash memory particles under the command to read the preset standard data (the fifth DQ signal value is directly the value actually read from the flash memory particles). 4) If the fifth DQ signal value returned by the flash memory particles is consistent with the preset standard data, determine that the delay value currently set for the DQS signal output link and the DQ signal output link is a valid value, and return to step 1) until the validity of all delay values ​​within the delay setting range of the DQS / DQ signal output link is determined. 5) According to the validity of all delay values ​​within the delay setting range of the DQS signal output link, determine the effective delay range of the DQS signal output link, so as to adjust the delay value of the DQS signal output link based on the effective delay range of the DQS signal output link. Similarly, according to the validity of all delay values ​​within the delay setting range of the DQ signal output link, determine the effective delay range of the DQ signal output link, so as to adjust the delay value of the DQ signal output link based on the effective delay range of the DQ signal output link.

[0113] As an optional embodiment, the target link also includes a DBI signal output link; wherein, after the delay values ​​of the DQS signal output link and the DQ signal output link are adjusted, the DBI function of the flash memory particle is turned on to execute the delay setting range based on the DBI signal output link, and set the delay value for the DBI signal output link;

[0114] Then, the validity of the delay value is determined according to the delay validity determination strategy corresponding to the target link, which also includes:

[0115] Writing preset standard data into flash memory particles;

[0116] Sending a command to read preset standard data to the flash memory particle, and receiving a sixth DQ signal value returned by the flash memory particle;

[0117] Determine the sixth DQ actual value returned by the flash memory particle according to the sixth DQ signal value and its corresponding flipping strategy;

[0118] If the sixth DQ actual value is consistent with the preset standard data, it is determined that the delay value currently set for the DBI signal output link is a valid value.

[0119] Specifically, after adjusting the delay value of the DQS / DQ signal output link, the present application adjusts the delay value of the DBI signal output link. When adjusting the delay value of the DBI signal output link, the DBI function of the flash memory particles needs to be turned on, so after adjusting the delay values ​​of the DQS signal output link and the DQ signal output link, turn on the DBI function of the flash memory particles.

[0120] The process of adjusting the delay value of the DBI signal output link is as follows: 1) Set a delay value for the DBI signal output link based on the delay setting range of the DBI signal output link (at this stage, the delay values ​​of the DQS signal output link and the DQ signal output link have been adjusted and will no longer change). 2) Write the preset standard data into the flash memory particles. 3) Send a command to read the preset standard data to the flash memory particles, and receive the sixth DQ signal value returned by the flash memory particles under the command to read the preset standard data. 4) Determine the actual value of the sixth DQ returned by the flash memory particles based on the sixth DQ signal value returned by the flash memory particles and its corresponding flipping strategy (this is the value actually read from the flash memory particles). If the actual value of the sixth DQ returned by the flash memory particles is consistent with the preset standard data, determine that the delay value currently set for the DBI signal output link is a valid value, and return to step 1) until the validity of all delay values ​​within the delay setting range of the DBI signal output link is determined. 5) Determine the effective delay range of the DBI signal output link according to the validity of all delay values ​​within the delay setting range of the DBI signal output link, so as to adjust the delay value of the DBI signal output link based on the effective delay range of the DBI signal output link.

[0121] As an optional embodiment, determining the effective delay range of the target link according to the validity of all delay values, so as to adjust the delay value of the target link based on the effective delay range, includes:

[0122] Determine N continuous delay validity ranges corresponding to the target link according to the validity of all delay values; wherein N is a positive integer;

[0123] The largest effective delay range is selected from N consecutive effective delay ranges, and the largest effective delay range is used as the preferred effective delay range of the target link, so as to adjust the delay value of the target link based on the preferred effective delay range.

[0124] Specifically, the present application determines N consecutive effective delay ranges corresponding to the target link according to the validity of all delay values ​​within the delay setting range of the target link, such as determining two consecutive effective delay ranges [10, 20] and [50, 100] for a link. Then, the present application selects the largest effective delay range from the N consecutive effective delay ranges, and uses the selected largest effective delay range as the preferred effective delay range of the target link, such as determining two consecutive effective delay ranges [10, 20] and [50, 100] for a link.

[0125] [50,100], where the range size of the effective delay range [10,20] is 10, and the range size of the effective delay range [50,100] is 50. The effective delay range [50,100] is used as the preferred effective delay range of this link. The purpose is to adjust the delay value of the target link based on the preferred effective delay range of the target link. Specifically, the delay value of the target link can be adjusted to the middle value of the preferred effective delay range. In this way, the fault tolerance of the delay value is maximized, and the correctness of the read and write data can be ensured for as long as possible.

[0126] As an optional embodiment, setting a delay value for the target link based on a delay setting range of the target link connected to the flash memory particle on the PHY includes:

[0127] Based on the delay setting range of the input link connected to the flash memory particle on the PHY, set a delay value for the input link;

[0128] After the delay values ​​of all input links are adjusted, a delay value is set for the output link based on the delay setting range of the output link connected to the flash memory particles on the PHY to enter the delay value adjustment of the output link.

[0129] Specifically, the present application divides the delay value adjustment process of the DQS / DQ / DBI link into first executing the delay value adjustment of the input link on the PHY, and then executing the delay value adjustment of the output link on the PHY. This is because: the delay value adjustment of the input link on the PHY only involves the reading process, and the delay value adjustment of the output link on the PHY involves both the writing process and the reading process; the present application first adjusts the delay value of the input link on the PHY to ensure the correctness of the reading process, and then adjusts the delay value of the output link on the PHY on the basis of the correctness of the reading process to ensure the correctness of the writing process.

[0130] In summary, this application has two methods for adjusting the delay value of the DQS / DQ / DBI link: 1) Figure 3 and Figure 4 As shown in the first delay value adjustment method: the delay values ​​of the input link and the output link are adjusted together with DQS / DQ and DBI; 2) as Figure 5 , Figure 6 , Figure 7and Figure 8 As shown, the second delay value adjustment method is as follows: the delay values ​​of the input link and the output link are adjusted separately for DQS / DQ and DBI. The two delay value adjustment methods have been introduced in detail in the above embodiments, and will not be repeated in this application.

[0131] The present application also provides a storage device, including:

[0132] Flash memory particles;

[0133] A flash memory controller including a PHY is used to implement the steps of any of the above-mentioned link delay adjustment methods when executing a computer program stored in the controller.

[0134] For an introduction to the storage device provided in this application, please refer to the embodiment of the delay adjustment method described above, and this application will not go into details here.

[0135] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0136] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A link delay adjustment method, characterized in that: Applications include flash memory controllers with PHY, including: After the preset delay adjustment condition is met, based on the delay setting range of the target link connected to the flash memory particle on the PHY, a delay value is set for the target link; wherein the target link includes an input link and an output link; Determine the validity of the delay value according to the delay validity determination strategy corresponding to the target link to obtain the validity of all delay values ​​within the delay setting range; Determining a delay validity range of the target link according to the validity of all the delay values, so as to adjust the delay value of the target link based on the delay validity range; The adjusting the delay value of the target link comprises: jointly adjusting the delay value of the input link; the input link includes a DQS signal input link, a DQ signal input link and a DBI signal input link; Or, jointly adjusting the delay value of the output link; the output link includes a DQS signal output link, a DQ signal output link and a DBI signal output link; or, after the delay values ​​of the DQS signal input link and the DQ signal input link are adjusted, the delay value of the DBI input signal link is adjusted; Or, after the delay values ​​of the DQS signal output link and the DQ signal output link are adjusted, the delay value of the DBI output signal link is adjusted.

2. The link delay adjustment method according to claim 1, characterized in that: The target link includes a DQS signal input link, a DQ signal input link and a DBI signal input link; wherein the DBI function of the flash memory particle is in an on state; Then determining the validity of the delay value according to the delay validity determination strategy corresponding to the target link includes: Sending a read parameter page command to the flash memory particle, and receiving a first DQ signal value and a first DBI signal value returned by the flash memory particle; Determine a first DQ actual value returned by the flash memory particle according to the first DQ signal value and the first DBI signal value; If the first DQ actual value is consistent with the DQ standard value corresponding to the read parameter page command, it is determined that the delay values ​​currently set for the DQS signal input link, the DQ signal input link, and the DBI signal input link are valid values.

3. The link delay adjustment method according to claim 1, characterized in that: The target link includes a DQS signal output link, a DQ signal output link and a DBI signal output link; wherein the DBI function of the flash memory particle is in an on state; Then determining the validity of the delay value according to the delay validity determination strategy corresponding to the target link includes: Writing preset standard data into the flash memory particles; Sending a command to read the preset standard data to the flash memory particle, and receiving a second DQ signal value and a second DBI signal value returned by the flash memory particle; Determine a second DQ actual value returned by the flash memory particle according to the second DQ signal value and the second DBI signal value; If the second DQ actual value is consistent with the preset standard data, it is determined that the delay values ​​currently set for the DQS signal output link, the DQ signal output link, and the DBI signal output link are valid values.

4. The link delay adjustment method according to claim 1, characterized in that: The target link includes a DQS signal input link and a DQ signal input link; wherein the DBI function of the flash memory particle is in a closed state; Then determining the validity of the delay value according to the delay validity determination strategy corresponding to the target link includes: Sending a read parameter page command to the flash memory particle, and receiving a third DQ signal value returned by the flash memory particle; If the third DQ signal value is consistent with the DQ standard value corresponding to the read parameter page command, it is determined that the delay values ​​currently set for the DQS signal input link and the DQ signal input link are valid values.

5. The link delay adjustment method according to claim 4, characterized in that: The target link also includes a DBI signal input link; wherein, after the delay values ​​of the DQS signal input link and the DQ signal input link are adjusted, the DBI function of the flash memory particle is turned on to execute a delay setting range based on the DBI signal input link and set a delay value for the DBI signal input link; Then determining the validity of the delay value according to the delay validity determination strategy corresponding to the target link, further comprising: Sending a read parameter page command to the flash memory particle, and receiving a fourth DQ signal value returned by the flash memory particle; Determine the fourth DQ actual value returned by the flash memory particle according to the fourth DQ signal value and its corresponding flip strategy; If the fourth DQ actual value is consistent with the DQ standard value corresponding to the read parameter page command, it is determined that the delay value currently set for the DBI signal input link is a valid value.

6. The link delay adjustment method according to claim 1, characterized in that: The target link includes a DQS signal output link and a DQ signal output link; wherein the DBI function of the flash memory particle is in a closed state; Then determining the validity of the delay value according to the delay validity determination strategy corresponding to the target link includes: Writing preset standard data into the flash memory particles; Sending a command to read the preset standard data to the flash memory particle, and receiving a fifth DQ signal value returned by the flash memory particle; If the fifth DQ signal value is consistent with the preset standard data, it is determined that the delay values ​​currently set for the DQS signal output link and the DQ signal output link are valid values.

7. The link delay adjustment method according to claim 6, characterized in that: The target link also includes a DBI signal output link; wherein, after the delay values ​​of the DQS signal output link and the DQ signal output link are adjusted, the DBI function of the flash memory particle is turned on to execute a delay setting range based on the DBI signal output link and set a delay value for the DBI signal output link; Then determining the validity of the delay value according to the delay validity determination strategy corresponding to the target link, further comprising: Writing preset standard data into the flash memory particles; Sending a command to read the preset standard data to the flash memory particle, and receiving a sixth DQ signal value returned by the flash memory particle; Determine the sixth DQ actual value returned by the flash memory particle according to the sixth DQ signal value and its corresponding flipping strategy; If the sixth DQ actual value is consistent with the preset standard data, it is determined that the delay value currently set for the DBI signal output link is a valid value.

8. The link delay adjustment method according to claim 1, wherein: Determining a delay validity range of the target link according to the validity of all the delay values, so as to adjust the delay value of the target link based on the delay validity range, comprising: Determine N continuous delay validity ranges corresponding to the target link according to the validity of all the delay values; wherein N is a positive integer; A maximum effective delay range is selected from the N consecutive effective delay ranges, and the maximum effective delay range is used as a preferred effective delay range of the target link, so as to adjust the delay value of the target link based on the preferred effective delay range.

9. The link delay adjustment method according to any one of claims 1 to 8, characterized in that: The method further comprises: setting a delay value for a target link connected to a flash memory particle on the PHY based on a delay setting range of the target link on the PHY, comprising: Based on the delay setting range of the input link connected to the flash memory particle on the PHY, setting a delay value for the input link; After the delay values ​​of all the input links are adjusted, a delay value is set for the output link based on the delay setting range of the output link connected to the flash memory particle on the PHY to enter the delay value adjustment of the output link.

10. A storage device, characterized in that: include: Flash memory particles; A flash memory controller including a PHY is used to implement the steps of the link delay adjustment method as described in any one of claims 1 to 9 when executing a computer program stored in the controller.

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