Display device, chip-on-film manufacturing equipment, and chip-on-film manufacturing method

Abstract

The display device includes a base film, a driving chip arranged under the base film, a first pad arranged under the base film and connected to the driving chip, and a display panel including a first connecting pad connected to the first pad, wherein one side of the first pad has a first inclined surface at a first angle relative to a top surface of the first pad, and the first angle is an acute angle.

Description

Technical Field

[0001] The invention relates to a display device, and an apparatus and a method for manufacturing a chip-on-film. Background Art

[0002] Generally, a display device includes a display panel including a plurality of pixels and a driver chip for driving the plurality of pixels. The driver chip is arranged on a flexible film, and the flexible film is connected to the display panel. The driver chip is connected to the plurality of pixels of the display panel through the flexible film. This connection method is defined as a chip-on-film method.

[0003] A plurality of pads connected to the driving chip are arranged on the flexible film, and the display panel includes a plurality of connection pads connected to a plurality of pixels. The plurality of pads are connected to contact the plurality of connection pads, respectively, and thus the driving chip is connected to the plurality of pixels.

[0004] The plurality of pads and the plurality of connecting pads are connected to each other in various ways. For example, the plurality of pads and the plurality of connecting pads may be electrically connected to each other through an anisotropic conductive film (ACF). In addition, the plurality of pads and the plurality of connecting pads may be connected to each other by ultrasonic bonding without using an anisotropic conductive film. Summary of the invention

[0005] Technical issues

[0006] An object of the present invention is to provide a display device capable of preventing a plurality of pads from being short-circuited, an apparatus for manufacturing a chip-on-film, and a method for manufacturing a chip-on-film.

[0007] Technical Solution

[0008] A display device according to an embodiment of the present invention includes a base film, a driving chip arranged under the base film, a first pad arranged under the base film and connected to the driving chip, and a display panel including a first connecting pad connected to the first pad, wherein one side of the first pad has a first inclined surface at a first angle relative to a top surface of the first pad, and the first angle is an acute angle.

[0009] The one side of the first pad is adjacent to a side of the base film connected to the display panel.

[0010] The one side of the base film has a second inclined surface at the first angle with respect to the top surface of the base film.

[0011] The first inclined surface and the second inclined surface are arranged on the same plane.

[0012] The first pad extends in a first direction intersecting an extending direction of the one side of the base film, and the first angle is set to an angle of 30 to 80 degrees with respect to the first direction.

[0013] The first pad is provided in plurality, and the plurality of first pads are arranged along the one side of the base film by extending in the first direction.

[0014] The first pad includes a first portion having the first inclined surface defined thereon and a second portion around the first portion.

[0015] The first portion is spaced apart from the first connection pad, and the second portion is in contact with the first connection pad.

[0016] Based on the first direction, the first portion has a length less than or equal to 1 / 2 of a length of the first pad.

[0017] The equipment for manufacturing a COF film according to an embodiment of the present invention includes a first retainer portion, a second retainer portion, and a stamping portion, a flexible circuit film is arranged on the top surface of the first retainer portion, and a first opening extending downward is defined in the first retainer portion, the second retainer portion is arranged on the flexible circuit film to overlap with the first retainer portion around the first opening and move up and down, and the stamping portion is arranged on the flexible circuit film to overlap with the first opening and move up and down. The flexible circuit film includes a base film, a driver chip arranged under the base film, and a first pad arranged under the base film and connected to the driver chip. The first opening exposes a portion of the first pad and the driver chip, and each of the top surface of the first retainer portion, the bottom surface of the second retainer portion, and the bottom surface of the stamping portion has an inclined surface at a predetermined angle relative to a first direction.

[0018] A method for manufacturing a COF film according to an embodiment of the present invention includes: arranging a flexible circuit film on a first retainer portion having a first opening defined therein; moving a second retainer portion arranged on the flexible circuit film to overlap the first retainer portion around the first opening downward to fix the flexible circuit film around the first opening; and inserting a punching portion arranged on the flexible circuit film to overlap the first opening into the first opening to cut the flexible circuit film along an edge of the punching portion. The flexible circuit film includes a base film, a driver chip arranged under the base film, and a first pad arranged under the base film and connected to the driver chip. The first opening exposes a portion of the first pad and the driver chip, and each of a top surface of the first retainer portion, a bottom surface of the second retainer portion, and a bottom surface of the punching portion has an inclined surface at a predetermined angle relative to a first direction.

[0019] A display device according to an embodiment of the present invention includes a base film, a driving chip arranged under the base film, a first pad arranged under the base film and connected to the driving chip, and a display panel including a first connecting pad overlapping the first pad and connected to the first pad when viewed on a plane. A portion of the first pad is spaced apart from an upper portion of the first connecting pad.

[0020] Beneficial Effects

[0021] According to an embodiment of the present invention, in a chip on film, one side of each of the plurality of first pads may have an inclined surface, and thus, during ultrasonic bonding, energy transferred due to ultrasonic vibration may be reduced to prevent the plurality of first pads from short-circuiting. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a plan view of a display device according to an embodiment of the present invention.

[0023] Figure 2 yes Figure 1 Equivalent circuit diagram of a pixel.

[0024] Figure 3 yes Figure 2 Schematic cross-sectional view of a pixel shown in .

[0025] Figure 4 is an enlarged view of the flip chip film to show Figure 1 Detailed structure of the Chip on Film.

[0026] Figure 5 is along Figure 4 A cross-sectional view taken along line II'.

[0027] Figure 6 It is shown Figure 5 2 is a view of a connection state between the first and second pads and the first and second connecting pads shown in FIG.

[0028] Figure 7 It is shown Figure 5 An enlarged view of the first and second pads and the first and second connecting pads shown in FIG.

[0029] Figure 8 yes Figure 7 An enlarged view of the first pad is shown in FIG.

[0030] Fig. 9 is a view for explaining a method of connecting a first pad to a first connection pad.

[0031] Fig.10 is a view for explaining connection between the comparison pad and the first connection pad.

[0032] Fig.11 is a perspective view of an apparatus for manufacturing a chip on film according to an embodiment of the present invention.

[0033] Fig.12 is along Fig.11 A cross-sectional view taken along line II-II' shown in FIG.

[0034] Fig.13 yes Fig.12 A perspective view of the second retainer portion and the stamping portion shown in FIG.

[0035] Fig.14 It is shown Fig.12 2 is a view of a planar configuration of the first retainer portion, the second retainer portion and the stamping portion shown in FIG.

[0036] Figures 15 to 20 It is used to explain the use Fig.11 A view of a method for manufacturing a chip on film of an apparatus for manufacturing a chip on film shown in FIG.

[0037] Fig.21 is based on Fig. 20 A cross-sectional view of a chip-on-film manufactured by the method for manufacturing a chip-on-film shown in FIG. DETAILED DESCRIPTION

[0038] In the present specification, it will also be understood that when a component (or region, layer, portion) is referred to as being “on,” “connected to” or “coupled to” another component, the component can be directly arranged on / connected to / coupled to the other component, or an intervening third component may also be present.

[0039] The same reference numerals refer to the same elements throughout. In addition, in the drawings, the thickness, proportion and size of components are exaggerated for clarity of illustration.

[0040] The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] It will be understood that although terms such as "first" and "second" are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one component from other components. For example, a first element referred to as a first element in an embodiment can be referred to as a second element in another embodiment without departing from the scope of the appended claims. Unless otherwise indicated, terms in the singular may include plural forms.

[0042] In addition, “under”, “below”, “above”, “upper”, etc. are used to explain the relationship between components shown in the drawings. These terms may be relative concepts and are described based on the directions expressed in the drawings.

[0043] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those generally understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant art, and will not be interpreted in an ideal or overly formal sense unless explicitly defined in this article.

[0044] The meaning of “include” or “comprising” specifies attributes, fixed numbers, steps, operations, elements, parts or a combination thereof, but does not exclude other attributes, fixed numbers, steps, operations, elements, parts or a combination thereof.

[0045] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0046] Figure 1 is a plan view of a display device according to an embodiment of the present invention.

[0047] Reference Figure 1 , a display device DD according to an embodiment of the present invention may include a display panel DP, a scan driver SDV, a chip on film COF, an emission driver EDV, a printed circuit board PCB, and a timing controller T-CON.

[0048] In the embodiment of the present invention, various image display panels capable of displaying images, such as a liquid crystal display panel, an electrowetting display panel, an electrophoretic display panel, or a light emitting display panel, may be used as the display panel DP.

[0049] In addition, the display panel DP according to the embodiment of the present invention may be a light-emitting display panel, but is not limited thereto. For example, the display panel DP may be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots, quantum rods, etc. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0050] The display panel DP may be a flexible display panel. For example, the display panel DP may include a plurality of electronic components arranged on a flexible substrate. The display panel DP may have a rectangular shape having a long side in a first direction DR1 and a short side in a second direction DR2 crossing the first direction DR1.

[0051] The display panel DP may have a plane defined by the first direction DR1 and the second direction DR2. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA.

[0052] The display panel DP may include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, and a plurality of emission lines EL1 to ELm. Here, m and n are natural numbers greater than 0. The plurality of pixels PX may be arranged in a matrix form, but is not limited thereto, and thus may be arranged in various forms. The plurality of pixels PX may be arranged in a display area DA and connected to the plurality of scan lines SL1 to SLm, the plurality of data lines DL1 to DLn, and the plurality of emission lines EL1 to ELm.

[0053] The scanning driver SDV and the emission driver EDV may be arranged in the non-display area NDA. The scanning driver SDV may be arranged in the non-display area NDA adjacent to any one of the long sides of the display panel DP. The emission driver EDV may be arranged in the non-display area NDA adjacent to the other of the long sides of the display panel DP. The scanning driver SDV and the emission driver EDV may be arranged across the display area DA.

[0054] The plurality of scan lines SL1 to SLm may extend in the second direction DR2 and be connected to the scan driver SDV. The plurality of emission lines EL1 to ELm may extend in the second direction DR2 and be connected to the emission driver EDV.

[0055] The chip on film COF may include a base film BF and a driver chip D-IC disposed on the base film BF. The driver chip D-IC may be defined as a data driver. The driver chip D-IC may be manufactured in the form of an integrated circuit chip and mounted on the base film BF.

[0056] Hereinafter, one of both sides of the base film BF that are opposite to each other in the first direction DR1 is defined as one side of the base film BF, and the other side is defined as the other side of the base film BF.

[0057] The base film BF may have a rectangular shape having short sides in the first direction DR1 and long sides in the second direction DR2. One side of the base film BF may be connected to the non-display area NDA adjacent to any one of the short sides of the display panel DP. The other side of the base film BF may be connected to the printed circuit board PCB.

[0058] Although not shown, a plurality of wires connected to the driving chip D-IC may be arranged on the base film BF. Figure 4 The plurality of lines arranged on the base film BF are described in detail. The plurality of data lines DL1 to DLn may extend in the first direction DR1 and be connected to the plurality of lines arranged on the base film BF. Therefore, the plurality of data lines DL1 to DLn may be connected to the driving chip D-IC through the base film BF.

[0059] The scan driver SDV may generate a plurality of scan signals, and the plurality of scan signals may be applied to the plurality of pixels PX through the plurality of scan lines SL1 to SLm. The plurality of scan signals may be sequentially applied to the plurality of pixels PX.

[0060] The driving chip D-IC may generate a plurality of data voltages and the plurality of data voltages may be applied to the plurality of pixels PX through the plurality of data lines DL1 to DLn. The emission driver EDV may generate a plurality of emission signals and the plurality of emission signals may be applied to the plurality of pixels PX through the plurality of emission lines EL1 to ELm.

[0061] The timing controller T-CON may be arranged on a printed circuit board PCB. The timing controller T-CON may be manufactured in the form of an integrated circuit chip and mounted on the printed circuit board PCB. Although not shown, in addition to the timing controller T-CON, various circuits such as a power generation circuit and an interface circuit may also be arranged on the printed circuit board PCB.

[0062] The timing controller T-CON may control the operation of the scan driver SDV, the driver chip D-IC, and the emission driver EDV. For example, the timing controller T-CON may generate a scan control signal, a data control signal, and an emission control signal in response to a control signal received from the outside. The timing controller T-CON may receive an image signal from the outside and convert the data format of the image signal to meet the interface specification with the driver chip D-IC, thereby providing the image signal with the converted data format to the driver chip D-IC.

[0063] The scan control signal and the emission control signal may be provided to the scan driver SDV and the emission driver EDV respectively through the driving chip D-IC. The scan control signal and the emission control signal may be provided to the scan driver SDV and the emission driver EDV respectively through the control signal line CSL. The control signal line CSL may be connected to the line arranged on the base film BF. The data control signal may be provided to the driving chip D-IC.

[0064] The scan driver SDV may generate a scan signal in response to a scan control signal, and the emission driver EDV may generate an emission signal in response to an emission control signal. The driving chip D-IC may receive an image signal whose data format is converted and generate a data voltage corresponding to the image signal in response to a data control signal.

[0065] The pixel PX may receive a data voltage in response to a scan signal. The pixel PX may emit light having a brightness corresponding to the data voltage in response to an emission signal to display an image. The emission time of the pixel PX may be controlled by the emission signal.

[0066] Figure 2 yes Figure 1 Equivalent circuit diagram of a pixel.

[0067] For example, an equivalent circuit diagram of a pixel PX is shown, but Figure 1 Other pixels PX shown in FIG. 1 may also have Figure 2 The same equivalent circuit diagram of the pixel PX shown in FIG.

[0068] Reference Figure 2 , the pixel PX may be connected to a corresponding scan line SLi among a plurality of scan lines SL1 to SLm, a corresponding data line DLj among a plurality of data lines DL1 to DLn, and a corresponding emission line ELi among a plurality of emission lines EL1 to ELm. i is a natural number less than or equal to m and greater than 0, and j is a natural number less than or equal to n and greater than 0.

[0069] The pixel PX may include a light emitting element OLED, a driving transistor T1, a capacitive element Cst, a switching transistor T2, and an emission control transistor T3. The light emitting element OLED may be defined as an organic light emitting diode.

[0070] A source terminal of the driving transistor T1 may receive the first voltage ELVDD, and a drain terminal of the driving transistor T1 may be connected to a source terminal of the emission control transistor T3. A gate terminal of the driving transistor T1 may be connected to a drain terminal of the switching transistor T2.

[0071] The gate terminal of the switching transistor T2 may be connected to the scan line SLi, and the source terminal of the switching transistor T2 may be connected to the data line DLj. The first electrode of the capacitor Cst may be connected to the source terminal of the driving transistor T1, and the second electrode of the capacitor Cst may be connected to the gate terminal of the driving transistor T1.

[0072] The gate terminal of the emission control transistor T3 may be connected to the emission line ELi, and the drain terminal of the emission control transistor T3 may be connected to the anode of the light emitting element OLED. The cathode of the light emitting element OLED may receive the second voltage ELVSS, and the second voltage ELVSS may have a level lower than that of the first voltage ELVDD.

[0073] The switching transistor T2 may be turned on in response to a scan signal SCAN provided through the scan line SLi. The turned-on switching transistor T2 may provide a data voltage DATA provided through the data line DLj to the gate terminal of the driving transistor T1.

[0074] The capacitance element Cst may charge the data voltage DATA applied to the gate terminal of the driving transistor T1 so that the data voltage DATA is maintained even after the switching transistor T2 is turned off.

[0075] The emission control transistor T3 may be turned on in response to an emission signal EM applied to the gate terminal through the emission line ELi. The turned-on emission control transistor T3 may be used to provide the current Ioled flowing through the driving transistor T1 to the light emitting element OLED. The pixel PX may emit light during the application time of the emission signal EM. The light emitting element OLED may emit light by changing the intensity according to the amount of the supplied current Ioled.

[0076] For example, the transistors T1 to T3 of the pixel PX may be PMOS transistors, but are not limited thereto, and the transistors T1 to T3 of the pixel PX may be NMOS transistors.

[0077] Figure 3 yes Figure 2 Schematic cross-sectional view of a pixel shown in .

[0078] Reference Figure 3 , the pixel PX may include a light emitting element OLED and a transistor TR connected to the light emitting element OLED. The light emitting element OLED may include a first electrode E1, a second electrode E2, and an organic emission layer OEL disposed between the first electrode E1 and the second electrode E2. The transistor TR may be Figure 2 The emission control transistor T3 shown in FIG.

[0079] The first electrode E1 may be an anode, and the second electrode E2 may be a cathode. The first electrode E1 may be defined as a pixel electrode, and the second electrode E2 may be defined as a common electrode.

[0080] The pixel PX may be divided into a pixel area PA and a non-pixel area NPA surrounding the pixel area PA. The light emitting element OLED may be disposed in the pixel area PA, and the transistor TR may be disposed in the non-pixel area NPA.

[0081] The transistor TR and the light emitting element OLED may be disposed on the substrate SUB. The buffer layer BFL may be disposed on the substrate SUB, and the buffer layer BFL may include an inorganic material.

[0082] The semiconductor layer SM of the transistor TR may be disposed on the buffer layer BFL. The semiconductor layer SM may include a semiconductor made of an inorganic material such as amorphous silicon or polycrystalline silicon or an organic semiconductor. In addition, the semiconductor layer SM may include an oxide semiconductor. Figure 3 Although not shown in FIG. 1 , the semiconductor layer SM may include a source region, a drain region, and a channel region between the source region and the drain region.

[0083] The first insulating layer INS1 may be disposed on the buffer layer BFL to cover the semiconductor layer SM. The first insulating layer INS1 may include an inorganic material. The gate electrode GE of the transistor TR overlapping the semiconductor layer SM may be disposed on the first insulating layer INS1. The gate electrode GE may be disposed to overlap the channel region of the semiconductor layer SM.

[0084] The second insulating layer INS2 may be disposed on the first insulating layer INS1 to cover the gate electrode GE. The second insulating layer INS2 may be defined as an interlayer dielectric. The second insulating layer INS2 may include an organic material and / or an inorganic material.

[0085] The source electrode SE and the drain electrode DE of the transistor TR may be arranged on the second insulating layer INS2 to be spaced apart from each other. The source electrode SE may be connected to the source region of the semiconductor layer SM through a first contact hole CH1 defined through the first insulating layer INS1 and the second insulating layer INS2. The drain electrode DE may be connected to the drain region of the semiconductor layer SM through a second contact hole CH2 defined through the first insulating layer INS1 and the second insulating layer INS2.

[0086] The third insulating layer INS3 may be disposed on the second insulating layer INS2 to cover the source electrode SE and the drain electrode DE of the transistor TR. The third insulating layer INS3 may be defined as a planarization layer providing a planar top surface and include an organic material.

[0087] The first electrode E1 may be disposed on the third insulating layer INS3. The first electrode E1 may be connected to the drain electrode DE of the transistor TR through a third contact hole CH3 defined through the third insulating layer INS3.

[0088] A pixel defining layer PDL through which a predetermined region of the first electrode E1 is exposed may be disposed on the first electrode E1 and the third insulating layer INS3. An opening PX_OP through which a predetermined portion of the first electrode E1 is exposed may be defined in the pixel defining layer PDL.

[0089] The organic emission layer OEL may be disposed on the first electrode E1 within the opening PX_OP. The organic emission layer OEL may emit one of red light, green light, and blue light. However, the embodiments of the present invention are not limited thereto. For example, the organic emission layer OEL may generate white light by a combination of organic materials that generate red light, green light, and blue light, respectively.

[0090] The second electrode E2 may be disposed on the pixel defining layer PDL and the organic emission layer OEL. A thin film encapsulation layer TFE may be disposed on the light emitting element OLED to cover the pixel PX.

[0091] A first voltage ELVDD may be applied to the first electrode E1, and a second voltage ELVSS may be applied to the second electrode E2. Holes and electrons injected into the organic emission layer OEL may be combined with each other to form excitons. While the excitons may transition to a ground state, the light emitting element OLED may emit light. The light emitting element OLED may emit red light, green light, or blue light according to the flow of current to display an image.

[0092] Figure 4 is an enlarged view of the flip chip film to show Figure 1 Detailed structure of the Chip on Film.

[0093] For convenience of description, a portion of the display panel DP connected to the chip-on-film COF and a portion of the printed circuit board PCB connected to the chip-on-film COF may be separated from the chip-on-film COF and Figure 4 are shown separately in .

[0094] Reference Figure 4 The chip on film COF may include a plurality of first pads PD1, a plurality of second pads PD2, a plurality of first signal lines SL1, and a plurality of second signal lines SL2. The plurality of first pads PD1, a plurality of second pads PD2, and a plurality of first signal lines SL1, and a plurality of second signal lines SL2 may be arranged on the base film BF.

[0095] The plurality of first pads PD1 may be arranged adjacent to one side of the base film BF. The plurality of first pads PD1 may extend in the first direction DR1 and may be arranged in the second direction DR2. Each of the plurality of first pads PD1 may have a rectangular shape having a long side in the first direction DR1 and a short side in the second direction DR2. One side of the base film BF may extend parallel to the second direction DR2. The plurality of first pads PD1 may be arranged along one side of the base film BF.

[0096] The plurality of second pads PD2 may be arranged adjacent to the other side of the base film BF. The plurality of second pads PD2 may extend in the first direction DR1 and may be arranged in the second direction DR2. Each of the plurality of second pads PD2 may have a rectangular shape having a long side in the first direction DR1 and a short side in the second direction DR2. The other side of the base film BF may extend parallel to the second direction DR2. The plurality of second pads PD2 may be arranged along the other side of the base film BF.

[0097] A distance between the first pads PD1 adjacent to each other may be smaller than a distance between the second pads PD2 adjacent to each other. The number of the first pads PD1 arranged on the base film BF may be greater than the number of the second pads PD2.

[0098] The driving chip D-IC may be disposed between the plurality of first pads PD1 and the plurality of second pads PD2. The driving chip D-IC may have a rectangular shape having long sides in the second direction DR2 and short sides in the first direction DR1.

[0099] The plurality of first pads PD1 and the plurality of second pads PD2 may be connected to the driver chip D-IC through the plurality of first signal lines SL1 and the plurality of second signal lines SL2. For example, the plurality of first signal lines SL1 may be arranged between the plurality of first pads PD1 and the driver chip D-IC to be connected to the plurality of first pads PD1 and the driver chip D-IC. The plurality of second signal lines SL2 may be arranged between the plurality of second pads PD2 and the driver chip D-IC to be connected to the plurality of second pads PD2 and the driver chip D-IC.

[0100] A plurality of first connection pads CPD1 may be arranged on the display panel DP. The plurality of first connection pads CPD1 may extend in the first direction DR1 and be arranged in the second direction DR2. Each of the plurality of first connection pads CPD1 may have a rectangular shape having a long side in the first direction DR1 and a short side in the second direction DR2.

[0101] A plurality of first connection pads CPD1 may be arranged in the non-display area NDA adjacent to one short side of the display panel DP. A plurality of control signal lines CSL and a plurality of data lines DL1 to DLn may be connected to the plurality of first connection pads CPD1.

[0102] The number of first connection pads CPD1 may be the same as the number of first pads PD1. The plurality of first connection pads CPD1 may be connected to the plurality of first pads PD1, respectively. Since the plurality of first connection pads CPD1 are connected to the plurality of first pads PD1, one side of the base film BF may be connected to the display panel DP, and the plurality of control signal lines CSL and the plurality of data lines DL1 to DLn may be connected to the driving chip D-IC through the plurality of first signal lines SL1.

[0103] A plurality of second connection pads CPD2 may be arranged on the printed circuit board PCB. The plurality of second connection pads CPD2 may extend in the first direction DR1 and be arranged in the second direction DR2. Each of the plurality of second connection pads CPD2 may have a rectangular shape having a long side in the first direction DR1 and a short side in the second direction DR2.

[0104] The plurality of second connection pads CPD2 may be adjacent to one side of the printed circuit board PCB. The plurality of second connection pads CPD2 may be connected to the plurality of third signal lines SL3. Although not shown, the third signal lines SL3 may be connected to the timing controller T-CON.

[0105] The number of the second connection pads CPD2 may be the same as the number of the second pads PD2. The plurality of second connection pads CPD2 may be connected to the plurality of second pads PD2, respectively. Since the plurality of second connection pads CPD2 are connected to the plurality of second pads PD2, the other side of the base film BF may be connected to the printed circuit board PCB, and the timing controller T-CON may be connected to the driving chip D-IC.

[0106] Figure 5 is along Figure 4 A cross-sectional view taken along line II'. Figure 6 It is shown Figure 5 2 is a view of a connection state between the first and second pads and the first and second connecting pads shown in FIG.

[0107] For example, Figure 6 Shows the corresponding Figure 5 In addition, for the convenience of description, Figure 5 and Figure 6 The cross sections of the first signal line SL1 and the second signal line SL2 are omitted.

[0108] Reference Figure 5, the first pad PD1 and the second pad PD2 may be arranged under the base film BF. Although not shown, the driver chip D-IC and the first signal line SL1 and the second signal line SL2 may also be arranged under the base film BF. The driver chip D-IC may be mounted on the bottom surface of the base film BF. The first pad PD1 and the second pad PD2 and the first signal line SL1 and the second signal line SL2 may be formed by patterning a predetermined conductive material on the bottom surface of the base film BF.

[0109] Hereinafter, a direction intersecting a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In essence, the third direction DR3 may intersect the plane defined by the first direction DR1 and the second direction DR2 perpendicularly. In addition, in this specification, the term "viewed from a plane" may mean a state viewed from the third direction D3.

[0110] Each of one side of the first pad PD1 and one side of the base film BF may have an inclined surface. One side of the first pad PD1 may be defined as a portion of the first pad PD1 adjacent to one side of the base film BF. Each of one side of the second pad PD2 and the other side of the base film BF may have an inclined surface. One side of the second pad PD2 may be defined as a portion of the second pad PD2 adjacent to the other side of the base film BF. Figure 7 The inclined surfaces of the first pad PD1 and the second pad PD2 are described in detail.

[0111] Reference Figure 6 The first pad PD1 may be arranged on the first connection pad CPD1 and may overlap the first connection pad CPD1 when viewed on a plane. The second pad PD2 may be arranged on the second connection pad CPD2 and may overlap the second connection pad CPD2 when viewed on a plane.

[0112] The first pad PD1 may be in contact with the first connection pad CPD1 and may be connected to the first connection pad CPD1. A portion of the first pad PD1 adjacent to one side of the base film BF may be spaced apart from an upper portion of the first connection pad CPD1 so as not to be in contact with the first connection pad CPD1. The second pad PD2 may be in contact with the second connection pad CPD2 and may be connected to the second connection pad CPD2.

[0113] Resin RIN may be disposed on each of both sides of the first pad PD1 and each of both sides of the first connection pad CPD1. In addition, resin RIN may be disposed on each of both sides of the second pad PD2 and each of both sides of the second connection pad CPD2.

[0114] The resin RIN may be arranged to cover both sides of the first pad PD1 and both sides of the first connection pad CPD1, thereby protecting the first pad PD1 and the first connection pad CPD1. In addition, the resin RIN may be arranged to cover both sides of the second pad PD2 and both sides of the second connection pad CPD2, thereby protecting the second pad PD2 and the second connection pad CPD2.

[0115] Figure 7 yes Figure 5 An enlarged view of the first and second pads and the first and second connecting pads shown in FIG. Figure 8 yes Figure 7 An enlarged view of the first pad is shown in FIG.

[0116] Reference Figure 7 , one side of the first pad PD1 may have a first inclined surface SLP1 at a first angle θ1 relative to the top surface of the first pad PD1. The top surface of the first pad PD1 may substantially have a plane defined by the first direction DR1 and the second direction DR2. The top surface of the first pad PD1 may be defined as one surface of the first pad PD1 facing the base film BF. The first inclined surface SLP1 may be an inclined surface at a first angle θ1 relative to the first direction DR1.

[0117] The first angle θ1 may be an acute angle. An acute angle may be defined as an angle less than 90 degrees. Therefore, the first inclined surface SLP1 may be defined as an inclined surface extending at an angle greater than 0 degrees and less than 90 degrees relative to the first direction DR1. In an embodiment of the present invention, the first angle θ1 may be set to 30 degrees to 80 degrees based on the first direction DR1.

[0118] One side of the base film BF may have a second inclined surface SLP2 at a first angle θ1 relative to the top surface of the base film BF. The top surface of the base film BF may substantially have a plane defined by the first direction DR1 and the second direction DR2. The second inclined surface SLP2 may be an inclined surface at the first angle θ1 relative to the first direction DR1.

[0119] The top surface of the base film BF may be defined as one surface of the base film BF opposite to the bottom surface of the base film BF facing the first pad PD1. The first inclined surface SLP1 and the second inclined surface SLP2 may be arranged on the same plane.

[0120] One side of the second pad PD2 may have a third inclined surface SLP3 at a second angle θ2 relative to the top surface of the second pad PD2. The top surface of the second pad PD2 may substantially have a plane defined by the first direction DR1 and the second direction DR2. The third inclined surface SLP3 may be an inclined surface at a second angle θ2 relative to the first direction DR1.

[0121] The second angle θ2 may be an obtuse angle. The obtuse angle may be defined as an angle greater than 90 degrees. Therefore, the third inclined surface SLP3 may be defined as an inclined surface extending at an angle greater than 90 degrees and less than 180 degrees with respect to the first direction DR1.

[0122] When based on the first direction DR1, the second angle θ2 may be defined as a value obtained by subtracting the first angle θ1 from 180 degrees. That is, the third inclined surface SLP3 may have a reverse inclined surface with respect to the first inclined surface SLP1. In an embodiment of the present invention, the second angle θ2 may be 100 to 150 degrees based on the first direction DR1.

[0123] The other side of the base film BF may have a fourth inclined surface SLP4 at a second angle θ2 relative to the top surface of the base film BF. The fourth inclined surface SLP4 may be an inclined surface at the second angle θ2 relative to the first direction DR1. The third inclined surface SLP3 and the fourth inclined surface SLP4 may be arranged on the same plane.

[0124] According to the method for manufacturing a chip-on-film (COF), the first inclined surface SLP1 and the second inclined surface SLP2 may have the same inclined surface, and the third inclined surface SLP3 and the fourth inclined surface SLP4 may have the same inclined surface. Figures 15 to 20 A method for manufacturing a chip-on-film (COF) is described in detail.

[0125] Reference Figure 7 and Figure 8 , the first pad PD1 may include a first portion PT1 having an inclined surface defined thereon and a second portion PT2 around the first portion PT1. The first portion PT1 may be spaced apart from an upper portion of the first connection pad CPD1 so as not to contact the first connection pad CPD1. The second portion PT2 may contact the first connection pad CPD1 and may be connected to the first connection pad CPD1.

[0126] When based on the first direction DR1, the first pad PD1 may have a first length L1, and the first portion PT1 may have a second length L2. The second length L2 may be less than or equal to 1 / 2 of the first length L1.

[0127] Fig. 9 is a view for explaining a method of connecting a first pad to a first connection pad. Fig.10 is a view for explaining connection between the comparison pad and the first connection pad.

[0128] Reference Fig. 9, the bottom surface of the first pad PD1 may contact the top surface of the first connection pad CPD1, and the ultrasonic vibration part ULP may be connected to the base film BF. In essence, the second portion PT2 of the first pad PD1 may contact the top surface of the first connection pad CPD1. The ultrasonic vibration part ULP may be defined as a horn.

[0129] The ultrasonic vibration part ULP may generate vibration having a predetermined frequency. For example, the ultrasonic vibration part ULP may generate ultrasonic vibration vibrating at a frequency of 35 KHz in the first direction DR1. The ultrasonic vibration may be applied to the first pad PD1 through the base film BF.

[0130] The first pad PD1 may vibrate in the first direction DR1 by ultrasonic vibration, and energy due to the ultrasonic vibration may be transferred to a contact surface between the first pad PD1 and the first connection pad CPD1. The principle of ultrasonic vibration is as follows.

[0131] When a solid is subjected to an external force, deformation may occur in the solid. In the case of a small external force, the solid may return to its original shape when the external force is removed. However, when the external force reaches a certain threshold, the solid may not return to its original shape, and therefore, permanent deformation may occur in the solid. This deformation may be defined as plastic deformation.

[0132] As the external force increases, the stress in the solid may also gradually increase. However, when the external force reaches a critical value, the permanent deformation may increase rapidly. The limit value of this stress (the above threshold value) can be defined as the yield value (yield point).

[0133] Energy due to ultrasonic vibration may be transferred to a contact surface (or contact interface) between the first pad PD1 and the first connection pad CPD1. Each of the first pad PD1 and the first connection pad CPD1 may include solid metal. Energy due to ultrasonic vibration may be defined as an external force.

[0134] Because the energy due to the ultrasonic vibration is transferred to the first pad PD1 and the first connection pad CPD1, the stress of the first pad PD1 and the first connection pad CPD1 may increase. When the stress reaches the yield value, plastic deformation may occur in the first pad PD1 and the first connection pad CPD1. In addition, the oxide layer on the contact surface (metal surface) of each of the first pad PD1 and the first connection pad CPD1 may be removed so that the first pad PD1 and the first connection pad CPD1 are in direct contact with each other.

[0135] Due to continuous friction and plastic deformation between the first pad PD1 and the first connection pad CPD1, heat may be generated to increase the temperature. In this case, atoms of the first pad PD1 and the first connection pad CPD1 may diffuse relative to each other on the contact surface between the first pad PD1 and the first connection pad CPD1 that are in direct contact with each other.

[0136] For example, atoms of the contact surface of the first pad PD1 may diffuse toward the first connection pad CPD1, and atoms of the contact surface of the first connection pad CPD1 may diffuse toward the first pad PD1. As a result, the first pad PD1 and the first connection pad CPD1 may be directly coupled to each other.

[0137] Since the first portion PT1 of the first pad PD1 does not contact the first connection pad CPD1, ultrasonic bonding may not be applied. The second portion PT2 of the first pad PD1 may contact the first connection pad CPD1 and may be directly connected to the first connection pad CPD1 through ultrasonic bonding.

[0138] Reference Fig.10 ,and Fig. 9 Unlike the first pad PD1 shown in FIG. 2 , the comparison pad PD1 ′ may not have an inclined surface and may have a rectangular shape when viewed in the second direction DR2 . The comparison pad PD1 ′ may be connected to the first connection pad CPD1 by ultrasonic bonding.

[0139] When the comparison pad PD1' has a rectangular shape, a contact area of ​​the comparison pad PD1' with the first connection pad CPD1 may be greater than a contact area of ​​the first pad PD1 with the first connection pad CPD1. Energy transferred to the comparison pad PD1' may be proportional to the contact area.

[0140] Strong energy due to ultrasonic vibration may be applied to the comparison pad PD1' having a wide contact area. In this case, when the comparison pad PD1' vibrates in the first direction DR1, one side of the base film BF and one side of the comparison pad PD1' may be peeled relative to each other.

[0141] When the comparison pad PD1' is peeled off from the base film BF, a portion of the peeled comparison pad PD1' may be bent in the second direction DR2 by ultrasonic energy, and the bent comparison pad PD1' may contact other adjacent comparison pads. That is, a short circuit phenomenon in which the comparison pads are short-circuited to each other may occur.

[0142] Reference Fig. 9In an embodiment of the present invention, the contact area of ​​the first pad PD1 in contact with the first connection pad CPD1 may be smaller than the contact area of ​​the comparison pad PD1' in contact with the first connection pad CPD1. Therefore, the energy applied to the first pad PD1 due to ultrasonic vibration may be smaller than the energy applied to the comparison pad PD1' due to ultrasonic vibration. In this case, the problem of the first pad PD1 peeling off from the base film BF or bending in the second direction DR2 may not occur. Therefore, the plurality of first pads PD1 may not be short-circuited to each other.

[0143] According to the embodiment of the present invention, since one side of the first pad PD1 of the chip on film COF has the first inclined surface SLP1, during ultrasonic bonding, transmitted energy due to ultrasonic vibration can be reduced to prevent the plurality of first pads PD1 from being short-circuited with each other.

[0144] A short circuit phenomenon may occur between a plurality of pads having a narrow distance therebetween, and a short circuit phenomenon may not occur between a plurality of pads having a wide distance therebetween. That is, a short circuit phenomenon may not substantially occur in the second pad PD2.

[0145] Fig.11 is a perspective view of an apparatus for manufacturing a chip on film according to an embodiment of the present invention. Fig.12 is along Fig.11 A cross-sectional view taken along line II-II' shown in FIG. Fig.13 yes Fig.12 A perspective view of the second retainer portion and the stamping portion shown in FIG. Fig.14 It is shown Fig.12 2 is a view of a planar configuration of the first retainer portion, the second retainer portion and the stamping portion shown in FIG.

[0146] For the convenience of explanation, Fig.13 In, when Fig.12 Compared with the structure shown in , the second retainer portion HDP2 is further spaced apart from the punching portion PCH in the upper and lower directions. Fig.14 and Fig.16 , the top surface of the first holder portion HDP1 is shown, and the step plane on one side of the first holder portion HDP1 is not shown.

[0147] Reference Fig.11 and Fig.12 , an apparatus AP for manufacturing a flip chip film may include an upper support plate USP, a connecting block CB, a first retainer portion HDP1, a plurality of first pillars SPC1, a plurality of pillar supports CSP, a second retainer portion HDP2, a plurality of second pillars SPC2, a punching portion PCH and a punching support portion PCS.

[0148] The upper support plate USP may have a plane defined by the first direction DR1 and the second direction DR2. The upper support plate USP may have a predetermined thickness in the third direction DR3. The upper support plate USP may have a rectangular shape when viewed on a plane.

[0149] The first retainer portion HDP1 may be arranged under the upper support plate USP. The first retainer portion HDP1 may have a rectangular shape when viewed on a plane. One of the two sides of the first retainer portion HDP1 that are opposite to each other in the first direction DR1 may have a stepped shape. The height of the other side of the two sides of the first retainer portion HDP1 may be lower than the height of one side of the first retainer portion HDP1. The top surface of the first retainer portion HDP1 may have an inclined surface U_SLP1 that is inclined at a predetermined angle relative to the first direction DR1.

[0150] A first opening OP1 extending downward may be defined in the first holder portion HDP1. The first opening OP1 may be defined by passing through the first holder portion HDP1 in the third direction DR3. A groove G may be defined in a top surface of the first holder portion HDP1. The groove G may extend in the first direction DR1 along the top surface of the first holder portion HDP1.

[0151] A plurality of first pillars SPC1 may be arranged between the upper support plate USP and the first retainer portion HDP1. Each of the plurality of first pillars SPC1 may have a cylindrical shape extending in the third direction DR3. Each of the plurality of first pillars SPC1 may be adjacent to a square vertex of the upper support plate USP and a square vertex of the first retainer portion HDP1. For example, although four first pillars SPC1 are arranged, the number of the first pillars SPC1 is not limited thereto.

[0152] A plurality of first pillars SPC1 may be connected to the first holder part HDP1 and the upper support plate USP. The upper support plate USP may move up and down along the plurality of first pillars SPC1. Although not shown, a driving part for moving the upper support plate USP up and down may be coupled to a connection block CB disposed on the upper support plate USP.

[0153] The plurality of column supports CSP may be inserted into the plurality of first connection holes CNH1 defined in the upper support plate USP to be connected to the upper support plate USP. Each of the plurality of column supports CSP may have a cylindrical shape extending in the third direction DR3 to extend upward from the top surface of the upper support plate USP and downward from the bottom surface of the upper support plate USP.

[0154] The plurality of first pillars SPC1 are inserted into the plurality of second connection holes CNH2 defined in the plurality of pillar supports CSP to extend upward from the plurality of pillar supports CSP, respectively. The plurality of pillar supports CSP may move up and down along the plurality of first pillars SPC1 together with the upper support plate USP.

[0155] The second retainer portion HDP2 may be arranged on the first retainer portion HDP1 and may be spaced apart upward from the first retainer portion HDP1. The second retainer portion HDP2 may overlap the first retainer portion HDP1 around the first opening OP1. The bottom surface of the second retainer portion HDP2 may have an inclined surface L_SLP2 at a predetermined inclined angle relative to the first direction DR1.

[0156] The punch support portion PCS may be disposed between the upper support plate USP and the second holder portion HDP2. The punch support portion PCS may be connected to a lower portion of the upper support plate USP. The punch support portion PCS may be disposed between the plurality of first pillars SPC1.

[0157] The punch portion PCH may be disposed on the first holder portion HDP1 to be connected to a lower portion of the punch support portion PCS and may extend in the third direction DR3 . The punch portion PCH may overlap the first opening OP1 .

[0158] A second opening OP2 extending downward may be defined in the second retainer portion HDP2. The second opening OP2 may be defined by passing through the second retainer portion HDP2 in the third direction DR3. The second opening OP2 may overlap with the first opening OP1. A lower portion of the punching portion PCH may be arranged in the second opening OP2. The bottom surface of the punching portion PCH may have an inclined surface L_SLP3 at a predetermined inclined angle relative to the first direction DR1.

[0159] A plurality of second pillars SPC2 may be connected to the second holder portion HDP2 to extend in the third direction DR3. A plurality of second pillars SPC2 may be connected to the punching support portion PCS and the upper support plate USP. A plurality of second pillars SPC2 may be inserted into a plurality of third connection holes CNH3 defined in the punching support portion PCS and the upper support plate USP.

[0160] The punching part PCH, the punching support part PCS and the second holder part HDP2 may move up and down together with the upper support plate USP. The upper support plate USP and the punching support part PCS may move up and down along the plurality of second support posts SPC2.

[0161] The plurality of inclined surfaces U_SLP1, L_SLP2, and L_SLP3 may have the same inclined angle with respect to the first direction DR1. An inclined angle θs defined between each of the plurality of inclined surfaces U_SLP1, L_SLP2, and L_SLP3 and the first direction DR1 may be 10 to 60 degrees.

[0162] Reference Fig.12 and Fig.13 , each of the plurality of second pillars SPC2 may have a cylindrical shape extending in the third direction DR3, and the punching portion PCH may be arranged between the plurality of second pillars SPC2. When viewed on a plane, the punching portion PCH may have a rectangular shape. For example, when viewed on a plane, the punching portion PCH may have a rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR2. Each of the first opening OP1 and the second opening OP2 may have a rectangular shape corresponding to the punching portion PCH.

[0163] Reference Fig.14 The groove G may be disposed between the plurality of first pillars SPC1 arranged in the second direction DR2 to extend in the first direction DR1. A length of the second holder part HDP2 may be greater than a length of the groove G based on the second direction DR2.

[0164] Figures 15 to 20 It is used to explain the use Fig.11 A view of a method for manufacturing a chip on film of an apparatus for manufacturing a chip on film shown in FIG.

[0165] For the convenience of explanation, Fig.15 , Fig.18 and Fig.19 Shown with Fig.12 The corresponding cross-section diagram and Fig.15 , Fig.18 and Fig.19 The first connection hole CNH1, the second connection hole CNH2, and the third connection hole CNH3 are not shown. Fig.17 and Fig. 20 yes Fig.15 and Fig.19 FIG. 1 is an enlarged view of the flexible circuit film FCF overlapping the first opening OP1 shown in FIG. Fig.15 , Fig.18 and Fig.19 The reference numerals of the first pad PD1 and the second pad PD2 are omitted.

[0166] Reference Fig.15 and Fig.16 , the flexible circuit film FCF may be arranged on the top surface of the first holder portion HDP1. In particular, the flexible circuit film FCF may be arranged in the groove G defined in the top surface of the first holder portion HDP1 to extend in the first direction DR1. The second holder portion HDP2 and the punching portion PCH may be arranged on the flexible circuit film FCF.

[0167] The flexible circuit film FCF may include a base film BF, a driving chip D-IC arranged under the base film BF, a plurality of first pads PD1 arranged under the base film BF and connected to the driving chip D-IC, and a plurality of second pads PD2 arranged under the base film BF and connected to the driving chip D-IC.

[0168] The driving chip D-IC, portions of the plurality of first pads PD1, and portions of the plurality of second pads PD2 may be arranged to overlap with the first opening OP1. Thus, the first opening OP1 may expose the driving chip D-IC, portions of the plurality of first pads PD1, and portions of the plurality of second pads PD2.

[0169] Reference Fig.17 , the first pad PD1 may be spaced apart from the driving chip D-IC in the first direction DR1, and the top surface of the first pad PD1 may be arranged higher than the top surface of the driving chip D-IC. The top surface of the second pad PD2 may be arranged lower than the top surface of the driving chip D-IC. The top surface of the driving chip D-IC and the top surface of the second pad PD2 may face the base film BF.

[0170] Reference Fig.18 , the upper support plate USP and the plurality of column supports CSP may move downward along the plurality of first support posts SPC1. In addition, the punch support part PCS, the punch part PCH, the second holder part HDP2, and the plurality of second support posts SPC2 may move downward together with the upper support plate USP.

[0171] The second holder portion HDP2 may move downward to fix the flexible circuit film FCF around the first opening OP1. In particular, the inclined surface L_SLP2 of the bottom surface of the second holder portion HDP2 may contact the top surface of the base film BF around the first opening OP1 to fix the base film BF.

[0172] Reference Fig.19 The upper support plate USP and the plurality of column supports CSP may move downward along the plurality of first pillars SPC1. In addition, the punch support PCS and the punch part PCH may move downward together with the upper support plate USP. The upper support plate USP and the punch support PCS may move downward along the plurality of second pillars SPC2.

[0173] The punching portion PCH may be moved downward and inserted into the first opening OP1. The flexible circuit film FCF may be cut along the edge of the punching portion PCH. The cut flexible circuit film FCF may fall from the first opening OP1 and may be collected by a manufacturer.

[0174] Reference Fig. 20, a portion of the cut flexible circuit film FCF may be formed as a chip on film COF. Since each of the top surface of the first holder part HDP1, the bottom surface of the second holder part HDP2, and the bottom surface of the punching part PCH has an inclined surface, the flexible circuit film FCF may be arranged to be inclined.

[0175] In this case, when the flexible circuit film FCF is cut, the first angle θ1 angled between the first inclined surface SLP1 of the first pad PD1 and the top surface of the first pad PD1 may be determined as a value obtained by subtracting the inclined angle θs from 90 degrees. The first angle θ1 angled between the second inclined surface SLP2 of the base film BF and the top surface of the base film BF may also be determined as a value obtained by subtracting the inclined angle θs from 90 degrees. In addition, the third inclined surface SLP3 and the fourth inclined surface SLP4 may have reverse inclined surfaces relative to the first inclined surface SLP1 and the second inclined surface SLP2, respectively.

[0176] Fig.21 is based on Fig. 20 A cross-sectional view of a chip-on-film manufactured by the method for manufacturing a chip-on-film shown in FIG.

[0177] Reference Fig.21 ,exist Fig.19 A portion of the mid-cut flexible circuit film FCF may be arranged horizontally, and thus, a Figure 5 As a result, one side of the first pad PD1 of the chip on film COF may have a first inclined surface SLP1.

[0178] It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention. Therefore, it is intended that the present invention covers modifications and variations of the invention, provided they fall within the scope of the appended claims and their equivalents. Therefore, to the maximum extent permitted by law, the scope of the present invention is determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

[0179] Industrial Applicability

[0180] A structure in which a plurality of pads are connected by ultrasonic bonding without using an anisotropic conductive film to prevent a short circuit from occurring may be a technology capable of improving the yield of a display device, and therefore, the present invention has high industrial applicability.

Claims

1. A display device, include: Basic membrane; A driving chip, wherein the driving chip is arranged under the base film; a first pad disposed under the base film and connected to the driving chip; as well as a display panel, the display panel comprising a first connection pad directly connected to the first pad, One side of the first pad has a first inclined surface at a first angle relative to a top surface of the first pad, and the first angle is an acute angle, so that a portion of the first connecting pad does not contact the first pad.

2. The display device according to claim 1, in, The one side of the first pad is adjacent to a side of the base film connected to the display panel.

3. The display device according to claim 2, in, The one side of the base film has a second inclined surface at the first angle with respect to the top surface of the base film.

4. The display device according to claim 3, in, The first inclined surface and the second inclined surface are arranged on the same plane.

5. The display device according to claim 2, in, The first pad extends in a first direction intersecting an extending direction of the one side of the base film, and the first angle is set to an angle of 30 to 80 degrees with respect to the first direction.

6. The display device according to claim 5, in, The first pad is provided in plurality, and the plurality of first pads are arranged along the one side of the base film by extending in the first direction.

7. The display device according to claim 5, in, The first pad comprises: a first portion having the first inclined surface defined thereon; and A second portion is provided, wherein the second portion is around the first portion.

8. The display device according to claim 7, in, The first portion is spaced apart from the first connection pad, and the second portion is in contact with the first connection pad.

9. The display device according to claim 7, in, Based on the first direction, the first portion has a length less than or equal to 1 / 2 of a length of the first pad.

10. The display device according to claim 2, further comprising a second pad disposed under the base film and connected to the driving chip, in, One side of the second pad is adjacent to the other side of the base film, the other side of the base film is opposite to the one side of the base film, and the one side of the second pad has a third inclined surface at a second angle relative to the top surface of the second pad, and the second angle is a value obtained by subtracting the first angle from 180 degrees.

11. The display device according to claim 10, in, The other side of the base film has a fourth inclined surface at the second angle with respect to the top surface of the base film.

12. The display device according to claim 11, in, The third inclined surface and the fourth inclined surface are arranged on the same plane. 13 . The display device of claim 1 , further comprising a resin disposed on both sides of the first pad and on both sides of the first connection pad.

14. A method for manufacturing a chip-on-film, the method include: disposing a flexible circuit film on a first holder portion having a first opening defined therein; moving downward a second retainer portion disposed on the flexible circuit film to overlap the first retainer portion around the first opening to fix the flexible circuit film around the first opening; as well as inserting a punching portion disposed on the flexible circuit film to overlap the first opening into the first opening to cut the flexible circuit film along an edge of the punching portion, Wherein, the flexible circuit film comprises: Basic membrane; a driving chip, the driving chip being arranged under the base film; and a first pad disposed under the base film and connected to the driving chip, The first opening exposes a portion of the first pad and the driving chip, and each of a top surface of the first retainer portion, a bottom surface of the second retainer portion, and a bottom surface of the stamping portion has an inclined surface at a predetermined angle relative to a first direction.

15. The method of claim 14, in, The first pad is spaced apart from the driving chip in the first direction, and a top surface of the first pad is arranged higher than a top surface of the driving chip.

16. The method of claim 15, in, The inclined surface forms an angle of 10 to 60 degrees relative to the first direction.

17. The method of claim 16, in, In the cut flexible circuit film, one side of the first pad adjacent to one side of the base film has a first inclined surface at a first angle relative to the first direction, and the first angle is determined by a value obtained by subtracting the predetermined angle from 90 degrees.

18. The method of claim 14, in, The flexible circuit film further includes a second pad connected to the driving chip, wherein a top surface of the second pad is arranged lower than a top surface of the driving chip, and the first opening exposes a portion of the second pad.

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