Fifth generation (5g) new radio channel equalization

Abstract

Apparatuses, systems, and techniques perform signal processing operations in fifth generation ("5G") wireless radio signals. In at least one embodiment, one or more processors equalize one or more 5G wireless radio signals in parallel.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 844,936, filed April 9, 2020, entitled “FIFTH GENERATION (5G) NEW RADIOCHANNEL EQUALIZATION”, the entire contents of which are incorporated herein by reference and used for all purposes. Technical Field

[0003] At least one embodiment relates to processing fifth-generation (5G) new radio signals. For example, at least one embodiment relates to a processor for performing channel equalization on one or more 5G new radio signals according to the various new technologies described herein. Background Technology

[0004] New communication standards have been developed to facilitate information exchange over wireless networks. These standards utilize the use of multiple transmitter or receiver antennas, which presents various signal processing challenges. The technologies for implementing these new communication standards are likely to be improved. Attached Figure Description

[0005] Figure 1 An example communication system for performing channel equalization according to at least one embodiment is shown;

[0006] Figure 2 An example of receiving a data frame according to at least one embodiment is shown;

[0007] Figure 3 An example of sub-slot-level signal equalization for low MIMO is shown according to at least one embodiment;

[0008] Figure 4 Examples of forward and backward substitutions used in signal equalization at a sub-slot level for low MIMO, according to at least one embodiment, are shown.

[0009] Figure 5 An example of sub-slot-level signal equalization for high MIMO is shown according to at least one embodiment;

[0010] Figure 6 An example of reverse substitution used in signal equalization at a sub-slot level for high MIMO, according to at least one embodiment, is shown;

[0011] Figure 7 An example of slot-level signal equalization for high-digital computing is shown according to at least one embodiment;

[0012] Figure 8Examples of other aspects of slot-level signal equalization for high-digital systems according to at least one embodiment are shown;

[0013] Figure 9 An example of reverse substitution used in slot-level signal equalization for high-digital electronics is shown, according to at least one embodiment.

[0014] Figure 10 An example process for channel equalization of one or more 5G radio signals according to at least one embodiment is shown;

[0015] Figure 11 An example data center system according to at least one embodiment is shown;

[0016] Figure 12A An example of an autonomous vehicle according to at least one embodiment is shown;

[0017] Figure 12B The illustration shows an embodiment according to at least one of the embodiments. Figure 12A Examples of camera positions and field of view for autonomous vehicles.

[0018] Figure 12C This is an illustration based on at least one embodiment. Figure 12A A block diagram of an example system architecture for autonomous vehicles.

[0019] Figure 12D The illustration is based on at least one embodiment for use in cloud-based servers and Figure 12A A diagram of a system for communication between autonomous vehicles.

[0020] Figure 13 This is a block diagram illustrating a computer system according to at least one embodiment;

[0021] Figure 14 This is a block diagram illustrating a computer system according to at least one embodiment;

[0022] Figure 15 A computer system according to at least one embodiment is shown;

[0023] Figure 16 A computer system according to at least one embodiment is shown;

[0024] Figure 17A A computer system according to at least one embodiment is shown;

[0025] Figure 17B A computer system according to at least one embodiment is shown;

[0026] Figure 17C A computer system according to at least one embodiment is shown;

[0027] Figure 17D A computer system according to at least one embodiment is shown;

[0028] Figure 17E and Figure 17F A shared programming model according to at least one embodiment is shown;

[0029] Figure 18 An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0030] Figure 19A and Figure 19B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0031] Figure 20A and Figure 20B Additional exemplary graphics processor logic according to at least one embodiment is shown;

[0032] Figure 21 A computer system according to at least one embodiment is shown;

[0033] Figure 22A A parallel processor according to at least one embodiment is shown;

[0034] Figure 22B A partitioning unit according to at least one embodiment is shown;

[0035] Figure 22C A processing cluster according to at least one embodiment is shown;

[0036] Figure 22D A graphics multiprocessor according to at least one embodiment is shown;

[0037] Figure 23 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated;

[0038] Figure 24 A graphics processor according to at least one embodiment is shown;

[0039] Figure 25 It is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0040] Figure 26 At least a portion of a graphics processor according to one or more embodiments is shown;

[0041] Figure 27 At least a portion of a graphics processor according to one or more embodiments is shown;

[0042] Figure 28At least a portion of a graphics processor according to one or more embodiments is shown;

[0043] Figure 29 It is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0044] Figure 30 It is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0045] Figure 31A and Figure 31B The thread execution logic is shown, which includes an array of processing elements of a graphics processor core;

[0046] Figure 32 A parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0047] Figure 33 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated;

[0048] Figure 34 A memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0049] Figure 35 A streaming multiprocessor according to at least one embodiment is illustrated;

[0050] Figure 36 The illustration depicts a network for transmitting data within a 5G wireless communication network according to at least one embodiment;

[0051] Figure 37 The illustration depicts a network architecture for a 5G LTE wireless network according to at least one embodiment;

[0052] Figure 38 This is a diagram illustrating some basic functions of a mobile telecommunications network / system operating according to LTE and 5G principles according to at least one embodiment;

[0053] Figure 39 A radio access network, which may be part of a 5G network architecture according to at least one embodiment, is shown;

[0054] Figure 40 An example illustration of a 5G mobile communication system using multiple different types of devices according to at least one embodiment is provided;

[0055] Figure 41 An example advanced system according to at least one embodiment is shown;

[0056] Figure 42The architecture of a network system according to at least one embodiment is shown;

[0057] Figure 43 Example components of a device according to at least one embodiment are shown;

[0058] Figure 44 An example interface of a baseband circuit according to at least one embodiment is shown;

[0059] Figure 45 An example of an uplink channel according to at least one embodiment is shown;

[0060] Figure 46 The architecture of a network system according to at least one embodiment is shown;

[0061] Figure 47 A control plane protocol stack according to at least one embodiment is shown;

[0062] Figure 48 A user plane protocol stack according to at least one embodiment is shown;

[0063] Figure 49 The components of a core network according to at least one embodiment are shown; and

[0064] Figure 50 Components of a system supporting Network Function Virtualization (NFV) according to at least one embodiment are shown. Detailed Implementation

[0065] Figure 1 An example communication system performing channel equalization according to at least one embodiment is illustrated. In at least one embodiment, the communication system 100 includes a transmitter 102 and a receiver 104. In at least one embodiment, the transmitter 102 and receiver 104 communicate according to a communication standard such as the 5G New Radio (“5G NR”) standard. In at least one embodiment, the transmitter 102 and receiver 104 each include multiple antennas and communicate using a multiple-input multiple-output (“MIMO”) protocol. In at least one embodiment, the multiple transmit and receive antennas are used for simultaneously transmitting one or more signals by the transmitter 102 through a radio channel and receiving the signals at the receiver 104.

[0066] In at least one embodiment, transmitter 102 includes antennas 106a-n to transmit one or more signals. In at least one embodiment, receiver 104 includes antennas 108a-n to receive one or more signals. In at least one embodiment, the antenna, for example... Figure 1 Any one or more of the antennas 106a-n depicted herein transmit one or more data frames (e.g. Figure 2The signal includes the data frame shown. In at least one embodiment, an antenna such as any one or more antennas 108a-n of receiver 104 receives the signal including the one or more data frames.

[0067] In at least one embodiment, a receiver 104 associated with the communication system 100 estimates a signal transmitted by a transmitter 102, wherein the signal may be attenuated by one or more of time-selection artifacts, frequency-selection artifacts, noise, and interference. In at least one embodiment, communication between the transmitter 102 and the receiver 104 uses channel equations. To describe, among which It is an N×1 received signal vector in the frequency domain. It is an M×1 transmitted signal vector in the frequency domain. H is an N×1 vector representing one or more of noise (e.g., additive white Gaussian noise), interference, and channel estimation error, and H is an N×M MIMO channel coupling matrix that provides channel gain between the transmit antenna portion and the receive antenna port combination. In at least one embodiment, H is used for channel equalization, thereby equalizing the received signal to approximately equal to the transmitted signal.

[0068] In at least one embodiment, receiver 104 performs channel equalization to estimate the transmitted signal affected by various artifacts, noise, and interference. In at least one embodiment, the channel equalization is a Physical Uplink Shared Channel (“PUSCH”) channel equalization for 5G radio signals. In at least one embodiment, the channel equalization is performed by a graphics processing unit (“GPU”) or other parallel processing unit (“PPU”). In at least one embodiment, the channel equalization includes estimating transmission errors and is performed on the GPU or other PPU using a least mean square estimation (“MMSE”) algorithm already adapted for parallel processing. In at least one embodiment, the channel equalization is adapted to perform slot-level or sub-slot-level processing. In at least one embodiment, the equalization is adjusted according to the MIMO order to maximize the opportunity for parallel computation on one or more GPUs or other PPUs.

[0069] In at least one embodiment, receiver 104 uses a linear equalization algorithm to perform channel equalization. In at least one embodiment, the receiver uses linear mean square error (“LMMSE”) estimation. In at least one embodiment, LMMSE estimation is performed by LMMSE equalizer 110. In at least one embodiment, LMMSE estimation averagely minimizes the error between the actual transmitted signal and its estimate at receiver 102, for example, by minimizing In at least one embodiment, the forward channel equation can be used to transform the received vector. Represented as A linear transformation is performed, and by using this linear transformation, a solution to the channel equations can be obtained using bounded delay. In at least one embodiment, this result is achieved using LMMSE filter coefficient calculations expressed as matrix-to-matrix and matrix-to-vector operations suitable for execution on a GPU or other PPU. In at least one embodiment, this includes solving the channel equations using augmented matrices and techniques such as Cholesky or LU decomposition. In at least one embodiment, these operations are performed by receiver 102 using a GPU or other PPU to perform channel estimation of the MIMO signal by executing tasks in parallel on said GPU or PPU.

[0070] Figure 2 An example of receiving a data frame according to at least one embodiment is shown. In at least one embodiment, an antenna in a MIMO system receives one or more data frames, such as data frame 200. In at least one embodiment, data frame 200 includes a physical resource block (“PRB”) 204. In at least one embodiment, the physical resource block (“PRB”) includes a plurality of subcarriers associated with a time slot. In at least one embodiment, the PRB includes 12 consecutive subcarriers in the frequency domain.

[0071] In at least one embodiment, symbol 202 is an orthogonal frequency division multiplexing (“OFDM”) symbol.

[0072] In at least one embodiment, a time slot includes multiple symbols 202. In at least one embodiment, a time slot includes fourteen ODFM symbols. In at least one embodiment, the symbols may be demodulation reference symbols (“DMRS”), data symbols, or some other symbol type. In at least one embodiment, sub-time slots correspond to symbols, such as ODFM symbols, and a time slot includes multiple sub-time slots.

[0073] In at least one embodiment, the GPU or other PPU performs time-slot-level and sub-time-slot-level processing of 5G signals based at least in part on one or more parallelization techniques described herein.

[0074] In at least one embodiment, for high MIMO cases, the receive vector is equalized per GPU or other PPU thread block. In at least one embodiment, the vector is equalized at the subcarrier level to produce a soft estimate of the transmitted signal.

[0075] In at least one embodiment, for low MIMO cases, parallelism is achieved by processing all subcarriers in the PRB within a single thread block of the GPU or other PPU. In at least one embodiment, when high-signal performance is present, the GPU or other PPU can achieve and utilize parallelism by processing multiple symbols simultaneously. In at least one embodiment, this is achieved by performing slot-level equalization.

[0076] In at least one embodiment, the GPU or other PPU uses an augmented matrix to perform equalization to solve for the MMSE coefficients and residuals in a single pass. In at least one embodiment, the MMSE coefficients and residual matrices are combined into an augmented matrix and then transformed. In at least one embodiment, joint computation reduces serial computation, while tiling increases parallelism to better utilize the GPU or other PPU. In at least one embodiment, the equalization is performed within a thread block. In at least one embodiment, the augmented matrix is ​​stored in shared memory accessible to multiple GPUs or PPUs. In at least one embodiment, modifications to the augmented matrix are performed in-situ. In at least one embodiment, the augmented matrix is ​​overwritten with an intermediate matrix in the shared memory.

[0077] In at least one embodiment, a GPU or other PPU is used to perform channel equalization for each subcarrier in parallel across multiple subcarriers. In at least one embodiment, cross-subcarrier channel equalization is performed for high MIMO scenarios. In at least one embodiment, a GPU or other PPU is used to perform channel equalization across a PRB containing multiple subcarriers (e.g., 12 subcarriers). In at least one embodiment, cross-PRB channel equalization is used for low MIMO scenarios. In at least one embodiment, cross-subcarrier channel equalization is performed by a task executed using multiple GPU or PPU thread blocks.

[0078] In at least one embodiment, sub-slot equalization is used with low power values ​​having medium slot durations or high power values ​​having short slot durations. In at least one embodiment, equalizer coefficient calculation is separated from coefficient application. In at least one embodiment, this approach reduces coefficient recalculation.

[0079] In at least one embodiment, sub-slot-level processing allows pipelined time slot arrivals to be processed through the physical layer. In at least one embodiment, sub-slot-level processing includes symbol-based processing. This approach can be flexible because, in at least one embodiment, it allows equalization to continue without waiting for the complete set of data symbols to arrive.

[0080] In at least one embodiment, slot-level equalization is used with high-number algorithms having short slot durations. In at least one embodiment, slot-level equalization includes merging equalizer coefficient calculation and coefficient application. In at least one embodiment, avoiding explicit coefficient calculation saves storage space and reduces memory bandwidth consumption for loading coefficients. In at least one embodiment, equalizing all data symbols for one slot at a time can increase available parallelism, thereby improving the utilization of GPUs or other PPUs.

[0081] Figure 3An example of signal equalization for a sub-slot level for low MIMO is shown according to at least one embodiment.

[0082] In at least one embodiment, such as Figure 3 As depicted in Example 300, channel equalization is performed via LMMSE estimation, for example... in It is a soft estimation vector. It is the receiving vector, and C LMMSE The MMSE coefficient matrix can be calculated as follows:

[0083]

[0084] Where H is the estimate of the channel coupling matrix, It is the signal energy covariance matrix. It is the average noise covariance matrix.

[0085] In at least one embodiment, the LMMSE equations are solved using a Cholesky decomposition with forward and backward substitutions. In at least one embodiment, this method is used for low-order MIMO cases.

[0086] In at least one embodiment, the intermediate matrix M 306 is calculated as follows: In at least one embodiment, the enhanced Gram matrix G 308 is calculated by Gram matrix calculation 302 as follows: In at least one embodiment, G 308 is subjected to LDL or Cholesky decomposition without square roots, such as G = U H DU.

[0087] In at least one embodiment, for matrix 310 in the i-th iteration of LDL decomposition 304, a single thread of the GPU or PPU thread block computes the i-th diagonal item of matrix portion D, followed by the upper diagonal element of the i-th row of matrix portion U. In at least one embodiment, multiple GPU or PPU threads compute the items of matrix portion D or matrix portion U in parallel. In at least one embodiment, the matrix portion is stored in shared memory accessible by the multiple GPU or PPU threads.

[0088] Figure 4 Examples of forward and backward substitutions used in signal equalization at a sub-slot level for low MIMO, according to at least one embodiment, are illustrated.

[0089] In at least one embodiment, according to Example 400, the forward substitution on the augmented matrix involves equation U H [J|K] = [I|M], where U H 402 involves part U of matrix 310, such as Figure 3As shown, M 410 corresponds to Figure 3 The intermediate matrix M is 306, and I408 is the identity matrix. In at least one embodiment, [I|M] corresponds to an augmented matrix containing a combination of I and M.

[0090] In at least one embodiment, the forward substitution further includes solving for intermediate matrices J 404 and K 406. In at least one embodiment, [J|K] corresponds to an augmented matrix containing a combination of J and K.

[0091] In at least one embodiment, the backward substitution on the augmented matrix involves the equation Where D 414 and U 412 involve parts D and U of matrix 310, such as Figure 3 As shown, matrices J 404 and K 406 are solved in the forward substitution. In at least one embodiment, the backward substitution further includes solving... and C LMMSE 416, 418, where G -1 Involving Figure 3 The G 308 shown.

[0092] Figure 5 Example 500 of signal equalization at the sub-slot level for high-order MIMO is illustrated according to at least one embodiment. In at least one embodiment, equalizer coefficient calculation is decoupled from coefficient application, as shown in Example 500. In at least one embodiment, coefficient application is performed at the ODFM symbol level to allow for symbol-by-symbol processing.

[0093] In at least one embodiment, LMMSE estimation is used to perform residual estimation and channel equalization, for example... in It is a soft estimation vector. It is the receiving vector, and C LMMSE It is the MMSE coefficient matrix, which can be calculated as follows: Where H is the estimate of the channel coupling matrix, It is the signal energy covariance matrix. It is the average noise covariance matrix.

[0094] In at least one embodiment, for high-order MIMO, LU decomposition and back-substitution are used to solve C. LMMSE In at least one embodiment, LU decomposition includes computing an intermediate matrix. In at least one embodiment, the intermediate matrix M 512 is calculated by the intermediate matrix calculation module 506. In at least one embodiment, the module includes processor-executable instructions compatible with execution on one or more GPUs or other PPUs. In at least one embodiment, the executable instructions are executed in parallel by one or more GPUs or other PPUs.

[0095] In at least one embodiment, the Gram matrix is ​​calculated as follows: In at least one embodiment, the Gram matrix G 508 is calculated by the Gram matrix calculation module 502. In at least one embodiment, the module includes processor-executable instructions compatible with execution on one or more GPUs or other PPUs.

[0096] In at least one embodiment, the combination comprises an augmented matrix including G 508, I 510, and M 512, where I 510 is the identity matrix.

[0097] In at least one embodiment, the joint LU decomposition 514 is performed on the augmented matrix, transforming [G|I|M] into [U|L]. -1 |F], where U = L\G and F = L\M.

[0098] Figure 6 An example of backward substitution used in signal equalization for a sub-slot level of high MIMO according to at least one embodiment is shown.

[0099] In at least one embodiment, according to Example 600, a backward substitution is performed on the augmented matrix to solve for the coefficients and error values ​​associated with the LMMSE estimate. In at least one embodiment, the augmented matrix is ​​decomposed using LU decomposition. In at least one embodiment, the backward substitution includes solving for the residual covariance and the soft estimate:

[0100]

[0101]

[0102] In at least one embodiment, the backward replacement module 608 pairs the augmented matrix [U|L] -1 |F] Perform a backward substitution to obtain 610 and C LMMSE 612. In at least one embodiment, elements U 602, L -1 604 and F 606 correspond to Figure 5 U 516 and L depicted in -1 518 and F 520.

[0103] In at least one embodiment, the module includes processor-executable instructions compatible with execution on one or more GPUs or other PPUs. In at least one embodiment, the executable instructions are executed in parallel by one or more GPUs or other PPUs.

[0104] In at least one embodiment, parallel computing 610 and C LMMSE612, where each of the multiple threads in the thread block solves the joint matrix. A column. In at least one embodiment, By applying C LMMSE To calculate:

[0105]

[0106] Where i = 0, 1, 2...N d -1.

[0107] Figure 7 An example of equalization for slotted signals for high-digital signals according to at least one embodiment is shown.

[0108] In at least one embodiment, according to Example 700, data symbols in a given frequency bin are equalized to increase available parallelism. In at least one embodiment, all data symbols in the frequency bin are equalized. In at least one embodiment, equalization is performed using LMMSE estimation via the following formula:

[0109]

[0110] Where H is the estimate of the channel coupling matrix, It is the signal energy covariance matrix. Related to average noise power, It is the receive vector. It is a soft estimation vector.

[0111] In at least one embodiment, slot-level equalization is performed by the receiver using LMMSE with LU decomposition. In at least one embodiment, slot-level equalization is performed by the receiver using LMMSE with Cholesky decomposition.

[0112] In at least one embodiment, multiple data frames 702 are received. In at least one embodiment, multiple data symbols are extracted from a given frequency bin f 704 and combined into a matrix Y. f 706. In at least one embodiment, all data symbols in the frequency bin are extracted and combined into Y. f 706.

[0113] In at least one embodiment, the intermediate matrix is ​​calculated as follows: In at least one embodiment, the channel estimation module 708 calculates... Then it can be based on Perform residual estimation and channel equalization. In at least one embodiment, the module includes processor-executable instructions compatible with execution on one or more GPUs or other PPUs. In at least one embodiment, the executable instructions are executed in parallel by one or more GPUs or other PPUs.

[0114] Figure 8 Example 800 illustrates a further aspect of slot-level signal equalization for high-digital signals according to at least one embodiment.

[0115] In at least one embodiment, the enhanced Gram matrix G 806 is calculated as:

[0116]

[0117] In at least one embodiment, matrix B 810 is then computed and combined into an augmented matrix [G|I|B]. In at least one embodiment, G 806 is computed by Gram matrix computation module 802 and matrix B 810 is computed by RHS matrix computation module 804. In at least one embodiment, the module includes processor-executable instructions compatible with execution on one or more GPUs or other PPUs. In at least one embodiment, the executable instructions are executed in parallel by one or more GPUs or other PPUs.

[0118] In at least one embodiment, LU decomposition is performed on the augmented matrix [G|I|B] to form [U|L] -1 |E], where U814, L816, and E818 are related according to U = L\G and E = L\B. In at least one embodiment, LU decomposition is performed by a joint LU decomposition module 812. In at least one embodiment, the module includes processor-executable instructions compatible with execution on one or more GPUs or other PPUs. In at least one embodiment, the executable instructions are executed in parallel by one or more GPUs or other PPUs.

[0119] Figure 9 An example 900 of backward substitution used in slotted-level signal equalization for high-resolution electromagnetism is illustrated according to at least one embodiment. In at least one embodiment, given the augmented matrix of LU decomposition, backward substitution solves for the residual covariance. and soft estimation

[0120]

[0121] In at least one embodiment, parallel computing and In at least one embodiment, each thread in the thread block solves for a joint matrix.

[0122] In at least one embodiment, elements U 902 and L -1 904 and E 906 correspond to Figure 8 U 802 and L depicted in -1 804 and E 806. In at least one embodiment, the backward replacement module 908 uses backward replacement to solve... 910 and 912. In at least one embodiment, as Figure 9 The backward replacement is performed as shown and described above. In at least one embodiment, the module includes processor-executable instructions compatible with execution on one or more GPUs or other PPUs. In at least one embodiment, the executable instructions are executed in parallel by one or more GPUs or other PPUs.

[0123] Figure 10 An example process for channel equalization of one or more 5G radio signals according to at least one embodiment is illustrated. Although Figure 10 The steps are depicted as a sequence, but the depicted sequence should not be construed as limiting the scope of potential embodiments to those conforming to the depicted sequence. For example, the depicted steps may be reordered or performed in parallel except where logically necessary. In at least some embodiments, certain steps may be omitted. In at least some embodiments, additional steps may be added.

[0124] In at least one embodiment, Figure 6 Certain steps or operations described are performed by one or more parallel processing devices. In at least one embodiment, the parallel processing device includes one or more PPUs. In at least one embodiment, the one or more PPUs are one or more GPUs. In at least one embodiment, the parallel processing device includes memory for storing physical channel descriptors and other information provided by the CPU prior to time slot processing time. In at least one embodiment, the parallel processing device includes circuitry and / or software capable of scheduling and executing task graphs, wherein the execution of the task graphs is performed at least in part by one or more parallel processing units.

[0125] At 1002, in at least one embodiment, a parallelization technique is selected based on MIMO configuration. In at least one embodiment, the MIMO configuration relates to the number of antennas used for transmitting or receiving signals. In at least one embodiment, the MIMO configuration is associated with multiple streams. At 1004, in at least one embodiment, a parallelization technique is selected based on 5G NR digitization. In at least one embodiment, a parallelization technique is selected based on both MIMO configuration and 5G NR digitization. In at least one embodiment, a specific parallelization technique is pre-selected or pre-configured based on MIMO configuration or digitization. In at least one embodiment, a parallelization technique is dynamically selected. In at least one embodiment, a parallelization technique is dynamically selected based on the MIMO configuration or digitization associated with one or more signals whose transmission errors are to be estimated. In at least one embodiment, dynamic selection is performed by a receiving device for performing channel equalization.

[0126] In 1006, in at least one embodiment, the receiving device receives one or more 5G NR radio signals. In at least one embodiment, the reception of the one or more signals is in accordance with a predetermined MIMO configuration or digitization, such as the MIMO configuration or digitization on which the parallelization technique is based.

[0127] In at least one embodiment, for a low MIMO configuration, the selected parallelization technique includes, based on... Figure 3 and Figure 4 The described technique performs channel equalization. In at least one embodiment, channel equalization includes recovery of the transmitted signal and estimation of the residual.

[0128] In at least one embodiment, for some high MIMO configurations, the selected parallelization technique includes, based on... Figure 5 and Figure 6 The techniques described are used to perform channel equalization.

[0129] In at least one embodiment, for some high MIMO configurations, the selected parallelization technique includes, based on... Figure 7 , Figure 8 and Figure 9 The techniques described are used to perform channel equalization.

[0130] At 1008, the receiving device schedules the execution of one or more GPU or other PPU tasks using a selected parallelization technique to perform LMMSE estimation. In at least one embodiment, the central processing unit (“CPU”) of the receiving device schedules tasks to perform LMMSE estimation on one or more GPUs or other PPUs using parallel execution. In at least one embodiment, the combination of tasks may be based on a selected parallelization technique. For example, in at least one embodiment, matrix computation may be subdivided according to the various techniques described with respect to the figures.

[0131] In 1010, the receiving device uses the parallel execution of scheduled tasks on one or more GPUs or other PPUs to perform LMMSE estimation.

[0132] Data Center

[0133] Figure 11 An example data center 1100 that can be used with at least one embodiment is shown. In at least one embodiment, the data center 1100 includes a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.

[0134] In at least one embodiment, such as Figure 11 As shown, the data center infrastructure layer 1110 may include a resource coordinator 1112, grouped computing resources 1114, and node computing resources (“nodes CR”) 1116(1)-1116(N), where “N” represents any integer, a positive integer. In at least one embodiment, nodes CR 1116(1)-1116(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 1116(1)-1116(N) may be servers having one or more of the aforementioned computing resources.

[0135] In at least one embodiment, the grouped computing resources 1114 may include individual groups (not shown) of node CRs housed in one or more racks, or a plurality of racks (also not shown) housed in data centers in various geographical locations. In at least one embodiment, the individual groups of node CRs within the grouped computing resources 1114 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0136] In at least one embodiment, resource coordinator 1112 may be configured or otherwise control one or more nodes CR1116(1)-1116(N) and / or grouped computing resources 1114. In at least one embodiment, resource coordinator 1112 may include a Software Design Infrastructure (“SDI”) management entity for data center 1100. In at least one embodiment, resource coordinator may include hardware, software, or some combination thereof.

[0137] In at least one embodiment, such as Figure 11 As shown, framework layer 1120 includes a job scheduler 1132, a configuration manager 1134, a resource manager 1136, and a distributed file system 1138. In at least one embodiment, framework layer 1120 may include a framework of software 1132 supporting software layer 1130 and / or one or more applications 1142 of application layer 1140. In at least one embodiment, software 1132 or application 1142 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1120 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark, which can utilize distributed file system 1138 for large-scale data processing (e.g., “big data”). TM (Hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1132 may include a Spark driver to facilitate the scheduling of workloads supported by various layers of data center 1100. In at least one embodiment, the configuration manager 1134 may be able to configure different layers, such as software layer 1130 and framework layer 1120 including Spark and a distributed file system 1138 for supporting large-scale data processing. In at least one embodiment, the resource manager 1136 is able to manage cluster or group computing resources mapped to or allocated to support distributed file system 1138 and job scheduler 1132. In at least one embodiment, cluster or group computing resources may include group computing resources 1114 on data center infrastructure layer 1110. In at least one embodiment, the resource manager 1136 may coordinate with resource coordinator 1112 to manage these mapped or allocated computing resources.

[0138] In at least one embodiment, the software 1132 included in software layer 1130 may include software used by at least a portion of nodes CR1116(1)-1116(N), grouped computing resources 1114, and / or the distributed file system 1138 of framework layer 1120. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0139] In at least one embodiment, one or more applications 1142 included in application layer 1140 may include one or more types of applications used by at least a portion of nodes CR1116(1)-1116(N), grouped computing resources 1114, and / or the distributed file system 1138 of framework layer 1120. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0140] In at least one embodiment, any of the configuration manager 1134, resource manager 1136, and resource coordinator 1112 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 1100 and can prevent underutilization and / or poor performance of the data center.

[0141] In at least one embodiment, data center 1100 may include tools, services, software, or other resources to train one or more machine learning models or to use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 1100. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 1100, by using weight parameters calculated through one or more training techniques described herein.

[0142] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0143] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0144] Autonomous vehicles

[0145] Figure 12A Examples of autonomous vehicles 1200 according to at least one embodiment are shown. In at least one embodiment, the autonomous vehicle 1200 (which may alternatively be referred to herein as "vehicle 1200") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle capable of accommodating one or more passengers. In at least one embodiment, vehicle 1200 may be a semi-tractor-trailer for hauling goods. In at least one embodiment, vehicle 1200 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0146] Autonomous vehicles can be described according to the levels of automation defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation in their standard “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., standard number J3016-2011206, published June 15, 2011; standard number J3016-201609, published September 30, 2016; and previous and future versions of this standard). In one or more embodiments, vehicle 1200 may be able to function according to one or more of the levels of autonomous driving from Level 1 to Level 5. For example, in at least one embodiment, vehicle 1200 may be able to perform conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5).

[0147] In at least one embodiment, vehicle 1200 may include, but is not limited to, components such as chassis, body, wheels (e.g., 2, 4, 6, 12, 112, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1200 may include, but is not limited to, propulsion system 1250, such as an internal combustion engine, a hybrid powertrain, a fully electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1250 may be connected to the drivetrain of vehicle 1200, which may include, but is not limited to, a transmission, to enable propulsion of vehicle 1200. In at least one embodiment, propulsion system 1250 may be controlled in response to receiving a signal from throttle / accelerator 1252.

[0148] In at least one embodiment, when the propulsion system 1250 is operating (e.g., when the vehicle 1200 is traveling), the steering system 1254 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 1200 (e.g., along a desired path or route). In at least one embodiment, the steering system 1254 may receive signals from the steering actuator 1256. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, the brake sensor system 1246 may be used to operate the vehicle brakes in response to signals received from the brake actuator 1248 and / or brake sensors.

[0149] In at least one embodiment, the controller 1236 may include, but is not limited to, one or more system-on-chips (“SoCs”). Figure 12AA controller 1236 (not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1200. For example, in at least one embodiment, controller 1236 may send signals to operate vehicle braking via brake actuator 1248, to operate steering system 1254 via one or more steering actuators 1256, and to operate propulsion system 1250 via one or more throttles / accelerators 1252. In at least one embodiment, one or more controllers 1236 may include one or more onboard (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a driver in driving vehicle 1200. In at least one embodiment, one or more controllers 1236 may include a first controller 1236 for autonomous driving functions, a second controller 1236 for functional safety functions, a third controller 1236 for artificial intelligence functions (e.g., computer vision), a fourth controller 1236 for infotainment functions, a fifth controller 1236 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 1236 may handle two or more of the above functions, and two or more controllers 1236 may handle a single function and / or any combination thereof.

[0150] In at least one embodiment, one or more controllers 1236 provide signals for controlling one or more components and / or systems of vehicle 1200 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data can be received from sensors, including but not limited to one or more Global Navigation Satellite System (“GNSS”) sensors 1258 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 1260, one or more ultrasonic sensors 1262, one or more LIDAR sensors 1264, one or more inertial measurement unit (IMU) sensors 1266 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1296, one or more stereo cameras 1268, one or more wide-angle cameras 1270 (e.g., fisheye cameras), one or more infrared cameras 1272, one or more surround cameras 1274 (e.g., 360-degree cameras), and remote cameras (…). Figure 12A (not shown in the image), medium-range camera ( Figure 12A(Not shown in the diagram) One or more speed sensors 1244 (e.g., for measuring the speed of vehicle 1200), one or more vibration sensors 1242, one or more steering sensors 1240, one or more brake sensors (e.g., as part of brake sensor system 1246) and / or other sensor types are received.

[0151] In at least one embodiment, one or more controllers 1236 may receive input (e.g., represented by input data) from the dashboard 1232 of the vehicle 1200 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1234, a voice signaler, a speaker, and / or other components of the vehicle 1200. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high-definition map). Figure 12A The HMI display 1234 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about the driving operation of the vehicle that has been, is being, or will be made (e.g., changing lanes now, exiting exit 34B within two miles, etc.). For example, in at least one embodiment, the HMI display 1234 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about the driving operation of the vehicle that has been, is being, or will be made (e.g., changing lanes now, exiting exit 34B within two miles, etc.).

[0152] In at least one embodiment, vehicle 1200 further includes a network interface 1224 that can communicate over one or more networks using one or more wireless antennas 1226 and / or one or more modems. For example, in at least one embodiment, network interface 1224 may be able to communicate over Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multicarrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 1226 may also enable communication between objects in the environment (e.g., vehicles, mobile devices) using one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (hereinafter “LPWAN”) (e.g., LoRaWAN, SigFox, etc. protocols).

[0153] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0154] Figure 12B The illustration shows an embodiment according to at least one of the embodiments. Figure 12A Examples of camera positions and fields of view for the autonomous vehicle 1200. In at least one embodiment, the camera and its respective field of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 1200.

[0155] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera suitable for use with components and / or systems of vehicle 1200. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 120 fps, 240 fps, etc. In at least one embodiment, the camera may be able to use a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red-to-clear (“RCCC”) color filter array, a red-to-clear-blue (“RCCB”) color filter array, a red-blue-green (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera with an array of RCCC, RCCB and / or RBGC color filters, may be used to improve photosensitivity.

[0156] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0157] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (3D-printed) assembly, to cut out stray light and reflections within the vehicle 1200 (e.g., reflections from the dashboard in the windshield mirror), which may interfere with the camera's image data capture capabilities. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly may be 3D-printed custom-made such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras may also be integrated within four pillars at each corner of the cabin.

[0158] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view including a portion of the environment in front of the vehicle 1200 can be used for surround view and, with the assistance of one or more controllers 1236 and / or control SoCs, to help identify forward paths and obstacles, thereby providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (e.g., traffic sign recognition).

[0159] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal-oxide-semiconductor”) color imager. In at least one embodiment, a wide-angle camera 1270 can be used to sense objects entering from the periphery (e.g., pedestrians, crosswalkers, or bicycles). Although in Figure 12B Only one wide-angle camera 1270 is shown; however, in other embodiments, the vehicle 1200 may have any number (including zero) of wide-angle cameras. In at least one embodiment, any number of remote cameras 1298 (e.g., a pair of remote stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, the remote camera 1298 can also be used for object detection and classification, as well as basic object tracking.

[0160] In at least one embodiment, any number of stereo cameras 1268 may also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1268 may include an integrated control unit comprising a scalable processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 1200, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1268 may include, but are not limited to, a compact stereo vision sensor, which may include, but is not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that can measure the distance from the vehicle 1200 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1268 may also be used in addition to those described herein.

[0161] In at least one embodiment, a camera (e.g., a side-view camera) having a field of view including a portion of the environment on the side of the vehicle 1200 can be used for surround viewing, thereby providing information for creating and updating the occupied grid, and generating a side collision warning. For example, in at least one embodiment, a surround camera 1274 (e.g., such as...) Figure 12B The four surround cameras 1274 shown can be positioned on the vehicle 1200. In at least one embodiment, one or more surround cameras 1274 may include, but are not limited to, any number and combination of wide-angle cameras 1270, one or more fisheye lenses, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye lens cameras may be located at the front, rear, and sides of the vehicle 1200. In at least one embodiment, the vehicle 1200 may use three surround cameras 1274 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., forward-facing cameras) as a fourth surround-view camera.

[0162] In at least one embodiment, a camera (e.g., a rear-view camera) having a field of view including a portion of the environment behind the vehicle 1200 can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy raster. In at least one embodiment, a wide variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1298 and / or one or more mid-range cameras 1276, one or more stereo cameras 1268, one or more infrared cameras 1272, etc.), as described herein.

[0163] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0164] Figure 12C The illustration shows an embodiment according to at least one of the embodiments. Figure 12A A block diagram of an example system architecture for an autonomous vehicle 1200. In at least one embodiment, Figure 12C Each of one or more components, one or more features, and one or more systems of vehicle 1200 is shown as connected via bus 1202. In at least one embodiment, bus 1202 may include, but is not limited to, a CAN data interface (which may alternatively be referred to herein as a "CAN bus"). In at least one embodiment, CAN may be a network within vehicle 1200 used to help control various features and functions of vehicle 1200, such as brake actuation, acceleration, braking, steering, windshield wipers, etc. In one embodiment, bus 1202 may be configured to have dozens or even hundreds of nodes, each node having its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1202 can be read to find steering wheel angle, ground speed, engine rotation speed ("RPM"), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1202 may be an ASIL B compliant CAN bus.

[0165] In at least one embodiment, FlexRay and / or Ethernet may be used in addition to or from CAN. In at least one embodiment, there may be any number of buses 1202, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 1202 may be used to perform different functions and / or may be used for redundancy. For example, a first bus 1202 may be used for a collision avoidance function, and a second bus 1202 may be used for actuation control. In at least one embodiment, each bus 1202 may communicate with any component of vehicle 1200, and two or more buses 1202 may communicate with the same component. In at least one embodiment, each of any number of system-on-chip (“SoC”) 1204, each of one or more controllers 1236, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of vehicle 1200) and may be connected to a common bus, such as a CAN bus.

[0166] In at least one embodiment, vehicle 1200 may include one or more controllers 1236, such as those described herein. Figure 12A As described above. In at least one embodiment, controller 1236 can be used for a variety of functions. In at least one embodiment, controller 1236 can be coupled to any of various other components and systems of vehicle 1200 and can be used to control vehicle 1200, artificial intelligence of vehicle 1200, infotainment and / or other functions of vehicle 1200.

[0167] In at least one embodiment, vehicle 1200 may include any number of SoCs 1204. In at least one embodiment, each of the SoCs 1204 may include, but is not limited to, a central processing unit (“one or more CPUs”) 1206, a graphics processing unit (“one or more GPUs”) 1208, one or more processors 1210, one or more caches 1212, one or more accelerators 1214, one or more data storage devices 1216, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1204 may be used to control vehicle 1200 on various platforms and systems. For example, in at least one embodiment, one or more SoCs 1204 may be combined with a high-definition (“HD”) map 1222 in a system (e.g., the system of vehicle 1200), the high-definition map 1222 being accessible from one or more servers via a network interface 1224. Figure 12C(Not shown in the image) Get map refresh and / or update.

[0168] In at least one embodiment, one or more CPUs 1206 may include CPU clusters or CPU complexes (which may alternatively be referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1206 may include multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more CPUs 1206 may include eight cores in an intercoupled multiprocessor configuration. In at least one embodiment, one or more CPUs 1206 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., 2MB L2 cache). In at least one embodiment, one or more CPUs 1206 (e.g., CCPLEX) may be configured to support simultaneous cluster operation, such that any combination of clusters of one or more CPUs 1206 can be active at any given time.

[0169] In at least one embodiment, one or more CPUs 1206 may implement power management functions, including but not limited to one or more of the following features: automatic clock gating of individual hardware modules to conserve dynamic power when idle; clock gating of each core when the core is not actively executing instructions due to executing Wait for Interrupt (“WFI”) / Event Wait (“WFE”) instructions; independent power supply for each core; clock gating of each core cluster when all cores are clock-gated or power-gated; and / or power gating of each core cluster when all cores are power-gated. In at least one embodiment, one or more CPUs 1206 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state for cores, clusters, and CCPLEX inputs. In at least one embodiment, the processing core may support a simplified power state input sequence in software, wherein the work is offloaded to the microcode.

[0170] In at least one embodiment, one or more GPUs 1208 may include integrated GPUs (or "iGPUs" herein). In at least one embodiment, one or more GPUs 1208 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1208 may use an enhanced tensor instruction set. In one embodiment, one or more GPUs 1208 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a Level 1 ("L1") cache (e.g., an L1 cache with at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512KB of storage capacity). In at least one embodiment, one or more GPUs 1208 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1208 may use a computation application programming interface (API). In at least one embodiment, one or more GPUs 1208 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0171] In at least one embodiment, one or more GPU 1208s may be power-optimized for optimal performance in automotive and embedded use cases. For example, in one embodiment, one or more GPU 1208s may be fabricated on FinFET (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores divided into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores may be divided into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 12 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level-zero (“L0”) instruction cache, a thread bundle scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix computation and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0172] In at least one embodiment, one or more GPUs 1208 may include high-bandwidth memory (“HBM”) and / or a 16GB HBM2 memory subsystem to provide a peak storage bandwidth of approximately 900GB / s in some examples. In at least one embodiment, in addition to or instead of HBM memory, synchronous graphics random access memory (“SGRAM”) may be used, such as graphics double data rate type five synchronous random access memory (“GDDR5”).

[0173] In at least one embodiment, one or more GPUs 1208 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support may be used to allow one or more GPUs 1208 to directly access the page tables of one or more CPUs 1206. In at least one embodiment, when a memory management unit (“MMU”) of one or more GPUs 1208 experiences a miss, an address translation request may be sent to one or more CPUs 1206. In response, in at least one embodiment, two CPUs of one or more CPUs 1206 may look up the virtual-physical mapping of the address in their page tables and transfer the translation back to one or more GPUs 1208. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for the memory of both one or more CPUs 1206 and one or more GPUs 1208, thereby simplifying the programming of one or more GPUs 1208 and the porting of applications to one or more GPUs 1208.

[0174] In at least one embodiment, one or more GPUs 1208 may include any number of access counters that can track the frequency of memory accesses by one or more GPUs 1208 to other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently, thereby improving the efficiency of shared memory ranges between processors.

[0175] In at least one embodiment, one or more SoCs 1204 may include any number of caches 1212, including those described herein. For example, in at least one embodiment, one or more caches 1212 may include a Level 3 (“L3”) cache available for one or more CPUs 1206 and one or more GPUs 1208 (e.g., connected to CPUs 1206 and GPUs 1208). In at least one embodiment, one or more caches 1212 may include a write-back cache that can, for example, track the state of a line using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, according to an embodiment, the L3 cache may include 4 MB of memory or more.

[0176] In at least one embodiment, one or more SoCs 1204 may include one or more accelerators 1214 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1204 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1208 and offload some tasks from one or more GPUs 1208 (e.g., freeing up more cycles from one or more GPUs 1208 to perform other tasks). In at least one embodiment, one or more accelerators 1214 may be used for a target workload (e.g., perceptual, convolutional neural network (“CNN”), recurrent neural network (“RNN”), etc.) that is sufficiently stable to withstand acceleration testing. In at least one embodiment, the CNN may include region-based or region convolutional neural networks (“RCNN”) and fast RCNN (e.g., for object detection) or other types of CNNs.

[0177] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more Tensor Processing Units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for specific sets of neural network types and floating-point operations and inference. In at least one embodiment, one or more DLAs are designed to provide higher performance per millimeter than typical general-purpose GPUs and typically significantly outperform CPUs. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions supporting, for example, INT12, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can execute neural networks, particularly CNNs, quickly and efficiently on processed or unprocessed data for any of the various functions, including, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection, recognition, and identification using data from microphone 1296; CNNs for face recognition and vehicle owner recognition using data from camera sensors; and / or CNNs for safety and / or safety-related events.

[0178] In at least one embodiment, the DLA can perform any function of one or more GPUs 1208, and by using an inference accelerator, for example, the designer can target one or more DLAs or one or more GPUs 1208 for any function. For example, in at least one embodiment, the designer can concentrate the CNN processing and floating-point operations on one or more DLAs, leaving other functions to one or more GPUs 1208 and / or one or more accelerators 1214.

[0179] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) may include programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1238, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0180] In at least one embodiment, the RISC core can interact with an image sensor (e.g., the image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, the RISC core may use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or storage devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0181] In at least one embodiment, DMA enables components of the PVA to access system memory independently of one or more CPUs 1206. In at least one embodiment, DMA can support any number of features for providing optimization to the PVA, including but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0182] In at least one embodiment, the vector processor may be a programmable processor designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may serve as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as a Single Instruction Multiple Data (“SIMD”) or Very Long Instruction Word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0183] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute general-purpose computer vision algorithms, except on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on a single image, or even execute different algorithms on a sequence of images or portions of images. In at least one embodiment, among others, any number of PVAs may be included in the hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error-correcting code (“ECC”) memory to enhance overall system security.

[0184] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory (“SRAM”) for providing high-bandwidth, low-latency SRAM to one or more accelerators 1214. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, comprising, for example, but not limited to, eight field-configurable memory blocks accessible to both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone providing high-speed access to the memory for both the PVA and DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using an APB).

[0185] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as bursty communication for continuous data transmission. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 615012 standard.

[0186] In at least one embodiment, one or more SoCs 1204 may include a real-time eye-tracking hardware accelerator. In at least one embodiment, the real-time eye-tracking hardware accelerator may be used to quickly and efficiently determine the location and extent of an object (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or for other purposes.

[0187] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) have broad applications for autonomous driving. In at least one embodiment, the PVA can be a programmable vision accelerator used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA at low power and low latency are well-matched to algorithmic domains requiring predictable processing. In other words, the PVA performs well in semi-intensive or intensive conventional computations, even on small datasets that may require predictable runtimes with low latency and low power consumption. In at least one embodiment, in an autonomous vehicle, such as vehicle 1200, the PVA may be designed to run classical computer vision algorithms, as they are efficient in object detection and integer mathematical operations.

[0188] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching during operation (e.g., structure recovery from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0189] In at least one embodiment, the PVA can be used to perform intensive optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0190] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, but not limited to, neural networks whose output is used for a confidence score for each object detection. In at least one embodiment, the confidence score can be represented or interpreted as a probability, or as providing a relative “weight” for each detection relative to other detections. In at least one embodiment, the confidence score measurement enables the system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, the system can set a threshold for the confidence score and only consider detections exceeding the threshold as true positives. In embodiments using an Automatic Emergency Braking (“AEB”) system, false positives would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score value. In at least one embodiment, the neural network may take at least a subset of parameters as its input, such as bounding box size, obtained ground plane estimate (e.g., from another subsystem), and outputs of one or more IMU sensors 1266 related to the vehicle 1200 orientation, distance, and 3D position estimate of the object obtained from the neural network and / or other sensors (e.g., one or more LiDAR sensors 1264 or one or more RADAR sensors 1260).

[0191] In at least one embodiment, one or more SoCs 1204 (e.g., a hardware acceleration cluster) may include one or more data storage devices 1216 (e.g., memory). In at least one embodiment, one or more data storage devices 1216 may be on-chip memory of one or more SoCs 1204, which may store neural networks to be executed on one or more GPUs 1208 and / or DLAs. In at least one embodiment, one or more data storage devices 1216 may have a sufficiently large capacity to store multiple instances of the neural network for redundancy and security. In at least one embodiment, one or more data storage devices 1212 may include L2 or L3 caches.

[0192] In at least one embodiment, one or more SoCs 1204 may include any number of processors 1210 (e.g., embedded processors). In at least one embodiment, one or more processors 1210 may include a startup and power management processor, which may be a dedicated processor and subsystem for handling startup power and management functions, as well as associated security implementations. In at least one embodiment, the startup and power management processor may be part of a startup sequence of one or more SoCs 1204s and may provide runtime power management services. In at least one embodiment, the startup power and management processor may provide clock and voltage programming, assist system low-power state transitions, thermal and temperature sensor management of one or more SoCs 1204s, and / or power state management of one or more SoCs 1204s. In at least one embodiment, each temperature sensor may be implemented with its output frequency proportional to temperature, and one or more SoCs 1204s may use the ring oscillator to detect the temperature of one or more CPUs 1206s, one or more GPUs 1208s, and / or one or more accelerators 1214s. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the startup and power management processor may enter a temperature fault routine and place one or more SoCs 1204s into a lower power state and / or place the vehicle 1200 into a driver’s safe stopping pattern (e.g., bring the vehicle 1200 to a safe stop).

[0193] In at least one embodiment, one or more processors 1210 may further include a set of embedded processors that can serve as an audio processing engine. The audio processing engine may be an audio subsystem capable of providing full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor having dedicated RAM.

[0194] In at least one embodiment, one or more processors 1210 may further include an always-on processor engine. In at least one embodiment, the automatic processing engine may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processor on the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, support for peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0195] In at least one embodiment, one or more processors 1210 may further include a security cluster engine, which includes, but is not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the security cluster engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In a secure mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1210 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1210 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0196] In at least one embodiment, one or more processors 1210 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by the video playback application to produce the final image for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1270, one or more surround cameras 1274, and / or one or more cabin monitoring camera sensors. In at least one embodiment, preferably, the cabin monitoring camera sensors are monitored by a neural network running on another instance of SoC 1204, the neural network being configured to recognize cabin events and respond accordingly. In at least one embodiment, the cabin system may perform, but is not limited to, lip reading to activate cellular service and make phone calls, instruct emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, and are otherwise disabled.

[0197] In at least one embodiment, the video image synthesizer may include enhanced temporal denoising for simultaneous spatial and temporal denoising. For example, in at least one embodiment, when motion occurs in the video, denoising appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, when the image or a portion of the image does not contain motion, temporal denoising performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0198] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic correction on the input stereo lens frames. In at least one embodiment, when using an operating system desktop, the video image compositor can also be used for user interface compositing and does not require one or more GPUs 1208 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1208 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 1208 to improve performance and responsiveness.

[0199] In at least one embodiment, one or more SoCs of SoC 1204 may further include a Mobile Industrial Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block that can be used for receiving video and input from a camera and associated pixel input functions. In at least one embodiment, one or more SoCs of SoC 1204 may further include an input / output controller that can be software controlled and can be used to receive I / O signals not assigned to a specific role.

[0200] In at least one embodiment, one or more SoCs of SoC 1204 may further include extensive peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management and / or other devices. In at least one embodiment, one or more SoCs of SoC 1204 may be used to process data from (e.g., connected via gigabit multimedia serial links and Ethernet channels) cameras, sensors (e.g., one or more LiDAR sensors 1264, one or more RADAR sensors 1260, etc., which may be connected via Ethernet channels), data from bus 1202 (e.g., vehicle 1200 speed, steering wheel position, etc.), data from one or more GNSS sensors 1258 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more SoCs of SoC 1204 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to free one or more CPUs 1206 from routine data management tasks.

[0201] In at least one embodiment, one or more SoCs 1204 can be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and effectively utilizes computer vision and ADAS technologies to achieve diversity and redundancy. This provides a platform offering a flexible and reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 1204 can be faster, more reliable, and even more energy and space efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1214, when combined with one or more CPUs 1206, one or more GPUs 1208, and one or more data storage devices 1216, can provide a fast and efficient platform for Level 3-5 autonomous vehicles.

[0202] In at least one embodiment, the computer vision algorithm can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute multiple processing algorithms on a variety of visual data. However, in at least one embodiment, the CPU typically cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in automotive ADAS applications and practical Level 3-5 autonomous vehicles.

[0203] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined to achieve Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPUs 1220) may include text and word recognition, thereby allowing a supercomputer to read and understand traffic signs, including signs for which the neural network has not yet been specifically trained. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing semantic understanding of symbols, and passing this semantic understanding to a path planning module running on a CPU Complex.

[0204] In at least one embodiment, for drives of levels 3, 4, or 5, multiple neural networks can run simultaneously. For example, in at least one embodiment, a warning sign consisting of a light bulb accompanied by the warning sign “Caution: flashing lights indicate icy conditions” can be interpreted independently or jointly by multiple neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text “flashing lights indicate icy conditions” can be interpreted by a second deployed neural network, which informs the vehicle’s path planning software (preferably executed on the CPU Complex) that icing conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network across multiple frames, informing the vehicle’s path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1208.

[0205] In at least one embodiment, the CNN for facial recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or the owner of vehicle 1200. In at least one embodiment, a normally open sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves it. In this way, one or more SoCs 1204 provide protection against theft and / or carjacking.

[0206] In at least one embodiment, the CNN for emergency vehicle detection and identification can use data from microphone 1296 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1204 use the CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, the CNN running on DLA is trained to identify the relative approach speed of emergency vehicles (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles in the area where the vehicle is operating, as identified by one or more GNSS sensors 1258. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in the United States, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 1262, to execute emergency vehicle safety routines, slow down the vehicle, pull the vehicle to the side of the road, stop, and / or leave the vehicle idle until the emergency vehicle passes.

[0207] In at least one embodiment, vehicle 1200 may include one or more CPUs 1218 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 1204 via high-speed interconnects (e.g., PCIe). In at least one embodiment, for example, one or more CPUs 1218 may include x86 processors. One or more CPUs 1218 may be used to perform any of a variety of functions, such as arbitrating the results of potential inconsistencies between ADAS sensors and one or more SoCs 1204, and / or monitoring the status and health of one or more controllers 1236 and / or on-chip infotainment system (“infotainment SoC”) 1230.

[0208] In at least one embodiment, vehicle 1200 may include one or more GPUs 1220 (e.g., one or more discrete GPUs or one or more dGPUs) coupled to one or more SoCs 1204 via high-speed interconnects (e.g., NVIDIA's NVLINK channels). In at least one embodiment, one or more GPUs 1220 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on inputs from sensors of vehicle 1200 (e.g., sensor data).

[0209] In at least one embodiment, vehicle 1200 may further include a network interface 1224, which may include, but is not limited to, one or more wireless antennas 1226 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1224 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., passenger client devices) via Internet cloud services (e.g., using servers and / or other network devices). In at least one embodiment, for communication with other vehicles, a direct link and / or an indirect link (e.g., via a network and on the Internet) may be established between vehicle 120 and another vehicle. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1200 with information about vehicles near vehicle 1200 (e.g., vehicles in front, to the side, and / or behind vehicle 1200). In at least one embodiment, the foregoing functionality may be part of a cooperative adaptive cruise control function of vehicle 1200.

[0210] In at least one embodiment, network interface 1224 may include a System-on-Chip (SoC) that provides modulation and demodulation functions and enables one or more controllers 1236 to communicate over a wireless network. In at least one embodiment, network interface 1224 may include a radio frequency (RF) front-end for up-conversion from baseband to RF and down-conversion from RF to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed using known processes and / or using a superheterodyne process. In at least one embodiment, the RF front-end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0211] In at least one embodiment, vehicle 1200 may further include one or more data storage devices 1228, which may include, but are not limited to, off-chip (e.g., one or more SoC 1204) storage. In at least one embodiment, one or more data storage devices 1228 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disk and / or other components and / or devices capable of storing at least one bit of data.

[0212] In at least one embodiment, the vehicle 1200 may further include one or more GNSS sensors 1258 (e.g., GPS and / or auxiliary GPS sensors) to assist in map creation, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1258 may be used, including, for example, but not limited to, GPS sensors connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0213] In at least one embodiment, vehicle 1200 may further include one or more RADAR sensors 1260. In at least one embodiment, one or more RADAR sensors 1260 may be used by vehicle 1200 for remote vehicle detection, even in dark and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, one or more RADAR sensors 1260 may use a CAN bus and / or bus 1202 (e.g., to transmit data generated by one or more RADAR sensors 1260) for control and access to object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, but not limited to, one or more of the RADAR sensors 1260 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 1260 are pulse Doppler RADAR sensors.

[0214] In at least one embodiment, one or more RADAR sensors 1260 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a 250m range). In at least one embodiment, one or more RADAR sensors 1260 can help distinguish between stationary and moving objects and can be used by the ADAS system 1238 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 1260 included in the long-range RADAR system may include, but are not limited to, a monostatic multimode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the four central antennas, can create a focused beammap designed to record the surrounding environment of the vehicle 1200 at a high speed while minimizing traffic interference from adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view, thereby enabling rapid detection of vehicles 1200 entering or leaving the lane.

[0215] In at least one embodiment, as an example, a mid-range RADAR system may include, for example, a range of up to 160m (front) or 120m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1260 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the rearward direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system may be used in ADAS system 1238 for blind spot detection and / or lane change assistance.

[0216] In at least one embodiment, the vehicle 1200 may further include one or more ultrasonic sensors 1262. In at least one embodiment, one or more ultrasonic sensors 1262, which may be positioned at the front, rear, and / or sides of the vehicle 1200, may be used for parking assistance and / or creating and updating occupancy detectors. In at least one embodiment, a wide variety of ultrasonic sensors 1262 may be used, and different ultrasonic sensors 1262 may be used for different detection ranges (e.g., 2.5m, 4m). In at least one embodiment, the ultrasonic sensors 1262 may operate at the ASIL B functional safety level.

[0217] In at least one embodiment, vehicle 1200 may include one or more LiDAR sensors 1264. In at least one embodiment, one or more LiDAR sensors 1264 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LiDAR sensors 1264 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 1200 may include multiple (e.g., two, four, six, etc.) LiDAR sensors 1264 that can use Ethernet (e.g., providing data to a Gigabit Ethernet switch).

[0218] In at least one embodiment, one or more LiDAR sensors 1264 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LiDAR sensors 1264 may, for example, have an advertising range of approximately 100m, an accuracy of 2cm-3cm, and support a 100Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LiDAR sensors may be used. In such an embodiment, one or more LiDAR sensors 1264 may include small devices that can be embedded in the front, rear, side, and / or corner locations of vehicle 1200. In at least one embodiment, one or more LiDAR sensors 1264, in such an embodiment, can provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for objects with low reflectivity, and have a range of 200m. In at least one embodiment, one or more forward-facing LiDAR sensors 1264 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0219] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200m around vehicle 1200. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and reflected light on each pixel, which in turn corresponds to the range from vehicle 1200 to the object. In at least one embodiment, flash LIDAR can allow the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of vehicle 1200. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per frame and can capture reflected laser light as intensity data for 3D ranging point clouds and co-registration.

[0220] In at least one embodiment, vehicle 1200 may further include one or more IMU sensors 1266. In at least one embodiment, one or more IMU sensors 1266 may be located at the center of the rear axle of vehicle 1200. In at least one embodiment, one or more IMU sensors 1266 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, a magnetic compass, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 1266 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 1266 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0221] In at least one embodiment, one or more IMU sensors 1266 can be implemented as a miniature, high-performance GPS-assisted inertial navigation system (“GPS / INS”) combining a microelectromechanical system (“MEMS”) inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm to provide position, velocity, and attitude estimations; in at least one embodiment, one or more IMU sensors 1266 enable vehicle 1200 to estimate heading by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1266 without input from magnetic sensors. In at least one embodiment, one or more IMU sensors 1266 and one or more GNSS sensors 1258 can be combined in a single integrated unit.

[0222] In at least one embodiment, vehicle 1200 may include one or more microphones 1296 placed inside and / or around vehicle 1200. In at least one embodiment, in addition, one or more microphones 1296 may be used for emergency vehicle detection and identification.

[0223] In at least one embodiment, vehicle 1200 may further include any number of camera types, including one or more stereo cameras 1268, one or more wide-angle cameras 1270, one or more infrared cameras 1272, one or more surround cameras 1274, one or more long-range cameras 1298, one or more mid-range cameras 1276, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire perimeter of vehicle 1200. In at least one embodiment, the type of camera used depends on vehicle 1200. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 1200. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1200 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may be, by way of example but not limited to, supporting gigabit multimedia serial link (“GMSL”) and / or gigabit Ethernet communication. In at least one embodiment, previously referenced herein Figure 12A and Figure 12B Each camera can be described in more detail.

[0224] In at least one embodiment, the vehicle 1200 may further include one or more vibration sensors 1242. In at least one embodiment, the one or more vibration sensors 1242 may measure vibrations of components of the vehicle 1200 (e.g., axles). For example, in at least one embodiment, changes in vibration may indicate changes in road surface conditions. In at least one embodiment, when two or more vibration sensors 1242 are used, differences between vibrations may be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a power drive axle and a free-rotating axle).

[0225] In at least one embodiment, vehicle 1200 may include ADAS system 1238. In at least one embodiment, ADAS system 1238 may include, but is not limited to, SoC. In at least one embodiment, ADAS system 1238 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions, and combinations thereof.

[0226] In at least one embodiment, the ACC system may use one or more RADAR sensors 1260, one or more LIDAR sensors 1264, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle adjacent to the vehicle 1200 and automatically adjusts the speed of the vehicle 1200 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance holding and suggests that the vehicle 1200 change lanes if necessary. In at least one embodiment, the lateral ACC is associated with other ADAS applications, such as LC and CW.

[0227] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from other vehicles via network interface 1224 and / or one or more wireless antennas 1226 via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Typically, V2V communication provides information about the vehicle immediately preceding it (e.g., a vehicle immediately in front of vehicle 1200 and in the same lane as it), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles preceding vehicle 1200, the CACC system can be more reliable and has the potential to improve traffic flow smoothness and reduce road congestion.

[0228] In at least one embodiment, the FCW system is designed to warn the driver of a hazard so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1260, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to components providing driver feedback, such as a display, speaker, and / or vibration. In at least one embodiment, the FCW system can provide warnings, for example, in the form of audible, visual, haptic, and / or rapid braking pulses.

[0229] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply brakes if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system may automatically apply brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic braking to support and / or brakes for impending collisions.

[0230] In at least one embodiment, when vehicle 1200 crosses lane markings, the LDW system provides visual, auditory, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver. In at least one embodiment, the LDW system is inactive when the driver indicates intentional lane departure, such as by activating turn signals. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 1200 begins to leave the lane, the LKA system provides steering input or braking to correct vehicle 1200.

[0231] In at least one embodiment, the BSW system detects and warns the driver of a vehicle in the blind spot. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses the turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback, such as a display, speaker, and / or vibration assembly.

[0232] In at least one embodiment, the RCTW system can provide visual, auditory, and / or tactile notifications when an object is detected outside the range of the rear camera while the vehicle 1200 is reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure the applied vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear-facing RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as displays, speakers, and / or vibration components.

[0233] In at least one embodiment, conventional ADAS systems may be prone to generating false alarms, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to determine whether a safe situation truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, the vehicle 1200 itself decides whether to follow the result of the main computer or the auxiliary computer (e.g., the first or second controller of controller 1236). For example, in at least one embodiment, ADAS system 1238 may be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor may run redundant software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from ADAS system 1238 may be provided to a monitoring MCU. In at least one embodiment, if the output from the main computer and the output from the auxiliary computer conflict, the monitoring MCU decides how to reconcile the conflict to ensure safe operation.

[0234] In at least one embodiment, the master computer may be configured to provide a confidence score to the supervisory MCU to indicate the master computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the master computer's instructions regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the master computer and the auxiliary computer indicate different results (e.g., conflicting), the supervisory MCU may arbitrate between the computers to determine the appropriate result.

[0235] In at least one embodiment, the supervisory MCU may be configured to run a neural network trained and configured to determine, at least in part, the conditions under which the auxiliary computer provides a false alarm based on outputs from a host computer and an auxiliary computer. In at least one embodiment, the neural network in the supervisory MCU may learn when the outputs of the auxiliary computer can be trusted and when they cannot. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, the neural network in the supervisory MCU may learn when the FCW system recognizes a metallic object that is not actually dangerous, such as a drain grating or manhole cover that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest operation. In at least one embodiment, the supervisory MCU may include at least one of a DLA or GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoC1204s.

[0236] In at least one embodiment, the ADAS system 1238 may include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the auxiliary computer may use classic computer vision rules (if-then), and the presence of a neural network in the supervisory MCU can improve reliability, security, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if a software vulnerability or bug exists in the software running on the host computer, and different software code running on the auxiliary computer provides consistent overall results, the supervisory MCU can more confidently assume that the overall result is correct and that the vulnerability in the software or hardware on the host computer will not lead to a significant error.

[0237] In at least one embodiment, the output of the ADAS system 1238 can be input to the perception module and / or the dynamic driving task module of the host computer. For example, in at least one embodiment, if the ADAS system 1238 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when identifying the object. In at least one embodiment, as described herein, the assistance computer can have its own neural network trained to reduce the risk of false alarms.

[0238] In at least one embodiment, vehicle 1200 may further include an infotainment SoC 1230 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1230 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1230 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total coverage distance, brake fuel level, fuel level, door opening / closing, air filter information, etc.) to vehicle 1200. For example, the infotainment SoC 1230 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, vehicle, in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, head-up display (“HUD”), HMI display 1234, telematics device, control panel (e.g., for controlling and / or interacting with various components, features and / or systems) and / or other components. In at least one embodiment, the infotainment SoC 1230 may further be used to provide information (e.g., visual and / or auditory) to a user of vehicle 1200, such as information from ADAS system 1238, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.) and / or other information.

[0239] In at least one embodiment, the infotainment SoC 1230 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1230 may communicate with other devices, systems, and / or components of the vehicle 1200 via bus 1202 (e.g., CAN bus, Ethernet, etc.). In at least one embodiment, the infotainment SoC 1230 may be coupled to a monitoring MCU, enabling the GPU of the infotainment system to perform some autonomous driving functions in the event of a failure of the main controller 1236 (e.g., the main computer and / or backup computer of the vehicle 1200). In at least one embodiment, the infotainment SoC 1230 may cause the vehicle 1200 to enter a driver-to-safe-stop mode, as described herein.

[0240] In at least one embodiment, vehicle 1200 may further include instrument panel 1232 (e.g., digital instrument panel, electronic instrument panel, digital instrument control panel, etc.). In at least one embodiment, instrument panel 1232 may include, but is not limited to, controllers and / or supercomputers (e.g., discrete controllers or supercomputers). In at least one embodiment, instrument panel 1232 may include, but is not limited to, any number and combination of a set of instruments, such as speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 1230 and instrument panel 1232. In at least one embodiment, instrument panel 1232 may be included as part of infotainment SoC 1230, or vice versa.

[0241] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0242] Figure 12D It is based on at least one embodiment in a cloud-based server and Figure 12AA diagram of a system 1276 for communication between autonomous vehicles 1200. In at least one embodiment, system 1276 may include, but is not limited to, one or more servers 1278, one or more networks 1290, and any number and type of vehicles, including vehicle 1200. In at least one embodiment, one or more servers 1278 may include, but is not limited to, multiple GPUs 1284(A)-1284(H) (collectively referred to herein as GPU 1284), PCIe switches 1282(A)-1282(D) (collectively referred to herein as PCIe switch 1282), and / or CPUs 1280(A)-1280(B) (collectively referred to herein as CPU 1280). GPU 1284, CPU 1280, and PCIe switch 1282 may be interconnected with high-speed interconnects, such as, but not limited to, NVLink interface 1288 developed by NVIDIA and / or PCIe connection 1286. In at least one embodiment, the GPU 1284 is connected via NVLink and / or NVSwitchSoC, and the GPU 1284 and PCIe switch 1282 are connected via PCIe interconnect. In at least one embodiment, although eight GPUs 1284, two CPUs 1280, and four PCIe switches 1282 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 1278 may include, but is not limited to, any combination of any number of GPUs 1284, CPUs 1280, and / or PCIe switches 1282. For example, in at least one embodiment, one or more servers 1278 may each include eight, sixteen, thirty-two, and / or more GPUs 1284.

[0243] In at least one embodiment, one or more servers 1278 may receive image data representing an image from a vehicle via one or more networks 1290, the image showing unexpected or changed road conditions, such as recently commenced roadworks. In at least one embodiment, one or more servers 1278 may transmit a neural network 1292, an updated neural network 1292, and / or map information 1294, including but not limited to information about traffic and road conditions, to the vehicle via one or more networks 1290. In at least one embodiment, updates to the map information 1294 may include, but are not limited to, updates to an HD map 1222, such as information about construction sites, potholes, sidewalks, floods, and / or other obstacles. In at least one embodiment, the neural network 1292, the updated neural network 1292, and / or map information 1294 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or at least based on training performed in a data center (e.g., using one or more servers 1278 and / or other servers).

[0244] In at least one embodiment, one or more servers 1278 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by the vehicle, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1290), and / or the machine learning model may be used by one or more servers 1278 to remotely monitor the vehicle.

[0245] In at least one embodiment, one or more servers 1278 may receive data from the vehicle and apply the data to state-of-the-art real-time neural networks for real-time intelligent inference. In at least one embodiment, one or more servers 1278 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1284, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1278 may include a deep learning infrastructure in a data center using CPU power.

[0246] In at least one embodiment, the deep learning infrastructure of one or more servers 1278 may be capable of fast, real-time inference and can use this capability to assess and verify the health of the processor, software, and / or associated hardware in vehicle 1200. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1200, such as image sequences and / or objects located by vehicle 1200 in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 1200, and if the results do not match and the deep learning infrastructure determines that the AI ​​in vehicle 1200 is malfunctioning, one or more servers 1278 may signal to vehicle 1200 to instruct the fail-safe computer of vehicle 1200 to take control, notify passengers, and complete a safe stopping operation.

[0247] In at least one embodiment, one or more servers 1278 may include one or more GPUs 1284 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, the combination of GPU-driven servers and inference acceleration enables real-time response. In at least one embodiment, for example, where performance is less critical, servers driven by CPUs, FPGAs, and other processors may be used for inference. In at least one embodiment, hardware architecture 1115 is used to execute one or more embodiments. This document incorporates... Figure 11 A and / or Figure 11 B provides details about the hardware architecture 1115.

[0248] Computer System

[0249] Figure 13 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system of interconnected devices and components, a system-on-a-chip (SOC), or some combination thereof formed with a processor 1300, which may include an execution unit to execute instructions. In at least one embodiment, according to this disclosure, such as the embodiments described herein, the computer system 1300 may include, but is not limited to, components such as processor 1302, whose execution unit includes logic to execute algorithms for process data. In at least one embodiment, the computer system 1300 may include a processor, such as those available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , CoreTM or A microprocessor may be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, computer system 1300 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0250] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0251] In at least one embodiment, computer system 1300 may include, but is not limited to, processor 1302, which may include, but is not limited to, one or more execution units 1308, to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, system 13 is a single-processor desktop or server system, but in another embodiment, system 13 may be a multiprocessor system. In at least one embodiment, processor 1302 may include, but is not limited to, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1302 may be coupled to processor bus 1310, which can transmit data signals between processor 1302 and other components in computer system 1300.

[0252] In at least one embodiment, processor 1302 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1304. In at least one embodiment, processor 1302 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1302. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 1306 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0253] In at least one embodiment, an execution unit 1308, including but not limited to logic for performing integer and floating-point operations, is also located within the processor 1302. In at least one embodiment, the processor 1302 may further include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, the execution unit 1308 may include logic for processing a packaged instruction set 1309. In at least one embodiment, by including the packaged instruction set 1309 in the instruction set of a general-purpose processor, along with associated circuitry for executing the instructions, packaged data in the general-purpose processor 1302 can be used to perform operations used by numerous multimedia applications. In one or more embodiments, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor’s data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor’s data bus to perform one or more operations on one data element at a time.

[0254] In at least one embodiment, execution unit 1308 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 1300 may include, but is not limited to, memory 1320. In at least one embodiment, memory 1320 may be implemented as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or another storage device. In at least one embodiment, memory 1320 may store instructions 1319 and / or data 1321 represented by data signals that can be executed by processor 1302.

[0255] In at least one embodiment, the system logic chip may be coupled to the processor bus 1310 and the memory 1320. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1316, and the processor 1302 may communicate with the MCH 1316 via the processor bus 1310. In at least one embodiment, the MCH 1316 may provide a high-bandwidth memory path 1318 to the memory 1320 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1316 may direct data signals between the processor 1302, the memory 1320, and other components in the computer system 1300, and bridge data signals between the processor bus 1310, the memory 1320, and the system I / O 1322. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1316 may be coupled to memory 1320 via high-bandwidth memory path 1318, and graphics / video card 1312 may be coupled to MCH 1316 via Accelerated Graphics Port (“AGP”) interconnect 1314.

[0256] In at least one embodiment, computer system 1300 may use system I / O 1322, which is a proprietary hub interface bus, to couple MCH 1316 to I / O controller hub (“ICH”) 1330. In at least one embodiment, ICH 1330 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 1320, chipset, and processor 1302. Examples may include, but are not limited to, audio controller 1329, firmware hub (“Flash BIOS”) 1328, wireless transceiver 1326, data storage 1324, a conventional I / O controller 1323 including user input and keyboard interfaces, serial expansion port 1327 (e.g., Universal Serial Bus (USB)), and network controller 1334. In at least one embodiment, data storage 1324 may include hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

[0257] In at least one embodiment, Figure 13 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 13 A system-on-a-chip (SoC) can be shown. In at least one embodiment, Figure 13The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1300 are interconnected using a Compute Fast Link (CXL) interconnect.

[0258] In at least one embodiment, referring to the figures, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the figures, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0259] Figure 14 This is a block diagram illustrating an electronic device 1400 for utilizing a processor 1410 according to at least one embodiment. In at least one embodiment, the electronic device 1400 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0260] In at least one embodiment, system 1400 may include, but is not limited to, processor 1410 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1410 uses a bus or interface coupling, such as an I²C bus, system management bus (“SMBus”), low pin count (LPC) bus, serial peripheral interface (“SPI”), high-definition audio (“HDA”) bus, serial advanced technology accessory (“SATA”) bus, universal serial bus (“USB”) (versions 1, 2, 3, etc.), or universal asynchronous receiver / transmitter (“UART”) bus. In at least one embodiment, Figure 14 The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 14 An exemplary system-on-a-chip (SoC) can be illustrated. In at least one embodiment, Figure 14 The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 14 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0261] In at least one embodiment, Figure 14It may include a display 1424, a touch screen 1425, a touchpad 1430, a near field communication unit (“NFC”) 1445, a sensor hub 1440, a thermal sensor 1446, a fast chipset (“EC”) 1435, a trusted platform module (“TPM”) 1438, a BIOS / firmware / flash (“BIOS, FW Flash”) 1422, a DSP 1460, a drive “SSD or HDD” 1420 (e.g., a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1450, a Bluetooth unit 1452, a wireless wide area network unit (“WWAN”) 1456, a global positioning system (GPS) 1455, a camera (“USB 3.0 camera”) 1454 (e.g., a USB 3.0 camera), or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1415 implemented in, for example, the LPDDR3 standard. These components can each be implemented in any suitable way.

[0262] In at least one embodiment, other components may be communicatively coupled to processor 1410 via the components described above. In at least one embodiment, accelerometer 1441, ambient light sensor (“ALS”) 1442, compass 1443, and gyroscope 1444 may be communicatively coupled to sensor hub 1440. In at least one embodiment, thermal sensor 1439, fan 1437, keyboard 1446, and touchpad 1430 may be communicatively coupled to EC 1435. In at least one embodiment, speaker 1463, earphone 1464, and microphone (“mic”) 1465 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1464, which in turn may be communicatively coupled to DSP 1460. In at least one embodiment, audio unit 1464 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1457 may be communicatively coupled to WWAN unit 1456. In at least one embodiment, components such as WLAN unit 1450, Bluetooth unit 1452, and WWAN unit 1456 can be implemented as next-generation form factor (NGFF).

[0263] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0264] Figure 15 A computer system 1500 according to at least one embodiment is shown. In at least one embodiment, the computer system 1500 is configured to implement various processes and methods described throughout this disclosure.

[0265] In at least one embodiment, the computer system 1500 includes, but is not limited to, at least one central processing unit (“CPU”) 1502 connected to a communication bus 1510 implemented using any suitable protocol, such as PCI (“Peripheral Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1500 includes, but is not limited to, main memory 1504 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data may be stored in main memory 1504 in the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“Network Interface”) 1522 provides an interface to other computing devices and networks for receiving data from the computer system 1500 and transferring data to other systems.

[0266] In at least one embodiment, the computer system 1500 includes, but is not limited to, an input device 1508, a parallel processing system 1512, and a display device 1506, which may be implemented using conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light-emitting diode (“LED”), plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1508 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the foregoing modules may reside on a single semiconductor platform to form the processing system.

[0267] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0268] Figure 16A computer system 1600 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1600 includes, but is not limited to, a computer 1610 and a USB stick 1620. In at least one embodiment, the computer 1610 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1610 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0269] In at least one embodiment, the USB stick 1620 includes, but is not limited to, a processing unit 1630, a USB interface 1640, and USB interface logic 1650. In at least one embodiment, the processing unit 1630 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1630 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 1630 includes an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1630 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing core 1630 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0270] In at least one embodiment, the USB interface 1640 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1640 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1640 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1650 may include any amount and type of logic enabling the processing unit 1630 to connect to a device (e.g., computer 1610) via the USB connector 1640.

[0271] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0272] Figure 17AAn exemplary architecture is illustrated, in which multiple GPUs 1710-1713 are communicatively coupled to multiple multi-core processors 1705-1706 via high-speed links 1740-1743 (e.g., bus / point-to-point interconnect, etc.). In one embodiment, the high-speed links 1740-1743 support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0273] Furthermore, in one embodiment, two or more GPUs 1710-1713 are interconnected via high-speed links 1729-1730, which may use the same or different protocols / links as those used for high-speed links 1740-1743. Similarly, two or more multi-core processors 1705-1706 may be connected via high-speed link 1728, which may be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, the same protocol / link (e.g., via a common interconnect structure) may be used. Figure 17A This shows all communication between the various system components.

[0274] In one embodiment, each multi-core processor 1705-1706 is communicatively coupled to processor memories 1701-1702 via memory interconnects 1726-1727, and each GPU 1710-1713 is communicatively coupled to GPU memories 1720-1723 via GPU memory interconnects 1750-1753. Memory interconnects 1726-1727 and 1750-1753 may utilize the same or different memory access technologies. By way of example and not limitation, processor memories 1701-1702 and GPU memories 1720-1723 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM. In one embodiment, some portions of the processor memories 1701-1702 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0275] As described in this article, although the various processors 1705-1706 and GPUs 1710-1713 can be physically coupled to specific memories 1701-1702 and 1720-1723 respectively, a unified memory architecture can be implemented, in which the same virtual system address space (also known as the “effective address” space) is distributed across the various physical memories. For example, processor memories 1701-1702 can each contain 64GB of system memory address space, and GPU memories 1720-1723 can each contain 32GB of system memory address space (resulting in a total addressable memory size of 256GB in this example).

[0276] Figure 17B Additional details are shown regarding the interconnection between a multi-core processor 1707 and a graphics acceleration module 1746 according to an exemplary embodiment. The graphics acceleration module 1746 may include one or more GPU chips integrated on a line card coupled to the processor 1707 via a high-speed link 1740. Alternatively, the graphics acceleration module 1746 may be integrated on the same package or chip as the processor 1707.

[0277] In at least one embodiment, the processor 1707 shown includes multiple cores 1760A-1760D, each core having a translation back buffer 1761A-1761D and one or more caches 1762A-1762D. In at least one embodiment, cores 1760A-1760D may include various other components (not shown) for executing instructions and processing data. Caches 1762A-1762D may include level 1 (L1) and level 2 (L2) caches. Furthermore, one or more shared caches 1756 may be included in caches 1762A-1762D and shared by the respective groups of cores 1760A-1760D. For example, one embodiment of the processor 1707 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1707 and the graphics acceleration module 1746 are connected to a system memory 1718, which may include... Figure 17A The processor memory 1701-1702 in the memory.

[0278] The consistency bus 1764 maintains consistency for data and instructions stored in the various caches 1762A-1762D, 1756 and system memory 1718 via inter-core communication. For example, each cache may have associated cache consistency logic / circuit to communicate via the consistency bus 1764 in response to the detection of a read or write to a specific cache line. In one implementation, a cache snooping protocol is implemented via the consistency bus 1764 to snoop on cache accesses.

[0279] In one embodiment, proxy circuitry 1725 communicatively couples graphics acceleration module 1746 to coherence bus 1764, thereby allowing graphics acceleration module 1746 to participate in cache coherence protocols as a peer of cores 1760A-1760D. Specifically, interface 1735 provides connectivity to proxy circuitry 1725 via high-speed link 1740 (e.g., PCIe bus, NVLink, etc.), and interface 1737 connects graphics acceleration module 1746 to link 1740.

[0280] In one implementation, the accelerator integrated circuit 1736 represents multiple graphics processing engines 1731, 1732, N of the graphics acceleration module 1746, providing cache management, memory access, context management, and interrupt management services. The graphics processing engines 1731, 1732, N may each include a separate graphics processing unit (GPU). Optionally, the graphics processing engines 1731, 1732, N may selectively include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1746 may be a GPU having multiple graphics processing engines 1731-1732, N, or the graphics processing engines 1731-1732, N may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0281] In one embodiment, the accelerator integrated circuit 1736 includes a memory management unit (MMU) 1739 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1714. The MMU 1739 may also include a translation back buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 1738 may store commands and data for effective access by graphics processing engines 1731-1732,N. In one embodiment, data stored in cache 1738 and graphics memories 1733-1734,M is kept consistent with core caches 1762A-1762D,1756 and system memory 1714. As previously mentioned, this task can be accomplished via proxy circuitry 1725 representing cache 1738 and graphics memory 1733-1734, M (e.g., sending updates related to modifications / accesses to cache lines on processor caches 1762A-1762D, 1756 to cache 1738 and receiving updates from cache 1738).

[0282] A set of registers 1745 stores context data for threads executed by graphics processing engines 1731, 1732, N, and context management circuitry 1748 manages the thread context. For example, context management circuitry 1748 can perform save and restore operations to save and restore the context of individual threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 1748 can store the current register value into a designated area in memory (e.g., identified by the context pointer). The register value can then be restored when returning to the context. In one embodiment, interrupt management circuitry 1747 receives and processes interrupts received from system devices.

[0283] In one implementation, MMU 1739 translates virtual / effective addresses from graphics processing engine 1731 into real / physical addresses in system memory 1714. One embodiment of accelerator integrated circuit 1736 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1746 and / or other accelerator devices. Graphics accelerator module 1746 may be dedicated to a single application executing on processor 1707, or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, where the resources of graphics processing engines 1731, 1732, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” based on processing requirements and priorities associated with VMs and / or applications, which are then allocated to different VMs and / or applications.

[0284] In at least one embodiment, the accelerator integrated circuit 1736 acts as a bridge to the system of the graphics acceleration module 1746, providing address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1736 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 1731-1732.

[0285] Because of the graphics processing engines 1731-1732, N's hardware resources are explicitly mapped to the real address space seen by the host processor 1707, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 1736 is to physically separate the graphics processing engines 1731-1732, N, so that they appear as independent units to the system.

[0286] In at least one embodiment, one or more graphics memories 1733-1734,M are coupled to each graphics processing engine 1731-1732,N. The graphics memories 1733-1734,M store instructions and data processed by each graphics processing engine 1731-1732,N. The graphics memories 1733-1734,M can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-RAM.

[0287] In one embodiment, to reduce data traffic on link 1740, a biasing technique can be used to ensure that the data stored in graphics memories 1733-1734, M is the data most frequently used by graphics processing engines 1731-1732, N, and preferably not used (or at least infrequently used) by cores 1760A-1760D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep the data needed by the cores (and preferably not graphics processing engines 1731-1732, N) in the core caches 1762A-1762D, 1756 and system memory 1714.

[0288] Figure 17C Another exemplary embodiment is shown, in which the accelerator integrated circuit 1736 is integrated within the processor 1707. In this embodiment, graphics processing engines 1731-1732,N communicate directly with the accelerator integrated circuit 1736 via a high-speed link 1740 through interfaces 1737 and 1735 (which can also utilize any form of bus or interface protocol). The accelerator integrated circuit 1736 can perform operations related to... Figure 17B The operations described are the same. However, due to its close proximity to the coherence bus 1764 and caches 1762A-1762D, 1756, it may have higher throughput. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by accelerator integrated circuit 1736 and a programming model controlled by graphics acceleration module 1746.

[0289] In at least one embodiment, graphics processing engines 1731-1732,N are dedicated to a single application or process within a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 1731-1732,N, thereby providing virtualization within a VM / partition.

[0290] In at least one embodiment, graphics processing engines 1731-1732, N can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1731-1732, N to allow each operating system to access them. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns graphics processing engines 1731-1732, N. In at least one embodiment, the operating system can virtualize graphics processing engines 1731-1732, N to provide access to each process or application.

[0291] In at least one embodiment, the graphics acceleration module 1746 or the respective graphics processing engines 1731-1732, N uses a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1714 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engines 1731-1732, N (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0292] Figure 17D An exemplary accelerator integration slice 1790 is shown. As used herein, a “slice” includes a designated portion of the processing resources of the accelerator integrated circuit 1736. The application’s effective address space 1782 in system memory 1718 stores process element 1783. In one embodiment, process element 1783 is stored in response to a GPU call 1781 from an application 1780 executing on processor 1707. Process element 1783 contains the process state of the corresponding application 1780. A job descriptor (WD) 1784 contained in process element 1783 may be a single job requested by the application, or it may contain a pointer to a job queue. In at least one embodiment, WD 1784 is a pointer to a job request queue in the application’s address space 1782.

[0293] The graphics acceleration module 1746 and / or the various graphics processing engines 1731-1732, N, can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 1784 to the graphics acceleration module 1746 to begin operations in a virtualized environment.

[0294] In at least one embodiment, the dedicated process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns either the graphics acceleration module 1746 or an individual graphics processing engine 1731. When the graphics acceleration module 1746 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 1736 for the owned partition; when the graphics acceleration module 1746 is assigned, the operating system initializes the accelerator integrated circuit 1736 for the owned process.

[0295] In operation, the WD fetch unit 1791 in the accelerator integrated slice 1790 fetches the next WD 1784, which includes instructions for the work to be performed by one or more graphics processing engines of the graphics acceleration module 1746. Data from the WD 1784 can be stored in register 1745 and used by the MMU 1739, interrupt management circuitry 1747, and / or context management circuitry 1748, as shown. For example, one embodiment of the MMU 1739 includes segment / page roaming circuitry for accessing segment / page tables 1786 within the OS virtual address space 1785. The interrupt management circuitry 1747 can handle interrupt events 1792 received from the graphics acceleration module 1746. When performing graphics operations, the effective address 1793 generated by the graphics processing engines 1731-1732,N is translated into a real address by the MMU 1739.

[0296] In one embodiment, for each graphics processing engine 1731-1732, N and / or graphics acceleration module 1746, the same set of registers 1745 is copied, and said registers 1745 can be initialized by a hypervisor or operating system. Each of these copied registers can be included in the accelerator integration slice 1790. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0297]

[0298] Table 2 shows exemplary registers that can be initialized by the operating system.

[0299]

[0300] In one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or graphics processing engine 1731-1732,N. It contains all the information required for the graphics processing engine 1731-1732,N to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0301] Figure 17E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1798, in which a list of process elements 1799 is stored. The hypervisor real address space 1798 can be accessed via a hypervisor 1796, which virtualizes the graphics acceleration module engine for operating system 1795.

[0302] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1746. In at least one embodiment, two programming models exist, wherein the graphics acceleration module 1746 is shared by multiple processes and partitions, time-slice sharing, and graphics-oriented sharing.

[0303] In this model, the hypervisor 1796 owns the graphics acceleration module 1746 and makes its functionality available to all operating systems 1795. For the graphics acceleration module 1746 to support virtualization through the hypervisor 1796, the graphics acceleration module 1746 may comply with the following: (1) the job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1746 must provide a context saving and restoration mechanism; (2) the graphics acceleration module 1746 guarantees that the job requests of the application are completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 1746 provides the ability to preempt job processing; and (3) when operating in a directed shared programming model, fairness among the processes of the graphics acceleration module 1746 must be ensured.

[0304] In at least one embodiment, application 1780 needs to make an operating system 1795 system call using the graphics acceleration module 1746 type, working descriptor (WD), authority mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module 1746 type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module 1746 type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for the graphics acceleration module 1746 and can take the form of a graphics acceleration module 1746 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure describing the work to be performed by the graphics acceleration module 1746. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1736 and the graphics acceleration module 1746 does not support the User Authority Mask Overwrite Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1796 may selectively apply the Current Privilege Mask Overwrite Register (AMOR) value before placing the AMR into process element 1783. In at least one embodiment, the CSRP is one of registers 1745 that contains the effective address of a region in the application's address space 1782 for the graphics acceleration module 1746 to save and restore context state. This pointer is optional if saving state between jobs is not required or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0305] Upon receiving a system call, operating system 1795 can verify that application 1780 has been registered and granted permission to use graphics acceleration module 1746. Then, operating system 1795 uses...

[0306] The information shown in Table 3 is used to invoke management program 1796.

[0307]

[0308] Upon receiving a hypervisor call, hypervisor 1796 verifies that operating system 1795 has been registered and granted permission to use graphics acceleration module 1746. Then, hypervisor 1796 adds process element 1783 to the linked list of process elements of the corresponding graphics acceleration module 1746 type. The process element may include the information shown in Table 4.

[0309]

[0310] In at least one embodiment, the hypervisor initializes multiple accelerator integration slice 1790 registers 1745.

[0311] like Figure 17F As shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1701-1702 and GPU memories 1720-1723. In this implementation, operations performed on GPUs 1710-1713 utilize the same virtual / effective memory address space to access processor memories 1701-1702, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1701, a second portion to second processor memory 1702, a third portion to GPU memory 1720, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1701-1702 and GPU memories 1720-1723, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0312] In one embodiment, the bias / coherence management circuitry 1794A-1794E within one or more MMUs 1739A-1739E ensures cache coherence between the caches of one or more host processors (e.g., 1705) and the GPUs 1710-1713, and implements biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, although in Figure 17F Several instances of the bias / coherence management circuitry 1794A-1794E are shown, but the bias / coherence circuitry can be implemented within the MMU of one or more host processors 1705 and / or within the accelerator integrated circuit 1736.

[0313] One embodiment allows GPU-attached memories 1720-1723 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU-attached memories 1720-1723 as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. This arrangement allows the host processor 1705 to software-set operands and access computation results without the overhead of conventional I / O DMA data copying. Such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU-attached memories 1720-1723 without cache coherence overhead can be critical for the execution time of offloaded computations. For example, in cases with high volumes of streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 1710-1713. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0314] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which may be a page-granular structure (e.g., controlled at the memory page level) comprising 1 or 2 bits of memory pages attached to each GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in GPUs 1710-1713, the bias table can be implemented across one or more stolen memory ranges of GPU-attached memories 1720-1723. Alternatively, the entire bias table can be maintained within the GPU.

[0315] In at least one embodiment, prior to actual access to GPU memory, an access to the bias table entry associated with each access to GPU-attached memory 1720-1723 is performed, causing the following operations: First, a local request from GPUs 1710-1713 to locate its page in the GPU bias is directly forwarded to the corresponding GPU memory 1720-1723. A local request from the GPU to locate its page in the host bias is forwarded to processor 1705 (e.g., via the high-speed link described above). In one embodiment, a request from processor 1705 to locate the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, requests to GPU bias pages can be forwarded to GPUs 1710-1713. In at least one embodiment, if the GPU is not currently using the page, the GPU may subsequently migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed through a software-based mechanism, a hardware-assisted software mechanism, or, in limited cases, a purely hardware-based mechanism.

[0316] One mechanism for changing the bias state employs an API call (e.g., OpenCL) that subsequently invokes the GPU's device driver, which then sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migrations, performs a cache refresh operation on the host. In at least one embodiment, the cache refresh operation is used for migrations from the host processor 1705 bias to the GPU bias, but not for the reverse migration.

[0317] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 1705 cannot cache. To access these pages, the processor 1705 may request access from the GPU 1710, which may or may not grant access immediately. Therefore, to reduce communication between the processor 1705 and the GPU 1710, it is beneficial to ensure that the GPU bias pages are those required by the GPU, not those required by the host processor 1705, and vice versa.

[0318] One or more hardware structures 1115 are used to execute one or more embodiments. This document may combine... Figure 11 A and / or Figure 11 B provides details about one or more hardware structures 1115.

[0319] Figure 18Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0320] Figure 18 This is a block diagram illustrating an exemplary system on a chip integrated circuit 1800 that may be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1800 includes one or more application processors 1805 (e.g., CPUs), at least one graphics processor 1810, and may additionally include an image processor 1815 and / or a video processor 1820, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1800 includes peripheral or bus logic including a USB controller 1825, a UART controller 1830, an SPI / SDIO controller 1835, and an I.sup.2S / I.sup.2C controller 1840. In at least one embodiment, the integrated circuit 1800 may include a display device 1845 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1850 and a Mobile Industrial Processor Interface (MIPI) display interface 1855. In at least one embodiment, storage may be provided by a flash memory subsystem 1860, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1865 for accessing an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits also include an embedded security engine 1870.

[0321] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0322] Figures 19A-19B Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0323] Figures 19A-19BThis is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 19A An exemplary graphics processor 1910, which can be fabricated using one or more IP cores according to at least one embodiment, is shown. Figure 19B An additional exemplary graphics processor 1940, which can be fabricated using one or more IP cores, is shown according to at least one embodiment. In at least one embodiment, Figure 19A The graphics processor 1910 is a low-power graphics processor core. In at least one embodiment, Figure 19B The graphics processor 1940 is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 1910 and 1940 may be... Figure 18 A variant of the 1810 graphics processor.

[0324] In at least one embodiment, the graphics processor 1910 includes a vertex processor 1905 and one or more fragment processors 1915A-1915N (e.g., 1915A, 1915B, 1915C, 1915D to 1915N-1 and 1915N). In at least one embodiment, the graphics processor 1910 can execute different shader programs via separate logic, such that the vertex processor 1905 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1915A-1915N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 1905 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 1915A-1915N use the primitive and vertex data generated by the vertex processor 1905 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 1915A-1915N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0325] In at least one embodiment, the graphics processor 1910 additionally includes one or more memory management units (MMUs) 1920A-1920B, one or more caches 1925A-1925B, and one or more circuit interconnects 1930A-1930B. In at least one embodiment, one or more MMUs 1920A-1920B provide virtual-to-physical address mappings for the graphics processor 1910, including virtual-to-physical address mappings for the vertex processor 1905 and / or fragment processors 1915A-1915N. Besides referencing vertex or image / texture data stored in one or more caches 1925A-1925B, this mapping may also reference vertex or image / texture data stored in memory. In at least one embodiment, one or more MMUs 1920A-1920B may be synchronized with other MMUs within the system, including with… Figure 18 One or more application processors 1805, graphics processors 1815, and / or video processors 1820 are associated with one or more MMUs, enabling each processor 1805-1820 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1930A-1930B enable the graphics processor 1910 to connect to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0326] In at least one embodiment, the graphics processor 1940 includes Figure 19A The graphics processor 1910 includes one or more MMUs 1920A-1920B, caches 1925A-1925B, and circuit interconnects 1930A-1930B. In at least one embodiment, the graphics processor 1940 includes one or more shader cores 1955A-1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F to 1955N-1 and 1955N) that provide a unified shader core architecture, wherein a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores may vary. In at least one embodiment, the graphics processor 1940 includes an inter-core task manager 1945 that acts as a thread dispatcher to assign execution threads to one or more shader cores 1955A-1955N and a tile unit 1958 to accelerate tile-based rendering operations, wherein rendering operations of a scene are subdivided in image space, for example, to take advantage of local spatial consistency within the scene or to optimize the use of internal caches.

[0327] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0328] Figures 20A-20B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, Figure 20A It shows that it can be included in Figure 18 The graphics core 2000 within the graphics processor 1810, and in at least one embodiment, may be as follows: Figure 19B The Unified Shader Cores 1955A-1955N are shown. Figure 20B A highly parallel general-purpose graphics processing unit 2030 suitable for deployment on a multi-chip module is shown in at least one embodiment.

[0329] In at least one embodiment, the graphics core 2000 includes a shared instruction cache 2002, texture units 2018, and a cache / shared memory 2020, which are shared for execution resources within the graphics core 2000. In at least one embodiment, the graphics core 2000 may include multiple slices 2001A-2001N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 2000. Slices 2001A-2001N may include supporting logic, including local instruction caches 2004A-2004N, thread schedulers 2006A-2006N, thread dispatchers 2008A-2008N, and a set of registers 2010A-2010N. In at least one embodiment, slices 2001A-2001N may include a set of additional functional units (AFU2012A-2012N), floating-point units (FPU 2014A-2014N), integer arithmetic logic units (ALU 2016-2016N), address calculation units (ACU 2013A-2013N), double-precision floating-point units (DPFPU 2015A-2015N), and matrix processing units (MPU2017A-2017N).

[0330] In at least one embodiment, the FPU 2014A-2014N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 2015A-2015N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 2016A-2016N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 2017A-2017N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 2017-2017N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 2012A-2012N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0331] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0332] Figure 20BA general-purpose processing unit (GPGPU) 2030 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by a set of graphics processing units. In at least one embodiment, the GPGPU 2030 can be directly linked to other instances of the GPGPU 2030 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 2030 includes a host interface 2032 for connection to a host processor. In at least one embodiment, the host interface 2032 is a PCI Express interface. In at least one embodiment, the host interface 2032 may be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 2030 receives commands from the host processor and uses a global scheduler 2034 to allocate execution threads associated with those commands to a set of compute clusters 2036A-2036H. In at least one embodiment, compute clusters 2036A-2036H share a cache memory 2038. In at least one embodiment, cache memory 2038 can be used as a higher-level cache than cache memory within computing clusters 2036A-2036H.

[0333] In at least one embodiment, the GPGPU 2030 includes memories 2044A-2044B, which are coupled to computing clusters 2036A-2036H via a set of memory controllers 2042A-2042B. In at least one embodiment, memories 2044A-2044B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0334] In at least one embodiment, each of the computing clusters 2036A-2036H includes a set of graphics cores, for example... Figure 20A The graphics core 2000 may include various types of integer and floating-point logic units that can perform computational operations across a range of precisions, including precisions suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 2036A-2036H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0335] In at least one embodiment, multiple instances of the GPGPU 2030 can be configured as a computing cluster. In at least one embodiment, the communication used for synchronization and data exchange by the computing clusters 2036A-2036H varies between embodiments. In at least one embodiment, the multiple instances of the GPGPU 2030 communicate via a host interface 2032. In at least one embodiment, the GPGPU 2030 includes an I / O hub 2039 that couples the GPGPU 2030 to a GPU link 2040, enabling direct connection to other instances of the GPGPU 2030. In at least one embodiment, the GPU link 2040 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between the multiple instances of the GPGPU 2030. In at least one embodiment, the GPU link 2040 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, the multiple instances of the GPGPU 2030 reside in a separate data processing system and communicate via network devices accessible through the host interface 2032. In at least one embodiment, GPU link 2040 may be configured to enable connection to a host processor other than or alternative to host interface 2032.

[0336] In at least one embodiment, the GPGPU 2030 can be configured to train a neural network. In at least one embodiment, the GPGPU 2030 can be used within an inference platform. In at least one embodiment, when the GPGPU 2030 is used for inference, the GPGPU 2030 may include fewer compute clusters 2036A-2036H compared to when the GPGPU 2030 is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 2044A-2044B can differ between inference and training configurations, wherein a higher bandwidth memory technology is dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2030 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during the inference operation of the deployed neural network.

[0337] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0338] Figure 21 A block diagram of a computer system 2100 according to at least one embodiment is shown. In at least one embodiment, the computer system 2100 includes a processing subsystem 2101 having one or more processors 2102 and a system memory 2104 communicating via an interconnect path that may include a memory hub 2105. In at least one embodiment, the memory hub 2105 may be a separate component within a chipset component or may be integrated within one or more processors 2102. In at least one embodiment, the memory hub 2105 is coupled to an I / O subsystem 2111 via a communication link 2106. In at least one embodiment, the I / O subsystem 2111 includes an I / O hub 2107 that enables the computer system 2100 to receive input from one or more input devices 2108. In at least one embodiment, the I / O hub 2107 enables a display controller to provide output to one or more display devices 2110A, the display controller being included in one or more processors 2102. In at least one embodiment, one or more display devices 2110A coupled to the I / O hub 2107 may include local, internal, or embedded display devices.

[0339] In at least one embodiment, the processing subsystem 2101 includes one or more parallel processors 2112 coupled to the memory hub 2105 via a bus or other communication link 2113. In at least one embodiment, the communication link 2113 can be any of many standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication architecture. In at least one embodiment, the one or more parallel processors 2112 form a computationally concentrated parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a multi-core integrated (MIC) processor. In at least one embodiment, the one or more parallel processors 2112 form a graphics processing subsystem that can output pixels to one or more display devices 2110A coupled via an I / O hub 2107. In at least one embodiment, the one or more parallel processors 2112 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 2110B.

[0340] In at least one embodiment, system storage unit 2114 may be connected to I / O hub 2107 to provide a storage mechanism for computer system 2100. In at least one embodiment, I / O switch 2116 may be used to provide an interface mechanism to enable connectivity between I / O hub 2107 and other components, such as network adapter 2118 and / or wireless network adapter 2119 which may be integrated into the platform, and various other devices that can be added via one or more additional devices 2120. In at least one embodiment, network adapter 2118 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 2119 may include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more wireless devices.

[0341] In at least one embodiment, the computer system 2100 may include other components not explicitly shown, such as USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 2107. In at least one embodiment, the interconnection can be implemented using any suitable protocol (e.g., PCI-based protocols such as PCI-Express or other bus or point-to-point communication interfaces and / or protocols). Figure 21 The communication paths of various components, such as NV-Link high-speed interconnect or interconnect protocols.

[0342] In at least one embodiment, one or more parallel processors 2112 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 2112 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computer system 2100 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2112, memory hub 2105, processor 2102, and I / O hub 2107 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computer system 2100 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 2100 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computer system.

[0343] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0344] processor

[0345] Figure 22A A parallel processor 2200 according to at least one embodiment is illustrated. In at least one embodiment, various components of the parallel processor 2200 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2200 is according to an exemplary embodiment. Figure 21 The variant of the parallel processor 2112 shown.

[0346] In at least one embodiment, the parallel processor 2200 includes a parallel processing unit 2202. In at least one embodiment, the parallel processing unit 2202 includes an I / O unit 2204 that enables communication with other devices, including other instances of the parallel processing unit 2202. In at least one embodiment, the I / O unit 2204 can be directly connected to other devices. In at least one embodiment, the I / O unit 2204 is connected to other devices using a hub or switch interface (e.g., a memory hub 2105). In at least one embodiment, the connection between the memory hub 2105 and the I / O unit 2204 forms a communication link 2113. In at least one embodiment, the I / O unit 2204 is connected to a host interface 2206 and a memory crossbar switch 2216, wherein the host interface 2206 receives commands for performing processing operations, and the memory crossbar switch 2216 receives commands for performing memory operations.

[0347] In at least one embodiment, when host interface 2206 receives a command buffer via I / O unit 2204, host interface 2206 can direct work operations to execute those commands to front end 2208. In at least one embodiment, front end 2208 is coupled to scheduler 2210, which is configured to assign commands or other work items to processing cluster array 2212. In at least one embodiment, scheduler 2210 ensures that processing cluster array 2212 is correctly configured and in an active state before assigning tasks to processing cluster array 2212. In at least one embodiment, scheduler 2210 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2210 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing array 2212. In at least one embodiment, host software can demonstrate workloads scheduled on processing array 2212 via one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed on the processing array 2212 by the scheduler 2210 logic within the microcontroller, which includes the scheduler 2210.

[0348] In at least one embodiment, the processing cluster array 2212 may include up to "N" processing clusters (e.g., clusters 2214A, 2214B to 2214N). In at least one embodiment, each cluster 2214A-2214N of the processing cluster array 2212 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2210 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2214A-2214N of the processing cluster array 2212, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2210, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2212. In at least one embodiment, different clusters 2214A-2214N of the processing cluster array 2212 may be assigned to process different types of programs or to perform different types of computations.

[0349] In at least one embodiment, the processing cluster array 2212 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2212 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2212 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0350] In at least one embodiment, the processing cluster array 2212 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2212 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2212 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2202 may transfer data from system memory via I / O unit 2204 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2222) and then written back to system memory.

[0351] In at least one embodiment, when the parallel processing unit 2202 is used to perform graphics processing, the scheduler 2210 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among the multiple clusters 2214A-2214N of the processing cluster array 2212. In at least one embodiment, portions of the processing cluster array 2212 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2214A-2214N may be stored in a buffer to allow intermediate data to be transferred between the clusters 2214A-2214N for further processing.

[0352] In at least one embodiment, the processing cluster array 2212 may receive processing tasks to be executed via a scheduler 2210, which receives commands defining the processing tasks from a front end 2208. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 2210 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 2208. In at least one embodiment, the front end 2208 may be configured to ensure that the processing cluster array 2212 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0353] In at least one embodiment, each of one or more instances of the parallel processing unit 2202 may be coupled to the parallel processor memory 2222. In at least one embodiment, the parallel processor memory 2222 may be accessed via a memory crossbar switch 2216, which may receive memory requests from the processing cluster array 2212 and the I / O unit 2204. In at least one embodiment, the memory crossbar switch 2216 may be accessed via a memory interface 2218. In at least one embodiment, the memory interface 2218 may include a plurality of partition units (e.g., partition units 2220A, 2220B to 2220N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 2222. In at least one embodiment, the plurality of partition units 2220A-2220N are configured to be equal to the number of memory units, such that the first partition unit 2220A has a corresponding first memory unit 2224A, the second partition unit 2220B has a corresponding memory unit 2224B, and the Nth partition unit 2220N has a corresponding Nth memory unit 2224N. In at least one embodiment, the number of partition units 2220A-2220N may not be equal to the number of memory devices.

[0354] In at least one embodiment, memory cells 2224A-2224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 2224A-2224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 2224A-2224N, allowing partitioning cells 2220A-2220N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 2222. In at least one embodiment, local instances of the parallel processor memory 2222 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0355] In at least one embodiment, any of clusters 2214A-2214N of the processing cluster array 2212 can process data to be written to any memory cell 2224A-2224N within the parallel processor memory 2222. In at least one embodiment, the memory crossbar switch 2216 can be configured to transfer the output of each cluster 2214A-2214N to any partition cell 2220A-2220N or another cluster 2214A-2214N, and clusters 2214A-2214N can perform further processing operations on the output. In at least one embodiment, each cluster 2214A-2214N can communicate with the memory interface 2218 via the memory crossbar switch 2216 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 2216 has a connection to the memory interface 2218 for communication with the I / O unit 2204, and a connection to a local instance of the parallel processor memory 2222, thereby enabling processing units within different processing clusters 2214A-2214N to communicate with system memory or other memory not local to the parallel processing unit 2202. In at least one embodiment, the memory crossbar switch 2216 may use virtual channels to separate traffic flows between clusters 2214A-2214N and partition units 2220A-2220N.

[0356] In at least one embodiment, multiple instances of the parallel processing unit 2202 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2202 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2202 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 2202 or the parallel processor 2200 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0357] Figure 22B This is a block diagram of partitioning unit 2220 according to at least one embodiment. In at least one embodiment, partitioning unit 2220 is... Figure 22AAn example of one of the partitioning units 2220A-2220N. In at least one embodiment, partitioning unit 2220 includes L2 cache 2221, frame buffer interface 2225, and ROP 2226 (raster operation unit). L2 cache 2221 is a read / write cache configured to perform load and store operations received from memory crossbar switch 2216 and ROP 2226. In at least one embodiment, L2 cache 2221 outputs read miss and urgent write-back requests to frame buffer interface 2225 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via frame buffer interface 2225. In at least one embodiment, frame buffer interface 2225 interacts with one of the memory cells in the parallel processor memory (such as memory cells 2224A-2224N of FIG. 22 (e.g., within parallel processor memory 2222)).

[0358] In at least one embodiment, ROP 2226 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2226 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 2226 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2226 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0359] In at least one embodiment, ROP 2226 is included within each processing cluster (e.g., clusters 2214A-2214N of FIG. 22), rather than within partition unit 2220. In at least one embodiment, read and write requests for pixel data are made via memory crossbar switch 2216 instead of pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device (such as...). Figure 21 Displayed by one or more display devices 2110, routed by processor 2102 for further processing, or by... Figure 22A One of the processing entities within the parallel processor 2200 is routed for further processing.

[0360] Figure 22CThis is a block diagram of a processing cluster 2214 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is an example of one of the processing clusters 2214A-2214N of FIG. 22. In at least one embodiment, the processing cluster 2214 may be configured to execute a number of threads in parallel, wherein the term "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0361] In at least one embodiment, the operation of the processing cluster 2214 can be controlled by a pipeline manager 2232 that assigns processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2232 receives instructions from the scheduler 2210 of FIG. 22 and manages the execution of these instructions via the graphics multiprocessor 2234 and / or texture unit 2236. In at least one embodiment, the graphics multiprocessor 2234 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2214 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 2214 may include one or more instances of the graphics multiprocessor 2234. In at least one embodiment, the graphics multiprocessor 2234 can process data, and the data crossover switch 2240 can be used to distribute the processed data to one of several possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2232 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossover switch 2240.

[0362] In at least one embodiment, each graphics multiprocessor 2234 within the processing cluster 2214 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0363] In at least one embodiment, instructions sent to the processing cluster 2214 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a general program on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 2234. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2234. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2234. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2234, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2234.

[0364] In at least one embodiment, the graphics multiprocessor 2234 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2234 may forgo the internal cache and use a cache memory (e.g., L1 cache 2248) within the processing cluster 2214. In at least one embodiment, each graphics multiprocessor 2234 may also access an L2 cache within partition units (e.g., partition units 2220A-2220N of FIG. 22), which are shared among all processing clusters 2214 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2234 may also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2202 may be used as global memory. In at least one embodiment, the processing cluster 2214 includes multiple instances of the graphics multiprocessor 2234, which may share common instructions and data that may be stored in the L1 cache 2248.

[0365] In at least one embodiment, each processing cluster 2214 may include a memory management unit (“MMU”) 2245 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2245 may reside within the memory interface 2218 of FIG22. In at least one embodiment, MMU 2245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more specifically, tiling) and optionally to cache line indices. In at least one embodiment, MMU 2245 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 2234 or the L1 cache or processing cluster 2214. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0366] In at least one embodiment, the processing cluster 2214 may be configured such that each graphics multiprocessor 2234 is coupled to a texture unit 2236 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2234, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2234 outputs a processed task to a data crossbar switch 2240 to provide the processed task to another processing cluster 2214 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 2216. In at least one embodiment, the preROP 2242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2234 and direct the data to a ROP unit that may be located together with partitioning units described herein (e.g., partitioning units 2220A-2220N of FIG. 22). In at least one embodiment, the PreROP 2242 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0367] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0368] Figure 22D A graphics multiprocessor 2234 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 2234 is coupled to a pipeline manager 2232 of a processing cluster 2214. In at least one embodiment, the graphics multiprocessor 2234 has an execution pipeline including, but not limited to, an instruction cache 2252, an instruction unit 2254, an address mapping unit 2256, a register file 2258, one or more general-purpose graphics processing unit (GPGPU) cores 2262, and one or more load / store units 2266. The GPGPU cores 2262 and the load / store units 2266 are coupled to a cache memory 2272 and a shared memory 2270 via a memory and cache interconnect 2268.

[0369] In at least one embodiment, instruction cache 2252 receives a stream of instructions to be executed from pipeline manager 2232. In at least one embodiment, instructions are cached in instruction cache 2252 and dispatched to instruction unit 2254 for execution. In at least one embodiment, instruction unit 2254 may dispatch instructions as thread groups (e.g., thread bundles), assigning each thread of the thread group to a different execution unit within GPGPU core 2262. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2256 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by load / store unit 2266.

[0370] In at least one embodiment, register file 2258 provides a set of registers for functional units of graphics multiprocessor 2234. In at least one embodiment, register file 2258 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 2234 (e.g., GPGPU core 2262, load / store unit 2266). In at least one embodiment, register file 2258 is partitioned among each functional unit, such that a dedicated portion of register file 2258 is allocated to each functional unit. In at least one embodiment, register file 2258 is partitioned among different thread bundles being executed by graphics multiprocessor 2234.

[0371] In at least one embodiment, each of the GPGPU cores 2262 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2234. In at least one embodiment, the GPGPU cores 2262 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 2234 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2262 may also include fixed-function or special-function logic.

[0372] In at least one embodiment, the GPGPU core 2262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 2262 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed using a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel using a single SIMD8 logic unit.

[0373] In at least one embodiment, the memory and cache interconnect 2268 is an interconnect network connecting each functional unit of the graphics multiprocessor 2234 to the register file 2258 and the shared memory 2270. In at least one embodiment, the memory and cache interconnect 2268 is a cross-switch interconnect that allows the load / store unit 2266 to perform load and store operations between the shared memory 2270 and the register file 2258. In at least one embodiment, the register file 2258 can operate at the same frequency as the GPGPU core 2262, resulting in very low latency for data transfer between the GPGPU core 2262 and the register file 2258. In at least one embodiment, the shared memory 2270 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 2234. In at least one embodiment, the cache memory 2272 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 2236. In at least one embodiment, the shared memory 2270 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in cache memory 2272, the thread executing on GPGPU core 2262 can also programmatically store data in shared memory.

[0374] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0375] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0376] Figure 23 A multi-GPU computing system 2300 according to at least one embodiment is illustrated. In at least one embodiment, the multi-GPU computing system 2300 may include a processor 2302 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2306A-D via a host interface switch 2304. In at least one embodiment, the host interface switch 2304 is a PCI Express switch device that couples the processor 2302 to a PCI Express bus, through which the processor 2302 communicates with the GPGPUs 2306A-D. The GPGPUs 2306A-D may be interconnected via a set of high-speed P2P GPU-to-GPU links 2316. In at least one embodiment, the GPU-to-GPU links 2316 are connected to each of the GPGPUs 2306A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 2316 enable direct communication between each GPGPU 2306A-D without communication via the host interface bus 2304 to which the processor 2302 is connected. In at least one embodiment, when GPU-to-GPU traffic is directed to the P2P GPU link 2316, the host interface bus 2304 remains available for system memory access or, for example, communication with other instances of the multi-GPU computing system 2300 via one or more network devices. While in at least one embodiment, the GPGPUs 2306A-D are connected to the processor 2302 via the host interface switch 2304, in at least one embodiment, the processor 2302 includes direct support for the P2P GPU link 2316 and can be directly connected to the GPGPUs 2306A-D.

[0377] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0378] Figure 24This is a block diagram of a graphics processor 2400 according to at least one embodiment. In at least one embodiment, the graphics processor 2400 includes a ring interconnect 2402, a pipeline front end 2404, a media engine 2437, and graphics cores 2480A-2480N. In at least one embodiment, the ring interconnect 2402 couples the graphics processor 2400 to other processing units, said processing units including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2400 is one of many processors integrated within a multi-core processing system.

[0379] In at least one embodiment, the graphics processor 2400 receives multiple batches of commands via a ring interconnect 2402. In at least one embodiment, the input commands are interpreted by a command streamer 2403 in a pipeline front-end 2404. In at least one embodiment, the graphics processor 2400 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2480A-2480N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2403 provides the commands to the geometry pipeline 2436. In at least one embodiment, for at least some media processing commands, the command streamer 2403 provides the commands to a video front-end 2434, which is coupled to a media engine 2437. In at least one embodiment, the media engine 2437 includes a video quality engine (VQE) 2430 for video and image post-processing, and a multi-format encoding / decoding (MFX) engine 2433 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2436 and the media engine 2437 each generate an execution thread for the thread execution resources provided by at least one graphics core 2480A.

[0380] In at least one embodiment, the graphics processor 2400 includes scalable thread execution resources featuring modular cores 2480A-2480N (sometimes referred to as core slices), each graphics core having multiple sub-cores 2450A-550N, 2460A-2460N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2400 may have any number of graphics cores 2480A to 2480N. In at least one embodiment, the graphics processor 2400 includes a graphics core 2480A having at least a first sub-core 2450A and a second sub-core 2460A. In at least one embodiment, the graphics processor 2400 is a low-power processor having a single sub-core (e.g., 2450A). In at least one embodiment, the graphics processor 2400 includes multiple graphics cores 2480A-2480N, each graphics core including a set of first sub-cores 2450A-2450N and a set of second sub-cores 2460A-2460N. In at least one embodiment, each of the first sub-cores 2450A-2450N includes at least a first set of execution units 2452A-2452N and media / texture samplers 2454A-2454N. In at least one embodiment, each of the second sub-cores 2460A-2460N includes at least a second set of execution units 2462A-2462N and samplers 2464A-2464N. In at least one embodiment, each of the sub-cores 2450A-2450N and 2460A-2460N shares a set of shared resources 2470A-2470N. In at least one embodiment, the shared resources include a shared cache memory and pixel operation logic.

[0381] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0382] Figure 25This is a block diagram illustrating a microarchitecture for a processor 2500 according to at least one embodiment, the processor 2500 including logic circuitry for executing instructions. In at least one embodiment, the processor 2500 can execute instructions, including x86 instructions, ARM instructions, and special-purpose instructions for application-specific integrated circuits (ASICs). In at least one embodiment, the processor 2510 may include registers for storing packaged data, such as the 64-bit wide MMX registers used in Intel Corporation's Santa Clara, California-enabled MMX technology microprocessors. TM Registers. In at least one embodiment, MMX registers available in integer and floating-point forms can operate alongside packaged data elements accompanied by Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technologies can hold such packaged data operands. In at least one embodiment, processor 2510 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0383] In at least one embodiment, processor 2500 includes an ordered front end (“front end”) 2501 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, front end 2501 may include several units. In at least one embodiment, instruction prefetcher 2526 fetches instructions from memory and provides the instructions to instruction decoder 2528, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2528 decodes the received instructions into one or more machine-executable so-called “micro-instructions” or “micro-operations” (also referred to as “micro-operations” or “micro-instructions”). In at least one embodiment, instruction decoder 2528 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, trace cache 2530 may assemble the decoded micro-instructions into a program-ordered sequence or trace in micro-instruction queue 2534 for execution. In at least one embodiment, when the trace cache 2530 encounters complex instructions, the microcode ROM 2532 provides the microinstructions required to complete the operation.

[0384] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-instructions are required to complete an instruction, the instruction decoder 2528 may access the microcode ROM 2532 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-instructions for processing at the instruction decoder 2528. In at least one embodiment, if multiple micro-instructions are required to complete the operation, the instructions may be stored in the microcode ROM 2532. In at least one embodiment, the trace cache 2530 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2532 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2532 has completed the micro-operation ordering of the instructions, the machine front end 2501 may resume fetching micro-operations from the trace cache 2530.

[0385] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2503 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions descend the pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 2503 includes, but is not limited to, an allocator / register renamer 2540, a memory microinstruction queue 2542, an integer / floating-point microinstruction queue 2544, a memory scheduler 2546, a fast scheduler 2502, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2504, and a simple floating-point scheduler (“simple FP scheduler”) 2506. In at least one embodiment, the fast scheduler 2502, the slow / general-purpose floating-point scheduler 2504, and the simple floating-point scheduler 2506 are also collectively referred to as “microinstruction schedulers 2502, 2504, 2506”. In at least one embodiment, the allocator / register renamer 2540 allocates the machine buffers and resources required for the sequential execution of each microinstruction. In at least one embodiment, the allocator / register renamer 2540 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 2540 also allocates entries for each microinstruction in one of two microinstruction queues, a memory microinstruction queue 2542 for memory operations and an integer / floating-point microinstruction queue 2544 for non-memory operations, preceding the memory scheduler 2546 and microinstruction schedulers 2502, 2504, and 2506. In at least one embodiment, the microinstruction schedulers 2502, 2504, and 2506 determine when they are ready to execute a microinstruction based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2502 can schedule on each half of the master clock cycle, while the slow / general-purpose floating-point scheduler 2504 and the simple floating-point scheduler 2506 can schedule once per master processor clock cycle. In at least one embodiment, microinstruction schedulers 2502, 2504, and 2506 arbitrate the scheduling port to schedule microinstructions for execution.

[0386] In at least one embodiment, execution block b11 includes, but is not limited to, integer register file / tribute network 2508, floating-point register file / tribute network (“FP register file / tribute network”) 2510, address generation units (“AGU”) 2512 and 2514, fast arithmetic logic units (“fast ALU”) 2516 and 2518, slow arithmetic logic unit (“slow ALU”) 2520, floating-point ALU (“FP”) 2522, and floating-point movement unit (“FP movement”) 2524. In at least one embodiment, integer register file / tribute network 2508 and floating-point register file / bypass network 2510 are also referred to herein as “register files 2508, 2510”. In at least one embodiment, AGUs 2512 and 2514, fast ALUs 2516 and 2518, slow ALU 2520, floating-point ALU 2522, and floating-point movement unit 2524 are also referred to herein as "execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524". In at least one embodiment, execution block b11 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0387] In at least one embodiment, register files 2508 and 2510 may be arranged between microinstruction schedulers 2502, 2504, and 2506 and execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524. In at least one embodiment, the integer register file / tribute network 2508 performs integer operations. In at least one embodiment, the floating-point register file / tribute network 2510 performs floating-point operations. In at least one embodiment, each of the register files 2508 and 2510 may include, but is not limited to, a tribute network that can bypass or forward recently completed results not yet written to the register file to a new dependent object. In at least one embodiment, register files 2508 and 2510 can communicate data with each other. In at least one embodiment, the integer register file / tribute network 2508 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, the floating-point register file / branch network 2510 may include, but is not limited to, entries with a width of 128 bits, since floating-point instructions typically have operands with a width of 64 to 128 bits.

[0388] In at least one embodiment, execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524 can execute instructions. In at least one embodiment, register files 2508 and 2510 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2500 can be, but is not limited to, any number of execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524, and combinations thereof. In at least one embodiment, floating-point ALU 2522 and floating-point move unit 2524 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2522 can be, but is not limited to, a 64-bit multiplication-64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to the fast ALUs 2516 and 2518. In at least one embodiment, the fast ALUs 2516 and 2518 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to the slow ALU 2520, because the slow ALU 2520 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by AGUS 2512 and 2514. In at least one embodiment, the fast ALU 2516, fast ALU 2518, and slow ALU 2520 can perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 2516, fast ALU 2518, and slow ALU 2520 can be implemented to support various data bit sizes, including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating-point ALU 2522 and the floating-point movement unit 2524 can be implemented to support a range of operands with various bit widths. In at least one embodiment, the floating-point ALU 2522 and the floating-point movement unit 2524 can operate on 128-bit wide packaged data operands in conjunction with SIMD and multimedia instructions.

[0389] In at least one embodiment, microinstruction schedulers 2502, 2504, and 2506 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed within processor 2500, processor 2500 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily deprives the scheduler of the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and may allow independent operations to be completed. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0390] In at least one embodiment, the term "register" may refer to an onboard processor storage location that can be used as part of an instruction that identifies operands. In at least one embodiment, a register may be one that can be used externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented using a variety of different techniques via circuitry within the processor, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

[0391] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0392] Figure 26A block diagram of a processing system according to at least one embodiment is shown. In at least one embodiment, system 2600 includes one or more processors 2602 and one or more graphics processors 2608, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2602 or processor cores 2607. In at least one embodiment, system 2600 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0393] In at least one embodiment, system 2600 may include or be integrated into a server-based gaming platform, including a game console, mobile game console, handheld game console, or online game console, which are game and media consoles. In at least one embodiment, system 2600 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, processing system 2600 may also include components coupled to or integrated into a wearable device, such as a smartwatch, smart glasses, augmented reality, or virtual reality device. In at least one embodiment, processing system 2600 is a television or set-top box device having one or more processors 2602 and a graphical interface generated by one or more graphics processors 2608.

[0394] In at least one embodiment, each of the one or more processors 2602 includes one or more processor cores 2607 for processing instructions that, when executed, perform operations against the system and user software. In at least one embodiment, each of the one or more processor cores 2607 is configured to process a particular instruction set 2609. In at least one embodiment, the instruction set 2609 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, each processor core 2607 may process a different instruction set 2609, which may include instructions that facilitate the emulation of other instruction sets. In at least one embodiment, the processor core 2607 may also include other processing devices, such as a digital signal processor (DSP).

[0395] In at least one embodiment, processor 2602 includes cache memory 2604. In at least one embodiment, processor 2602 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among various components of processor 2602. In at least one embodiment, processor 2602 also uses an external cache (e.g., a Level 3 (L3) cache or a last-level cache (LLC)) (not shown), which can be shared among processor cores 2607 using known cache coherence techniques. In at least one embodiment, processor 2602 further includes a register file 2606, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 2606 may include general-purpose registers or other registers.

[0396] In at least one embodiment, one or more processors 2602 are coupled to one or more interface buses 2610 to transmit communication signals, such as address, data, or control signals, between the processors 2602 and other components in the system 2600. In at least one embodiment, the interface bus 2610 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface 2610 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 2602 includes an integrated memory controller 2616 and a platform controller hub 2630. In at least one embodiment, the memory controller 2616 facilitates communication between memory devices and other components of the processing system 2600, while the platform controller hub (PCH) 2630 provides connectivity to input / output (I / O) devices via a local I / O bus.

[0397] In at least one embodiment, memory device 2620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or a device with suitable performance for use as processor memory. In at least one embodiment, memory device 2620 may be used as system memory of processing system 2600 to store data 2622 and instructions 2621 for use when one or more processors 2602 execute an application or process. In at least one embodiment, memory controller 2616 is also coupled to an optional external graphics processor 2612, which may communicate with one or more graphics processors 2608 of processor 2602 to perform graphics and media operations. In at least one embodiment, display device 2611 may be connected to processor 2602. In at least one embodiment, display device 2611 may include one or more internal display devices, such as in mobile electronic devices or laptop devices, or external display devices connected via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 2611 may include a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) or augmented reality (AR) applications.

[0398] In at least one embodiment, the platform controller hub 2630 enables peripheral devices to connect to the storage device 2620 and the processor 2602 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 2646, a network controller 2634, a firmware interface 2628, a wireless transceiver 2626, a touch sensor 2625, and a data storage device 2624 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 2624 may be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2625 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2626 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or LTE transceiver. In at least one embodiment, the firmware interface 2628 enables communication with the system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2634 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to interface bus 2610. In at least one embodiment, audio controller 2646 is a multi-channel high-definition audio controller. In at least one embodiment, processing system 2600 includes an optional legacy I / O controller 2640 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. In at least one embodiment, platform controller hub 2630 may also be connected to one or more Universal Serial Bus (USB) controllers 2642 that connect input devices, such as a keyboard and mouse combination 2643, a camera 2644, or other USB input devices.

[0399] In at least one embodiment, instances of the memory controller 2616 and platform controller hub 2630 may be integrated into a discrete external graphics processor, such as external graphics processor 2612. In at least one embodiment, the platform controller hub 2630 and / or the memory controller 2616 may be external to one or more processors 2602. For example, in at least one embodiment, system 2600 may include an external memory controller 2616 and platform controller hub 2630, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset communicating with processor 2602.

[0400] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0401] Figure 27 This is a block diagram of a processor 2700 having one or more processor cores 2702A-2702N, an integrated memory controller 2714, and an integrated graphics processor 2708 according to at least one embodiment. In at least one embodiment, the processor 2700 may include additional cores, up to and including additional cores 2702N indicated by dashed boxes. In at least one embodiment, each processor core 2702A-2702N includes one or more internal cache units 2704A-2704N. In at least one embodiment, each processor core may also access one or more shared cache units 2706.

[0402] In at least one embodiment, internal cache units 2704A-2704N and shared cache unit 2706 represent a cache memory hierarchy within processor 2700. In at least one embodiment, cache memory units 2704A-2704N may include at least one level of instruction and data cache within each processor core and one or more levels of cache in a shared intermediate cache, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, wherein the highest level of cache preceding external memory is classified as LLC. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2706 and 2704A-2704N.

[0403] In at least one embodiment, the processor 2700 may further include a set of one or more bus controller units 2716 and a system agent core 2710. In at least one embodiment, one or more bus controller units 2716 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 2710 provides management functions for various processor components. In at least one embodiment, the system agent core 2710 includes one or more integrated memory controllers 2714 to manage access to various external memory devices (not shown).

[0404] In at least one embodiment, one or more processor cores 2702A-2702N include support for multi-threaded concurrent processing. In at least one embodiment, system agent core 2710 includes components for coordinating and operating cores 2702A-2702N during multi-threaded processing. In at least one embodiment, system agent core 2710 may additionally include a power control unit (PCU) including logic and components for regulating one or more power states of processor cores 2702A-2702N and graphics processor 2708.

[0405] In at least one embodiment, processor 2700 further includes a graphics processor 2708 for performing graph processing operations. In at least one embodiment, graphics processor 2708 is coupled to a shared cache unit 2706 and a system proxy core 2710 including one or more integrated memory controllers 2714. In at least one embodiment, system proxy core 2710 further includes a display controller 2711 for driving graphics processor outputs to one or more coupled displays. In at least one embodiment, display controller 2711 may also be a separate module coupled to graphics processor 2708 via at least one interconnect, or it may be integrated within graphics processor 2708.

[0406] In at least one embodiment, ring-based interconnect unit 2712 is used to couple internal components of processor 2700. In at least one embodiment, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, may be used. In at least one embodiment, graphics processor 2708 is coupled to ring interconnect 2712 via I / O link 2713.

[0407] In at least one embodiment, I / O link 2713 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory module 2718 (e.g., eDRAM module). In at least one embodiment, each of processor cores 2702A-2702N and graphics processor 2708 uses embedded memory module 2718 as a shared last-level cache.

[0408] In at least one embodiment, processor cores 2702A-2702N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2702A-2702N are heterogeneous in terms of instruction set architecture (ISA), with one or more processor cores 2702A-2702N executing a common instruction set, while one or more other processor cores 2702A-2702N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, processor cores 2702A-2702N are heterogeneous in terms of microarchitecture, with one or more cores having relatively high power consumption coupled to one or more power cores having lower power consumption. In at least one embodiment, processor 2700 may be implemented on one or more chips or implemented as a SoC integrated circuit.

[0409] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0410] Figure 28 This is a block diagram of a graphics processor 2800, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In at least one embodiment, the graphics processor 2800 communicates with registers on the graphics processor 2800 and commands placed in memory via a memory-mapped I / O interface. In at least one embodiment, the graphics processor 2800 includes a memory interface 2814 for accessing memory. In at least one embodiment, the memory interface 2814 is an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0411] In at least one embodiment, the graphics processor 2800 further includes a display controller 2802 for driving display output data to the display device 2820. In at least one embodiment, the display controller 2802 includes a combination of hardware for one or more overlay planes of the display device 2820 and multi-layer video or user interface elements. In at least one embodiment, the display device 2820 may be an internal or external display device. In at least one embodiment, the display device 2820 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In at least one embodiment, the graphics processor 2800 includes a video codec engine 2806 for encoding, decoding, or transcoding media into one or more media encoding formats, encoding, decoding, or transcoding from one or more media encoding formats, or encoding, decoding, or transcoding between one or more media encoding formats, including but not limited to Moving Picture Experts Group (MPEG) formats (e.g., MPEG-2), Advanced Video Coding (AVC) formats (e.g., H.264 / MPEG-4 AVC, and SMPTE 421M / VC-1), and Joint Picture Experts Group (JPEG) formats (e.g., JPEG) and MotionJPEG (MJPEG) formats.

[0412] In at least one embodiment, the graphics processor 2800 includes a block image transfer (BLIT) engine 2804 to perform two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfer. However, in at least one embodiment, one or more components of a graphics processing engine (GPE) 2810 are used to perform 2D graphics operations. In at least one embodiment, the GPE 2810 is a computational engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0413] In at least one embodiment, GPE 2810 includes a 3D pipeline 2812 for performing 3D operations, such as rendering 3D images and scenes using processing functions that manipulate 3D primitive shapes (e.g., rectangles, triangles, etc.). In at least one embodiment, 3D pipeline 2812 includes programmable and fixed function elements that perform various tasks and / or generate execution threads to 3D / media subsystem 2815. While 3D pipeline 2812 can be used to perform media operations, in at least one embodiment, GPE 2810 also includes a media pipeline 2816 for performing media operations such as video post-processing and image enhancement.

[0414] In at least one embodiment, the media pipeline 2816 includes fixed-function or programmable logic units for performing one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, replacing or representing the video codec engine 2806. In at least one embodiment, the media pipeline 2816 also includes a thread generation unit for generating threads to execute on the 3D / media subsystem 2815. In at least one embodiment, the generated threads perform computations of media operations on one or more graphics execution units included in the 3D / media subsystem 2815.

[0415] In at least one embodiment, the 3D / media subsystem 2815 includes logic for executing threads generated by the 3D pipeline 2812 and the media pipeline 2816. In at least one embodiment, the 3D pipeline 2812 and the media pipeline 2816 send thread execution requests to the 3D / media subsystem 2815, which includes thread dispatch logic for arbitrating various requests and dispatching them to available thread execution resources. In at least one embodiment, the execution resources include an array of graphics execution units for processing 3D and media threads. In at least one embodiment, the 3D / media subsystem 2815 includes one or more internal caches for thread instructions and data. In at least one embodiment, the subsystem 2815 also includes shared memory, including registers and addressable memory, for sharing data among threads and storing output data.

[0416] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0417] Figure 29 This is a block diagram of a graphics processing engine 2910 of a graphics processor according to at least one embodiment. In at least one embodiment, the graphics processing engine (GPE) 2910 is... Figure 28 The version of GPE 2810 shown is illustrated. In at least one embodiment, the media pipeline 2916 is optional and may not be explicitly included in the GPE 2910. In at least one embodiment, a separate media and / or image processor is coupled to the GPE 2910.

[0418] In at least one embodiment, GPE 2910 is coupled to or includes command stream converter 2903, which provides command streams to 3D pipeline 2912 and / or media pipeline 2916. In at least one embodiment, command stream converter 2903 is coupled to memory, which may be system memory, or one or more of internal cache memory and shared cache memory. In at least one embodiment, command stream converter 2903 receives commands from memory and sends the commands to 3D pipeline 2912 and / or media pipeline 2916. In at least one embodiment, the commands are instructions, primitives, or micro-operations retrieved from a circular buffer that stores commands for 3D pipeline 2912 and media pipeline 2916. In at least one embodiment, the circular buffer may further include a batch command buffer storing multiple commands in batches. In at least one embodiment, commands for 3D pipeline 2912 may further include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 2912 and / or image data and memory objects for media pipeline 2916. In at least one embodiment, the 3D pipeline 2912 and the media pipeline 2916 process commands and data by performing operations or by dispatching one or more execution threads to the graphics core array 2914. In at least one embodiment, the graphics core array 2914 includes one or more graphics core blocks (e.g., one or more graphics cores 2915A, one or more graphics cores 2915B), each block including one or more graphics cores. In at least one embodiment, each graphics core includes a set of graphics execution resources, which include general and graphics-specific execution logic for performing graphics and computation operations, as well as fixed-function texture processing and / or machine learning and artificial intelligence acceleration logic.

[0419] In at least one embodiment, the 3D pipeline 2912 includes fixed functions and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2914. In at least one embodiment, the graphics core array 2914 provides a unified execution resource block for processing shader programs. In at least one embodiment, the multipurpose execution logic (e.g., execution units) within the graphics cores 2915A-2915B of the graphics core array 2914 includes support for various 3D API shader languages ​​and can execute multiple concurrently running threads associated with multiple shaders.

[0420] In at least one embodiment, the graphics core array 2914 further includes execution logic for performing media functions, such as video and / or image processing. In at least one embodiment, in addition to graphics processing operations, the execution unit also includes general-purpose logic programmable to perform parallel general-purpose computing operations.

[0421] In at least one embodiment, output data can be output to memory in a unified return buffer (URB) 2918, the output data being generated by a thread executing on the graphics core array 2914. In at least one embodiment, the URB 2918 can store data from multiple threads. In at least one embodiment, the URB 2918 can be used to send data between different threads executing on the graphics core array 2914. In at least one embodiment, the URB 2918 can also be used for synchronization between threads on the graphics core array 2914 and fixed-function logic within shared-function logic 2920.

[0422] In at least one embodiment, the graphics core array 2914 is scalable, such that it includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of the GPE 2910. In at least one embodiment, the execution resources are dynamically scalable, such that they can be enabled or disabled as needed.

[0423] In at least one embodiment, the graphics core array 2914 is coupled to shared function logic 2920, which includes multiple resources shared among the graphics cores in the graphics core array 2914. In at least one embodiment, the shared functions performed by the shared function logic 2920 are embodied in hardware logic units that provide dedicated supplementary functions to the graphics core array 2914. In at least one embodiment, the shared function logic 2920 includes, but is not limited to, a sampler 2921, math 2922, and inter-thread communication (ITC) logic 2923. In at least one embodiment, one or more caches 2925 are included in or coupled to the shared function logic 2920.

[0424] In at least one embodiment, shared functionality is used if the demand for dedicated functionality is insufficient to be contained within the graphics core array 2914. In at least one embodiment, a single instance of the dedicated functionality is used in shared functionality logic 2920 and shared among other execution resources within the graphics core array 2914. In at least one embodiment, a specific shared functionality may be included within shared functionality logic 2916 within the graphics core array 2914, said specific shared functionality being widely used within shared functionality logic 2920 of the graphics core array 2914. In at least one embodiment, shared functionality logic 2916 within the graphics core array 2914 may include some or all of the logic within shared functionality logic 2920. In at least one embodiment, all logic elements within shared functionality logic 2920 may be replicated within shared functionality logic 2916 of the graphics core array 2914. In at least one embodiment, shared functionality logic 2920 is excluded to support shared functionality logic 2916 within the graphics core array 2914.

[0425] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0426] Figure 30 This is a block diagram of the hardware logic of a graphics processor core 3000 according to at least one embodiment described herein. In at least one embodiment, the graphics processor core 3000 is included within a graphics core array. In at least one embodiment, the graphics processor core 3000 (sometimes referred to as a core slice) may be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 3000 is an example of a graphics core slice, and the graphics processor described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 3000 may include a fixed-function block 3030 coupled to a plurality of subcores 3001A-3001F, the subcores also referred to as subslices, which include modular blocks of general-purpose and fixed-function logic.

[0427] In at least one embodiment, the fixed-function block 3030 includes a geometry and fixed-function pipeline 3036, which, for example, may be shared by all sub-cores of the graphics processor 3000 in a lower-performance and / or lower-power graphics processor implementation. In at least one embodiment, the geometry and fixed-function pipeline 3036 includes a 3D fixed-function pipeline, a video front-end unit, a thread generator and a thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0428] In at least one fixed embodiment, the fixed functional block 3030 further includes a graphics SoC interface 3037, a graphics microcontroller 3038, and a media pipeline 3039. In at least one embodiment, the graphics SoC interface 3037 provides an interface between the graphics core 3000 and other processor cores in the on-chip integrated circuit system. In at least one embodiment, the graphics microcontroller 3038 is a programmable subprocessor configurable to manage various functions of the graphics processor 3000, including thread dispatch, scheduling, and preemption. In at least one embodiment, the media pipeline 3039 includes logic that facilitates decoding, encoding, preprocessing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 3039 implements media operations via requests for computation or sampling logic within subcores 3001-3001F.

[0429] In at least one embodiment, the SoC interface 3037 enables the graphics core 3000 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared last-level cache, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 3037 also enables communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enables the use and / or implementation of global memory atoms that can be shared between the graphics core 3000 and the CPU within the SoC. In at least one embodiment, the SoC interface 3037 also implements power management control for the graphics core 3000 and enables interfacing between the clock domain of the graphics core 3000 and other clock domains within the SoC. In at least one embodiment, the SoC interface 3037 enables the receipt of command buffers from a command stream converter and a global thread dispatcher, configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, when a media operation is to be performed, commands and instructions may be dispatched to the media pipeline 3039, or when a graphics processing operation is to be performed, they may be assigned to the geometry and fixed-function pipeline (e.g., geometry and fixed-function pipeline 3036, and / or geometry and fixed-function pipeline 3014).

[0430] In at least one embodiment, the graphics microcontroller 3038 can be configured to perform various scheduling and management tasks on the graphics core 3000. In at least one embodiment, the graphics microcontroller 3038 can perform graphics and / or compute workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 3002A-3002F, 3004A-3004F in subcores 3001A-3001F. In at least one embodiment, host software executing on the CPU core of the SoC including the graphics core 3000 can submit a workload of one of a plurality of graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operation includes determining which workload should be run next, submitting the workload to a command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In at least one embodiment, the graphics microcontroller 3038 may also facilitate a low-power or idle state of the graphics core 3000, thereby providing the graphics core 3000 with the ability to save and restore registers across low-power state transitions within the graphics core 3000, independent of the operating system and / or the graphics driver software on the system.

[0431] In at least one embodiment, the graphics core 3000 may have up to N more or fewer modular sub-cores than the illustrated sub-cores 3001A-3001F. For each group of N sub-cores, in at least one embodiment, the graphics core 3000 may further include shared functional logic 3010, shared and / or cache memory 3012, geometry / fixed-function pipeline 3014, and additional fixed-function logic 3016 to accelerate various graphics and computational processing operations. In at least one embodiment, the shared functional logic 3010 may include logic units (e.g., samplers, mathematical and / or inter-thread communication logic) that can be shared by each of the N sub-cores within the graphics core 3000. The shared and / or cache memory 3012 may be the last-level cache of the N sub-cores 3001A-3001F within the graphics core 3000, and may also be used as shared memory accessible by multiple sub-cores. In at least one embodiment, a geometry / fixed function pipeline 3014 may be included to replace the geometry / fixed function pipeline 3036 within the fixed function block 3030, and similar logic units may be included.

[0432] In at least one embodiment, the graphics core 3000 includes additional fixed-function logic 3016, which may include various fixed-function acceleration logics for use by the graphics core 3000. In at least one embodiment, the additional fixed-function logic 3016 includes additional geometry pipelines for use in position-only shading. In position-only shading, there are at least two geometry pipelines, and in the full geometry pipeline and culling pipeline within the geometry and fixed-function pipelines 3014, 3036, it is an additional geometry pipeline that can be included in the additional fixed-function logic 3016. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of the application, each with a separate environment. In at least one embodiment, position-only shading can hide long culling runs of discarded triangles, thereby allowing shading to be completed earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed-function logic 3016 can execute the position shader in parallel with the main application and typically generates critical results faster than the full pipeline because the culling pipeline acquires and occludes the positional attributes of vertices without performing rasterization and rendering pixels to the framebuffer. In at least one embodiment, the culling pipeline can use the generated critical results to compute visibility information for all triangles, regardless of whether those triangles were culled. In at least one embodiment, the full pipeline (which may be referred to as the replay pipeline in this case) can consume visibility information to skip culled triangles and only occlude the visible triangles that are ultimately passed to the rasterization stage.

[0433] In at least one embodiment, the additional fixed-function logic 3016 may also include machine learning acceleration logic, such as fixed-function matrix multiplication logic, for implementing optimizations for machine learning training or inference.

[0434] In at least one embodiment, each graphics subcore 3001A-3001F includes a set of execution resources that can be used to perform graphics, media, and computational operations in response to requests from the graphics pipeline, media pipeline, or shader program. In at least one embodiment, the graphics subcore 3001A-3001F includes multiple EU arrays 3002A-3002F, 3004A-3004F, thread dispatch and inter-thread communication (TD / IC) logic 3003A-3003F, 3D (e.g., texture) samplers 3005A-3005F, media samplers 3006A-3006F, shader processors 3007A-3007F, and shared local memory (SLM) 3008A-3008F. Each of the EU arrays 3002A-3002F and 3004A-3004F contains multiple execution units, which are general-purpose graphics processing units capable of servicing graphics, media, or computational operations, performing floating-point and integer / fixed-point logic operations, including graphics, media, or computational shader programs. In at least one embodiment, the TD / IC logic 3003A-3003F performs local thread dispatch and thread control operations for the execution units within the subcore and facilitates communication between threads executing on the execution units of the subcore. In at least one embodiment, the 3D samplers 3005A-3005F can read data associated with textures or other 3D graphics into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the sampling state and texture format configured and associated with a given texture. In at least one embodiment, the media samplers 3006A-3006F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics subcore 3001A-3001F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each subcore 3001A-3001F may utilize shared local memory 3008A-3008F within each subcore, enabling threads executing within a thread group to use a common pool of on-chip memory for execution.

[0435] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0436] Figures 31A-31BThe diagram illustrates thread execution logic 3100 of an array of processing elements including a graphics processor core, according to at least one embodiment. Figure 31A At least one embodiment is shown in which thread execution logic 3100 is used. Figure 31B Exemplary internal details of an execution unit according to at least one embodiment are shown.

[0437] like Figure 31A As shown, in at least one embodiment, thread execution logic 3100 includes a shader processor 3102, a thread dispatcher 3104, an instruction cache 3106, a scalable execution unit array including multiple execution units 3108A-3108N, a sampler 3110, a data cache 3112, and a data port 3114. In at least one embodiment, the scalable execution unit array can be dynamically scaled, for example, based on the computational requirements of the workload, by enabling or disabling one or more execution units (e.g., any one of execution units 3108A, 3108B, 3108C, 3108D, through 3108N-1 and 3108N). In at least one embodiment, the scalable execution units are interconnected via an interconnect structure linking to each execution unit. In at least one embodiment, the thread execution logic 3100 includes one or more connections to memory (such as system memory or cache memory) via one or more of the instruction cache 3106, data port 3114, sampler 3110, and execution units 3108A-3108N. In at least one embodiment, each execution unit (e.g., 3108A) is an independent programmable general-purpose computing unit capable of executing multiple concurrent hardware threads, processing multiple data elements in parallel for each thread. In at least one embodiment, the array of execution units 3108A-3108N is scalable to include any number of individual execution units.

[0438] In at least one embodiment, execution units 3108A-3108N are primarily used to execute shader programs. In at least one embodiment, shader processor 3102 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 3104. In at least one embodiment, thread dispatcher 3104 includes logic for arbitrating thread initialization celebrations from the graphics and media pipeline and for instantiating requested threads on one or more execution units 3108A-3108N. For example, in at least one embodiment, the geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In at least one embodiment, thread dispatcher 3104 can also handle runtime thread generation requests from executing shader programs.

[0439] In at least one embodiment, execution units 3108A-3108N support an instruction set that includes native support for many standard 3D graphics shader instructions, enabling shader programs in graphics libraries (e.g., Direct3D and OpenGL) to execute with minimal conversion. In at least one embodiment, the execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, and / or vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., computation and media shaders). In at least one embodiment, each execution unit 3108A-3108N includes one or more arithmetic logic units (ALUs) capable of performing multiple-issue single-instruction multiple-data (SIMD) operations, and multithreaded operation enables an efficient execution environment despite higher latency memory access. In at least one embodiment, each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread states. In at least one embodiment, execution is multiple issues per clock cycle to a pipeline capable of integer, single-precision, and double-precision floating-point operations, SIMD branching functions, logical operations, a priori operations, and other operations. In at least one embodiment, while waiting for data from one of the memory or shared functions, dependency logic within execution units 3108A-3108N causes the waiting thread to sleep until the requested data is returned. In at least one embodiment, while the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, in at least one embodiment, during the latency associated with vertex shader operations, the execution unit can perform operations on the pixel shader, fragment shader, or another type of shader program (including different vertex shaders).

[0440] In at least one embodiment, each of the execution units 3108A-3108N operates on an array of data elements. In at least one embodiment, the plurality of data elements is an "execution size" or the number of instruction channels. In at least one embodiment, an execution channel is a logical unit for execution of data element access, masking, and flow control within an instruction. In at least one embodiment, the plurality of channels may be independent of the plurality of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In at least one embodiment, the execution units 3108A-3108N support integer and floating-point data types.

[0441] In at least one embodiment, the execution unit instruction set includes SIMD instructions. In at least one embodiment, various data elements can be stored in registers as encapsulated data types, and the execution unit will process various elements based on the data size of those elements. For example, in at least one embodiment, when operating on a 256-bit wide vector, 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 64-bit encapsulated data elements (four-word (QW) size data elements), eight separate 32-bit encapsulated data elements (double-word (DW) size data elements), sixteen separate 16-bit encapsulated data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, in at least one embodiment, different vector widths and register sizes are possible.

[0442] In at least one embodiment, one or more execution units may be combined into a fused execution unit 3109A-3109N having thread control logic (3107A-3107N) for executing fused EUs. In at least one embodiment, multiple EUs may be merged into an EU group. In at least one embodiment, the number of EUs in a fused EU group may be configured to execute separate SIMD hardware threads. The number of EUs in a fused EU group may vary depending on the embodiment. In at least one embodiment, each EU may execute various SIMD widths, including but not limited to SIMD8, SIMD16, and SIMD32. In at least one embodiment, each fused graphics execution unit 3109A-3109N includes at least two execution units. For example, in at least one embodiment, a fused execution unit 3109A includes a first EU 3108A, a second EU 3108B, and thread control logic 3107A shared by the first EU 3108A and the second EU 3108B. In at least one embodiment, thread control logic 3107A controls the threads executing on the fused graphics execution unit 3109A, thereby allowing each EU within the fused execution units 3109A-3109N to execute using a common instruction pointer register.

[0443] In at least one embodiment, one or more internal instruction caches (e.g., 3106) are included in the thread execution logic 3100 to cache thread instructions for the execution unit. In at least one embodiment, one or more data caches (e.g., 3112) are included to cache thread data during thread execution. In at least one embodiment, a sampler 3110 is included to provide texture sampling for 3D operations and media sampling for media operations. In at least one embodiment, the sampler 3110 includes dedicated texture or media sampling functions to process texture or media data during the sampling process before providing sampled data to the execution unit.

[0444] During execution, in at least one embodiment, the graphics and media pipeline sends thread initiation requests to thread execution logic 3100 via thread creation and dispatch logic. In at least one embodiment, once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 3102 is invoked to further compute output information and cause the results to be written to output surfaces (e.g., color buffer, depth buffer, stencil buffer, etc.). In at least one embodiment, the pixel shader or fragment shader computes values ​​of various vertex attributes to be interpolated on the rasterized objects. In at least one embodiment, the pixel processor logic within shader processor 3102 then executes a pixel or fragment shader program provided by an application programming interface (API). In at least one embodiment, to execute the shader program, shader processor 3102 dispatches threads to execution units (e.g., 3108A) via thread dispatcher 3104. In at least one embodiment, shader processor 3102 uses texture sampling logic in sampler 3110 to access texture data in a texture map stored in memory. In at least one embodiment, arithmetic operations on the texture data and the input geometry data are performed to calculate pixel color data for each geometric segment, or one or more pixels are discarded for further processing.

[0445] In at least one embodiment, data port 3114 provides a memory access mechanism for thread execution logic 3100 to output processed data to memory for further processing on the graphics processor output pipeline. In at least one embodiment, data port 3114 includes or is coupled to one or more cache memories (e.g., data cache 3112) to cache data for memory access via the data port.

[0446] like Figure 31BAs shown, in at least one embodiment, the graphics execution unit 3108 may include an instruction fetch unit 3137, a general-purpose register file array (GRF) 3124, an architecture register file array (ARF) 3126, a thread arbiter 3122, a send unit 3130, a branch unit 3132, a set of SIMD floating-point units (FPUs) 3134, and in at least one embodiment, a set of dedicated integer SIMD ALUs 3135. In at least one embodiment, the GRF 3124 and ARF 3126 include a set of general-purpose register files and architecture register files associated with each concurrent hardware thread that may be active in the graphics execution unit 3108. In at least one embodiment, the architecture state of each thread is maintained in the ARF 3126, while data used during thread execution is stored in the GRF 3124. In at least one embodiment, the execution state of each thread, including the instruction pointer of each thread, may be stored in thread-specific registers in the ARF 3126.

[0447] In at least one embodiment, the graphics execution unit 3108 has an architecture that is a combination of simultaneous multithreading (SMT) and fine-grained interleaved multithreading (IMT). In at least one embodiment, the architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and the number of registers per execution unit, wherein execution unit resources are logically allocated for executing multiple simultaneous threads.

[0448] In at least one embodiment, the graphics execution unit 3108 can jointly issue multiple instructions, each of which can be a different instruction. In at least one embodiment, the thread arbiter 3122 of the graphics execution unit thread 3108 can dispatch instructions to one of the sending unit 3130, the branching unit 3142, or the SIMD FPU 3134 for execution. In at least one embodiment, each execution thread can access 128 general-purpose registers in the GRF 3124, where each register can store 32 bytes and can be accessed as a SIMD 8-element vector of 32-bit data elements. In at least one embodiment, each execution unit thread can access 4KB of the GRF 3124, although the embodiments are not limited thereto, and more or fewer register resources may be provided in other embodiments. In at least one embodiment, although the number of threads per execution unit may also vary depending on the embodiment, a maximum of seven threads can be executed simultaneously. In at least one embodiment where seven threads can access 4KB, the GRF 3124 can store a total of 28KB. In at least one embodiment, the flexible addressing mode can allow registers to be addressed together to efficiently build wider registers or rectangular block data structures representing strides.

[0449] In at least one embodiment, memory operations, sampler operations, and other longer-latency system communications are scheduled via a “send” instruction executed by message sending unit 3130. In at least one embodiment, branch instructions are dispatched to a dedicated branching unit 3132 to facilitate SIMD divergence and eventual convergence.

[0450] In at least one embodiment, the graphics execution unit 3108 includes one or more SIMD floating-point units (FPUs) 3134 to perform floating-point operations. In at least one embodiment, the one or more FPUs 3134 also support integer computation. In at least one embodiment, the one or more FPUs 3134 can perform up to M 32-bit floating-point (or integer) operations in SIMD, or up to 2M 16-bit integer or 16-bit floating-point operations in SIMD. In at least one embodiment, at least one FPU provides extended mathematical capabilities to support high-throughput a priori mathematical functions and double-precision 64-bit floating-point operations. In at least one embodiment, a set of 8-bit integer SIMD ALUs 3135 is also present and can be specifically optimized to perform operations related to machine learning computations.

[0451] In at least one embodiment, an array of multiple instances of the graphics execution unit 3108 may be instantiated in a graphics sub-core group (e.g., a sub-slice). In at least one embodiment, the execution unit 3108 may execute instructions across multiple execution channels. In at least one embodiment, each thread executing on the graphics execution unit 3108 executes on a different channel.

[0452] In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to process one or more fifth-generation (5G) radio signals. In at least one embodiment, referring to the accompanying drawings, one or more circuits, processors, or other devices or technologies are adapted to equalize one or more 5G radio signals in parallel. In at least one embodiment, signal processing is performed according to the embodiments described herein, for example, regarding... Figure 1-10 Those described.

[0453] Figure 32A parallel processing unit (“PPU”) 3200 according to at least one embodiment is illustrated. In at least one embodiment, the PPU 3200 is configured with machine-readable code that, if executed by the PPU 3200, causes the PPU 3200 to perform some or all of the processes and techniques described herein. In at least one embodiment, the PPU 3200 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multi-threading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simple instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a set of instructions configured to be executed by the PPU 3200. In at least one embodiment, the PPU 3200 is a graphics processing unit (“GPU”) configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data to generate two-dimensional (“2D”) image data for display on a display device, such as a liquid crystal display (“LCD”) device. In at least one embodiment, the PPU 3200 is used to perform computations, such as linear algebra operations and machine learning operations. Figure 32 An example parallel processor is shown for illustrative purposes only and should be interpreted as a non-limiting example of a processor architecture contemplated within the scope of this disclosure, which may be supplemented and / or replaced by any suitable p...

Claims

1. A processor, comprising: One or more circuits, which use two or more threads and one or more sets of stored matrix information accessed in parallel by the two or more threads, to equalize one or more 5G radio signals, wherein the coefficients and residual values ​​of the linear minimum mean square error (LMMSE) estimate are solved using an augmented matrix corresponding to the one or more sets of stored matrix information to equalize the one or more 5G radio signals.

2. The processor of claim 1, wherein the one or more circuits are configured to solve for the coefficients and residuals of the LMMSE estimate based at least in part on Cholesky decomposition, forward substitution, and backward substitution.

3. The processor of claim 1, wherein the one or more circuits are configured to solve for the coefficients and residuals of the LMMSE estimate based at least in part on LU decomposition and backward substitution.

4. The processor of claim 1, wherein the technique of using parallel computing to equalize the one or more 5G radio signals is selected based at least in part on a multiple-input multiple-output (MIMO) configuration.

5. The processor of claim 4, wherein the technique for parallel equalization of the one or more 5G radio signals includes at least one of time slot level equalization or sub-time slot level equalization, wherein a time slot includes multiple symbols and a sub-time slot includes one symbol.

6. The processor of claim 4, wherein the technique for parallel equalization of the one or more 5G radio signals includes parallel equalization of multiple subcarriers.

7. The processor of claim 1, wherein one or more circuits are configured to equalize the one or more 5G radio signals by performing at least channel estimation using a data structure overlaid in shared memory.

8. The processor of claim 1, wherein the one or more 5G radio signals are equalized in parallel by performing channel equalization corresponding to a plurality of subcarriers in parallel.

9. The processor of claim 1, wherein one or more circuits execute instructions to parallel equalize the one or more 5G radio signals using data stored in shared memory.

10. The processor of claim 1, wherein the two or more threads are graphics processing unit (GPU) threads.

11. A system comprising: One or more processors are configured to equalize one or more 5G radio signals using two or more threads and one or more sets of stored matrix information accessed in parallel by the two or more threads, wherein the one or more processors are configured to equalize the one or more 5G radio signals by solving for coefficients and residual values ​​of a linear minimum mean square error (LMMSE) estimate using at least an augmented matrix corresponding to the one or more sets of stored matrix information.

12. The system of claim 11, wherein the augmented matrix is ​​covered by an intermediate matrix in shared memory.

13. The system of claim 11, wherein the one or more processors are configured to determine, at least in part, to perform at least one of Cholesky or LU decomposition to solve for the coefficients and residuals of the LMMSE estimate based on a multiple-input multiple-output (MIMO) configuration.

14. The system of claim 11, wherein the one or more processors are configured to perform the equalization in parallel by at least equalizing the data symbols associated with the frequency bin.

15. The system of claim 11, wherein the one or more processors are configured to perform the equalization in parallel with respect to a plurality of subcarriers.

16. The system of claim 11, wherein the parallel processing unit thread block equalizes the subcarriers associated with the physical resource block.

17. The system of claim 11, wherein the two or more threads are graphics processing unit (GPU) threads.

18. A non-transitory machine-readable medium having a set of instructions stored thereon, such that if the set of instructions is executed by one or more processors, the one or more processors at least: One or more 5G radio signals are equalized using two or more threads and one or more sets of stored matrix information accessed in parallel by the two or more threads. in, The one or more processors equalize the one or more 5G radio signals by solving for the coefficients and error values ​​of the linear minimum mean square error (LMMSE) estimate using at least an augmented matrix corresponding to the set or more of stored matrix information.

19. The non-transitory machine-readable medium of claim 18, wherein the augmented matrix overlays an intermediate matrix in shared memory.

20. The non-transitory machine-readable medium of claim 18, wherein if the set of instructions is executed by the one or more processors, the one or more processors are further configured to determine, at least in part, to perform at least one of Cholesky or LU decomposition to solve for the coefficients and error values ​​of the error estimate based on a multiple-input multiple-output (MIMO) configuration.

21. The non-transitory machine-readable medium of claim 18, wherein if the set of instructions is executed by the one or more processors, the one or more processors are further made to perform equalization at least in part based on at least one of forward substitution or backward substitution.

22. The non-transitory machine-readable medium of claim 18, wherein if the set of instructions is executed by the one or more processors, the one or more processors further cause the data symbols of the frequency bins to be equalized in parallel.

23. The non-transitory machine-readable medium of claim 18, wherein if the set of instructions is executed by the one or more processors, the one or more processors are further configured to perform the equalization in parallel with respect to a plurality of subcarriers.

24. The non-transitory machine-readable medium of claim 18, wherein parallel processing unit thread blocks balance all subcarriers associated with a physical resource block in parallel.

25. The non-transitory machine-readable medium of claim 18, wherein the two or more threads are graphics processing unit (GPU) threads.

26. A system comprising: One or more antennas for receiving one or more 5G radio signals; as well as One or more parallel processing units are configured to equalize one or more 5G radio signals using two or more threads and one or more sets of stored matrix information accessed in parallel by the two or more threads, wherein the one or more parallel processing units are configured to use augmented matrices corresponding to the one or more sets of stored matrix information to solve for coefficients and residual values ​​of linear minimum mean square error (LMMSE) estimates to equalize the one or more 5G radio signals.

27. The system of claim 26, wherein the one or more parallel processing units are used to store the augmented matrix overlaid on an intermediate matrix in a memory shared by the one or more parallel processing units.

28. The system of claim 26, wherein the one or more parallel processing units are configured to determine, at least in part, to perform at least one of Cholesky or LU decomposition to solve for the coefficients and residuals of the LMMSE estimate based on the multiple-input multiple-output MIMO configuration of the one or more antennas.

29. The system of claim 26, wherein the LMMSE estimation is based at least in part on at least one of forward substitution or backward substitution.

30. The system of claim 26, wherein the selection of the strategy for parallelizing LMMSE estimation is based at least in part on the configuration of the one or more antennas.

31. The system of claim 26, wherein parallel processing unit thread blocks balance subcarriers associated with physical resource blocks in parallel.

32. The system of claim 26, wherein the two or more threads are graphics processing unit (GPU) threads.

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