A method for executing instructions based on hash values, computing equipment and storage medium

Abstract

The present invention discloses an instruction execution method based on hash value, a computing device and a storage medium. The method comprises the steps of: submitting a first storage instruction for storing data in an internal memory to a processor; constructing a data storage segment in the internal memory; generating a second storage address for storing data according to the data storage segment; generating a second storage instruction according to the second storage address, the second storage instruction being suitable for storing the data to be stored by the first storage instruction, and the processor will not generate a data storage abnormality message when executing the second storage instruction; storing data in the data storage segment of the internal memory by executing the second storage instruction by the processor; generating a second read instruction according to the first read instruction; and reading data from the data storage segment of the internal memory by executing the second read instruction by the processor. The present invention can prevent the atomicity of data access from being lost, thereby avoiding the abnormal operation of certain special application programs.

Description

Technical Field

[0001] The present invention relates to the field of computer instruction execution, and in particular to an instruction execution method based on a hash value, a computing device and a storage medium. Background Art

[0002] With the continuous development of computer technology, more and more applications have been developed. Correspondingly, the application data is increasing, and the data structure is becoming more and more complex. Therefore, the system's memory access performance for complex data structures in memory is becoming more and more important, directly affecting the running speed of key applications. When storing data, special storage situations often occur. When the application accesses these stored data, the processor does not support special memory access instructions for the data, and an error will occur. The processor cannot directly process this type of memory access instruction to operate the data.

[0003] Therefore, in the prior art, in order to access these stored data, the data access instructions are changed so that the instructions for application accessing these data become normal instructions, and the processor can execute the data access. One of the solutions is to convert the original cross-border access instructions into two cross-border access instructions. By executing the two cross-border access instructions, the complete data can be successfully stored or read.

[0004] However, this method converts one memory access into multiple memory accesses, which essentially changes the memory access model of the application. For some special application scenarios, the atomicity of one memory access is destroyed by multiple memory accesses. If the application relies on the atomicity of memory access, in this case, the destruction of atomicity will cause data errors or errors, which may cause the application to run abnormally in severe cases.

[0005] To this end, a new hash-based instruction execution method is needed. Summary of the invention

[0006] To this end, the present invention provides an instruction execution method based on a hash value, in an effort to solve or at least alleviate the above problems.

[0007] According to one aspect of the present invention, there is provided an instruction execution method based on a hash value, which is suitable for execution in a computing device, the computing device comprising a processor, an internal memory, and running one or more applications, the storage area of ​​the internal memory being mapped as a storage space, and the application reading and writing data in the internal memory with a storage address in the storage space, the method comprising the steps of: submitting a first storage instruction for storing data in the internal memory to the processor; when the processor cannot normally execute the first storage instruction due to a first storage address of the data stored in the first storage instruction, and a data storage exception message is generated, constructing a data storage segment in the internal memory; generating a second storage address for storing data according to the data storage segment; generating a second storage instruction according to the second storage address, the second storage instruction being suitable for storing the data to be stored by the first storage instruction, and the processor will not generate a data storage exception message when executing the second storage instruction; storing data in the data storage segment of the internal memory by executing the second storage instruction by the processor; generating a second read instruction according to the first read instruction when a first read instruction for reading data in the internal memory is received and the processor cannot normally execute the first read instruction due to a first read address of the data read by the first read instruction; and reading data from the data storage segment of the internal memory by executing the second read instruction by the processor.

[0008] Optionally, in the method according to the present invention, generating a second storage address for storing data according to the data storage segment includes the steps of: calculating a hash value of the first storage address according to the first storage address; and allocating a second storage address for storing data in the data storage segment according to the hash value of the first storage address.

[0009] Optionally, in the method according to the present invention, generating the second storage instruction according to the second storage address includes the step of: replacing the first storage address in the first storage instruction with the second storage address to obtain the second storage instruction.

[0010] Optionally, in the method according to the present invention, storing data in the internal memory by executing the second storage instruction through the memory includes the steps of: obtaining a second storage address for storing the data according to the second storage instruction; and storing the data to be stored in the second storage address.

[0011] Optionally, the method according to the present invention further includes the steps of: establishing an address mapping table, the address mapping table including one or more data rows; and storing a hash value of the first storage address and a corresponding second storage address in the data row.

[0012] Optionally, in the method according to the present invention, generating a second read instruction according to the first read instruction includes the steps of: calculating a hash value of the first read address according to the first read address; querying a hash value of the first storage address that is the same as the hash value of the first read address from an address mapping table; using a second storage address corresponding to the hash value of the first storage address found as a second read address; and generating a second read instruction according to the second read address.

[0013] Optionally, in the method according to the present invention, generating the second read instruction according to the second read address includes the step of: replacing the first read address in the first read instruction with the second read address to obtain the second read instruction.

[0014] Optionally, in the method according to the present invention, reading data from the data storage segment of the internal memory according to the second read instruction by the processor includes the steps of: obtaining a second read address for reading data according to the second read instruction; and reading the data to be read from the second read address.

[0015] Optionally, in the method according to the present invention, the first storage instruction includes a non-boundary storage instruction, and the second storage instruction includes an in-boundary storage instruction.

[0016] Optionally, in the method according to the present invention, the first read instruction includes a non-boundary read instruction, and the second read instruction includes an in-boundary read instruction.

[0017] According to another aspect of the present invention, a computing device is provided, comprising: one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include instructions for executing a hash value-based instruction execution method according to the present invention.

[0018] According to another aspect of the present invention, a computer-readable storage medium storing one or more programs is provided, wherein the one or more programs include instructions that, when executed by a computing device, cause the computing device to execute a method in a hash value-based instruction execution method according to the present invention.

[0019] The hash value-based instruction execution method of the present invention is suitable for execution in a computing device, which includes a processor, an internal memory, and runs one or more applications, and includes the steps of: submitting a first storage instruction for storing data in the internal memory to the processor, and when the processor cannot normally execute the first storage instruction due to the storage address of the data stored in the first storage instruction, and a data storage exception message is generated, constructing a data storage segment in the internal memory; generating a second storage address for storing data according to the data storage segment; generating a second storage instruction according to the second storage address, the second storage instruction is suitable for storing the data to be stored by the first storage instruction, and the processor will not generate a data storage exception message when executing the second storage instruction; in order to avoid that when storing data, threads of other cores of the processor execute data reading instructions, incomplete data is read from a location where data storage has not been completed, causing an error in the application operation, a new address is selected to store data. Then, the processor executes the second storage instruction to store data in the data storage segment of the internal memory. When the processor receives the first read instruction to read data in the internal memory, and the processor cannot normally execute the first read instruction due to the first read address of the data read by the first read instruction, the processor generates a second read instruction according to the first read instruction, and the processor executes the second read instruction to read data from the data storage segment of the internal memory. The present invention can avoid reading data from the first read address when data storage is not completed; reading data from the second read address can constrain the edge effect caused by the change of the memory access model of the application, so that the atomicity of data access is not lost, thereby avoiding the abnormal operation of some special applications due to such edge effects, thereby improving the stability of the application and the compatibility of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to achieve the above and related purposes, certain illustrative aspects are described herein in conjunction with the following description and accompanying drawings, which indicate various ways in which the principles disclosed herein can be practiced, and all aspects and their equivalents are intended to fall within the scope of the claimed subject matter. By reading the following detailed description in conjunction with the accompanying drawings, the above and other purposes, features and advantages disclosed by the present invention will become more apparent. Throughout the present disclosure, the same reference numerals generally refer to the same parts or elements.

[0021] Figure 1 A schematic diagram showing a structure of a processor and an internal memory deployed in a computing device according to an exemplary embodiment of the present invention is shown;

[0022] Figure 2 shows a block diagram of a computing device 200 according to an exemplary embodiment of the present invention;

[0023] Figure 3A flow chart of a hash value-based instruction execution method 300 according to an exemplary embodiment of the present invention is shown;

[0024] Figure 4 A schematic diagram showing a method of generating a second storage instruction in the prior art according to an exemplary embodiment of the present invention; and

[0025] Figure 5 A schematic diagram of destroying instruction atomicity according to an exemplary embodiment of the present invention is shown. DETAILED DESCRIPTION

[0026] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to enable the scope of the present disclosure to be fully conveyed to those skilled in the art. The same reference numerals generally refer to the same components or elements.

[0027] Figure 1 FIG. 1 shows a schematic diagram of a structure in which a processor and an internal memory are deployed in a computing device according to an exemplary embodiment of the present invention. Figure 1 As shown, the computing device 200 includes a processor 204 and an internal memory 140. An operating system 220 is also installed in the computing device 200, and the application 110 runs on the operating system 220. The present invention does not limit the specific type of the operating system 220. Figure 1 The number of applications shown is only exemplary. There is no limit to the number and type of applications running on the operating system 220. The internal memory 140 is suitable for storing the operating data of the operating system 220 and the applications 110, and the processor 204 is suitable for processing the operating data.

[0028] Figure 1 The specific structure of the computing device 200 is as follows: Figure 2 Provide detailed explanation. Figure 2 FIG. 2 shows a block diagram of a computing device 200 according to an exemplary embodiment of the present invention. Figure 2 As shown, in a basic configuration 202, computing device 200 typically includes a system memory 206 and one or more processors 204. A memory bus 208 may be used for communication between processor 204 and system memory 206.

[0029] Depending on the desired configuration, the processor 204 can be any type of processor, including but not limited to: a microprocessor (μP), a microcontroller (μC), a digital information processor (DSP), or any combination thereof. The processor 204 can include one or more levels of cache such as a primary cache 210 and a secondary cache 212, a processor core 214, and registers 216. An example processor core 214 can include an arithmetic logic unit (ALU), a floating point unit (FPU), a digital signal processing core (DSP core), or any combination thereof. An example memory controller 218 can be used with the processor 204, or in some implementations, the memory controller 218 can be an internal part of the processor 204.

[0030] Depending on the desired configuration, the system memory 206 may be any type of memory, including but not limited to: volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.), or any combination thereof. The system memory 206 may include an operating system 220, one or more programs 222, and program data 228. In some embodiments, the program 222 may be arranged to be executed by one or more processors 204 on the operating system using the program data 228 to execute the instructions 223 of the method 300 according to the present invention.

[0031] The computing device 200 may also include a storage interface bus 234. The storage interface bus 234 enables communication from storage devices 232 (e.g., removable storage 236 and non-removable storage 238) to the basic configuration 202 via the bus / interface controller 230. At least a portion of the operating system 220, the program 222, and the data 224 may be stored on the removable storage 236 and / or the non-removable storage 238, and when the computing device 200 is powered on or the program 222 is to be executed, it is loaded into the system memory 206 via the storage interface bus 234 and executed by the one or more processors 204.

[0032] The computing device 200 may also include an interface bus 240 that facilitates communication from various interface devices (e.g., output devices 242, peripheral interfaces 244, and communication devices 246) to the basic configuration 202 via the bus / interface controller 230. Example output devices 242 include a graphics processing unit 248 and an audio processing unit 250. They can be configured to facilitate communication with various external devices such as a display or speakers via one or more A / V ports 252. Example peripheral interfaces 244 may include a serial interface controller 254 and a parallel interface controller 256, which may be configured to facilitate communication with external devices such as input devices (e.g., keyboards, mice, pens, voice input devices, touch input devices) or other peripherals (e.g., printers, scanners, etc.) via one or more I / O ports 258. Example communication devices 246 may include a network controller 260, which may be arranged to communicate with one or more other computing devices 262 via a network communication link via one or more communication ports 264.

[0033] A network communication link can be an example of a communication medium. Communication media can generally be embodied as computer-readable instructions, data structures, program modules in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium. A "modulated data signal" can be a signal in which one or more of its data sets or its changes can be carried out in a manner that encodes information in the signal. As non-limiting examples, communication media can include wired media such as a wired network or a dedicated line network, and various wireless media such as sound, radio frequency (RF), microwave, infrared (IR) or other wireless media. The term computer-readable medium used herein can include both storage media and communication media.

[0034] In the computing device 200 according to the present invention, the program 222 includes multiple program instructions of the hash value-based instruction execution method 300, which can instruct the processor 204 to execute some steps of the hash value-based instruction execution method 300 in the computing device 200 of the present invention, so that each part in the computing device 200 executes instructions by executing the hash value-based instruction execution method 300.

[0035] The computing device 200 can be implemented as a server, such as a file server 240, a database 250, a server, an application server, etc. These electronic devices can be such as personal digital assistants (PDAs), wireless network browsing devices, application-specific devices, or hybrid devices that can include any of the above functions. It can be implemented as a personal computer including desktop computers and notebook computer configurations. In some embodiments, the computing device 200 is configured to execute the hash value-based instruction execution method 300.

[0036] Figure 3 FIG. 3 is a flow chart of a method 300 for executing an instruction based on a hash value according to an exemplary embodiment of the present invention. The method 300 for executing an instruction based on a hash value in the present invention is suitable for execution in a computing device, and is further suitable for execution by a computer such as Figure 1 The operating system 220 shown in FIG. Figure 3 As shown, the hash value-based instruction execution method 300 begins at step S310, submitting a first storage instruction of the application 110 to store data in the internal memory 140 to the processor 204. When the application 110 needs to store data in the internal memory 140, it needs to submit the first storage instruction of the storage data to the processor 204 for execution via the operating system 220. The storage area of ​​the internal memory 140 is mapped to a storage space, and the application 110 stores data in the internal memory 140 using a storage address in the storage space.

[0037] Then, step S320 is executed to construct a data storage segment in the internal memory when the processor 204 cannot normally execute the first storage instruction due to the storage address of the data stored by the first storage instruction.

[0038] According to one embodiment of the present invention, when the storage address is not bounded in the internal memory 140, the processor 204 cannot execute the special operation instruction, and a data storage exception message will be generated. The first storage instruction includes a non-bounded storage instruction. When the data to be read by the application 110 is not stored in the internal memory 140, the first operation instruction is a non-bounded memory access instruction, and the data storage exception message is a non-bounded memory storage exception. Non-bounded means that the starting position of the data stored in the memory is not aligned with the natural boundary of the data of this type stored sequentially in the memory. For example, a 32-bit register, when storing data normally, the register stores a complete 32-bit data, and the first address of the data storage is the first address of the register. However, when the storage is not bounded, the calculator only stores a part of the 32-bit data, and the first address of the 32-bit data is offset from the first address of the register, and the first address of the data is at a certain address in the middle of the register. The other part of the 32-bit data is stored in the next register. Or for a 32-bit register, the processor 204 supports reading 16 bits of data at a time. When the first address of the 16-bit data is in the middle of the 32-bit register, that is, cross-border storage of the 16-bit data occurs, the processor 204 cannot read the data normally. The processor 204 cannot completely retrieve the 16-bit data stored separately according to one instruction, so the processor 204 will throw an exception. The non-bounded memory storage exception means that on a processor 204 that does not support direct storage of non-bounded data, directly storing non-bounded data will cause the processor 204 to throw an exception.

[0039] Figure 4 FIG. 2 shows a schematic diagram of generating a second storage instruction in the prior art according to an exemplary embodiment of the present invention. Figure 4 As shown, when converting the out-of-bounds memory access instruction, the instruction decomposition calculation sequence is first executed, and the first half storage instruction and the second half storage instruction are generated according to the storage address of the first storage instruction. The first half storage instruction and the second half storage instruction are respectively suitable for storing data according to the first half address and the half address, and finally the first half storage instruction and the second half storage instruction are used as the second storage instruction. The first half storage instruction and the second half storage instruction include the in-bounds storage instruction.

[0040] In the above instruction conversion process, the memory access model of application 110 is changed, and one memory operation is split into multiple operations, which leads to edge effects, especially changes in the atomicity of memory access. When the correctness of the running logic of application 110 depends on the assumption of atomicity, the lack of atomicity will cause the application 110 to run abnormally.

[0041] Figure 5 FIG. 2 shows a schematic diagram of destroying instruction atomicity according to an exemplary embodiment of the present invention. Figure 5 As shown, since the first half memory access instruction and the second half memory access instruction are two independent operations, there is no atomicity, and there is a horizon gap between them, and other horizons can be inserted. If a thread of another processing core performs a memory access and write operation in its horizon, the integrity of the data will be destroyed, which may cause the application 110 to run abnormally.

[0042] Therefore, in the present invention, a data storage segment is constructed in the internal memory, the location of the data storage segment in the internal memory is different from the first storage address, and a blank segment without storing data in the internal memory is selected as the data storage segment.

[0043] Subsequently, step S330 is executed to generate a second storage address for storing data according to the data storage segment. Specifically, the hash value of the first storage address is calculated through the first storage address, and then the second storage address for storing data in the data storage segment is allocated according to the hash value of the first storage address. Since the address of the data stored in this application run does not change, other addresses for writing data will not be confused with the first storage address, and the hash value calculated according to the first storage address is also unique. According to the hash value of the first storage address, a second storage address of the storage address is allocated in the internal memory, and when data needs to be written to the first storage address again, data can be written to the second storage address according to the hash value.

[0044] Subsequently, step S340 is executed to generate a second storage instruction according to the second storage address, the second storage instruction is suitable for storing the data to be stored by the first storage instruction, and the processor does not generate a data storage exception message when executing the second storage instruction. Specifically, when the second storage instruction is generated according to the second storage address, the first storage address in the first storage instruction is replaced with the second storage address to obtain the second storage instruction, so as to store data in the second storage address according to the second storage instruction.

[0045] Subsequently, step S350 is executed, and the processor executes the second storage instruction to store data in the data storage segment of the internal memory. Specifically, a second storage address for storing data is obtained according to the second storage instruction, and the data to be stored is stored in the second storage address. The second storage instruction includes a boundary storage instruction. The second storage address allocated in the internal memory is a boundary address. When the processor stores data according to the second storage instruction, the data can be stored in the boundary address at one time, and the atomicity of the data storage process will not be destroyed. Since the processor stores the data in the boundary address at one time, when reading the data, there will be no situation where the data is not completely stored, resulting in abnormal data reading.

[0046] According to one embodiment of the present invention, after storing data in the second storage address, an address mapping table is also established, the address mapping table including one or more data rows for storing the hash value of the storage address of the non-boundary storage instruction and the allocated second storage address. Then, the hash value of the first storage address and the corresponding second storage address are stored in the data row.

[0047] During the data storage process, there is no need to convert non-boundary instructions to boundary instructions, which saves time and computer resources for converting instructions. In addition, the second storage address is stored, and there is no need to convert instructions when reading data again. The second storage address is determined directly according to the hash value, which can improve the data access speed.

[0048] Subsequently, step S360 is executed. When a first read instruction for reading data in an internal memory is received, and the processor cannot normally execute the first read instruction due to the first read address of the data read by the first read instruction, a second read instruction is generated according to the first read instruction. According to one embodiment of the present invention, the first read instruction includes a non-boundary read instruction, and the second read instruction includes a bounded read instruction. When the processor executes the first read instruction, a data read exception message is thrown. When the first read instruction is a non-boundary read instruction, the data read exception message is a non-boundary memory read exception. After the second read instruction is generated according to the first read instruction, when the processor executes the second read instruction, no data read exception message is generated.

[0049] When generating the second read instruction according to the first read instruction, the hash value of the first read address is calculated according to the first read address, and the hash value of the first storage address that is the same as the hash value of the first read address is searched from the address mapping table. Then, the second storage address corresponding to the hash value of the first storage address is used as the second read address, and the second read instruction is generated according to the second read address. When generating the second read instruction according to the second read address, the first read address in the first read instruction is replaced with the second read address to obtain the second read instruction.

[0050] Subsequently, step S370 is executed, where the processor executes a second read instruction to read data from the data storage segment of the internal memory. Specifically, a second read address for reading data is obtained according to the second read instruction, and the data to be read is then read from the second read address.

[0051] The hash value-based instruction execution method of the present invention is suitable for execution in a computing device, which includes a processor, an internal memory, and runs one or more applications, and includes the steps of: submitting a first storage instruction for storing data in the internal memory to the processor, and when the processor cannot normally execute the first storage instruction due to the storage address of the data stored in the first storage instruction, and a data storage exception message is generated, constructing a data storage segment in the internal memory; generating a second storage address for storing data according to the data storage segment; generating a second storage instruction according to the second storage address, the second storage instruction is suitable for storing the data to be stored by the first storage instruction, and the processor will not generate a data storage exception message when executing the second storage instruction; in order to avoid that when storing data, threads of other cores of the processor execute data reading instructions, incomplete data is read from a location where data storage has not been completed, causing an error in the application operation, a new address is selected to store data. Then, the processor executes the second storage instruction to store data in the data storage segment of the internal memory. When the processor receives the first read instruction to read data in the internal memory, and the processor cannot normally execute the first read instruction due to the first read address of the data read by the first read instruction, the processor generates a second read instruction according to the first read instruction, and the processor executes the second read instruction to read data from the data storage segment of the internal memory. The present invention can avoid reading data from the first read address when data storage is not completed; reading data from the second read address can constrain the edge effect caused by the change of the memory access model of the application, so that the atomicity of data access is not lost, thereby avoiding the abnormal operation of some special applications due to such edge effects, thereby improving the stability of the application and the compatibility of the entire system.

[0052] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0053] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this method of disclosure should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim.

[0054] Those skilled in the art will appreciate that the modules or units or groups of the devices in the examples disclosed herein may be arranged in the device as described in the embodiment, or alternatively may be located in one or more devices different from the devices in the example. The modules in the foregoing examples may be combined into one module or may be divided into multiple submodules.

[0055] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or groups in the embodiments may be combined into one module or unit or group, and in addition they may be divided into a plurality of submodules or subunits or subgroups. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device so disclosed may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0056] Furthermore, those skilled in the art will appreciate that although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features from different embodiments is meant to be within the scope of the present invention and to form different embodiments.

[0057] In addition, some of the embodiments are described herein as methods or combinations of method elements that can be implemented by a processor of a computer system or by other devices that perform the functions. Therefore, a processor with necessary instructions for implementing the method or method elements forms a device for implementing the method or method elements. In addition, the elements described herein of the device embodiments are examples of devices for implementing the functions performed by the elements for the purpose of implementing the invention.

[0058] The various techniques described herein may be implemented in combination with hardware or software, or a combination thereof. Thus, the method and apparatus of the present invention, or some aspects or portions of the method and apparatus of the present invention may be in the form of program codes (i.e., instructions) embedded in a tangible medium, such as a floppy disk, a CD-ROM, a hard disk drive, or any other machine-readable storage medium, wherein when the program is loaded into a machine such as a computer and executed by the machine, the machine becomes a device for practicing the present invention.

[0059] In the case where the program code is executed on a programmable computer, the computing device generally includes a processor, a storage medium readable by the processor (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device. The memory is configured to store the program code; the processor is configured to execute the hash value-based instruction execution method of the present invention according to the instructions in the program code stored in the memory.

[0060] By way of example and not limitation, computer readable media include computer storage media and communication media. Computer readable media include computer storage media and communication media. Computer storage media stores information such as computer readable instructions, data structures, program modules or other data. Communication media generally embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and includes any information delivery medium. Any combination of the above is also included within the scope of computer readable media.

[0061] As used herein, unless otherwise specified, the use of ordinal numbers "first," "second," "third," etc. to describe common objects merely indicates that different instances of similar objects are involved, and is not intended to imply that the objects so described must have a given order in time, space, order, or in any other manner.

[0062] Although the present invention has been described according to a limited number of embodiments, it will be apparent to those skilled in the art, with the benefit of the above description, that other embodiments may be envisioned within the scope of the invention thus described. In addition, it should be noted that the language used in this specification is selected primarily for readability and teaching purposes, rather than for explaining or defining the subject matter of the present invention. Therefore, many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the appended claims. The disclosure of the present invention is illustrative, not restrictive, with respect to the scope of the present invention, which is defined by the appended claims.

Claims

1. A method for executing instructions based on hash values, suitable for execution in a computing device, the computing device comprising a processor, an internal memory, and running one or more applications, the storage area of ​​the internal memory is mapped as a storage space, and the application reads and writes data in the internal memory with a storage address in the storage space, the method comprising the steps of: submitting a first storage instruction of the application to store data in the internal memory to the processor; When the processor cannot normally execute the first storage instruction due to the first storage address of the data stored by the first storage instruction, and generates a data storage exception message, a data storage segment is constructed in the internal memory, and the location of the data storage segment in the internal memory is different from the first storage address. The construction of the data storage segment in the internal memory includes: selecting a blank segment in the internal memory that does not store data as the data storage segment; Generate a second storage address for storing data according to the data storage segment, the second storage address is a boundary address, and when the processor stores data according to the second storage instruction, the data is stored in the boundary address at one time; generating a second storage instruction according to the second storage address, the second storage instruction being suitable for storing the data to be stored by the first storage instruction, and the processor will not generate a data storage exception message when executing the second storage instruction, the first storage instruction including an out-of-bounds storage instruction, and the second storage instruction including an in-bounds storage instruction; executing the second storage instruction by the processor to store data in the data storage section of the internal memory; When receiving a first read instruction to read data in the internal memory, the processor generates a second read instruction according to the first read instruction when the first read instruction cannot be normally executed due to a first read address of the data read by the first read instruction; Reading data from the data storage section of the internal memory by executing the second read instruction by the processor; Wherein, generating a second storage address for storing data according to the data storage segment comprises the steps of: Calculating a hash value of the first storage address according to the first storage address; allocating a second storage address for storing data in the data storage segment according to a hash value of the first storage address; Generating a second storage instruction according to the second storage address comprises the steps of: Replacing the first storage address in the first storage instruction with the second storage address to obtain a second storage instruction; The storing of data in the internal memory by executing the second storage instruction in the memory comprises the steps of: Obtaining a second storage address for storing data according to the second storage instruction; The data to be stored is stored in the second storage address.

2. The method of claim 1, wherein: The method further comprises the steps of: Establishing an address mapping table, wherein the address mapping table includes one or more data rows; A hash value of the first storage address and a corresponding second storage address are stored in the data row.

3. The method of claim 2, wherein: Generating a second read instruction according to the first read instruction comprises the steps of: Calculating a hash value of the first read address according to the first read address; Querying the address mapping table for a hash value of a first storage address that is the same as the hash value of the first read address; Using the second storage address corresponding to the hash value of the found first storage address as the second read address; A second read instruction is generated according to the second read address.

4. The method of claim 3, wherein: Generating a second read instruction according to the second read address comprises the steps of: The first read address in the first read instruction is replaced with the second read address to obtain a second read instruction.

5. The method of claim 4, wherein: The reading of data from the data storage section of the internal memory by the processor according to the second read instruction comprises the steps of: Obtaining a second read address for reading data according to the second read instruction; The data to be read is read from the second read address.

6. The method according to any one of claims 1 to 5, wherein: The first read instruction includes a non-boundary read instruction, and the second read instruction includes an in-boundary read instruction.

7. A computing device comprising: one or more processors; Memory; as well as One or more devices comprising instructions for executing the method according to any one of claims 1-6.

8. A computer-readable storage medium storing one or more programs, the one or more programs comprising instructions which, when executed by a computing device, cause the computing device to perform the method according to any one of claims 1 to 6.

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