Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate, a word line and a bit line. The semiconductor substrate has active regions separated from each other and extending along a first direction. The word line is formed in the semiconductor substrate. The active region intersects with one or more word lines respectively. The word lines respectively have a wide portion and a narrow portion extending continuously on the wide portion along a second direction. The wide portion is located at the intersection of the word line and the active region. The bit line is formed on the semiconductor substrate and extends along a third direction intersecting the first direction and the second direction.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a dynamic random access memory (DRAM) device and a manufacturing method thereof. Background Art

[0002] As the feature size of dynamic random access memory (DRAM) cells is becoming increasingly smaller, the spacing between adjacent word lines is shortened. As a result, the contact area between the active area between adjacent word lines and the overlying capacitor contact window becomes smaller, resulting in write recovery time (tWR) failure. Several solutions have been used to address this problem, but none of them does not cause unintended side effects when used. For example, one of these solutions includes reducing the isolation width between adjacent word lines, which may cause interference between adjacent dynamic random access memory cells. As another example, the width / diameter of the word line is reduced to obtain additional contact area of ​​the active area, but the conductivity of the word line may be compromised. Summary of the invention

[0003] The present invention provides a semiconductor device, comprising: a semiconductor substrate having active regions separated from each other and extending along a first direction. Word lines are formed in the semiconductor substrate, wherein the active regions intersect with one or more word lines respectively, and the word lines respectively have a wide portion and a narrow portion extending continuously on the wide portion along a second direction, and the wide portion is located at the intersection of the word line and the active region. Bit lines are formed on the semiconductor substrate and extend along a third direction intersecting the first direction and the second direction.

[0004] The present invention provides a method for manufacturing a semiconductor device. The method includes: providing a semiconductor substrate having an active area and a trench isolation structure, wherein the active area extends along a first direction, and the trench isolation structure extends between the active areas. Forming an initial gate trench at the top surface of the semiconductor substrate, wherein the initial gate trench extends through the active area and the trench isolation structure along a second direction intersecting the first direction. Forming an insulating liner on the sidewall of the initial gate trench. Using the insulating liner as a mask, the initial gate trench is further extended downward into the semiconductor substrate through an etching process to form a gate trench. Performing a first oxidation process to oxidize the exposed surface of a portion of the gate trench in the active area to form a sacrificial layer. Removing the insulating liner and the sacrificial layer. Filling a conductive material in the gate trench to form a word line.

[0005] As described above, the portion of the word line in the active area has a wide bottom and a narrow top, respectively. On the other hand, the other portion of the word line in the trench isolation structure extending between the active areas has only a narrow portion. Therefore, the top of the word line has a narrow size, so the top area of ​​the active area is less occupied by the word line and the overlying insulating material extending from the top of the word line to the top surface of the substrate. Therefore, the contact area between the active area and the capacitor contact window formed thereon can be increased. In addition, by using such an architecture to increase the contact area of ​​the active area, the isolation of the adjacent word line extending between the active area and the active area can be prevented from being damaged. In addition, since the word line has a wide bottom, the word line can still be guaranteed to have a low resistivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A is a schematic plan view of a semiconductor device according to some embodiments of the present invention;

[0007] Figure 1B yes Figure 1A A schematic cross-sectional view along the A-A' tangent line is shown in FIG.

[0008] Figure 1C yes Figure 1A A schematic cross-sectional view along the BB' line is shown in FIG.

[0009] Figure 2 yes Figure 1A A manufacturing flow chart of a semiconductor device shown in;

[0010] FIG. 3A to FIG. 3J yes Figure 2 A schematic cross-sectional view of the structure at various stages during the manufacturing process taken along a first direction as shown in FIG.

[0011] FIG. 4A to FIG. 4J yes Figure 2 A schematic cross-sectional view of the structure at various stages during the manufacturing process taken along a second direction as shown in FIG.

[0012] Figure 5A and Figure 5B is a schematic cross-sectional view of a semiconductor device according to an alternative embodiment of the present invention.

[0013] Description of Figure Numbers

[0014] 10, 10a: semiconductor device;

[0015] AA: active area;

[0016] A-A', B-B': tangent line;

[0017] AG: air gap;

[0018] AW: Active word line;

[0019] BC: bit line contact window;

[0020] BL: bit line;

[0021] BR, BR': barrier layer;

[0022] CC: capacitor contact window;

[0023] CM: conductive material;

[0024] CM1: additional conductive material;

[0025] DT: Deep Trench Isolation;

[0026] D1: first direction, direction;

[0027] D2: second direction,direction;

[0028] D3: third direction, direction;

[0029] GD: gate dielectric layer;

[0030] HM: hard mask pattern;

[0031] H1, H2: height;

[0032] IL: insulation layer;

[0033] IS: insulation material;

[0034] LL: insulation lining;

[0035] NP, NP1, NP2: narrow part;

[0036] PW: passive word line;

[0037] SB: semiconductor substrate;

[0038] Scc: spacing;

[0039] SL: sacrificial layer;

[0040] ST: shallow trench isolation;

[0041] S1, S2: lateral intervals;

[0042] S100, S102, S104, S106, S108, S110, S112, S114, S116, S118, S120: steps;

[0043] T: transistor;

[0044] TI: Trench isolation structure;

[0045] TP: wide part;

[0046] TR1: initial gate trench;

[0047] TR2: gate trench;

[0048] WL: word line;

[0049] W1, W2, W3: width. DETAILED DESCRIPTION

[0050] Figure 1A is a schematic plan view of a semiconductor device 10 according to some embodiments of the present invention. Figure 1B yes Figure 1A A schematic cross-sectional view along the AA' line is shown in FIG. Figure 1C yes Figure 1A It should be noted that for the sake of simplicity, Figure 1B Zhongyu Figure 1C Some of the omitted Figure 1A The components shown in .

[0051] Please refer to Figure 1A , the semiconductor device 10 includes a word line WL, a bit line BL and a transistor T. The word line WL extends along a direction D1, and the bit line BL extends along a direction D2 intersecting the direction D1. Each transistor T is electrically connected to one of the word lines WL and one of the bit lines BL, and is further electrically contacted to a storage capacitor (not shown). Each storage capacitor (not shown) and the transistor T connected thereto jointly form a memory cell. The gate terminal of each transistor T is a part of the corresponding word line WL. In addition, one of the source terminal and the drain terminal of each transistor T is electrically connected to the corresponding bit line BL through a bit line contact window BC, and the other source terminal and the drain terminal of each transistor T is electrically connected to the storage capacitor (not shown) through a capacitor contact window CC. In some embodiments, the source terminal and the drain terminal of each transistor T are shallow portions in the active area AA, and a doped region (such as Figure 1B Zhongyu Figure 1C). The active area AA extends along a direction D3 intersecting the direction D1 and the direction D2. Each active area AA is shared by two transistors T and intersects two word lines WL and one bit line BL. A portion of each active area AA between the corresponding word lines WL can be used for the function of sharing a source terminal point or a drain terminal point, and is electrically connected to one of the bit lines BL through a bit line contact window BC therebetween. On the other hand, a portion of each active area AA located on the opposite side of the corresponding bit line contact window BC is electrically connected to two storage capacitors (not shown) through a capacitor contact window CC therebetween. In some embodiments, the bit line contact window BC is formed to have a circular top view shape, and the capacitor contact window CC is formed to have a rectangular top view shape. In addition, the occupied area of ​​each bit line contact window BC may be larger than the occupied area of ​​each capacitor contact window CC. Each word line WL has a narrow portion NP and a plurality of wide portions TP. The wide portions TP are spaced apart from each other. The narrow portion NP extends continuously along the direction D1, and the wide portion TP is covered by the continuously extending narrow portion NP. The wide portion TP is disposed at a position where the word line WL intersects the corresponding active area AA. The lateral spacing S1 between the wide portion TP of one word line WL and the narrow portion NP of an adjacent word line WL is shorter than the lateral spacing S2 between the narrow portion NP of one word line WL and the narrow portion NP of an adjacent word line WL. Each wide portion TP may extend outward from the central axis of the corresponding word line WL along the extension direction (i.e., direction D3) of the corresponding active area AA. Some side surfaces of each wide portion TP (e.g., the long side surfaces of each wide portion TP) may be substantially coplanar with the contour of the corresponding active area AA. In addition, the segments of the narrow portion NP of each word line WL extending between the active areas AA have two different lengths, and these segments have two different lengths alternately arranged along the direction D1.

[0052] Please refer to Figure 1A and Figure 1B The word lines WL are buried in the semiconductor substrate SB and may be separated from the top surface of the semiconductor substrate SB by the insulating material IS. The height H1 of the section of the narrow portion NP of each word line WL overlapping the wide portion TP is much smaller than the height H2 of the section of the narrow portion NP not overlapping the wide portion TP. In other words, the shorter section of the narrow portion NP (in Figure 1B The narrow portion NP1 is located on the wide portion TP, while the higher section of the narrow portion NP (in Figure 1B The narrow portion NP2 in FIG. 1 extends between the wide portions TP (e.g. Figure 1A As shown in FIG. 1 , the upper section of the narrow portion NP (ie, the narrow portion NP2) and the insulating material IS thereon extend in the trench isolation structure TI formed in the semiconductor substrate SB. Figure 1AAs shown in , the trench isolation structure TI extends between the active areas AA. On the other hand, the wide portion TP, the shorter section of the narrow portion NP (i.e., the narrow portion NP1), and the insulating material IS thereon extend within the active area AA. Since they are formed within the active area AA and become part of the transistor T, each of the wide portion TP and the shorter section of the narrow portion NP (i.e., the narrow portion NP1) can be considered as an active word line AW. On the other hand, since they are formed within the trench isolation structure TI, the higher section of each narrow portion NP (i.e., the narrow portion NP2) can be considered as an inactive word line PW. The active word line AW contacts the active area AA through the gate dielectric layer GD. The gate dielectric layer GD further covers the sidewalls of the insulating material IS located on the active word line AW. In the manufacturing process for forming the semiconductor device 10, an air gap AG can be formed in the active word line AW, and will be referred to as Fig. 3I Further description is given. In addition, the top surface of the active word line AW and the passive word line PW are substantially coplanar with each other, and the bottom end of the active word line AW may be higher than the bottom end of the passive word line PW.

[0053] like Figure 1BAs shown in , each bit line contact window BC is formed on the top of the corresponding active area AA extending between and above two active word lines AW, and further extends to the top of the corresponding active area AA and the insulating material IS located on these active word lines AW. In addition, each capacitor contact window CC is formed on the top of the corresponding active area AA extending between and above an active word line AW and a passive word line PW, and further extends to the top of the corresponding active area AA and the top of the trench isolation structure TI in which the passive word line PW is located. The bit line contact window BC and the capacitor contact window CC are laterally isolated from each other by one or more insulating layers IL formed on the semiconductor substrate SB. The occupied area of ​​the top of the active area AA where the corresponding capacitor contact window CC is located is determined by the spacing Scc between the insulating material IS located on the top of the active word line AW and the adjacent parts of the trench isolation structure TI in which the passive word line PW is set. The insulating material IS has a width W1 substantially equal to or slightly larger than the width of the top of the active word line AW (i.e., the width of the narrow portion NP of the word line WL along the direction D3), rather than the width of the bottom of the active word line AW (i.e., the width of the wide portion TP of the word line WL along the direction D3). Therefore, compared with forming an active word line AW including only the wide portion TP, the insulating material IS located on the narrow portion NP of the active word line AW according to an embodiment of the present invention can be laterally separated from the adjacent portion of the trench isolation structure TI by a larger spacing (i.e., spacing Scc). Therefore, the top of the active area AA where the corresponding capacitor contact window CC is located can have a larger occupied area, and the contact area between the top of the active area AA and the corresponding capacitor contact window CC can be increased. The contact resistance between the active area AA and the corresponding capacitor contact window CC can be reduced. Furthermore, compared to increasing the contact area between the top of the active area AA and the corresponding capacitor contact window CC by reducing the occupied area of ​​the trench isolation structure TI, forming the active word line AW with the top narrow portion NP and the bottom wide portion TP according to the embodiment of the present invention can increase the contact area between the top of the active area AA and the corresponding capacitor contact window CC without damaging the isolation between the passive word line PW (located in the trench isolation structure TI) and the adjacent active area AA. Furthermore, compared to increasing the contact area between the top of the active area AA and the corresponding capacitor contact window CC by forming the active word line AW with only the narrow portion NP (similar to the passive word line PW), forming the active word line AW with the top narrow portion NP and the bottom wide portion TP according to the embodiment of the present invention can increase the contact area between the top of the active area AA and the corresponding capacitor contact window CC while ensuring the low resistivity of the active word line AW.

[0054] Please refer to Figure 1A and Figure 1C, the active word lines AW and the passive word lines PW are alternately arranged along the extension direction of the word lines (i.e., direction D1). The width W2 of some passive word lines PW respectively between closely adjacent active word lines AW is much smaller than the width W3 of other passive word lines PW between loosely adjacent active word lines AW. Similarly, the width of the portion of the trench isolation structure TI respectively between closely adjacent active word lines AW is much smaller than the width of another portion of the trench isolation structure TI between loosely adjacent active word lines AW. In some embodiments, the depth of those portions of the trench isolation structure TI having a smaller width may be smaller than the depth of those portions of the trench isolation structure TI having a larger width. In addition, those portions of the trench isolation structure TI having a larger width include a deep trench isolation DT and a shallow trench isolation ST formed in the deep trench isolation DT. The bottom surface and sidewall of the shallow trench isolation ST are covered by the deep trench isolation DT, and the deep trench isolation DT and the shallow trench isolation ST are made of different insulating materials, such as silicon oxide and silicon nitride.

[0055] Figure 2 yes Figure 1A Schematic diagram of the manufacturing process of the semiconductor device shown in FIG. FIG. 3A to FIG. 3J yes Figure 2 Schematic cross-sectional view of the structure at various stages during the manufacturing process taken along the AA′ line shown in FIG. FIG. 4A to FIG. 4J yes Figure 2 Schematic cross-sectional view of the structure at various stages during the manufacturing process taken along the BB′ line shown in FIG.

[0056] Please refer to Figure 2 , Figure 3A and Figure 4A , step S100 is performed, and an initial gate trench TR1 is formed at the top surface of the semiconductor substrate SB. The semiconductor substrate SB is provided with an active area AA and a trench isolation structure TI surrounding each active area AA. Figure 4A As shown, each initial gate trench TR1 passes through the active area AA and the trench isolation structure TI along the direction D1. In addition, the depth of each initial gate trench TR1 is substantially constant along its extension direction (ie, the direction D1). Figure 3A As shown, some portions of each initial gate trench TR1 are formed in those portions of the trench isolation structure TI including the deep trench isolation DT and the shallow trench isolation ST, respectively. During the formation of the initial gate trench TR1, the top of each shallow trench isolation ST and the surrounding portion of the corresponding deep trench isolation DT are removed. On the other hand, the other portions of each initial gate trench TR1 are formed in the active area AA and extend from the top surface of the active area AA in the active area AA. Before performing the etching process for forming the initial gate trench TR1, a hard mask pattern HM having an opening for defining the initial gate trench TR1 is formed on the semiconductor substrate SB.

[0057] Please refer to Figure 2 , Figure 3B and Figure 4B , step S102 is performed, and an insulating liner LL is conformally formed on the current structure. The insulating liner LL generally covers the current structure. The top surface and sidewalls of the hard mask pattern HM and the initial gate trench TR1 are covered by the insulating liner LL. The material of the insulating liner LL may include silicon oxide, silicon nitride, silicon oxynitride, the like, or a combination thereof.

[0058] Please refer to Figure 2 , Figure 3C and Figure 4C , step S104 is performed to remove the portion of the insulating liner LL covering the bottom surface of the initial gate trench TR1. In some embodiments, the portion of the insulating liner LL covering the top surface of the hard mask pattern HM is removed along with the portion of the insulating liner LL covering the bottom surface of the initial gate trench TR1. On the other hand, the portion of the insulating liner LL covering the sidewall of the initial gate trench TR1 and the hard mask pattern HM are retained. The method for removing these portions of the insulating liner LL includes an anisotropic etching process.

[0059] Please refer to Figure 2 , Figure 3D and Figure 4D , step S106 is performed, and the initial gate trench TR1 is further extended downward in the semiconductor substrate SB to form a gate trench TR2. The method for forming the gate trench TR2 includes etching the structure located below the initial gate trench TR1 by using the remaining portion of the insulating liner LL and the hard mask pattern HM as a shielding mask. Some gate trenches TR2 in the trench isolation structure TI may have a depth greater than the depth of other gate trenches TR2 in the active area AA, and this may be due to the etching selectivity between the material of the trench isolation structure TI and the material of the semiconductor substrate SB. In other words, during the formation of the gate trench TR2, the etching rate of the trench isolation structure TI may be greater than the etching rate of the active area AA. Figure 3D As shown, the remaining portion of the insulating liner LL covering the top sidewall of the gate trench TR2 and the bottom surface and bottom sidewall of the gate trench TR2 are exposed. Figure 4D As shown, a portion of the bottom surface of each gate trench TR2 in the active area AA is higher than a portion of the bottom surface of each gate trench TR2 in the trench isolation structure TI. That is, each gate trench TR2 has an uneven bottom surface.

[0060] Please refer to Figure 2 , Figure 3E and Figure 4E, perform step S108, and perform a first oxidation process. During the oxidation process, the exposed portion of the semiconductor substrate SB in the gate trench TR2 is oxidized to form a sacrificial layer SL, while the exposed portion of the trench isolation structure TI and the insulating liner LL in the gate trench TR2 and the top surface of the hard mask pattern HM may not be oxidized. In this way, a sacrificial layer SL extending from the bottom sidewall of a portion of the gate trench TR2 into the semiconductor substrate SB is formed in the active area AA. The thickness of the sacrificial layer SL is greater than the thickness of the insulating liner LL, so after removing the sacrificial layer SL and the insulating liner LL, the bottom of these portions of the gate trench TR2 in the active area AA may be wider than the top of these portions of the gate trench TR2. In some embodiments, the oxidation process may be a plasma oxidation process, and the process temperature of the plasma oxidation process may be in the range of 450°C to 700°C.

[0061] Please refer to Figure 2 , Figure 3F and Figure 4F , perform step S110 to remove the remaining portions of the sacrificial layer SL and the insulating liner LL. After removing the insulating liner LL, the portion of the gate trench TR2 in the trench isolation structure TI has a bottom and a top that is slightly wider than the bottom, respectively. On the other hand, after removing the insulating liner LL and the sacrificial layer SL, the portion of the gate trench TR2 in the active area AA has a top and a bottom that is wider than the top. In some embodiments, the remaining portions of the sacrificial layer SL and the insulating liner LL are removed by an anisotropic etching process. During such an anisotropic etching process, due to the etching selectivity of the material of the trench isolation structure TI relative to the material of the sacrificial layer SL and the insulating liner LL, the previously exposed portion of the trench isolation structure TI may not be removed.

[0062] Please refer to Figure 2 , Figure 3G and Figure 4G , step S112 is performed to form a gate dielectric layer GD in a portion of the gate trench TR2 in the active area AA. In some embodiments, a portion of the semiconductor substrate SB exposed in the gate trench TR2 in the active area AA is oxidized, and a shallow area of ​​the exposed portion of the semiconductor substrate SB is oxidized to form the gate dielectric layer GD. On the other hand, due to the difference in materials, the exposed portion of the trench isolation structure TI and the hard mask pattern HM may not be oxidized and may remain unchanged. For example, the oxidation process may include an in situ steam generation (ISSG) process.

[0063] Please refer to Figure 2 , Figure 3H and Figure 4H, step S114 is performed, a barrier layer BR is conformally formed on the current structure, the barrier layer BR covers the current structure as a whole, and the exposed surface of the gate dielectric layer GD, the trench isolation structure TI and the hard mask pattern HM are covered by the barrier layer BR. The barrier layer BR is made of a conductive material (e.g., titanium nitride).

[0064] Please refer to Figure 2 , Fig. 3I and Fig. 4I , step S116 is performed to form a conductive material CM on the current structure. The conductive material CM fills the gate trench TR2 and further extends to the topmost surface of the barrier layer BR. In some embodiments, during the formation of the conductive material CM, an air gap AG may be formed in a portion of the gate trench TR2 within the active area AA. In these embodiments, the air gap AG may be located in the lower portion (i.e., the wider portion) of the gate trench TR2. In alternative embodiments, a conductive material CM without an air gap may be formed. The material of the conductive material CM may include, for example, tungsten.

[0065] Please refer to Figure 2 , Figure 3J and Figure 4J , perform step S118 to remove the top of the barrier layer BR and the top of the conductive material CM. After removing the top of the barrier layer BR and the top of the conductive material CM, the top surface and sidewalls of the hard mask pattern HM, the top sidewalls of the trench isolation structure TI, and the top sidewalls of the gate dielectric layer GD are exposed, and the remaining portion of the barrier layer BR and the conductive material CM together form a word line WL. The top surfaces of the word lines WL can be substantially coplanar with each other and above the lower portion (i.e., the wider portion) of the gate trench TR2 in the active area AA, and below the top surface of the semiconductor substrate SB. As shown in reference Figure 1A and Figure 1B As described, the portion of the word line WL formed in the active area AA is considered as the active word line AW, and the portion of the word line WL formed in the trench isolation structure TI is considered as the passive word line PW. In some embodiments, the method of removing the top of the barrier layer BR and the conductive material CM includes an etch-back process.

[0066] Please refer to Figure 2 , Figure 1B and Figure 1C, perform step S120 to form an insulating material IS, a bit line contact window BC and a capacitor contact window CC. The insulating material IS fills the gate trench TR, and the word line WL is covered by the insulating material IS. The bit line contact window BC extends from above the semiconductor substrate SB to a portion of an active area AA between and above adjacent active word lines AW. In some embodiments, each bit line contact window BC extends laterally to a portion of an adjacent insulating material IS through a portion of the gate dielectric layer GD. On the other hand, the capacitor contact window CC extends from above the semiconductor substrate SB to a portion of an active area AA between and above the active word line AW and the passive word line PW. The insulating material IS may include, for example, silicon nitride, and the materials of the bit line contact window BC and the capacitor contact window CC may include, for example, polysilicon.

[0067] In some embodiments, the hard mask pattern HM is removed, and at least one insulating layer IL is formed on the semiconductor substrate SB to isolate the bit line contact window BC from the capacitor contact window CC. Then, a bit line BL (eg, Figure 1A ) and a storage capacitor (not shown). So far, the semiconductor device 10 according to some embodiments of the present invention has been formed.

[0068] Figure 5A 1 is a schematic cross-sectional view (taken along line AA′) of a semiconductor device 10 a according to an alternative embodiment of the present invention. Figure 5B 1 is a schematic cross-sectional view of the semiconductor device 10 a (taken along the BB′ line). Figure 5A and Figure 5B The semiconductor device 10a shown in FIG. 1 is similar to the semiconductor device 10a shown in FIG. Figure 1B and Figure 1C The differences between the semiconductor device 10 and the semiconductor device 10 will be described below, and the same or similar parts will not be described in detail.

[0069] Please refer to Figure 5A and Figure 5B Each word line WL is a dual work function word line, and each word line WL further includes an additional conductive material CM1 extending continuously on the narrow portion NP. The additional conductive material CM1 has a work function different from the work function of the material forming the remaining portion of the word line WL (for example, referring to Figure 3H , Fig. 3I , Figure 4H and Fig. 4IFor example, the work function of the additional conductive material CM1 may be lower than the work function of the conductive material CM and the work function of the barrier layer BR, and the additional conductive material CM1 may be made of n-type doped polysilicon (e.g., phosphorus-doped polysilicon), and the conductive material CM may be made of tungsten. In order to form a word line WL with the additional conductive material CM1, refer to Figure 3J and Figure 4J During step S118 described, more conductive material CM and barrier layer BR are removed, and additional conductive material CM1 is subsequently formed on the remaining portions of conductive material CM and barrier layer BR by a deposition process. After depositing the additional conductive material CM1, an etch-back process may or may not be performed. In some embodiments, before forming the additional conductive material CM1, an additional barrier layer BR' is formed on the top surface of barrier layer BR and conductive material CM, and barrier layer BR' is located between the additional conductive material CM1 and the underlying conductive material CM and barrier layer BR. In addition, barrier layer BR and barrier layer BR' may be made of the same or different materials and may be formed by different methods. For example, barrier layer BR may be made of titanium nitride and formed by a chemical vapor deposition (CVD) process, while barrier layer BR' may be made of titanium nitride, titanium, or a combination thereof and formed by a physical vapor deposition (PVD) process.

[0070] As described above, the portion of the word line in the active area has a wide bottom and a narrow top, respectively. On the other hand, the other portion of the word line in the trench isolation structure extending between the active areas has only a narrow portion. Therefore, the top of the word line has a narrow size, so the top area of ​​the active area is less occupied by the word line and the covering insulating material extending from the top of the word line to the top surface of the substrate. Accordingly, the contact area between the active area and the capacitor contact window formed thereon can be increased. In addition, by using this configuration to increase the contact area of ​​the active area, it is possible to prevent the isolation of the active area from the adjacent word line extending between the active areas from being damaged. In addition, since the word line has a wide bottom, it is still possible to ensure that the word line has a low resistivity.

[0071] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the following claims.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate having active regions separated from each other and extending along a first direction; A word line formed in the semiconductor substrate, wherein the active region intersects with one or more of the word lines respectively, the word line comprises a conductive material, the conductive material has a wide portion and a narrow portion extending continuously on the wide portion along a second direction, and the wide portion is located at the intersection of the word line and the active region; as well as A bit line is formed on the semiconductor substrate and extends along a third direction intersecting the first direction and the second direction. The first section of the narrow portion is located in the active area and above the wide portion, the second section of the narrow portion extends between the active areas, and the second section of the narrow portion is a bottom and a top wider than the bottom.

2. The semiconductor device according to claim 1, wherein: The wide portion of the conductive material extends along the first direction.

3. The semiconductor device according to claim 1, wherein: The word line located in the active region has a first bottom width, the word line extending between the active regions has a second bottom width, and the first bottom width is greater than the second bottom width.

4. The semiconductor device according to claim 1, wherein: The height of the second section is greater than the height of the first section.

5. The semiconductor device according to claim 1, wherein: Also included is a trench isolation structure formed in the semiconductor substrate and extending between the active regions, wherein the second section of the narrow portion region extends in the trench isolation structure.

6. The semiconductor device according to claim 1, wherein: A bottom end of the second section of the narrow portion is lower than a bottom end of the first section of the narrow portion, and lower than a bottom end of the wide portion.

7. The semiconductor device according to claim 1, wherein: The second sections of the narrow portion of the conductive material of each of the word lines having different lengths are alternately arranged along the second direction.

8. The semiconductor device according to claim 1, wherein: The wide portion of the conductive material of one of the word lines is laterally spaced apart from the narrow portion of the conductive material of an adjacent word line at a first spacing along the first direction, and the narrow portion of the conductive material of one of the word lines is laterally spaced apart from the narrow portion of the conductive material of an adjacent word line at a second spacing along the first direction, and the first spacing is shorter than the second spacing.

9. The semiconductor device according to claim 1, wherein: Air gaps are respectively formed in the wide portions of the conductive material.

10. The semiconductor device according to claim 1, wherein: Each of the word lines further includes an additional conductive material extending continuously on the narrow portion, and the additional conductive material and the remaining portion of each of the word lines are made of a different material having a different work function.

11. The semiconductor device according to claim 10, wherein: Each of the word lines further includes a barrier layer located between the narrow portion and the additional conductive material.

12. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor substrate having an active region and a trench isolation structure, wherein the active region extends along a first direction, and the trench isolation structure extends between the active regions; forming an initial gate trench at a top surface of the semiconductor substrate, wherein the initial gate trench extends through the active area and the trench isolation structure along a second direction intersecting the first direction; forming an insulating liner on the sidewalls of the initial gate trench; Using the insulating liner as a mask, extending the initial gate trench further downward into the semiconductor substrate through an etching process to form a gate trench; performing a first oxidation process to oxidize an exposed surface of a portion of the gate trench in the active area to form a sacrificial layer; removing the insulating liner and the sacrificial layer; as well as A conductive material is filled in the gate trench to form a word line.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: After removing the insulating liner and the sacrificial layer, the portion of the gate trench in the active area has a top and a bottom wider than the top, respectively.

14. The method for manufacturing a semiconductor device according to claim 12, wherein: After the insulating liner is removed, the portion of the gate trench in the trench isolation structure has a bottom and a top wider than the bottom.

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