Computer device and method of manufacturing a computer device

Abstract

According to a first aspect, there is provided a computer structure comprising a first silicon substrate and a second silicon substrate. Computer circuitry configured to perform computing operations is formed in the first silicon substrate, which has a self-supporting depth and an inward-facing surface. A plurality of distributed capacitance units is formed in the second silicon substrate, which has an inward-facing surface positioned overlapping the inward-facing surface of the first substrate, and is connected to the first substrate via a set of connectors arranged to extend along a depth direction of the structure between the inward-facing surfaces. The inward-facing surfaces have matching planar surface dimensions. The second substrate has an outward-facing surface on which a plurality of connector terminals for connecting the computer structure to a supply voltage is arranged. The second substrate has a smaller depth than the first substrate.

Description

Technical Field

[0001] This disclosure relates to the control of power supply voltage variations in processing circuits within a computer architecture. Background Technology

[0002] Problems related to voltage source control in computer architectures are known. Specifically, large variations in the current demand of on-chip processing circuitry can cause unwanted artifacts in the supply voltage. These variations in current demand are known as load steps.

[0003] One illusion is a drop in supply voltage, which occurs when the load admittance suddenly increases. This is a result of the series resistance and inductance of any circuitry between the power supply and the current-drawing circuitry. The resistance and inductance of these intermediate components can be called parasitic resistance and inductance because they are not intended to be introduced into the circuitry but are unavoidable characteristics of circuit elements on a chip.

[0004] There are many ways to reduce power supply voltage droop. Intermediate circuitry can be modified, for example, by using shorter or larger diameter wires to reduce wire resistance. Lower impedance wires can also be used to reduce power supply voltage droop, as can removing connectors. However, these solutions are not suitable for chips with relatively fixed circuit dimensions. Furthermore, the current required compared to the circuit size means that such geometric changes have little effect on power supply voltage droop.

[0005] One known technique for limiting power supply voltage droop is to provide a capacitor between the power supply voltage and the circuit that draws current.

[0006] There are many possible sources of capacitance in computer architectures, some of which will be discussed further in the description below, but none of them are sufficient to address voltage droop in high current demand / low supply voltage architectures. Summary of the Invention

[0007] According to a first aspect of the present invention, a computer structure is provided, comprising: a first silicon substrate in which computer circuitry configured to perform computational operations is formed, the first substrate having a self-supporting depth and an inward-facing surface; a second silicon substrate in which a plurality of distributed capacitor cells are formed, the second substrate having an inward-facing surface that overlaps with and is positioned with respect to the inward-facing surface of the first substrate and is connected to the first substrate via a set of connectors extending in a depth direction of a structure between the inward-facing surfaces, the inward-facing surface of the second silicon substrate having a planar surface dimension matching that of the planar surface dimension of the inward-facing surface of the first silicon substrate; the second substrate having an outward-facing surface on which a plurality of connector terminals for connecting the computer structure to a power supply voltage are arranged, wherein the second substrate has a shallower depth than the first substrate.

[0008] The inward-facing surfaces of the first and second substrates can be bonded together by one or more bonding layers.

[0009] The connector may include a through-silicon via extending through a second silicon substrate to a first silicon substrate to provide an electrical connection between the connector terminals and the first silicon substrate.

[0010] Each distributed capacitor unit may include a predetermined number of capacitor blocks, each capacitor block having a capacitance in the range of 0.1nF to 1.5nF. The predetermined number may be between 10 and 20.

[0011] Each distributed capacitor unit can have a capacitance ranging from 5nF to 30nF.

[0012] The total planar area of ​​the distributed capacitor cells can be at least 80% of the total planar area of ​​the first silicon substrate, and the capacitance of the multiple distributed capacitor cells is 0.5 μF / mm². 2 Up to 3μF / mm 2 Within the range.

[0013] The first silicon substrate can have a depth of 400 μm to 1000 μm.

[0014] The second silicon substrate can have a non-self-supporting depth, which is less than 10 μm.

[0015] Distributed capacitor cells can be arranged in a regular array, with each distributed capacitor cell connected to a power supply voltage connector terminal and a ground connector terminal.

[0016] Each connector terminal can be connected to four different distributed capacitor terminals.

[0017] This set of connectors can provide a connection between the first silicon substrate and the second silicon substrate at the location of the connector terminals.

[0018] Each distributed capacitor unit may include two keep-out areas, which are located at the corresponding connector terminals, and the keep-out areas and capacitor blocks have the same size.

[0019] Each capacitor block may include an array of trench capacitors arranged in a hexagonal array, wherein each trench capacitor has six adjacent trench capacitors, and each trench capacitor is equidistant from each of its adjacent trench capacitors.

[0020] Through-silicon vias can be placed in the restricted areas of distributed capacitor cells.

[0021] A computer circuit may include multiple processing units, each having an execution unit and local memory, and the multiple processing units are configured to compute in parallel.

[0022] Computer circuitry may include synchronization circuitry configured to control multiple processing units to operate according to a batch synchronous parallel protocol.

[0023] Computer circuitry may include a clock connected to control the operation of the processing unit.

[0024] According to a second embodiment of the present invention, a method for manufacturing a computer structure is provided, the method comprising: providing a first silicon substrate including computer circuitry configured to perform computational operations, the first silicon substrate having a self-supporting depth; providing a second silicon substrate including a plurality of distributed capacitor cells; bonding an inward-facing surface of the first silicon substrate to an inward-facing surface of the second silicon substrate such that the inward-facing surfaces overlap and have matching planar surface dimensions; thinning the second silicon substrate such that the second substrate has a depth less than that of the first silicon substrate; and providing a plurality of connector terminals on an outward-facing surface of the second substrate for connecting the computer structure to a power supply voltage.

[0025] After thinning the second silicon substrate, through-silicon vias can be formed in the second silicon substrate to provide a connection between the connector terminals and the first silicon substrate.

[0026] The second silicon substrate can be thinned to a depth of less than 10 μm, giving the second silicon substrate a non-self-supporting depth.

[0027] The first silicon substrate can have a depth of 700 μm to 800 μm.

[0028] Distributed capacitor cells can be arranged in a regular array, and each distributed capacitor cell can be connected to a power supply voltage connector terminal and a ground connector terminal.

[0029] Each distributed capacitor unit may include a predetermined number of capacitor blocks and two keep-away zones, which are located at the positions of two connector terminals. The keep-away zones and capacitor blocks have the same size.

[0030] Through-silicon vias can be formed in the blackout zone. Attached Figure Description

[0031] To better understand the present invention and to illustrate how to implement it, reference will now be made to the following figures by way of example:

[0032] Figure 1 It is a graph showing the relationship between the drawn current and the clock frequency;

[0033] Figure 2 This is a circuit diagram illustrating the first two capacitor stages;

[0034] Figure 3This is a graph showing an example load step response of the Colossus Mk1 chip;

[0035] Figure 4 The simulation of the chip's load step response is shown;

[0036] Figure 5 and Figure 6 The unfolded diagram of the load step response simulation is shown;

[0037] Figure 7 and Figure 8 The load step response simulation of a chip with WoW capacitors is shown;

[0038] Figure 9 This is a schematic diagram of an example stacked die;

[0039] Figures 10A-10C The structure of the DRAM cell capacitor is shown;

[0040] Figure 11A and 11B This is a schematic diagram of a repeatable capacitor unit;

[0041] Figure 12 An example of a C4 convex graph is shown;

[0042] Figure 13 This is a circuit diagram illustrating the three levels of capacitors;

[0043] Figure 14 The display shows the power supply impedance at the chip bumps with and without WoW capacitors;

[0044] Figure 15 This is a schematic diagram of the structure including the IPU;

[0045] Figure 16 This is a schematic diagram of a single-chip processor architecture; and

[0046] Figure 17 The batch synchronous parallel protocol is shown. Detailed Implementation

[0047] question

[0048] Graphcore recently developed a special type of computer called an Intelligent Processing Unit (IPU), as described, for example, in U.S. Patent Application 15 / 886009.

[0049] Colossus is one such IPU chip manufactured by Graphcore. IPUs can be used in fields such as data analytics and artificial intelligence. IPUs have been optimized for massively parallel, low-precision floating-point computation, providing significantly higher computational density than other solutions.

[0050] Figure 1 This chart shows the relationship between the current drawn by the IPU (in amperes) and the IPU clock frequency (in MHz). The graph displays data collected from an IPU containing 1216 tiles. A linear relationship between the drawn current and the clock frequency can be observed; that is, the higher the frequency, the higher the chip's current demand.

[0051] A very significant current step occurs when most blocks of the IPU start or stop issuing AMP instructions, which are computation instructions provided to the execution units in each block.

[0052] The amount of current drawn by an IPU varies depending on the function it performs. The current drawn changes when the IPU changes its function or behavior. A very significant example of a current step occurs during Batch Synchronous Parallelism (BSP). According to BSP, each block in a multi-block array performs computation and exchange phases alternately. During the computation phase, each block performs one or more computational tasks locally on the block but does not communicate its computation results to any other block. During the exchange phase, each block is allowed to exchange one or more results from computations in a previous computation phase to one or more other blocks in the group and / or exchange one or more results of that computation from those one or more other blocks, but a new computation phase does not begin until that block completes its exchange phase. Furthermore, according to this form of BSP principle, barrier synchronization is placed at the juncture of transition from a computation phase to an exchange phase, or from an exchange phase to a computation phase, or both. In other words, either: (a) all blocks in the group must complete their respective computation phases before any block in the group is allowed to proceed to the next exchange phase; or (b) all blocks in the group must complete their respective exchange phases before any block in the group is allowed to proceed to the next computation phase; or (c) both. When used herein, the phrase “between the computation phase and the exchange phase” encompasses all of these options.

[0053] Current requirements were measured at six different clock frequencies, and the results are plotted on... Figure 1 The graph is represented by numbered dots, with these numbers indicating measured current in amperes. These measurements were taken almost continuously across all 1216 blocks of the IPU as AMP instructions were issued. Because current is proportional to clock frequency, a straight line was fitted from the results.

[0054] Therefore, high current is ideal for performance. However, this high current can exacerbate the power supply voltage droop problem, especially when multiple processing units on the chip generate instantaneous current demands.

[0055] In existing package structures used for one or more IPU chips, capacitors are provided at three levels. The first level is the capacitor provided close to the circuitry, referred to here as the die capacitor. This capacitor has the most direct effect because it is electrically closest to the current-drawing circuitry (in this case, the chip), thus having minimal parasitic impedance and resistance, but the capacitance is typically very small.

[0056] The second-stage capacitor is the capacitor provided at the edge of the die (see...). Figure 15 This capacitor can be referred to here as a packaged capacitor. Electrically further away from the current-drawing circuit than a die capacitor, it has more inserted resistance / inductance, and therefore takes longer to take effect.

[0057] The third level is referred to here as "external" capacitance. This is the capacitance effect of the pads on the printed circuit board (PCB) where the die is mounted (see...). Figure 15 Due to the physical distance between the pads and the die, this takes longer to take effect under load step conditions.

[0058] Figure 13 This is a circuit diagram showing the resistor, inductor, and capacitor (RLC) components that connect power supply 1302 to chip 1806. In this example, the chip is a Graphcore Colossus Mk2 chip. Die capacitors (first stage), package capacitors (second stage), and PCB capacitors (third stage) are all shown. Figure 13 In the circuit diagram.

[0059] Figure 2 This is a circuit diagram representing the first two capacitor stages. Figure 2 The chip 1806 in the text is a Graphcore Colossus Mk1 chip.

[0060] It should be understood that, despite Figure 2 and Figure 13 The specific values ​​for the capacitance, resistance, and inductance of the circuit elements are given, but other circuit elements can be used to make these values ​​different.

[0061] The first-stage capacitor is provided by die 1806, which in this example has a capacitance in the range of 10μF, for example, in the range of 5μF to 30μF, and a resistance in the range of 100μOhm. The capacitance and resistance are inherent to the circuit elements on die 1806.

[0062] Figure 2 The circuit diagram also shows the second-stage capacitance provided by capacitor 1808. There are hundreds of microfarads of capacitance, consisting of hundreds of discrete capacitors, for example, 300 capacitors, each with a capacitance of 1 μF, an inductor in the range of 2 pH, and a resistor in the range of 200 μOhm. These hundreds of discrete capacitors 1808 are located around die 1806 to minimize series parasitic inductance and resistance, specifically to add capacitance to the package. The package inductance and resistance can be referred to as parasitic inductance and parasitic resistance, respectively, because they are not specifically introduced into the circuit but are inherent inductance and resistance effects present in real electronic devices. The second-stage capacitance is on the order of 100 μF.

[0063] use Figure 1 The gradient of the straight line is used to calculate the switching capacitance using the following formula:

[0064]

[0065] Where C is capacitance, I is current, V is voltage, and F is clock frequency. It is approximately 2.5% of the total estimated on-die capacitance.

[0066] Supply voltage droop is related to capacitor usage but accumulates over high-frequency clock cycles. In each clock cycle, the supply voltage droops by 2.5%, corresponding to the percentage of on-chip capacitance calculated above. This is because 2.5% of the on-chip capacitance switches each clock cycle. The supply voltage drop accumulates over multiple clock cycles and, in some cases, consumes the total on-chip capacitance.

[0067] In this example, only four clock cycles can occur before the on-chip capacitor depletes to 10%. Shortly after the on-chip capacitor depletes, external capacitors, such as package capacitors, become the primary source of power. Compared to the capacitance associated with each clock cycle, when the on-chip capacitance is small (as in this case), external capacitors become the primary source of power after a very short period. This will be discussed later. Figure 5 To provide a more detailed explanation.

[0068] Figure 13 The diagram shows the RLC circuit for power supply decoupling of the Graphcore Colossus Mk2 logic chip. As mentioned above, this circuit represents all three levels of capacitance: die capacitance and package capacitance, such as... Figure 2 As shown, there are also external capacitors. The external capacitors are located on the other side of the die bumps relative to the chip, that is, between the power supply and the die bumps.

[0069] The die is shown to have capacitance in the range of 20 μF, for example, in the range of 5 μF to 30 μF, and resistance in the range of 300 μOhm. The package has resistance in the range of 200 μOhm, inductance in the range of 2 pH, and capacitance in the range of several hundred microfarads, for example, approximately 800 μF.

[0070] Frequency components of load transients below approximately 2MHz are handled by a combination of large (high-capacity) capacitors on the PCB near the package and a power feedback loop that monitors the power supply voltage at the die and responds to voltage droop by delivering more current.

[0071] like Figure 13 As shown, the third stage capacitance is on the order of 1000 μF and has a parasitic series inductance on the order of 10 pH.

[0072] It should be understood that the resistance, inductance, and capacitance values ​​given above for existing packages are provided as examples. Package designs and power supply configurations vary considerably. However, in all cases, it is necessary to increase the die capacitance, especially when dealing with high-frequency, high-current requirements. Figure 13 Each discrete capacitor shown has significant inherent series resistance and inductance, which are not shown in the RLC diagram.

[0073] Parasitic inductance affects when various discrete capacitors take effect. On-die capacitance takes effect within 0 to 0.25 ns after a load step. Packaged capacitors take effect after approximately 10 ns. Package / ball and PCB capacitors take effect after approximately 250 ns. Most power supplies include a regulator that operates a capacitor feedback loop to accommodate voltage droop, but this requires a longer response time, such as 1-2 μs.

[0074] Figure 3 The diagram shows the load step response of the Colossus Mk1 chip when a load step is applied, resulting in a voltage drop of approximately 50V. When performing computational operations, the load step corresponds to a change in the current demand from the on-chip processing circuitry.

[0075] For example, when chip behavior changes from performing high-power computations to exchanging data between blocks, there is a load step, which is less computationally intensive. As mentioned earlier, this load step can be exacerbated in a BSP architecture.

[0076] We hope to avoid power supply voltage V SS The droop of the power supply voltage is a rapid change. Ideally, the power supply voltage should remain constant so that changes in current have no effect on it. However, this is unlikely to be achieved due to the imperfections of electronic components. Therefore, the goal is to reduce the droop of the power supply voltage and eliminate rapid changes in it.

[0077] exist Figure 3 In the middle, the initial power supply voltage V applied to the IPU initial Approximately 800mV. Minimum voltage V min Approximately 750mV. There is a predetermined minimum supply voltage, which is the lowest voltage required for the chip to operate safely; below this voltage, the supply voltage cannot drop. Therefore, the supply voltage V must be monitored. DD Adjust the margin to ensure that the die experiences a V... min The voltage shall not be lower than the predetermined minimum power supply voltage.

[0078] The minimum supply voltage experienced at the die is affected by the transient response of the voltage to the load current. This includes supply voltage droop, which may include an undershoot. Voltage droop refers to the phenomenon where the supply voltage decreases in response to an increase in draw current until the regulator maintains the supply voltage. Therefore, this needs to be taken into account. Currently, this is achieved by increasing the initial supply voltage so that the minimum supply voltage experienced during the undershoot is higher than a predetermined minimum supply voltage.

[0079] Figure 4 The load step response simulation using the Graphcore Colossus Mk1 chip is shown, such as... Figure 2 As shown.

[0080] The graph shows the initial voltage of approximately 0.8-0.9V, or on the order of 1V, supplied at the die bumps of the IPU. Time is plotted on the x-axis, and the supply voltage on the y-axis. At t = 0.0001s, there is a step increase in current demand from 80A to 300A, which results in the load step response shown around time t = 0.0001s.

[0081] The initial supply voltage is the supply voltage when there is no load. When a load is applied, such as when current demand increases, current flows through electrical components, causing the inherent resistance and inductance of these components to cause the supply voltage to drop.

[0082] As can be seen, the power supply voltage stabilizes at around 0.8V. The difference between the initial power supply voltage and the stable or steady-state power supply voltage is caused by the drop in IR, which is maintained by the stable load line.

[0083] However, before stabilization, there is a supply voltage undershoot below the steady-state voltage. An undershoot occurs in the transient response when the supply voltage drops sharply below the smooth nominal voltage droop curve.

[0084] because Figure 2 The decoupling of the parasitic inductance and capacitor elements of the shown component will result in an initial undershoot. A second undershoot will occur later due to the regulator response. (See below for reference.) Figure 5 A more detailed description of the downward stroke.

[0085] Subsequently, at time t = 0.00136s, due to load release, a second load step response occurs, reducing the current demand. That is, the current decreases, therefore the supply voltage increases. Two overshoots occur; the first is due to... Figure 2 The decoupling of inductor and capacitor components, and the second is due to the power supply choke (see...). Figure 13 The voltage of the capacitor is dumped into the decoupling capacitor. This voltage dumping is derived from the following equation:

[0086] E = 0.5LI 2

[0087] Where L is the effective inductance and I is the current drawn by the chip.

[0088] Figure 5 The undershoot in the power supply voltage caused by the step response at time t = 0.0001 s is shown in more detail, as in the reference. Figure 4 The x-axis displays the time following a load step on a logarithmic scale.

[0089] The graphs show three undershoots: 508, 510, and 512. Three different graphs, 502, 504, and 506, have also been plotted, each representing a different step duration. Step duration is the time required to apply current. A longer step duration results in a longer delay before the first minimum voltage is achieved, because a shorter step duration causes the on-chip capacitor to deplete more quickly. However, the three graphs 502, 504, and 506 tend to have the same shape, and it can be seen that the three graphs meet at the second undershoot minimum and then follow the same shape. The three step durations shown are 5ns, 10ns, and 20ns, corresponding to graphs 506, 504, and 502, respectively. The 20ns step duration curve 502 will be discussed in further detail below.

[0090] The first undershoot of the power supply voltage occurs when the die capacitor discharges. The first power supply voltage undershoot of the 508 has a minimum voltage of approximately 0.79V, occurring about 10ns after a load step. This minimum voltage value can be calculated from the load step duration (a shorter step duration results in a lower minimum voltage), the die capacitance, and the package series impedance. As mentioned above, the minimum voltage occurs when the on-chip capacitor is depleted.

[0091] When the power supply voltage drops due to the discharge of the capacitor on the die, the voltage across the inductor connected in series with the capacitor on the die will gradually increase. Once this voltage is high enough, the power supply voltage will stop dropping and begin to rise.

[0092] The voltage briefly rises and then falls again, this time due to the discharge of the packaged capacitor. The second power supply voltage downscaling to the minimum of 510V is sensitive to the capacitance of the packaged capacitor and the series impedance of the PCB. The minimum power supply voltage occurs approximately 250ns after a load step, and the minimum value is approximately 0.77V.

[0093] When the power supply voltage drops for the second time, the voltage across the bulkin conductor gradually increases. Once this voltage is high enough, it prevents the power supply voltage from dropping further, causing the power supply voltage to rise until it reaches its peak value.

[0094] After the peak, the power supply voltage dropped a third time, this time due to the discharge of capacitors on the PCB. These capacitors are as follows: Figure 13 As shown. The minimum supply voltage occurs approximately 3 μs after a load step. The minimum value is approximately 0.79 volts. The minimum voltage is sensitive to the PCB capacitance and the power control loop response.

[0095] After the third power supply under-voltage 512, the power supply voltage rises and stabilizes at a steady-state voltage of approximately 0.8V. This is due to the regulator's response.

[0096] Figure 6 It shows Figure 5 The time step chart is 20ns, but there is an additional supply voltage spike of approximately 250ns at 602. This spike at 602 has a minimum value of approximately 0.75V.

[0097] Another reason for load steps in current is turning the clock on and off (e.g., ensuring that the current clock is safely deselected before implementing a different clock).

[0098] The spike at 250ns (602) is due to a brief 3ns load release caused by the clock deselect signal. Here, the clock temporarily stops and then restarts, causing the current to drop from 300A to 0A, and then very quickly increase back to 300A.

[0099] The power supply voltage has a predetermined minimum value, and it is undesirable for the power supply voltage to drop below this value. This minimum power supply voltage is determined by the minimum voltage at which the hardware can operate normally. A malfunction will occur if the voltage drops below this minimum value. The predetermined minimum permissible voltage value can be defined as an amount higher than the absolute minimum voltage, at which the IPU can operate to ensure that no malfunction occurs in the event of an unexpected low power supply voltage (undershoot).

[0100] Currently, ensuring V min The only way to prevent the voltage from dropping below the minimum permissible supply voltage is to increase the initial supply voltage. As described below, this has implications for both power consumption and performance.

[0101] The present invention aims to reduce power supply voltage undershoot.

[0102] Dynamic power and V DD 2 It is proportional to F, that is, the square of the power supply voltage multiplied by the clock frequency.

[0103] By reducing the undershoot, the difference between the initial supply voltage and the minimum supply voltage experienced due to voltage droop is reduced, thus allowing for a lower initial supply voltage while still limiting the minimum supply voltage to a predetermined V. min Therefore, the frequency can be increased without changing the dynamic power.

[0104] For example, if the downstroke can be reduced by 5%, V DD It can also be reduced by 5%. Then, to maintain the same dynamic power, the clock frequency can be increased. Therefore, the clock frequency can be increased by 11%. Since performance is directly proportional to clock frequency, performance can also be improved by 11%.

[0105] Various aspects of this invention were developed within the context of an IPU architecture featuring parallel processing units on multiple dies operating synchronously. (See references) Figure 16 This die is described. However, it should be understood that the present invention has a broader applicability to reducing voltage drops in chip processing power supplies.

[0106] Figure 16 The architecture of a single-chip processor 2 is schematically illustrated. Processor 2 includes multiple processing units referred to as blocks. In one embodiment, 1216 blocks are organized into arrays 6a and 6b. In the described example, each array has 76 blocks in eight columns (in practice, for redundancy, there are typically 80 blocks). Chip 2 has two chip-to-host links 8a and 8b arranged on one edge of chip 2 and four chip-to-chip links 30a and 30b. The chip can be connected together to form a card via an additional six chip-to-chip links 30a and 30b arranged along the other edge of the chip.

[0107] Chip 2 has a clock 3, which controls the timing of computer operation and other chip activities. The clock is connected to all active circuitry and components of the chip. Chip 2 includes a switching structure 34, to which all blocks and links are connected via multiple sets of interconnecting lines.

[0108] Each block 4 has processing circuitry and local memory. The processing circuitry includes an execution pipeline with one or more execution units.

[0109] It performs pipelined processing operations, such as mathematical calculations, and is responsible for executing exchange instructions that cause data to be exchanged between blocks within the chip. Each chip runs a batch synchronous parallel protocol, which includes computation and exchange phases. This protocol is as follows: Figure 17 As shown. Figure 17 The left-hand side of the diagram represents the computation phase, where each block 4 is in a phase where stateful codelets are executed on local memory. Although in Figure 17 In the diagram, block 4 is shown as arranged in a circle, but this is only for illustrative purposes and does not reflect the actual architecture.

[0110] After the computation phase, there is synchronization, indicated by arrow 30.

[0111] BSP itself is known in the art. According to BSP, each block 4 executes a computation phase 52 and an exchange (sometimes referred to as communication or messaging) phase 50 in alternating cycles. The computation and exchange phases are executed by the blocks that execute instructions. During computation phase 52, each block 4 executes one or more computation tasks locally on the block, but does not communicate any results of these computations with any other block 4. In exchange phase 50, each block 4 is allowed to exchange (communicate) one or more computation results from previous computation phases to one or more other blocks in the group and / or exchange (communicate) one or more computation results from one or more other blocks in the group, but has not yet executed any new computations that have a potential dependency on tasks executed on another block 4 or that tasks on another block 4 may depend on (not excluding other operations such as internal control-related operations that may be executed during the exchange phase). Furthermore, according to the principles of BSP, barrier synchronization is placed at the junction of the transition from computation phase 52 to exchange phase 50, or the junction of the transition from exchange phase 50 to computation phase 52, or both. In other words, either: (a) all blocks 4 are required to complete their respective computation phases 52 before any block 4 in the group is allowed to proceed to the next exchange phase 50; or (b) all blocks 4 in the group are required to complete their respective exchange phases 50 before any block 4 in the group is allowed to proceed to the next computation phase 52; or (c) both conditions are implemented. This sequence of exchange and computation phases can then be repeated multiple times. In BSP terminology, each repetition of the exchange and computation phases is referred to herein as a "superstep," consistent with its usage in some previous descriptions of BSP. It should be noted here that the term "superstep" is sometimes used in the art to refer to each of the exchange and computation phases.

[0112] One impact of the BSP protocol is that it exacerbates the current draw requirement because all or many blocks are computed and exchanged simultaneously. The current draw requirement for computation is much higher than that for exchange. Therefore, there is a large load step when blocks begin their computation phase simultaneously, corresponding to a large increase in current draw, and a second large load step when blocks begin their exchange phase simultaneously, this time corresponding to a large decrease in current draw.

[0113] Figure 15 A diagram showing the structure including the IPU is provided. A package substrate 1802 forms the base layer on which components are attached. The package substrate 1802 is a printed circuit board (PCB).

[0114] The die (or chip) 1806 is placed on the package substrate 1802. The die 1806 includes logic for performing calculations.

[0115] Surrounding the die 1806 is a capacitor array 1808. The capacitors are multilayer ceramic capacitors, measuring 0.5mm by 1mm. These capacitors 1808 are placed as close as possible to the package substrate 1802 of the die 1806 to reduce the inductance between the current-drawing circuitry and the capacitors. As described above, these discrete capacitors 1808 are considered to provide "on-chip" capacitance. It should be understood that, by using the aspects of the invention described below, this capacitance can be reduced or completely eliminated by providing on-chip capacitance over time.

[0116] The capacitor 1808 is surrounded by a reinforcing ring 1804. The reinforcing ring 1804 is a metal ring that is attached to the surface of the encapsulation substrate 1802 using epoxy adhesive. The reinforcing ring 1804 improves the robustness of the die.

[0117] As is known in the art, Figure 15 The structure is constructed using flip-chip technology. The die 1806 is attached to the package substrate 1802 using solder bumps or C4 balls, with the balls facing down. These are solder balls attached to the top side of the die 1806. Once the die 1806 is in place on the package substrate 1802, the structure is heated, causing the C4 balls to melt and the die 1806 to be soldered into place on the package substrate 1802. This process can be called "packaging".

[0118] The package substrate 1802 also includes a solder ball array. This array is located on the underside of the package substrate 1802 and is used to connect the package to the PCB. The package solder balls are much larger than C4 balls and have a greater pitch. A C4 ball is a connector terminal.

[0119] Other types of connector terminals, i.e., devices for connecting chips to other components, can be used. The form the connector terminals take can depend on the type of package and / or the method of connection to the package. For example, copper pillars are used as connector terminals when the chip is connected to a conventional package, and microbumps are used as connector terminals for flip chips on silicon interposers.

[0120] According to some embodiments of the present invention, a solution for reducing power supply voltage undershoot is provided, which uses wafer-to-wafer technology to provide surface-distributed capacitance with very low series impedance to the chip processing circuit.

[0121] Distributed capacitor chip 904 is stacked together with processor chip chip 902. This stacking may be referred to herein as chip-to-chip (WoW). In this disclosure, the processor chip chip referred to may be a Colossus Mk1 or Mk2 chip manufactured by Graphcore, although it will be understood that any processor chip may be used.

[0122] Processor chip 902 is the first silicon chip. That is, it forms the bottom of the stacked dies before being flipped. Distributed capacitor or DRAM chip 904 is the second silicon chip forming the top of the stacked dies. The arrangement of chips 902 and 904 before flipping... Figure 9 It is shown in the figure and explained in more detail later.

[0123] A corresponding bonding layer 922 is formed on the “inner” surface of each of the wafers 902 and 904, providing a connection between the two wafers 902 and 904. The bonding layer 922 will be described in more detail later. The DRAM wafer 904 is then stacked on top of the processor wafer 902, such that the two bonding layers 922 contact and align.

[0124] Once stacked, the DRAM wafer 904 is thinned. Wafer thinning can be achieved using known techniques to thin the substrate, thereby achieving the desired flatness, such as chemical mechanical polishing. It should be understood that other suitable known techniques can be used.

[0125] The DRAM chip 904 is thinned after stacking so that the processor chip 902 can provide sufficient support for it. The DRAM chip 904 is thinned to only a few micrometers thick, for example, the thinning thickness can be in the range of 3μm to 10μm. In contrast, the processor chip 904 can be approximately 700μm, or in the range of 400μm to 1000μm. The processor chip 902 has a self-supporting depth, meaning that the processor chip 902 is deep enough to support itself without an additional substrate. The DRAM chip 904 is thinned to have a non-self-supporting depth, meaning that the DRAM chip 904 cannot support itself without some kind of support layer (in this case, the processor chip 902).

[0126] Through-Silicon Vias (TSVs) 918 are created in DRAM wafer 904, providing connections to processor wafer 902. TSVs 918 can be fabricated using known techniques such as plasma etching to achieve an aspect ratio with a predetermined sidewall angle, which is the acute angle formed by the sidewall of the TSV with respect to the horizontal plane. TSVs are created after wafers 902 and 904 are stacked and DRAM wafer 904 is thinned. This allows TSVs to be formed in the stacked dies with very small diameters and very low pitches, with each TSV 918 having a diameter ranging from 2 μm to 5 μm. This is much smaller than the TSVs used in conventional CPUs. The pitch of the TSVs 918 (the distance between them) can also range from 2 μm to 5 μm.

[0127] A UBM layer 926 is formed on the “outer” surface of the DRAM wafer 904. The UBM layer 926 is a pad on the surface of the DRAM wafer 904 on which one or more solder joints or C4 balls 920 are deposited. The stacked wafers 902, 904 can then be connected to external circuitry using controlled stacking chip connections or “flip-chip” methods known in the art. The C4 balls form the connection between the stacked wafers 902, 904 and the external circuitry. It should be understood that in embodiments using different types of connector terminals, the UBM layer 926 may not be present.

[0128] In this arrangement, the capacitor layer acts as a power supply decoupling capacitor and includes multiple DRAM cell blocks (capacitor cells). DRAM cells consist of large, densely packed capacitor arrays. Currently, the capacitance of a DRAM cell at approximately 40nm is approximately 1500fF / μm. 2 Throughout approximately 800mm 2 On the die, this will have a total capacitance of approximately 1200μF. It should be understood that these values ​​are provided as examples and components with other characteristics can be used.

[0129] Figure 9An example of a structure formed as a result of stacking processor chip 902 and DRAM chip 904 to form a stacked die is shown.

[0130] The processor chip 902 comprises several layers. The bottom layer is the processor chip substrate 906. The processor chip 902 also includes a FinFET and a BeOL layer 908. This layer is located on top of the processor chip substrate 906. It should be understood that the terms "on top" and "on bottom" do not necessarily define any particular orientation, but rather define the relative positions of the layers with respect to each other.

[0131] A top metal (Mr) layer 910 is added on top of the finFET and BeOL layer 908. The Mr layer 910 replaces the application processor (AP) and / or redistribution (RDL) layers of the processor chip 902 for cases where there is no WoW capacitor layer.

[0132] DRAM chip 904 is located on top of processor chip 902. DRAM chip 904 may face down, such that the exposed (“outer”) surface of chip 904 is the back side of the chip. Alternatively, the back side of DRAM chip 904 may contact the top of processor chip 902, such that the exposed surface of DRAM chip 904 is the top side of the chip. Figure 9 The example shown illustrates a DRAM wafer 904 facing down, with the back side of the wafer exposed.

[0133] The exposed surfaces of wafers 902 and 904 are surfaces that do not contact one other wafer 902 or 904. That is to say, in Figure 9 In this context, the exposed ("external") surface of the processor chip 902 is the bottom surface of the processor chip substrate 906, while... Figure 9 In this context, the exposed (“outer”) surface of the DRAM wafer 904 is the top surface of the DRAM wafer substrate layer 914.

[0134] The back side of chips 902 and 904 refers to the side of substrate layers 906 and 914 where no additional layers are placed. Taking processor chip 902 as an example, the back side of processor chip 902 is the bottom side of processor substrate layer 906. The top side of chips 902 and 904 is the opposite side of chips 902 and 904. This is the outermost layer containing circuitry, such as the top of Mr layer 910 of processor chip 902. The top side of chips 902 and 904 must be connected to the power supply voltage, but does not need to be connected to the back side because no current-consuming circuitry is located there.

[0135] The surfaces of wafers 902 and 904 that face and overlap with each other can be referred to as inward-facing surfaces. The inward-facing surfaces of the two wafers 902 and 904 have the same shape and size, allowing them to match when overlapped. This means that the wafers share a common external shape and size when stacked.

[0136] It should be understood that the term “equal” as used herein should not be interpreted literally, but rather means approximately or preferably equal based on design factors as understood in the art, according to predetermined specifications of distance and / or size.

[0137] The DRAM chip 904 may include at least two layers: a capacitor substrate layer 914 which may be made of silicon and a stacked capacitor layer 916.

[0138] The capacitor substrate 914 can be made of silicon. Through-silicon vias (TSVs) 918 are formed in the capacitor substrate 914. These vias, located directly beneath the C4 balls 920 in the layer 914, provide a connection between the C4 balls and the top side of each wafer 902, 904. The C4 balls can provide power supply voltage V. DD Ground voltage V SS Connections to I / P ports, such as via a serializer / deserializer (SerDes). Note that each C4 ball 920 is associated with multiple TSV 918s.

[0139] The capacitor layer 916 may include two portions: a stacked capacitor portion 930 and a capacitor-free portion 928. The capacitor-free portion 928 is aligned with the portion of the capacitor base layer 914 that includes the TSV. This portion 928 of layer 916 includes vias and metal to allow electrical connections from the TSV 918 to the processor die 902.

[0140] The remaining area of ​​capacitor layer 916 includes capacitor portion 930. Figure 9 In the example, these regions include stacked capacitors with capacitance on the order of 1 / μm. Capacitor section 930 provides an array of stacked capacitors.

[0141] The capacitor layer 916 is approximately 2 μm thick. The capacitor layer 916 may be coated with a metal oxide.

[0142] An additional layer may be provided between the two wafers 902 and 904 to provide connectivity. This layer may be a bonding layer 922, which allows for connectivity between the two wafers 902 and 904. Although in Figure 9While shown as a single layer, a bonding layer 922 can be formed on each of wafers 902 and 904. The bonding layers of wafers 902 and 904 are mirror images of each other to provide the required connectivity. The bonding layer 922 may include an array of WoW connectors 924. These connectors provide an electrical connection between the DRAM die 904 and the processor die 902, allowing the power supply voltage connected to the C4 ball on the upper side of the structure to be supplied to the processor die 902.

[0143] Once the processor chip 902 and DRAM chip 904 have been stacked, the capacitor substrate layer 914 can be thinned. Only one substrate layer 906, 914 can be thinned because structural robustness needs to be maintained. The advantage of using a DRAM chip 904 with separate substrate and capacitor layers 914, 916 is that the capacitor substrate layer 914 can be thinned more easily than if the capacitor were embedded in the substrate, because care is not required to avoid the capacitor.

[0144] The under-ball metallization (UBM) layer 926 is located on the exposed surface of the capacitor wafer 904, which in this example is the back side of the capacitor substrate layer 914, so that it forms a connection between the C4 ball 920 and the DRAM wafer 904.

[0145] The DRAM chip 904 is used to provide capacitance and includes a regular electrical connection pattern, which makes it suitable for contact with the C4 ball. Furthermore, due to these connections, the resistance is reduced.

[0146] By using the area of ​​approximately 25μm by 25μm DRAM cells with each DRAM cell capacitor having a capacitance of approximately 15fF, the total capacitance of the capacitor block is approximately 0.8nF, and ranges from 0.5μF to 1.5μF. This can be provided by approximately 54,000 DRAM cell capacitors.

[0147] Figures 10A-10C The structure of the DRAM cell capacitor is shown.

[0148] Figure 10A A plan view of a cellular structure for a DRAM cell is shown. Each capacitor 1002 has six adjacent capacitors 1002, each capacitor being located equidistant from all six of its neighbors. The cellular structure provides a constant fill density for the capacitors 1002, and this density is higher than that in a square arrangement. This cellular structure for DRAM cells is known in the art. Figure 11B An aerial view of the same honeycomb structure is shown.

[0149] Figure 10CThis is an illustration of two trench capacitors 1002. The trench capacitors 1002 are formed in the stacked capacitor layer 916 of the DRAM wafer 904. The trench capacitors can be formed using known techniques such as plasma etching.

[0150] The trench capacitor 1002 includes a storage node 1004 and a dielectric film 1006 on the inner surface of the trench capacitor 1002. The storage node 1004 may include hemispherical grains of polycrystalline silicon. This layer 1004 increases the surface area of ​​the trench capacitor 1002. The storage node 1004 may, for example, double the surface area of ​​the trench capacitor 1002.

[0151] A dielectric film 1008 is formed on the surface of the storage node 1004. This film has a high dielectric constant. For example, it can include tantalum pentoxide, aluminum oxide, hafnium dioxide, or any other suitable material.

[0152] The trench capacitor 1002 has a patterned high aspect ratio, for example, the high aspect ratio is greater than 10.

[0153] Figure 11A and Figure 11B A repeatable capacitor cell 1100 is shown, which can be used as the WoW capacitor chip disclosed herein.

[0154] Figure 11A A single reusable capacitor cell 1100 is shown, with a total area of ​​approximately 10,000 μm. 2 The capacitance is on the order of 10nF, for example, in the range of 5nF ​​to 30nF. The size of the repeatable capacitor cell 1100 can be defined by the C4 ball pitch, as discussed later. The total distributed capacitance depends on the size of the processor chip 902, the total area of ​​the processor chip 902 covered by the repeatable capacitor cell 1100, and the capacitance of the repeatable capacitor cell 1100. (See reference...) Figure 12 The reusable capacitor cell 1100 discussed covers at least 80% of the area of ​​the processor chip 902. The total distributed capacitance provided by the reusable capacitor cell 1100 for each die is in the range of 650 μF to 850 μF. For different die sizes, the total distributed capacitance will take different values. The distributed capacitance is greater than 0.5 μF / mm². 2 Preferably at 0.5 μF / mm 2 Up to 3μF / mm 2 Within this range. Multiple patterned dies can be present on each DRAM chip 904. For example, approximately 65 patterned dies can be present on each chip. The number of dies on each DRAM chip 904 can depend on the die size.

[0155] The repeatable capacitor cell 1100 includes 13 capacitor blocks 1104 and two hold-out regions 1102a and 1102b. The hold-out regions 1102a and 1102b correspond to capacitor-free regions 928 of the capacitor layer 916 of the DRAM wafer 904. Each capacitor block 1104 and hold-out regions 1102a and 1102b can have a size of approximately 25 μm by 25 μm. It should be understood that the dimensions given herein are merely example dimensions, and any other suitable dimensions can be used. Furthermore, the number of capacitor blocks 1104 in each repeatable capacitor cell 1100 can vary depending on the size of the repeatable capacitor cell 1100 and the capacitor blocks 1104.

[0156] The capacitor blocks 1104 and the restricted areas 1102a and 1102b are arranged such that they form a rectangle of 5 by 3 blocks. No capacitors are provided in the restricted areas 1102a and 1102b. Thus, the repeatable capacitor unit 1100 is a rectangle comprising a region of 15 units, but with two units removed from opposite corners. That is, the top row comprises 4 capacitor blocks 1104, and the middle row comprises 5 capacitor blocks 1104, with the first end of the middle row being the same as the first end of the top row. Figure 11A The left end of the middle row is aligned with the bottom row, which includes four capacitor blocks 1104. The second end of the middle row corresponds to the same end of the bottom row. Figure 11A Align the right end of the capacitor. The diagonal length of the repeatable capacitor cell 1100 is equal to the bump pitch, because the opposite corners include the forbidden areas 1102a and 1102b.

[0157] It should be understood that Figure 11A The structures shown and described above are only one possible structure for the repeatable capacitor 1100. The layout and number of capacitor blocks 1104 depend on the size of the capacitor blocks 1104 and the spacing of the C4 spheres. As described below, there must be forbidden zones 1102a and 1102b at the positions of the C4 spheres, and each repeatable capacitor unit 1100 is connected to two different C4 spheres at opposite corners. Therefore, depending on the size of the blocks 1104 and the spacing of the C4 spheres, a larger or smaller number of capacitor blocks 1104 may be required to produce repeatable capacitor units 1100 that meet these requirements. The number of capacitor blocks 1104 constituting the repeatable capacitor unit 1100 can be between 10 and 20.

[0158] Forbidden zones 1102a and 1102b provide capacitor-free areas where C4 bumps connect to the TSV 918 of the DRAM chip 904. Supply voltage V DD and ground voltage V S3 It is applied at the opposite corner of the repeatable capacitor block 1100. Figure 11AIn the example, the power supply voltage is applied to the upper right corner of the power supply exclusion zone 1102a, and the ground voltage is applied to the lower left corner of the ground exclusion zone 1102b.

[0159] The spacing of the TSV 918 affects the size of the keep-out regions 1102a and 1102b. A finer spacing allows these regions 1102a and 1102b to be smaller. Smaller keep-out regions 1102a and 1102b are ideal because there are no capacitors in keep-out regions 1102a and 1102b; therefore, the smaller the keep-out regions 1102a and 1102b, the higher the capacitance of the repeatable capacitor cell 1100 for a constant-size repeatable capacitor cell 1100.

[0160] The array of chip-to-chip connectors can be seen. Figure 11A The example illustrates WoW connectors 924 evenly spaced on the surface of a DRAM wafer 904. The WoW connectors 924 can have a pitch on the order of 2 μm; for example, the pitch can be in the range of 1 μm to 5 μm. It should be understood that other WoW connector pitches are also possible depending on the requirements of the processor wafer 902. Figure 9 As shown, the WoW connector 924 provides a connection between the DRAM chip 904 and the processor chip 902.

[0161] WoW connector 924 can be divided into two categories according to its function: V which connects to the power supply voltage. DD WoW connector and V connected to ground SS WoW connector 924.

[0162] Power supply restricted area 1102a mainly includes V DD WoW connector, while the grounding exclusion zone 1102b mainly includes V SS WoW connector. Capacitor cell 1104, aligned in the x-direction with the grounding exclusion zone 1102b, includes V... SS WoW connector. Capacitor block 1104, aligned in the x-direction with the power outage region 1102a, includes some V... DD WoW connector.

[0163] Some WoW connectors 924 may not be V. SS or V DD Connectors. There may be no connection between these connectors and the processor chip 902. For example, the WoW connector 924 does not connect to V. SS or V DD C4 ball alignment, that is, along the middle row of capacitor block 1104.

[0164] Figure 11BA capacitor layer comprising multiple repeatable capacitor cells 1100 is shown. The repeatable capacitor cells 1100 are aligned to produce multiple rows of V0. DD WoW connector and V SS WoW connector.

[0165] The forbidden zones 1102a and 1102b are aligned so that a group of four forbidden zones 1102a and 1102b of the same type are grouped together. Each group of four forbidden zones 1102a and 1102b is associated with a single C4 ball 920.

[0166] The repeatable capacitor unit 1100 can be replicated approximately 75,000 times per die. It should be understood that the number of repeatable capacitor units 1100 per die will depend on the size of the die and the repeatable capacitor unit 1100.

[0167] When using DRAM chip 904 as the capacitor layer Figure 9 The structure shown has many advantages.

[0168] First, the processor chip 902 does not need to be changed in any way. Thinning of the logic layer requires careful thinning to avoid logic issues or redesigning the logic to allow for thinning. The TSV 918 can be formed within the DRAM chip to allow connection to the logic chip. There is no need to redesign the processing circuitry within the processing die. Therefore, by using the DRAM chip as the top layer, there is no need for an expensive and time-consuming redesign of the logic chip, allowing the same logic chip to be used with or without WOW capacitor chips, using the same mask set for most layers.

[0169] However, in an alternative embodiment, the two chips 902 and 904 can be switched. That is, Figure 9 The bottom wafer shown is DRAM wafer 904, and the top wafer is processor wafer 902. Processor wafer 902 will be thinned, and TSV 918 will be generated through the substrate 906 of processor wafer 902. In this embodiment, DRAM wafer 904 will still provide on-die capacitance. However, hold regions 1102a and 1102b will need to be generated on processor wafer 902. This will require a redesign of the logic on processor wafer 902. Furthermore, the area available for logic will be reduced. The area of ​​processor wafers is often limited, therefore it is preferable that there are no hold regions in processor wafer 902. The silicon area in DRAM wafer 904 is less valuable than the silicon area in processor wafer 904.

[0170] Figure 12An example C4 relief pattern 1202 used in this invention is shown. The dimensions of relief pattern 1202 correspond to the size of the die, which is 25.7 mm by 32 mm in this case. It should be understood that other dies of different sizes may be used in this invention.

[0171] The convexity diagram 1202 displays each convexity as a discrete point. Three different colored points are shown. Red dots represent V. DD The bumps and black dots represent V-shapes. SS Bumps, with green dots representing "other" bumps. For example, other bumps can be used for I / O ports.

[0172] Other bumps cluster together to form patch 1204, which is located around the outer periphery of the processor die. A small amount of V... SS The bump is located in the patch 1204. The die body 1206 includes a V-shaped... DD and V SS The columns of bumps are shown more clearly in the unfolded diagram 1208. The centers of the bumps on the processor die are separated by the bump spacing, as shown... Figure 12 As shown. The bump pitch can be approximately 150 μm, but other sizes are also acceptable. The bump pitch can range from 25 μm to 250 μm.

[0173] Repeatable capacitor 1100 only covers V DD -V SS The bump pattern area means that it only covers the die body 1206 and not the surface mount 1204. For example, there are no repeatable capacitors on the I / O ports. For example, there could be approximately 75,000 repeatable capacitor cells 1100 covering the die body 1206.

[0174] Figure 7 The load step response of the Colossus Mk1 with a 750 μF on-chip capacitor is shown. The improved load step response 702 is shown superimposed on the 20 ns step response 502. The 5 ns step response 506 is also shown.

[0175] As a reference Figure 5 The 20ns step response 502 is discussed, and the improved step response 702 has three minimum supply voltages.

[0176] The minimum first power supply voltage of 704 is the result of the discharge of capacitors on the distributed chip. The capacitors on the chip include, for example... Figure 2 and Figure 13The diagram shows both the chip's inherent on-chip capacitance and the DRAM chip 904 capacitor. The minimum undershoot is approximately 0.835V, occurring about 10ns after a load step is applied. It can be seen that this minimum supply voltage is significantly larger than the minimum supply voltage of curve 502 without the DRAM chip 904 capacitor. This is because the percentage of the capacitance associated with each clock switch in the total on-chip capacitance is much lower, resulting in a much smaller supply voltage drop for the same number of clock switches.

[0177] The second supply voltage undershoot 706 is the result of the discharge of on-chip capacitors and package capacitors. This undershoot 706 has a minimum value of approximately 0.795V. The minimum supply voltage at the undershoot is sensitive to the series impedance of on-chip capacitors, package capacitors, and the PCB.

[0178] The third undervoltage event 708 is due to the discharge of the PCB capacitor. As before, the minimum voltage value is sensitive to PCB capacitors and the response of the power control loop.

[0179] A spike 710 caused by clock switching still exists in the power supply voltage. However, this spike 710 only increases the power supply voltage, and its amplitude is significantly reduced compared to the spike 602, which has no distributed on-chip capacitors in the IPU response.

[0180] from Figure 7 As can be seen from the graphs, the minimum voltage increased by approximately 45mV by introducing distributed on-chip capacitors. The improved minimum voltage in the load step response 702 appears as a result of discharging the PCB capacitors and has a value of approximately 0.795V. The difference between the initial voltage and the minimum voltage has been reduced from over 0.1V without on-chip capacitors to approximately 0.06V. This reduction in the difference in supply voltage means that the initial voltage can be reduced from approximately 0.855V to around 0.81V while still maintaining the same minimum supply voltage.

[0181] Figure 8 Improved load step responses 702 and 502 over longer time periods are shown, which include load step increases, such as Figure 4 As shown, a significant improvement in undershoot can be observed. However, the overshoot experienced with a step increase in load shows almost no improvement. While the maximum supply voltage is important for power consumption, the impact of overshoot on IPU performance is far less than that of undershoot because it does not affect the initial supply voltage and the maximum voltage is not required to ensure fault-free hardware operation.

[0182] Figure 14The graph shows the power supply impedance at the bumps of the Colossus Mk2 die. The graph on the left shows the power supply impedance without a WoW capacitor, and the graph on the right shows the power supply impedance with a WoW capacitor. These graphs are impedance versus frequency in μOhms.

[0183] Each graph displays four distinct curves. Curves 1502a and 1502b show the effect of frequency on the impedance of capacitors mounted on the printed circuit board (BD), including large capacitors with a minimum impedance of approximately 180 kHz and other smaller capacitors with a minimum impedance up to 1 MHz. Curves 1504a and 1504b show the effect of frequency on package impedance. Curves 1506a and 1506b show the effect of frequency on die impedance. Curve 1508a shows the overall effect of frequency on power supply impedance. The overall effect is the superimposed effect due to the three components shown in the graph.

[0184] While the impedance response of capacitors mounted on the printed circuit board and package is similar at different frequencies with and without WoW capacitors, the on-die impedance drops significantly at much lower frequencies with WoW capacitors. This has the effect of minimizing the overall impedance at lower frequencies, as can be seen by comparing the overall impedance curves 1508a and 1508b. WoW capacitors also have the effect of reducing the minimum overall impedance. This minimum occurs at approximately 6e 7 At a frequency of Hz.

[0185] Another advantage of WoW capacitors is that, as WoW capacitors provide on-chip capacitance, the need for discrete on-chip capacitors 1808 is reduced. Therefore, the number of discrete capacitors 1808 can be reduced, or the need for discrete capacitors 1808 can be completely eliminated, thus eliminating the need for discrete capacitors 1808. In such an embodiment, the WoW capacitor will provide the entire first-stage capacitance.

[0186] Embodiments of this invention utilize wafer-to-wafer (WoW) technology. WoW technology is a relatively new development in die manufacturing. Currently, it is used to manufacture GPUs, allowing them to become more powerful without increasing their physical size. The layers are stacked vertically along the printed circuit board (PCB), rather than horizontally.

[0187] Unlike traditional interconnects used in multi-chip modules (MCMs), WoW uses through-silicon vias (TSVs) to allow communication between stacked dies. This improves power efficiency and reduces latency between modules. To provide a way to transmit signals to / from the die, i.e., to access the back-end process line (BeOL) layer of the die, a TSV is fabricated for I / O through one of the dies. Because the dies are mirrored, a TSV through one die allows power supply voltage to be delivered to both dies. This provides direct connectivity between logic and the C4 ball array.

[0188] The logic layer is thinned to reduce the chip's thickness. This is possible because once the front-end line process (FeOL) and BeOL layers have been formed on the silicon layer of the wafer, the silicon layer no longer provides further functionality. Logic wafers can be thinned to only a few micrometers in thickness.

[0189] Then, as is known in the art, the resulting stacked wafer can be bumped, monolithized, and conventionally packaged (flip-chip BGA).

[0190] It should be understood that the above embodiments have been described by way of example only. Once the disclosure herein is given, other variations or uses of the disclosed technology will become apparent to those skilled in the art. The scope of this disclosure is not limited to the described embodiments, but only to the appended claims.

Claims

1. A computer architecture, comprising: A first silicon substrate in which computer circuitry configured to perform computational operations is formed, the first silicon substrate having a self-supporting depth and a facing surface; A second silicon substrate in which a plurality of distributed capacitor cells are formed, the second silicon substrate having a facing surface that overlaps with the facing surface of a first silicon substrate and is connected to the first silicon substrate via a set of connectors that extend in the depth direction of the structure between the facing surfaces, the facing surface of the second silicon substrate having a planar surface size that matches the planar surface size of the facing surface of the first silicon substrate. The second silicon substrate has an outer surface on which multiple connector terminals for connecting a computer structure to a power supply voltage are arranged, wherein the second silicon substrate has a smaller depth than the first silicon substrate.

2. The computer architecture according to claim 1, wherein, The facing surfaces of the first silicon substrate and the second silicon substrate are bonded together by one or more bonding layers.

3. The computer architecture according to any one of the preceding claims, wherein, The connector includes a through-silicon via extending through a second silicon substrate to a first silicon substrate to provide an electrical connection between the connector terminals and the first silicon substrate.

4. The computer architecture according to claim 1, wherein, Each distributed capacitor unit includes a predetermined number of capacitor blocks, each capacitor block having a capacitance in the range of 0.1 nF to 1.5 nF.

5. The computer architecture according to claim 4, wherein, The predetermined quantity is between 10 and 20.

6. The computer architecture according to any one of claims 4 or 5, wherein, Each distributed capacitor unit has a capacitance ranging from 5nF to 30nF.

7. The computer architecture according to any one of claims 1-2 and 4-5, wherein, The total planar area of ​​the distributed capacitor cells is at least 80% of the total planar area of ​​the first silicon substrate, and the capacitance of the plurality of distributed capacitor cells is in the range of 0.5µF / mm² to 3µF / mm².

8. The computer architecture according to any one of claims 1-2 and 4-5, wherein, The first silicon substrate has a depth of 400 µm to 1000 µm.

9. The computer architecture according to any one of claims 1-2 and 4-5, wherein, The second silicon substrate has a non-self-supporting depth, which is less than 10 µm.

10. The computer architecture according to any one of claims 1-2 and 4-5, wherein, The distributed capacitor units are arranged in a regular array, and each distributed capacitor unit is connected to the power supply voltage connector terminal and the ground connector terminal.

11. The computer architecture according to claim 10, wherein, Each connector terminal connects to four different distributed capacitor units.

12. The computer architecture according to any one of claims 1-2 and 4-5, wherein, The set of connectors provides a connection between a first silicon substrate and a second silicon substrate that are axially aligned with the connector terminals.

13. The computer architecture according to claim 4, wherein, Each distributed capacitor unit includes two hold-out areas located at the corresponding connector terminals, and the hold-out areas and capacitor blocks have the same size.

14. The computer architecture according to any one of claims 4 or 5, wherein, Each capacitor block includes an array of trench capacitors arranged in a hexagonal array, wherein each trench capacitor has six adjacent trench capacitors, and each trench capacitor is equidistant from each of its adjacent trench capacitors.

15. The computer architecture according to claim 13, wherein, The connector includes a through-silicon via extending through a second silicon substrate to a first silicon substrate to provide an electrical connection between the connector terminals and the first silicon substrate, wherein the through-silicon via is disposed in a restricted area of ​​the distributed capacitor cell.

16. The computer architecture according to any one of claims 13 or 15, wherein, The first silicon substrate has a depth of 700 µm to 800 µm.

17. The computer architecture according to claim 1, wherein, The computer circuit includes multiple processing units, each having an execution unit and local memory, and the multiple processing units are configured for parallel computing.

18. The computer architecture according to claim 17, wherein, The computer circuitry includes a synchronization circuit configured to control the plurality of processing units to operate according to a batch synchronous parallel protocol.

19. The computer architecture according to claim 17 or 18, wherein, The computer circuitry includes a clock connected to control the operation of the processing unit.

20. A method for manufacturing a computer architecture, the method comprising: A first silicon substrate is provided, the first silicon substrate including computer circuitry configured to perform computational operations, the first silicon substrate having a self-supporting depth; Provide a second silicon substrate comprising multiple distributed capacitor units; The facing surface of the first silicon substrate is bonded to the facing surface of the second silicon substrate, such that the facing surfaces are overlapped and positioned, and the facing surfaces have matching planar surface dimensions. The second silicon substrate is thinned so that the second silicon substrate has a depth smaller than that of the first silicon substrate; as well as Multiple connector terminals are provided on the outer surface of the second silicon substrate for connecting the computer structure to a power supply voltage.

21. The method of claim 20, further comprising, after thinning the second silicon substrate, forming a through-silicon via in the second silicon substrate to provide a connection between the connector terminal and the first silicon substrate.

22. The method according to any one of claims 20 and 21, wherein, The second silicon substrate is thinned to a depth of less than 10 µm, giving the second silicon substrate a non-self-supporting depth.

23. The method according to any one of claims 20 and 21, wherein, The distributed capacitor cells are arranged in a regular array, and the method includes connecting each distributed capacitor cell to a power supply voltage connector terminal and a ground connector terminal.

24. The method according to claim 23, wherein, Each distributed capacitor unit includes a predetermined number of capacitor blocks and two guard zones located at the positions of two connector terminals. The guard zones and capacitor blocks have the same size.

25. The method of claim 24, comprising: After thinning the second silicon substrate, through-silicon vias are formed in the second silicon substrate to provide a connection between the connector terminals and the first silicon substrate; as well as The through-silicon via is formed at the location of the no-coverage zone.

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